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ServerSync/lib/pygments/lexers/__pycache__/hdl.cpython-314.pyc

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Init im going to bed -=-
2026-02-12 02:28:23 +02:00
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pygments.lexers.hdl
~~~~~~~~~~~~~~~~~~~
Lexers for hardware descriptor languages.
:copyright: Copyright 2006-2025 by the Pygments team, see AUTHORS.
:license: BSD, see LICENSE for details.
N)<06>
RegexLexer<EFBFBD>bygroups<70>include<64>using<6E>this<69>words) <09>Text<78>Comment<6E>Operator<6F>Keyword<72>Name<6D>String<6E>Number<65> Punctuation<6F>
Whitespace<EFBFBD> VerilogLexer<65>SystemVerilogLexer<65> VhdlLexerc<00><>a<00>]tRt^toRtRtRR.tR.tR.tRt Rt
Rt R R
] PR 3R ]3R ]!]P"]43R] P$3R] P&3R]3R]R3R]P*3R]P.3R]P.3R]P03R]P23R]P43R]P63R]3R]P43R]3R]3R]P<3R]!]]P@]!43R ]!]]P@]!4R!3]"!R9R"R#7]3]"!R:R$R"R%7] P3]"!R;R&R"R%7]PF3]"!R<R"R#7]PH3R']PJ3R(]3R)]3.RR*]R+3R,]P"3R-]3R ]!]P"]43R.]3.R R/] P3R0] P&3R1] P$R+3R2] P3R3] P3R4]R+3.R!R5]P@R+3./t&R6t'R7t(Vt)R8#)=rz7
For verilog source code with preprocessor directives.
<EFBFBD>verilog<6F>vz*.vztext/x-verilogz%https://en.wikipedia.org/wiki/Verilogz1.4<EFBFBD>(?:\s|//.*?\n|/[*].*?[*]/)+<2B>rootz ^\s*`define<6E>macro<72>\s+<2B>(\\)(\n)<29>/(\\\n)?/(\n|(.|\n)*?[^\\]\n)<29>/(\\\n)?[*](.|\n)*?[*](\\\n)?/<2F>[{}#@]<5D>L?"<22>string<6E>4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'<27>%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?<3F>(\d+\.\d*|\.\d+|\d+[fF])[fF]?z([0-9]+)|(\'h)[0-9a-fA-F]+z([0-9]+)|(\'b)[01]+z([0-9]+)|(\'d)[0-9]+z([0-9]+)|(\'o)[0-7]+z\'[01xz]z\d+[Ll]?<3F>[~!%^&*+=|?:<>/-]<5D> [()\[\],.;\']<5D> `[a-zA-Z_]\w*<2A>^(\s*)(package)(\s+)<29>^(\s*)(import)(\s+)<29>import<72>\b<><01>suffix<69>`)<02>prefixr,z\$<24>[a-zA-Z_]\w*:(?!:)<29>\$?[a-zA-Z_]\w*<2A>\\(\S+)<29>"<22>#pop<6F>/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})<29> [^\\"\n]+<2B>\\<5C>[^/\n]+<2B>/[*](.|\n)*?[*]/z//.*?\n<>/<2F> (?<=\\)\n<>\n<> [\w:]+\*?c <0C>j<00>^pRV9d
VR, pRV9d
VR, pRV9d
VR, pV#)zXVerilog code will use one of reg/wire/assign for sure, and that
is not common elsewhere.<2E>regg<67><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>?<3F>wire<72>assign<67>)<02>text<78>results& <20>:/tmp/pip-target-qd_sq_1j/lib/python/pygments/lexers/hdl.py<70> analyse_text<78>VerilogLexer.analyse_text<78>s?<00><00><13><06> <10>D<EFBFBD>=<3D> <12>c<EFBFBD>M<EFBFBD>F<EFBFBD> <11>T<EFBFBD>><3E> <12>c<EFBFBD>M<EFBFBD>F<EFBFBD> <13>t<EFBFBD> <1B> <12>c<EFBFBD>M<EFBFBD>F<EFBFBD><15> <0A>rAN)q<>always<79> always_comb<6D> always_ff<66> always_latch<63>andr@<00> automatic<69>begin<69>break<61>buf<75>bufif0<66>bufif1<66>case<73>casex<65>casez<65>cmos<6F>const<73>continue<75>deassign<67>default<6C>defparam<61>disable<6C>do<64>edge<67>else<73>end<6E>endcase<73> endfunction<6F> endgenerate<74> endmodule<6C>
endpackage<EFBFBD> endprimitive<76>
endspecify<EFBFBD>endtable<6C>endtask<73>enum<75>event<6E>final<61>for<6F>force<63>forever<65>fork<72>function<6F>generate<74>genvar<61>highz0<7A>highz1<7A>if<69>initial<61>inout<75>input<75>integer<65>join<69>large<67>
localparam<EFBFBD> macromodule<6C>medium<75>module<6C>nand<6E>negedge<67>nmos<6F>nor<6F>not<6F>notif0<66>notif1<66>or<6F>output<75>packed<65> parameter<65>pmos<6F>posedge<67> primitive<76>pull0<6C>pull1<6C>pulldown<77>pullup<75>rcmos<6F>ref<65>release<73>repeat<61>return<72>rnmos<6F>rpmos<6F>rtran<61>rtranif0<66>rtranif1<66>scalared<65>signed<65>small<6C>specify<66> specparam<61>strengthr <00>strong0<67>strong1<67>struct<63>table<6C>task<73>tran<61>tranif0<66>tranif1<66>type<70>typedef<65>unsigned<65>var<61>vectored<65>void<69>wait<69>weak0<6B>weak1<6B>while<6C>xnor<6F>xor)<1B>
accelerate<EFBFBD>autoexpand_vectornets<74>
celldefine<EFBFBD>default_nettyper_<00>elsif<69> endcelldefine<6E>endif<69>
endprotect<EFBFBD> endprotected<65>expand_vectornets<74>ifdef<65>ifndefr<00> noaccelerate<74>noexpand_vectornets<74>noremove_gatenames<65>noremove_netnames<65>nounconnected_drive<76>protect<63> protected<65>remove_gatenames<65>remove_netnames<65>resetall<6C> timescale<6C>unconnected_drive<76>undef)4<>bits<74>
bitstoreal<EFBFBD>bitstoshortreal<61> countdrivers<72>display<61>fclose<73>fdisplay<61>finish<73>floor<6F>fmonitor<6F>fopen<65>fstrobe<62>fwrite<74>
getpattern<EFBFBD>history<72>incsavery<00>itor<6F>key<65>list<73>log<6F>monitor<6F>
monitoroff<EFBFBD> monitoron<6F>nokey<65>nolog<6F>printtimescale<6C>random<6F>readmemb<6D>readmemh<6D>realtime<6D>
realtobits<EFBFBD>reset<65> reset_count<6E> reset_value<75>restart<72>rtoi<6F>save<76>scale<6C>scope<70>shortrealtobits<74>
showscopes<EFBFBD> showvariables<65>showvars<72> sreadmemb<6D> sreadmemh<6D>stime<6D>stop<6F>strobe<62>time<6D>
timeformat<EFBFBD>write)<17>byte<74>shortint<6E>int<6E>longintrzr<00>bit<69>logicr><00>supply0<79>supply1<79>tri<72>triand<6E>trior<6F>tri0<69>tri1<69>trireg<65>uwirer?<00>wand<6E> worshortreal<61>realr<6C>)*<2A>__name__<5F>
__module__<EFBFBD> __qualname__<5F>__firstlineno__<5F>__doc__<5F>name<6D>aliases<65> filenames<65> mimetypes<65>url<72> version_added<65>_wsr <00>Preprocrrr <00>Escape<70>Single<6C> Multiliner<00>Charr<00>Float<61>Hex<65>Bin<69>Integer<65>Octr
r <00>Constantr <00> Namespacerr<00>Builtin<69>Type<70>Label<65>tokensrE<00>__static_attributes__<5F>__classdictcell__)<01> __classdict__s@rDrrs<><00><><00><00><08> <15>D<EFBFBD><18>#<23><1E>G<EFBFBD><16><07>I<EFBFBD>!<21>"<22>I<EFBFBD>
1<EFBFBD>C<EFBFBD><19>M<EFBFBD> )<29>C<EFBFBD> <0F> <1B>W<EFBFBD>_<EFBFBD>_<EFBFBD>g<EFBFBD> 6<> <13>Z<EFBFBD> <20> <18>(<28>6<EFBFBD>=<3D>=<3D>*<2A>=<3D> ><3E> -<2D>w<EFBFBD>~<7E>~<7E> ><3E> .<2E><07>0A<30>0A<30> B<> <16> <0B> $<24> <13>V<EFBFBD>X<EFBFBD> &<26> D<>f<EFBFBD>k<EFBFBD>k<EFBFBD> R<> 5<>v<EFBFBD>|<7C>|<7C> D<> -<2D>v<EFBFBD>|<7C>|<7C> <<3C> *<2A>F<EFBFBD>J<EFBFBD>J<EFBFBD> 7<> #<23>V<EFBFBD>Z<EFBFBD>Z<EFBFBD> 0<> $<24>f<EFBFBD>n<EFBFBD>n<EFBFBD> 5<> $<24>f<EFBFBD>j<EFBFBD>j<EFBFBD> 1<> <18>&<26> !<21> <18>&<26>.<2E>.<2E> )<29> !<21>8<EFBFBD> ,<2C> <1D>{<7B> +<2B> <1D>t<EFBFBD>}<7D>}<7D> -<2D> $<24>h<EFBFBD>z<EFBFBD>7<EFBFBD>;L<>;L<>d<EFBFBD>&S<> T<> #<23>X<EFBFBD>j<EFBFBD>'<27>:K<>:K<>T<EFBFBD>%R<> <15> <17><13>:<3A>"CH<01>#I<01>$<15>% <16>(<13><19>"&<26>e<EFBFBD>5<><15>_<EFBFBD>_<EFBFBD> <1E><13>W<01><1D>U<EFBFBD> ,<2C><12>\<5C>\<5C>
<1B><13>1<>:?<3F> @<01>
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<EFBFBD>Z <11> <11>6<EFBFBD>6<EFBFBD> "<22> ?<3F><16><1D><1D> O<> <19>6<EFBFBD> "<22> <18>(<28>6<EFBFBD>=<3D>=<3D>*<2A>=<3D> ><3E> <12>F<EFBFBD>O<EFBFBD> 
<EFBFBD> <10> <17><17><1F><1F> )<29> <20>'<27>"3<>"3<> 4<> <17><17><1E><1E><16> 0<> <11>7<EFBFBD>?<3F>?<3F> #<23> <19>7<EFBFBD>?<3F>?<3F> +<2B> <12>J<EFBFBD><06> '<27> 
<EFBFBD> <11> <19>4<EFBFBD>><3E>><3E>6<EFBFBD> 2<>
<EFBFBD>{`<06>F<EFBFBD>D <16> rGc <00> <00>]tRt^<5E>tRtRtRR.tRR.tR.tRt Rt
R t R
.R ] !] ]P4R 3NR ] !] ]P"] 43NR] !] ]P"] 4R3NR] 3NR] !]P&] 43NR]P(3NR]P*3NR]3NR]R3NR]P.3NR]P23NR]P23NR]P43NR]P63NR]P83NR]P:3NR]3NR]P83NR ]3N]!R9R!R"7]P@3NR#]3NR$]!PD3N]!R:R!R"7]3NR%] !]PF] ]!PH43NR&] !]PF] ]!PH43NR'] !]PF] ]] ]!PH43N]!R;R!R"7]PJ3N]!R<R!R"7]P3N]!R=R!R"7]!PL3NR(]!PN3NR)]!3NR*]!3NRR+]R,3R-]P&3R.]3R] !]P&] 43R/]3.R R0]P3R1]P*3R2]P(R,3R3]P3R4]P3R5] R,3.RR6]!P"R,3./t(R7t)R8#)>rz]
Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
1800-2009 standard.
<EFBFBD> systemverilog<6F>svz*.svz*.svhztext/x-systemverilogz+https://en.wikipedia.org/wiki/SystemVerilog<6F>1.5rrz^(\s*)(`define)rr'r(r)rrrrrrr r!r"r#z4([1-9][_0-9]*)?\s*\'[sS]?[bB]\s*[xXzZ?01][_xXzZ?01]*z6([1-9][_0-9]*)?\s*\'[sS]?[oO]\s*[xXzZ?0-7][_xXzZ?0-7]*z6([1-9][_0-9]*)?\s*\'[sS]?[dD]\s*[xXzZ?0-9][_xXzZ?0-9]*zB([1-9][_0-9]*)?\s*\'[sS]?[hH]\s*[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]*z
\'[01xXzZ]z [0-9][_0-9]*r$r*r+z[()\[\],.;\'$]r&z(class)(\s+)([a-zA-Z_]\w*)z(extends)(\s+)([a-zA-Z_]\w*)z,(endclass\b)(?:(\s*)(:)(\s*)([a-zA-Z_]\w*))?r/r0r1r2r3r4r5r6r7r8z//.*?$r9r:r;r<rAN)<02>inside<64>dist)<29><> accept_on<6F>aliasrHrIrJrKrL<00>assertr@<00>assumerM<00>beforerN<00>bind<6E>bins<6E>binsofrOrPrQrRrSrTrU<00>cell<6C>checker<65>clockingrV<00>config<69>
constraint<EFBFBD>contextrX<00>cover<65>
covergroup<EFBFBD>
coverpoint<EFBFBD>crossrYrZr[<00>designr\r]r^r_r`ra<00>
endchecker<EFBFBD> endclocking<6E> endconfigrbrc<00>endgroup<75> endinterfacerdrerf<00>
endprogram<EFBFBD> endproperty<74> endsequencergrhrirj<00>
eventually<EFBFBD>expect<63>export<72>externrl<00> first_matchrmrn<00>foreachrorp<00>forkjoinrqrrrs<00>globalrtrurv<00>iff<66>ifnone<6E> ignore_bins<6E> illegal_bins<6E>implies<65>
implementsr)<00>incdirrrwrxry<00>instance<63> interconnect<63> interface<63> intersectr{<00>join_any<6E> join_noner|<00>let<65>liblist<73>library<72>localr}r~<00>matchesr<00>modportr<74>r<>r<><00>nettype<70>new<65>nexttimer<65>r<><00>noshowcancelledr<64>r<>r<><00>nullr<6C>r<><00>packager<65>r<>r<>r<>r<><00>priority<74>program<61>propertyr<79>r<>r<>r<>r<><00>pulsestyle_ondetect<63>pulsestyle_onevent<6E>pure<72>rand<6E>randc<64>randcase<73> randsequencer<65>r<><00> reject_onr<6E>r<><00>restrictr<74>r<>r<>r<>r<>r<><00>s_always<79> s_eventually<6C>
s_nexttime<EFBFBD>s_until<69> s_until_withr<68><00>sequence<63> showcancelledr<64><00>soft<66>solver<65>r<><00>static<69>strongr<67>r<>r<><00>super<65>sync_accept_on<6F>sync_reject_onr<6E><00>taggedr<64>r<00>
throughout<EFBFBD> timeprecision<6F>timeunitr<74>r<>r<>r<><00>union<6F>unique<75>unique0<65>until<69>
until_with<EFBFBD>untyped<65>user<65><00>virtualr<6C><00>
wait_order<EFBFBD>weakr<6B>r<>r<><00>wildcard<72>with<74>withinr<6E>r<>)!rr<00>chandlerWrkrrzrrrr<>r>r<00> shortrealr<6C>r rr<>r<>r<>r<>r r
r r r rrrrrr?<00>wor)z `__FILE__z `__LINE__z`begin_keywordsz `celldefinez`default_nettypez`definez`elsez`elsifz `end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz `resetallz
`timescalez`unconnected_drivez`undefz `undefineall)<29>z$exitz$finishz$stopz $realtimez$stimez$timez$printtimescalez $timeformatz $bitstorealz$bitstoshortrealz$castz$itorz $realtobitsz$rtoiz$shortrealtobitsz$signedz $unsignedz$bitsz $isunboundedz $typenamez $dimensionsz$highz
$incrementz$leftz$lowz$rightz$sizez$unpacked_dimensionsz$acosz$acoshz$asinz$asinhz$atanz$atan2z$atanhz$ceilz$clog2z$cosz$coshz$expz$floorz$hypotz$lnz$log10z$powz$sinz$sinhz$sqrtz$tanz$tanhz
$countbitsz
$countonesz
$isunknownz$onehotz$onehot0z$infoz$errorz$fatalz$warningz$assertcontrolz$assertfailoffz $assertfailonz $assertkillz$assertnonvacuousonz
$assertoffz $assertonz$assertpassoffz $assertpassonz$assertvacuousoffz$changedz $changed_gclkz$changing_gclkz $falling_gclkz$fellz
$fell_gclkz $future_gclkz$pastz
$past_gclkz $rising_gclkz$rosez
$rose_gclkz$sampledz$stablez $stable_gclkz $steady_gclkz$coverage_controlz $coverage_getz$coverage_get_maxz$coverage_mergez$coverage_savez $get_coveragez$load_coverage_dbz$set_coverage_db_namez$dist_chi_squarez $dist_erlangz$dist_exponentialz $dist_normalz $dist_poissonz$dist_tz $dist_uniformz$randomz$q_addz$q_examz$q_fullz $q_initializez $q_removez$async$and$arrayz$async$and$planez$async$nand$arrayz$async$nand$planez$async$nor$arrayz$async$nor$planez$async$or$arrayz$async$or$planez$sync$and$arrayz$sync$and$planez$sync$nand$arrayz$sync$nand$planez$sync$nor$arrayz$sync$nor$planez$sync$or$arrayz$sync$or$planez$systemz$displayz $displaybz $displayhz $displayoz$monitorz $monitorbz $monitorhz $monitoroz $monitoroffz
$monitoronz$strobez$strobebz$strobehz$strobeoz$writez$writebz$writehz$writeoz$fclosez $fdisplayz
$fdisplaybz
$fdisplayhz
$fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz $fmonitorz
$fmonitorbz
$fmonitorhz
$fmonitoroz$fopenz$freadz$fscanfz$fseekz$fstrobez $fstrobebz $fstrobehz $fstrobeoz$ftellz$fwritez$fwritebz$fwritehz$fwriteoz$rewindz$sformatz $sformatfz$sscanfz$swritez$swritebz$swritehz$swriteoz$ungetcz $readmembz $readmemhz
$writemembz
$writememhz$test$plusargsz$value$plusargsz$dumpallz $dumpfilez
$dumpflushz
$dumplimitz$dumpoffz$dumponz
$dumpportsz $dumpportsallz$dumpportsflushz$dumpportslimitz $dumpportsoffz $dumpportsonz $dumpvars)*rrrrrrrrrrrr rrr r!r r,r r"r#r$rr%rr&r(r*r)r'r
r<00>Wordr r+<00> Declaration<6F>Classr.r-r/r0r1rArGrDrr<00>sO<00><00><08> <1B>D<EFBFBD><1E><04>%<25>G<EFBFBD><17><17>!<21>I<EFBFBD>'<27>(<28>I<EFBFBD>
7<EFBFBD>C<EFBFBD><19>M<EFBFBD> )<29>C<EFBFBD> <0F>}
<EFBFBD> <1F><18>*<2A>g<EFBFBD>o<EFBFBD>o<EFBFBD>!F<><07> P<>}
<EFBFBD> $<24>h<EFBFBD>z<EFBFBD>7<EFBFBD>;L<>;L<>j<EFBFBD>&Y<> Z<>}
<EFBFBD>$<24>X<EFBFBD>j<EFBFBD>'<27>:K<>:K<>Z<EFBFBD>%X<>Zb<5A> c<>}
<EFBFBD>
<14>Z<EFBFBD> <20> }
<EFBFBD> <19>(<28>6<EFBFBD>=<3D>=<3D>*<2A>=<3D> ><3E> }
<EFBFBD>.<2E>w<EFBFBD>~<7E>~<7E> ><3E>}
<EFBFBD>/<2F><07>0A<30>0A<30> B<>}
<EFBFBD><17> <0B> $<24>}
<EFBFBD><14>V<EFBFBD>X<EFBFBD> &<26>}
<EFBFBD>E<01>f<EFBFBD>k<EFBFBD>k<EFBFBD> R<>}
<EFBFBD>6<>v<EFBFBD>|<7C>|<7C> D<>}
<EFBFBD>.<2E>v<EFBFBD>|<7C>|<7C> <<3C>}
<EFBFBD> E<01> <13>Z<EFBFBD>Z<EFBFBD> <19>!}
<EFBFBD>$G<01> <13>Z<EFBFBD>Z<EFBFBD> <19>%}
<EFBFBD>(G<01> <13>^<5E>^<5E> <1D>)}
<EFBFBD>,S<01> <13>Z<EFBFBD>Z<EFBFBD> <19>-}
<EFBFBD>2<1B>F<EFBFBD> #<23>3}
<EFBFBD>4<1D>f<EFBFBD>n<EFBFBD>n<EFBFBD> -<2D>5}
<EFBFBD>8"<22>8<EFBFBD> ,<2C>9}
<EFBFBD>:<13>%<25>e<EFBFBD> 4<>h<EFBFBD>m<EFBFBD>m<EFBFBD> D<>;}
<EFBFBD>><1F> <0B> ,<2C>?}
<EFBFBD>@<1E>t<EFBFBD>}<7D>}<7D> -<2D>A}
<EFBFBD>D<13>(<1F>R<1D>S)<1E>T<15>U* <16>E}
<EFBFBD>\+<2B> <15>g<EFBFBD>)<29>)<29>:<3A>t<EFBFBD>z<EFBFBD>z<EFBFBD> B<> D<01>]}
<EFBFBD>`-<2D> <15>g<EFBFBD>)<29>)<29>:<3A>t<EFBFBD>z<EFBFBD>z<EFBFBD> B<> D<01>a}
<EFBFBD>d=<3D> <15>g<EFBFBD>)<29>)<29>:<3A>{<7B>J<EFBFBD>PT<50>PZ<50>PZ<50> [<5B> ]<01>e}
<EFBFBD>j<13>@<01><1D> <1E><15>\<5C>\<5C>
<1B>k}
<EFBFBD>B<13>N<01> <1D> <1E><15>_<EFBFBD>_<EFBFBD> <1E>C}
<EFBFBD>T<13>M<12>Z <20>[M!<21>\<12>\<5C>\<5C>]N <1B>U}
<EFBFBD>t#<23>D<EFBFBD>J<EFBFBD>J<EFBFBD> /<2F>u}
<EFBFBD>v <20><14> &<26>w}
<EFBFBD>x<18><14> <1E>y}
<EFBFBD>| <11> <11>6<EFBFBD>6<EFBFBD> "<22> ?<3F><16><1D><1D> O<> <19>6<EFBFBD> "<22> <18>(<28>6<EFBFBD>=<3D>=<3D>*<2A>=<3D> ><3E> <12>F<EFBFBD>O<EFBFBD> 
<EFBFBD> <10> <17><17><1F><1F> )<29> <20>'<27>"3<>"3<> 4<> <16><07><0E><0E><06> /<2F> <11>7<EFBFBD>?<3F>?<3F> #<23> <19>7<EFBFBD>?<3F>?<3F> +<2B> <12>J<EFBFBD><06> '<27> 
<EFBFBD> <11> <19>4<EFBFBD>><3E>><3E>6<EFBFBD> 2<>
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For VHDL source code.
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bit_vector<EFBFBD>file_open_kind<6E>file_open_status<75>
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