avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/post/cpu/ppc4xx/Makefile

@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2002-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cache_4xx.o
+obj-y += cache.o
+obj-y += denali_ecc.o
+obj-y += ether.o
+obj-y += fpu.o
+obj-y += ocm.o
+obj-y += spr.o
+obj-y += uart.o
+obj-y += watchdog.o

u-boot/post/cpu/ppc4xx/cache.c

@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+/* Cache test
+ *
+ * This test verifies the CPU data and instruction cache using
+ * several test scenarios.
+ */
+
+#include <post.h>
+
+#if CONFIG_POST & CONFIG_SYS_POST_CACHE
+
+#include <asm/mmu.h>
+#include <watchdog.h>
+
+#define CACHE_POST_SIZE	1024
+
+int cache_post_test1 (int tlb, void *p, int size);
+int cache_post_test2 (int tlb, void *p, int size);
+int cache_post_test3 (int tlb, void *p, int size);
+int cache_post_test4 (int tlb, void *p, int size);
+int cache_post_test5 (int tlb, void *p, int size);
+int cache_post_test6 (int tlb, void *p, int size);
+
+#ifdef CONFIG_440
+static unsigned char testarea[CACHE_POST_SIZE]
+__attribute__((__aligned__(CACHE_POST_SIZE)));
+#endif
+
+int cache_post_test (int flags)
+{
+	void *virt = (void *)CONFIG_SYS_POST_CACHE_ADDR;
+	int ints;
+	int res = 0;
+	int tlb = -1;		/* index to the victim TLB entry */
+
+	/*
+	 * All 44x variants deal with cache management differently
+	 * because they have the address translation always enabled.
+	 * The 40x ppc's don't use address translation in U-Boot at all,
+	 * so we have to distinguish here between 40x and 44x.
+	 */
+#ifdef CONFIG_440
+	int word0, i;
+
+	/*
+	 * Allocate a new TLB entry, since we are going to modify
+	 * the write-through and caching inhibited storage attributes.
+	 */
+	program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
+		    TLB_WORD2_I_ENABLE);
+
+	/* Find the TLB entry */
+	for (i = 0;; i++) {
+		if (i >= PPC4XX_TLB_SIZE) {
+			printf ("Failed to program tlb entry\n");
+			return -1;
+		}
+		word0 = mftlb1(i);
+		if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
+			tlb = i;
+			break;
+		}
+	}
+#endif
+	ints = disable_interrupts ();
+
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE);
+	WATCHDOG_RESET ();
+	if (res == 0)
+		res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE);
+
+	if (ints)
+		enable_interrupts ();
+
+#ifdef CONFIG_440
+	remove_tlb((u32)virt, CACHE_POST_SIZE);
+#endif
+
+	return res;
+}
+
+#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */

u-boot/post/cpu/ppc4xx/cache_4xx.S

@@ -0,0 +1,473 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+#include <post.h>
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#if CONFIG_POST & CONFIG_SYS_POST_CACHE
+
+	.text
+
+	/*
+	 * All 44x variants deal with cache management differently
+	 * because they have the address translation always enabled.
+	 * The 40x ppc's don't use address translation in U-Boot at all,
+	 * so we have to distinguish here between 40x and 44x.
+	 */
+#ifdef CONFIG_440
+/* void cache_post_disable (int tlb)
+ */
+cache_post_disable:
+	tlbre	r0, r3, 0x0002
+	ori	r0, r0, TLB_WORD2_I_ENABLE@l
+	tlbwe	r0, r3, 0x0002
+	sync
+	isync
+	blr
+
+/* void cache_post_wt (int tlb)
+ */
+cache_post_wt:
+	tlbre	r0, r3, 0x0002
+	ori	r0, r0, TLB_WORD2_W_ENABLE@l
+	andi.	r0, r0, ~TLB_WORD2_I_ENABLE@l
+	tlbwe	r0, r3, 0x0002
+	sync
+	isync
+	blr
+
+/* void cache_post_wb (int tlb)
+ */
+cache_post_wb:
+	tlbre	r0, r3, 0x0002
+	andi.	r0, r0, ~TLB_WORD2_W_ENABLE@l
+	andi.	r0, r0, ~TLB_WORD2_I_ENABLE@l
+	tlbwe	r0, r3, 0x0002
+	sync
+	isync
+	blr
+#else
+/* void cache_post_disable (int tlb)
+ */
+cache_post_disable:
+	lis	r0, 0x0000
+	ori	r0, r0, 0x0000
+	mtdccr	r0
+	sync
+	isync
+	blr
+
+/* void cache_post_wt (int tlb)
+ */
+cache_post_wt:
+	lis	r0, 0x8000
+	ori	r0, r0, 0x0000
+	mtdccr	r0
+	lis	r0, 0x8000
+	ori	r0, r0, 0x0000
+	mtdcwr	r0
+	sync
+	isync
+	blr
+
+/* void cache_post_wb (int tlb)
+ */
+cache_post_wb:
+	lis	r0, 0x8000
+	ori	r0, r0, 0x0000
+	mtdccr	r0
+	lis	r0, 0x0000
+	ori	r0, r0, 0x0000
+	mtdcwr	r0
+	sync
+	isync
+	blr
+#endif
+
+/* void cache_post_dinvalidate (void *p, int size)
+ */
+cache_post_dinvalidate:
+	dcbi	r0, r3
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE
+	subic.	r4, r4, CONFIG_SYS_CACHELINE_SIZE
+	bgt	cache_post_dinvalidate
+	sync
+	blr
+
+/* void cache_post_dstore (void *p, int size)
+ */
+cache_post_dstore:
+	dcbst	r0, r3
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE
+	subic.	r4, r4, CONFIG_SYS_CACHELINE_SIZE
+	bgt	cache_post_dstore
+	sync
+	blr
+
+/* void cache_post_dtouch (void *p, int size)
+ */
+cache_post_dtouch:
+	dcbt	r0, r3
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE
+	subic.	r4, r4, CONFIG_SYS_CACHELINE_SIZE
+	bgt	cache_post_dtouch
+	sync
+	blr
+
+/* void cache_post_iinvalidate (void)
+ */
+cache_post_iinvalidate:
+	iccci	r0, r0
+	sync
+	blr
+
+/* void cache_post_memset (void *p, int val, int size)
+ */
+cache_post_memset:
+	mtctr	r5
+1:
+	stb	r4, 0(r3)
+	addi	r3, r3, 1
+	bdnz	1b
+	blr
+
+/* int cache_post_check (void *p, int size)
+ */
+cache_post_check:
+	mtctr	r4
+1:
+	lbz	r0, 0(r3)
+	addi	r3, r3, 1
+	cmpwi	r0, 0xff
+	bne	2f
+	bdnz	1b
+	li	r3, 0
+	blr
+2:
+	li	r3, -1
+	blr
+
+#define CACHE_POST_DISABLE()		\
+	mr	r3, r10;		\
+	bl	cache_post_disable
+
+#define CACHE_POST_WT()			\
+	mr	r3, r10;		\
+	bl	cache_post_wt
+
+#define CACHE_POST_WB()			\
+	mr	r3, r10;		\
+	bl	cache_post_wb
+
+#define CACHE_POST_DINVALIDATE()	\
+	mr	r3, r11;		\
+	mr	r4, r12;		\
+	bl	cache_post_dinvalidate
+
+#define CACHE_POST_DFLUSH()		\
+	mr	r3, r11;		\
+	mr	r4, r12;		\
+	bl	cache_post_dflush
+
+#define CACHE_POST_DSTORE()		\
+	mr	r3, r11;		\
+	mr	r4, r12;		\
+	bl	cache_post_dstore
+
+#define CACHE_POST_DTOUCH()		\
+	mr	r3, r11;		\
+	mr	r4, r12;		\
+	bl	cache_post_dtouch
+
+#define CACHE_POST_IINVALIDATE()	\
+	bl	cache_post_iinvalidate
+
+#define CACHE_POST_MEMSET(val)		\
+	mr	r3, r11;		\
+	li	r4, val;		\
+	mr	r5, r12;		\
+	bl	cache_post_memset
+
+#define CACHE_POST_CHECK()		\
+	mr	r3, r11;		\
+	mr	r4, r12;		\
+	bl	cache_post_check;	\
+	mr	r13, r3
+
+/*
+ * Write and read 0xff pattern with caching enabled.
+ */
+	.global cache_post_test1
+cache_post_test1:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WB()
+	CACHE_POST_DINVALIDATE()
+
+	/* Write the negative pattern to the test area */
+	CACHE_POST_MEMSET(0xff)
+
+	/* Read the test area */
+	CACHE_POST_CHECK()
+
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/*
+ * Write zeroes with caching enabled.
+ * Write 0xff pattern with caching disabled.
+ * Read 0xff pattern with caching enabled.
+ */
+	.global cache_post_test2
+cache_post_test2:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WB()
+	CACHE_POST_DINVALIDATE()
+
+	/* Write the zero pattern to the test area */
+	CACHE_POST_MEMSET(0)
+
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	/* Write the negative pattern to the test area */
+	CACHE_POST_MEMSET(0xff)
+
+	CACHE_POST_WB()
+
+	/* Read the test area */
+	CACHE_POST_CHECK()
+
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/*
+ * Write-through mode test.
+ * Write zeroes, store the cache, write 0xff pattern.
+ * Invalidate the cache.
+ * Check that 0xff pattern is read.
+ */
+	.global cache_post_test3
+cache_post_test3:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WT()
+	CACHE_POST_DINVALIDATE()
+
+	/* Cache the test area */
+	CACHE_POST_DTOUCH()
+
+	/* Write the zero pattern to the test area */
+	CACHE_POST_MEMSET(0)
+
+	CACHE_POST_DSTORE()
+
+	/* Write the negative pattern to the test area */
+	CACHE_POST_MEMSET(0xff)
+
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	/* Read the test area */
+	CACHE_POST_CHECK()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/*
+ * Write-back mode test.
+ * Write 0xff pattern, store the cache, write zeroes.
+ * Invalidate the cache.
+ * Check that 0xff pattern is read.
+ */
+	.global cache_post_test4
+cache_post_test4:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WB()
+	CACHE_POST_DINVALIDATE()
+
+	/* Cache the test area */
+	CACHE_POST_DTOUCH()
+
+	/* Write the negative pattern to the test area */
+	CACHE_POST_MEMSET(0xff)
+
+	CACHE_POST_DSTORE()
+
+	/* Write the zero pattern to the test area */
+	CACHE_POST_MEMSET(0)
+
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	/* Read the test area */
+	CACHE_POST_CHECK()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/*
+ * Load the test instructions into the instruction cache.
+ * Replace the test instructions.
+ * Check that the original instructions are executed.
+ */
+	.global cache_post_test5
+cache_post_test5:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WT()
+	CACHE_POST_IINVALIDATE()
+
+	/* Compute r13 = cache_post_test_inst */
+	bl	cache_post_test5_reloc
+cache_post_test5_reloc:
+	mflr	r13
+	lis	r0, (cache_post_test_inst - cache_post_test5_reloc)@h
+	ori	r0, r0, (cache_post_test_inst - cache_post_test5_reloc)@l
+	add	r13, r13, r0
+
+	/* Copy the test instructions to the test area */
+	lwz	r0, 0(r13)
+	stw	r0, 0(r11)
+	lwz	r0, 8(r13)
+	stw	r0, 4(r11)
+	sync
+
+	/* Invalidate the cache line */
+	icbi	r0, r11
+	sync
+	isync
+
+	/* Execute the test instructions */
+	mtlr	r11
+	blrl
+
+	/* Replace the test instruction */
+	lwz	r0, 4(r13)
+	stw	r0, 0(r11)
+	sync
+
+	/* Do not invalidate the cache line */
+	isync
+
+	/* Execute the test instructions */
+	mtlr	r11
+	blrl
+	mr	r13, r3
+
+	CACHE_POST_IINVALIDATE()
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/*
+ * Load the test instructions into the instruction cache.
+ * Replace the test instructions and invalidate the cache.
+ * Check that the replaced instructions are executed.
+ */
+	.global cache_post_test6
+cache_post_test6:
+	mflr	r9
+	mr	r10, r3		/* tlb		*/
+	mr	r11, r4		/* p		*/
+	mr	r12, r5		/* size		*/
+
+	CACHE_POST_WT()
+	CACHE_POST_IINVALIDATE()
+
+	/* Compute r13 = cache_post_test_inst */
+	bl	cache_post_test6_reloc
+cache_post_test6_reloc:
+	mflr	r13
+	lis	r0, (cache_post_test_inst - cache_post_test6_reloc)@h
+	ori	r0, r0, (cache_post_test_inst - cache_post_test6_reloc)@l
+	add	r13, r13, r0
+
+	/* Copy the test instructions to the test area */
+	lwz	r0, 4(r13)
+	stw	r0, 0(r11)
+	lwz	r0, 8(r13)
+	stw	r0, 4(r11)
+	sync
+
+	/* Invalidate the cache line */
+	icbi	r0, r11
+	sync
+	isync
+
+	/* Execute the test instructions */
+	mtlr	r11
+	blrl
+
+	/* Replace the test instruction */
+	lwz	r0, 0(r13)
+	stw	r0, 0(r11)
+	sync
+
+	/* Invalidate the cache line */
+	icbi	r0, r11
+	sync
+	isync
+
+	/* Execute the test instructions */
+	mtlr	r11
+	blrl
+	mr	r13, r3
+
+	CACHE_POST_IINVALIDATE()
+	CACHE_POST_DINVALIDATE()
+	CACHE_POST_DISABLE()
+
+	mr	r3, r13
+	mtlr	r9
+	blr
+
+/* Test instructions.
+ */
+cache_post_test_inst:
+	li	r3, 0
+	li	r3, -1
+	blr
+
+#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */

u-boot/post/cpu/ppc4xx/denali_ecc.c

@@ -0,0 +1,259 @@
+/*
+ * (C) Copyright 2007
+ * Developed for DENX Software Engineering GmbH.
+ *
+ * Author: Pavel Kolesnikov <concord@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <watchdog.h>
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#include <post.h>
+
+#if CONFIG_POST & CONFIG_SYS_POST_ECC
+
+/*
+ * MEMORY ECC test
+ *
+ * This test performs the checks ECC facility of memory.
+ */
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <asm/ppc440.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const static uint8_t syndrome_codes[] = {
+	0xF4, 0XF1, 0XEC, 0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
+	0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
+	0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
+	0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
+	0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62,
+	0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A,
+	0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23,
+	0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
+	0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
+};
+
+#define ECC_START_ADDR		0x10
+#define ECC_STOP_ADDR		0x2000
+#define ECC_PATTERN		0x01010101
+#define ECC_PATTERN_CORR	0x11010101
+#define ECC_PATTERN_UNCORR	0x61010101
+
+inline static void disable_ecc(void)
+{
+	uint32_t value;
+
+	sync(); /* Wait for any pending memory accesses to complete. */
+	mfsdram(DDR0_22, value);
+	mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
+		| DDR0_22_CTRL_RAW_ECC_DISABLE);
+}
+
+inline static void clear_and_enable_ecc(void)
+{
+	uint32_t value;
+
+	sync(); /* Wait for any pending memory accesses to complete. */
+	mfsdram(DDR0_00, value);
+	mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+	mfsdram(DDR0_22, value);
+	mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
+		| DDR0_22_CTRL_RAW_ECC_ENABLE);
+}
+
+static uint32_t get_ecc_status(void)
+{
+	uint32_t int_status;
+#if defined(DEBUG)
+	uint8_t syndrome;
+	uint32_t hdata, ldata, haddr, laddr;
+	uint32_t value;
+#endif
+
+	mfsdram(DDR0_00, int_status);
+	int_status &= DDR0_00_INT_STATUS_MASK;
+
+#if defined(DEBUG)
+	if (int_status & (DDR0_00_INT_STATUS_BIT0 | DDR0_00_INT_STATUS_BIT1)) {
+		mfsdram(DDR0_32, laddr);
+		mfsdram(DDR0_33, haddr);
+		haddr &= 0x00000001;
+		if (int_status & DDR0_00_INT_STATUS_BIT1)
+			debug("Multiple accesses");
+		else
+			debug("A single access");
+
+		debug(" outside the defined physical memory space detected\n"
+		      "        addr = 0x%01x%08x\n", haddr, laddr);
+	}
+	if (int_status & (DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT3)) {
+		unsigned int bit;
+
+		mfsdram(DDR0_23, value);
+		syndrome = (value >> 16) & 0xff;
+		for (bit = 0; bit < sizeof(syndrome_codes); bit++)
+			if (syndrome_codes[bit] == syndrome)
+				break;
+
+		mfsdram(DDR0_38, laddr);
+		mfsdram(DDR0_39, haddr);
+		haddr &= 0x00000001;
+		mfsdram(DDR0_40, ldata);
+		mfsdram(DDR0_41, hdata);
+		if (int_status & DDR0_00_INT_STATUS_BIT3)
+			debug("Multiple correctable ECC events");
+		else
+			debug("Single correctable ECC event");
+
+		debug(" detected\n        0x%01x%08x - 0x%08x%08x, bit - %d\n",
+		      haddr, laddr, hdata, ldata, bit);
+	}
+	if (int_status & (DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT5)) {
+		mfsdram(DDR0_23, value);
+		syndrome = (value >> 8) & 0xff;
+		mfsdram(DDR0_34, laddr);
+		mfsdram(DDR0_35, haddr);
+		haddr &= 0x00000001;
+		mfsdram(DDR0_36, ldata);
+		mfsdram(DDR0_37, hdata);
+		if (int_status & DDR0_00_INT_STATUS_BIT5)
+			debug("Multiple uncorrectable ECC events");
+		else
+			debug("Single uncorrectable ECC event");
+
+		debug(" detected\n        0x%01x%08x - 0x%08x%08x, "
+		      "syndrome - 0x%02x\n",
+		      haddr, laddr, hdata, ldata, syndrome);
+	}
+	if (int_status & DDR0_00_INT_STATUS_BIT6)
+		debug("DRAM initialization complete\n");
+#endif /* defined(DEBUG) */
+
+	return int_status;
+}
+
+static int test_ecc(uint32_t ecc_addr)
+{
+	uint32_t value;
+	volatile uint32_t *const ecc_mem = (volatile uint32_t *)ecc_addr;
+	int ret = 0;
+
+	WATCHDOG_RESET();
+
+	debug("Entering test_ecc(0x%08x)\n", ecc_addr);
+	/* Set up correct ECC in memory */
+	disable_ecc();
+	clear_and_enable_ecc();
+	out_be32(ecc_mem, ECC_PATTERN);
+	out_be32(ecc_mem + 1, ECC_PATTERN);
+	ppcDcbf((u32)ecc_mem);
+
+	/* Verify no ECC error reading back */
+	value = in_be32(ecc_mem);
+	disable_ecc();
+	if (ECC_PATTERN != value) {
+		debug("Data read error (no-error case): "
+		      "expected 0x%08x, read 0x%08x\n", ECC_PATTERN, value);
+		ret = 1;
+	}
+	value = get_ecc_status();
+	if (0x00000000 != value) {
+		/* Expected no ECC status reported */
+		debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
+		      0x00000000, value);
+		ret = 1;
+	}
+
+	/* Test for correctable error by creating a one-bit error */
+	out_be32(ecc_mem, ECC_PATTERN_CORR);
+	ppcDcbf((u32)ecc_mem);
+	clear_and_enable_ecc();
+	value = in_be32(ecc_mem);
+	disable_ecc();
+	/* Test that the corrected data was read */
+	if (ECC_PATTERN != value) {
+		debug("Data read error (correctable-error case): "
+		      "expected 0x%08x, read 0x%08x\n", ECC_PATTERN, value);
+		ret = 1;
+	}
+	value = get_ecc_status();
+	if ((DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT7) != value) {
+		/* Expected a single correctable error reported */
+		debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
+		      DDR0_00_INT_STATUS_BIT2, value);
+		ret = 1;
+	}
+
+	/* Test for uncorrectable error by creating a two-bit error */
+	out_be32(ecc_mem, ECC_PATTERN_UNCORR);
+	ppcDcbf((u32)ecc_mem);
+	clear_and_enable_ecc();
+	value = in_be32(ecc_mem);
+	disable_ecc();
+	/* Test that the corrected data was read */
+	if (ECC_PATTERN_UNCORR != value) {
+		debug("Data read error (uncorrectable-error case): "
+		      "expected 0x%08x, read 0x%08x\n", ECC_PATTERN_UNCORR,
+		      value);
+		ret = 1;
+	}
+	value = get_ecc_status();
+	if ((DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT7) != value) {
+		/* Expected a single uncorrectable error reported */
+		debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
+		      DDR0_00_INT_STATUS_BIT4, value);
+		ret = 1;
+	}
+
+	/* Remove error from SDRAM and enable ECC. */
+	out_be32(ecc_mem, ECC_PATTERN);
+	ppcDcbf((u32)ecc_mem);
+	clear_and_enable_ecc();
+
+	return ret;
+}
+
+int ecc_post_test(int flags)
+{
+	int ret = 0;
+	uint32_t value;
+	uint32_t iaddr;
+
+	mfsdram(DDR0_22, value);
+	if (0x3 != DDR0_22_CTRL_RAW_DECODE(value)) {
+		debug("SDRAM ECC not enabled, skipping ECC POST.\n");
+		return 0;
+	}
+
+	/* Mask all interrupts. */
+	mfsdram(DDR0_01, value);
+	mtsdram(DDR0_01, (value & ~DDR0_01_INT_MASK_MASK)
+		| DDR0_01_INT_MASK_ALL_OFF);
+
+	for (iaddr = ECC_START_ADDR; iaddr <= ECC_STOP_ADDR; iaddr += iaddr) {
+		ret = test_ecc(iaddr);
+		if (ret)
+			break;
+	}
+	/*
+	 * Clear possible errors resulting from ECC testing.  (If not done, we
+	 * we could get an interrupt later on when exceptions are enabled.)
+	 */
+	set_mcsr(get_mcsr());
+	debug("ecc_post_test() returning %d\n", ret);
+	return ret;
+}
+#endif /* CONFIG_POST & CONFIG_SYS_POST_ECC */
+#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */

u-boot/post/cpu/ppc4xx/ether.c

@@ -0,0 +1,419 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+/*
+ * Ethernet test
+ *
+ * The Ethernet Media Access Controllers (EMAC) are tested in the
+ * internal loopback mode.
+ * The controllers are configured accordingly and several packets
+ * are transmitted. The configurable test parameters are:
+ *   MIN_PACKET_LENGTH - minimum size of packet to transmit
+ *   MAX_PACKET_LENGTH - maximum size of packet to transmit
+ *   CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
+ *     is tested with a different frame length. Starting with
+ *     MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
+ *     Defaults to 10 and can be overriden in the board config header.
+ */
+
+#include <post.h>
+
+#if CONFIG_POST & CONFIG_SYS_POST_ETHER
+
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-mal.h>
+#include <asm/ppc4xx-emac.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Get count of EMAC devices (doesn't have to be the max. possible number
+ * supported by the cpu)
+ *
+ * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
+ * EMAC count is possible. As it is needed for the Kilauea/Haleakala
+ * 405EX/405EXr eval board, using the same binary.
+ */
+#if defined(CONFIG_BOARD_EMAC_COUNT)
+#define LAST_EMAC_NUM	board_emac_count()
+#else /* CONFIG_BOARD_EMAC_COUNT */
+#if defined(CONFIG_HAS_ETH3)
+#define LAST_EMAC_NUM	4
+#elif defined(CONFIG_HAS_ETH2)
+#define LAST_EMAC_NUM	3
+#elif defined(CONFIG_HAS_ETH1)
+#define LAST_EMAC_NUM	2
+#else
+#define LAST_EMAC_NUM	1
+#endif
+#endif /* CONFIG_BOARD_EMAC_COUNT */
+
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_MFR_ETH_CLK_SEL_V(n)	((0x01<<27) / (n+1))
+#endif
+
+#define MIN_PACKET_LENGTH	64
+#define MAX_PACKET_LENGTH	1514
+#ifndef CONFIG_SYS_POST_ETH_LOOPS
+#define CONFIG_SYS_POST_ETH_LOOPS	10
+#endif
+#define PACKET_INCR	((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \
+			 CONFIG_SYS_POST_ETH_LOOPS)
+
+static volatile mal_desc_t tx __cacheline_aligned;
+static volatile mal_desc_t rx __cacheline_aligned;
+static char *tx_buf;
+static char *rx_buf;
+
+int board_emac_count(void);
+
+static void ether_post_init (int devnum, int hw_addr)
+{
+	int i;
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+	unsigned mode_reg;
+	sys_info_t sysinfo;
+#endif
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
+	unsigned long mfr;
+#endif
+
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+	/* Need to get the OPB frequency so we can access the PHY */
+	get_sys_info (&sysinfo);
+#endif
+
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	/* provide clocks for EMAC internal loopback  */
+	mfsdr (SDR0_MFR, mfr);
+	mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
+	mtsdr (SDR0_MFR, mfr);
+	sync ();
+#endif
+	/* reset emac */
+	out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
+	sync ();
+
+	for (i = 0;; i++) {
+		if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST))
+			break;
+		if (i >= 1000) {
+			printf ("Timeout resetting EMAC\n");
+			break;
+		}
+		udelay (1000);
+	}
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+	/* Whack the M1 register */
+	mode_reg = 0x0;
+	if (sysinfo.freqOPB <= 50000000);
+	else if (sysinfo.freqOPB <= 66666667)
+		mode_reg |= EMAC_MR1_OBCI_66;
+	else if (sysinfo.freqOPB <= 83333333)
+		mode_reg |= EMAC_MR1_OBCI_83;
+	else if (sysinfo.freqOPB <= 100000000)
+		mode_reg |= EMAC_MR1_OBCI_100;
+	else
+		mode_reg |= EMAC_MR1_OBCI_GT100;
+
+	out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg);
+
+#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
+
+	/* set the Mal configuration reg */
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+	mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
+	       MAL_CR_PLBLT_DEFAULT | 0x00330000);
+#else
+	mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
+	/* Errata 1.12: MAL_1 -- Disable MAL bursting */
+	if (get_pvr() == PVR_440GP_RB) {
+		mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
+	}
+#endif
+	/* setup buffer descriptors */
+	tx.ctrl = MAL_TX_CTRL_WRAP;
+	tx.data_len = 0;
+	tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
+
+	rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
+	rx.data_len = 0;
+	rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
+	flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
+	flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
+
+	switch (devnum) {
+	case 1:
+		/* setup MAL tx & rx channel pointers */
+#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
+		mtdcr (MAL0_TXCTP2R, &tx);
+#else
+		mtdcr (MAL0_TXCTP1R, &tx);
+#endif
+#if defined(CONFIG_440)
+		mtdcr (MAL0_TXBADDR, 0x0);
+		mtdcr (MAL0_RXBADDR, 0x0);
+#endif
+		mtdcr (MAL0_RXCTP1R, &rx);
+		/* set RX buffer size */
+		mtdcr (MAL0_RCBS1, PKTSIZE_ALIGN / 16);
+		break;
+	case 0:
+	default:
+		/* setup MAL tx & rx channel pointers */
+#if defined(CONFIG_440)
+		mtdcr (MAL0_TXBADDR, 0x0);
+		mtdcr (MAL0_RXBADDR, 0x0);
+#endif
+		mtdcr (MAL0_TXCTP0R, &tx);
+		mtdcr (MAL0_RXCTP0R, &rx);
+		/* set RX buffer size */
+		mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16);
+		break;
+	}
+
+	/* Enable MAL transmit and receive channels */
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+	mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (devnum*2)));
+#else
+	mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> devnum));
+#endif
+	mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> devnum));
+
+	/* set internal loopback mode */
+#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
+	out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 |
+		  EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
+		  EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
+		  in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
+#else
+	out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE |
+		  EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
+		  EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
+		  in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
+#endif
+
+	/* set transmit enable & receive enable */
+	out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE);
+
+	/* enable broadcast address */
+	out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE);
+
+	/* set transmit request threshold register */
+	out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000);	/* 256 byte threshold */
+
+	/* set receive	low/high water mark register */
+#if defined(CONFIG_440)
+	/* 440s has a 64 byte burst length */
+	out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000);
+#else
+	/* 405s have a 16 byte burst length */
+	out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
+#endif /* defined(CONFIG_440) */
+	out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000);
+
+	/* Set fifo limit entry in tx mode 0 */
+	out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003);
+	/* Frame gap set */
+	out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008);
+	sync ();
+}
+
+static void ether_post_halt (int devnum, int hw_addr)
+{
+	int i = 0;
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	unsigned long mfr;
+#endif
+
+	/* 1st reset MAL channel */
+	/* Note: writing a 0 to a channel has no effect */
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+	mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> (devnum * 2));
+#else
+	mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> devnum);
+#endif
+	mtdcr (MAL0_RXCARR, MAL_TXRX_CASR >> devnum);
+
+	/* wait for reset */
+	while (mfdcr (MAL0_RXCASR) & (MAL_TXRX_CASR >> devnum)) {
+		if (i++ >= 1000)
+			break;
+		udelay (1000);
+	}
+	/* emac reset */
+	out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
+
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	/* remove clocks for EMAC internal loopback  */
+	mfsdr (SDR0_MFR, mfr);
+	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
+	mtsdr (SDR0_MFR, mfr);
+#endif
+}
+
+static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
+{
+	int i = 0;
+
+	while (tx.ctrl & MAL_TX_CTRL_READY) {
+		if (i++ > 100) {
+			printf ("TX timeout\n");
+			return;
+		}
+		udelay (1000);
+		invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
+	}
+	tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
+		EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
+	tx.data_len = length;
+	memcpy (tx.data_ptr, packet, length);
+	flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
+	flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
+	sync ();
+
+	out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0);
+	sync ();
+}
+
+static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
+{
+	int length;
+	int i = 0;
+
+	while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
+		if (i++ > 100) {
+			printf ("RX timeout\n");
+			return 0;
+		}
+		udelay (1000);
+		invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
+	}
+	length = rx.data_len - 4;
+	if (length <= max_length) {
+		invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length);
+		memcpy(packet, rx.data_ptr, length);
+	}
+	sync ();
+
+	rx.ctrl |= MAL_RX_CTRL_EMPTY;
+	flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
+	sync ();
+
+	return length;
+}
+
+  /*
+   * Test routines
+   */
+
+static void packet_fill (char *packet, int length)
+{
+	char c = (char) length;
+	int i;
+
+	/* set up ethernet header */
+	memset (packet, 0xff, 14);
+
+	for (i = 14; i < length; i++) {
+		packet[i] = c++;
+	}
+}
+
+static int packet_check (char *packet, int length)
+{
+	char c = (char) length;
+	int i;
+
+	for (i = 14; i < length; i++) {
+		if (packet[i] != c++)
+			return -1;
+	}
+
+	return 0;
+}
+
+	char packet_send[MAX_PACKET_LENGTH];
+	char packet_recv[MAX_PACKET_LENGTH];
+static int test_ctlr (int devnum, int hw_addr)
+{
+	int res = -1;
+	int length;
+	int l;
+
+	ether_post_init (devnum, hw_addr);
+
+	for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH;
+	     l -= PACKET_INCR) {
+		packet_fill (packet_send, l);
+
+		ether_post_send (devnum, hw_addr, packet_send, l);
+
+		length = ether_post_recv (devnum, hw_addr, packet_recv,
+					  sizeof (packet_recv));
+
+		if (length != l || packet_check (packet_recv, length) < 0) {
+			goto Done;
+		}
+	}
+
+	res = 0;
+
+Done:
+
+	ether_post_halt (devnum, hw_addr);
+
+	if (res != 0) {
+		post_log ("EMAC%d test failed\n", devnum);
+	}
+
+	return res;
+}
+
+int ether_post_test (int flags)
+{
+	int res = 0;
+	int i;
+
+	/* Allocate tx & rx packet buffers */
+	tx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
+	rx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
+
+	if (!tx_buf || !rx_buf) {
+		printf ("Failed to allocate packet buffers\n");
+		res = -1;
+		goto out_free;
+	}
+
+	for (i = 0; i < LAST_EMAC_NUM; i++) {
+		if (test_ctlr (i, i*0x100))
+			res = -1;
+	}
+
+out_free:
+	free (tx_buf);
+	free (rx_buf);
+
+	return res;
+}
+
+#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */

u-boot/post/cpu/ppc4xx/fpu.c

@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Sergei Poselenov <sposelenov@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_440EP) || \
+    defined(CONFIG_440EPX)
+
+#include <asm/processor.h>
+#include <asm/ppc4xx.h>
+
+
+int fpu_status(void)
+{
+	if (mfspr(SPRN_CCR0) & CCR0_DAPUIB)
+		return 0; /* Disabled */
+	else
+		return 1; /* Enabled */
+}
+
+
+void fpu_disable(void)
+{
+	mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) | CCR0_DAPUIB);
+	mtmsr(mfmsr() & ~MSR_FP);
+}
+
+
+void fpu_enable(void)
+{
+	mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) & ~CCR0_DAPUIB);
+	mtmsr(mfmsr() | MSR_FP);
+}
+
+#endif

u-boot/post/cpu/ppc4xx/ocm.c

@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2008 Ilya Yanok, EmCraft Systems, yanok@emcraft.com
+ *
+ * Developed for DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+
+/*
+ * This test attempts to verify on-chip memory (OCM). Result is written
+ * to the scratch register and if test succeed it won't be run till next
+ * power on.
+ */
+
+#include <post.h>
+
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OCM_TEST_PATTERN1	0x55555555
+#define OCM_TEST_PATTERN2	0xAAAAAAAA
+
+#if CONFIG_POST & CONFIG_SYS_POST_OCM
+
+static uint ocm_status_read(void)
+{
+	return in_be32((void *)CONFIG_SYS_OCM_STATUS_ADDR) &
+		CONFIG_SYS_OCM_STATUS_MASK;
+}
+
+static void ocm_status_write(uint value)
+{
+	out_be32((void *)CONFIG_SYS_OCM_STATUS_ADDR, value |
+		(in_be32((void *)CONFIG_SYS_OCM_STATUS_ADDR) &
+			~CONFIG_SYS_OCM_STATUS_MASK));
+}
+
+static inline int ocm_test_word(uint value, uint *address)
+{
+	uint read_value;
+
+	*address = value;
+	sync();
+	read_value = *address;
+
+	return (read_value != value);
+}
+
+int ocm_post_test(int flags)
+{
+	uint   old_value;
+	int    ret = 0;
+	uint  *address = (uint*)CONFIG_SYS_OCM_BASE;
+
+	if (ocm_status_read() == CONFIG_SYS_OCM_STATUS_OK)
+		return 0;
+	for (; address < (uint*)(CONFIG_SYS_OCM_BASE + CONFIG_SYS_OCM_SIZE); address++) {
+		old_value = *address;
+		if (ocm_test_word(OCM_TEST_PATTERN1, address) ||
+				ocm_test_word(OCM_TEST_PATTERN2, address)) {
+			ret = 1;
+			*address = old_value;
+			printf("OCM POST failed at %p!\n", address);
+			break;
+		}
+		*address = old_value;
+	}
+	ocm_status_write(ret ? CONFIG_SYS_OCM_STATUS_FAIL : CONFIG_SYS_OCM_STATUS_OK);
+	return ret;
+}
+#endif /* CONFIG_POST & CONFIG_SYS_POST_OCM */

u-boot/post/cpu/ppc4xx/spr.c

@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+/*
+ * SPR test
+ *
+ * The test checks the contents of Special Purpose Registers (SPR) listed
+ * in the spr_test_list array below.
+ * Each SPR value is read using mfspr instruction, some bits are masked
+ * according to the table and the resulting value is compared to the
+ * corresponding table value.
+ */
+
+#include <post.h>
+
+#if CONFIG_POST & CONFIG_SYS_POST_SPR
+
+#include <asm/processor.h>
+
+#ifdef CONFIG_4xx_DCACHE
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+static struct {
+	int number;
+	char * name;
+	unsigned long mask;
+	unsigned long value;
+} spr_test_list [] = {
+	/* Standard Special-Purpose Registers */
+
+	{0x001,	"XER",		0x00000000,	0x00000000},
+	{0x008,	"LR",		0x00000000,	0x00000000},
+	{0x009,	"CTR",		0x00000000,	0x00000000},
+	{0x016,	"DEC",		0x00000000,	0x00000000},
+	{0x01a,	"SRR0",		0x00000000,	0x00000000},
+	{0x01b,	"SRR1",		0x00000000,	0x00000000},
+	{0x110,	"SPRG0",	0x00000000,	0x00000000},
+	{0x111,	"SPRG1",	0x00000000,	0x00000000},
+	{0x112,	"SPRG2",	0x00000000,	0x00000000},
+	{0x113,	"SPRG3",	0x00000000,	0x00000000},
+	{0x11f,	"PVR",		0x00000000,	0x00000000},
+
+	/* Additional Special-Purpose Registers.
+	 * The values must match the initialization
+	 * values from arch/powerpc/cpu/ppc4xx/start.S
+	 */
+	{0x30,	"PID",		0x00000000,	0x00000000},
+	{0x3a,	"CSRR0",	0x00000000,	0x00000000},
+	{0x3b,	"CSRR1",	0x00000000,	0x00000000},
+	{0x3d,	"DEAR",		0x00000000,	0x00000000},
+	{0x3e,	"ESR",		0x00000000,	0x00000000},
+#ifdef CONFIG_440
+	{0x3f,	"IVPR",		0xffff0000,	0x00000000},
+#endif
+	{0x100,	"USPRG0",	0x00000000,	0x00000000},
+	{0x104,	"SPRG4",	0x00000000,	0x00000000},
+	{0x105,	"SPRG5",	0x00000000,	0x00000000},
+	{0x106,	"SPRG6",	0x00000000,	0x00000000},
+	{0x107,	"SPRG7",	0x00000000,	0x00000000},
+	{0x10c,	"TBL",		0x00000000,	0x00000000},
+	{0x10d,	"TBU",		0x00000000,	0x00000000},
+#ifdef CONFIG_440
+	{0x11e,	"PIR",		0x0000000f,	0x00000000},
+#endif
+	{0x130,	"DBSR",		0x00000000,	0x00000000},
+	{0x134,	"DBCR0",	0x00000000,	0x00000000},
+	{0x135,	"DBCR1",	0x00000000,	0x00000000},
+	{0x136,	"DBCR2",	0x00000000,	0x00000000},
+	{0x138,	"IAC1",		0x00000000,	0x00000000},
+	{0x139,	"IAC2",		0x00000000,	0x00000000},
+	{0x13a,	"IAC3",		0x00000000,	0x00000000},
+	{0x13b,	"IAC4",		0x00000000,	0x00000000},
+	{0x13c,	"DAC1",		0x00000000,	0x00000000},
+	{0x13d,	"DAC2",		0x00000000,	0x00000000},
+	{0x13e,	"DVC1",		0x00000000,	0x00000000},
+	{0x13f,	"DVC2",		0x00000000,	0x00000000},
+	{0x150,	"TSR",		0x00000000,	0x00000000},
+	{0x154,	"TCR",		0x00000000,	0x00000000},
+#ifdef CONFIG_440
+	{0x190,	"IVOR0",	0x0000fff0,	0x00000100},
+	{0x191,	"IVOR1",	0x0000fff0,	0x00000200},
+	{0x192,	"IVOR2",	0x0000fff0,	0x00000300},
+	{0x193,	"IVOR3",	0x0000fff0,	0x00000400},
+	{0x194,	"IVOR4",	0x0000fff0,	0x00000500},
+	{0x195,	"IVOR5",	0x0000fff0,	0x00000600},
+	{0x196,	"IVOR6",	0x0000fff0,	0x00000700},
+	{0x197,	"IVOR7",	0x0000fff0,	0x00000800},
+	{0x198,	"IVOR8",	0x0000fff0,	0x00000c00},
+	{0x199,	"IVOR9",	0x00000000,	0x00000000},
+	{0x19a,	"IVOR10",	0x0000fff0,	0x00000900},
+	{0x19b,	"IVOR11",	0x00000000,	0x00000000},
+	{0x19c,	"IVOR12",	0x00000000,	0x00000000},
+	{0x19d,	"IVOR13",	0x0000fff0,	0x00001300},
+	{0x19e,	"IVOR14",	0x0000fff0,	0x00001400},
+	{0x19f,	"IVOR15",	0x0000fff0,	0x00002000},
+#endif
+	{0x23a,	"MCSRR0",	0x00000000,	0x00000000},
+	{0x23b,	"MCSRR1",	0x00000000,	0x00000000},
+	{0x23c,	"MCSR",		0x00000000,	0x00000000},
+	{0x370,	"INV0",		0x00000000,	0x00000000},
+	{0x371,	"INV1",		0x00000000,	0x00000000},
+	{0x372,	"INV2",		0x00000000,	0x00000000},
+	{0x373,	"INV3",		0x00000000,	0x00000000},
+	{0x374,	"ITV0",		0x00000000,	0x00000000},
+	{0x375,	"ITV1",		0x00000000,	0x00000000},
+	{0x376,	"ITV2",		0x00000000,	0x00000000},
+	{0x377,	"ITV3",		0x00000000,	0x00000000},
+	{0x378,	"CCR1",		0x00000000,	0x00000000},
+	{0x390,	"DNV0",		0x00000000,	0x00000000},
+	{0x391,	"DNV1",		0x00000000,	0x00000000},
+	{0x392,	"DNV2",		0x00000000,	0x00000000},
+	{0x393,	"DNV3",		0x00000000,	0x00000000},
+	{0x394,	"DTV0",		0x00000000,	0x00000000},
+	{0x395,	"DTV1",		0x00000000,	0x00000000},
+	{0x396,	"DTV2",		0x00000000,	0x00000000},
+	{0x397,	"DTV3",		0x00000000,	0x00000000},
+#ifdef CONFIG_440
+	{0x398,	"DVLIM",	0x0fc1f83f,	0x0001f800},
+	{0x399,	"IVLIM",	0x0fc1f83f,	0x0001f800},
+#endif
+	{0x39b,	"RSTCFG",	0x00000000,	0x00000000},
+	{0x39c,	"DCDBTRL",	0x00000000,	0x00000000},
+	{0x39d,	"DCDBTRH",	0x00000000,	0x00000000},
+	{0x39e,	"ICDBTRL",	0x00000000,	0x00000000},
+	{0x39f,	"ICDBTRH",	0x00000000,	0x00000000},
+	{0x3b2,	"MMUCR",	0x00000000,	0x00000000},
+	{0x3b3,	"CCR0",		0x00000000,	0x00000000},
+	{0x3d3,	"ICDBDR",	0x00000000,	0x00000000},
+	{0x3f3,	"DBDR",		0x00000000,	0x00000000},
+};
+
+static int spr_test_list_size = ARRAY_SIZE(spr_test_list);
+
+int spr_post_test (int flags)
+{
+	int ret = 0;
+	int i;
+
+	unsigned long code[] = {
+		0x7c6002a6,				/* mfspr r3,SPR */
+		0x4e800020				/* blr          */
+	};
+	unsigned long (*get_spr) (void) = (void *) code;
+
+#ifdef CONFIG_4xx_DCACHE
+	/* disable cache */
+	change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
+#endif
+	for (i = 0; i < spr_test_list_size; i++) {
+		int num = spr_test_list[i].number;
+
+		/* mfspr r3,num */
+		code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
+
+		asm volatile ("isync");
+
+		if ((get_spr () & spr_test_list[i].mask) !=
+			(spr_test_list[i].value & spr_test_list[i].mask)) {
+			post_log ("The value of %s special register "
+				  "is incorrect: 0x%08X\n",
+					spr_test_list[i].name, get_spr ());
+			ret = -1;
+		}
+	}
+#ifdef CONFIG_4xx_DCACHE
+	/* enable cache */
+	change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
+
+	return ret;
+}
+
+#endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */

u-boot/post/cpu/ppc4xx/uart.c

@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * Copyright 2010, Stefan Roese, DENX Software Engineering, sr@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <serial.h>
+
+/*
+ * UART test
+ *
+ * The controllers are configured to loopback mode and several
+ * characters are transmitted.
+ */
+
+#include <post.h>
+
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+
+/*
+ * This table defines the UART's that should be tested and can
+ * be overridden in the board config file
+ */
+#ifndef CONFIG_SYS_POST_UART_TABLE
+#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1, \
+			CONFIG_SYS_NS16550_COM2, CONFIG_SYS_NS16550_COM3, \
+			CONFIG_SYS_NS16550_COM4	}
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int test_ctlr (struct NS16550 *com_port, int index)
+{
+	int res = -1;
+	char test_str[] = "*** UART Test String ***\r\n";
+	int i;
+	int divisor;
+
+	divisor = (get_serial_clock() + (gd->baudrate * (16 / 2))) /
+		(16 * gd->baudrate);
+	NS16550_init(com_port, divisor);
+
+	/*
+	 * Set internal loopback mode in UART
+	 */
+	out_8(&com_port->mcr, in_8(&com_port->mcr) | UART_MCR_LOOP);
+
+	/* Reset FIFOs */
+	out_8(&com_port->fcr, UART_FCR_RXSR | UART_FCR_TXSR);
+	udelay(100);
+
+	/* Flush RX-FIFO */
+	while (NS16550_tstc(com_port))
+		NS16550_getc(com_port);
+
+	for (i = 0; i < sizeof (test_str) - 1; i++) {
+		NS16550_putc(com_port, test_str[i]);
+		if (NS16550_getc(com_port) != test_str[i])
+			goto done;
+	}
+	res = 0;
+done:
+	if (res)
+		post_log ("uart%d test failed\n", index);
+
+	return res;
+}
+
+int uart_post_test (int flags)
+{
+	int i, res = 0;
+	static unsigned long base[] = CONFIG_SYS_POST_UART_TABLE;
+
+	for (i = 0; i < ARRAY_SIZE(base); i++) {
+		if (test_ctlr((struct NS16550 *)base[i], i))
+			res = -1;
+	}
+	serial_reinit_all ();
+
+	return res;
+}
+
+#endif /* CONFIG_POST & CONFIG_SYS_POST_UART */

u-boot/post/cpu/ppc4xx/watchdog.c

@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+/*
+ * Watchdog test
+ *
+ * The test verifies the watchdog timer operation.
+ * On the first iteration, the test routine disables interrupts and
+ * makes a 10-second delay. If the system does not reboot during this delay,
+ * the watchdog timer is not operational and the test fails. If the system
+ * reboots, on the second iteration the test routine reports a success.
+ */
+
+#include <post.h>
+
+#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG
+
+#include <watchdog.h>
+
+int watchdog_post_test (int flags)
+{
+	if (flags & POST_REBOOT) {
+		/* Test passed */
+		return 0;
+	}
+	else {
+		/* 10-second delay */
+		int ints = disable_interrupts ();
+		ulong base = post_time_ms (0);
+
+		while (post_time_ms (base) < 10000)
+			;
+		if (ints)
+			enable_interrupts ();
+
+		/*
+		 * If we have reached this point, the watchdog timer
+		 * does not work
+		 */
+		return -1;
+	}
+}
+
+#endif /* CONFIG_POST & CONFIG_SYS_POST_WATCHDOG */