Kevin/Jibo-Platform-Tools-OLD
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

avionic design with actual uboot and tooling

Browse Source 
submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
u-boot/include/power/act8846_pmic.h Normal file
View File

@@ -0,0 +1,37 @@
/*
* Copyright (C) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PMIC_ACT8846_H_
#define _PMIC_ACT8846_H_
#include <asm/gpio.h>
#define ACT8846_NUM_OF_REGS 12
#define BUCK_VOL_MASK 0x3f
#define LDO_VOL_MASK 0x3f
#define BUCK_EN_MASK 0x80
#define LDO_EN_MASK 0x80
#define VOL_MIN_IDX 0x00
#define VOL_MAX_IDX 0x3f
struct act8846_reg_table {
char *name;
char reg_ctl;
char reg_vol;
};
struct pmic_act8846 {
struct pmic *pmic;
int node; /*device tree node*/
struct gpio_desc pwr_hold;
struct udevice *dev;
};
#endif

30
u-boot/include/power/as3722.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (C) 2014 NVIDIA Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __POWER_AS3722_H__
#define __POWER_AS3722_H__
#include <asm/types.h>
#define AS3722_GPIO_OUTPUT_VDDH (1 << 0)
#define AS3722_GPIO_INVERT (1 << 1)
struct udevice;
int as3722_init(struct udevice **devp, unsigned int bus, unsigned int address);
int as3722_sd_enable(struct udevice *pmic, unsigned int sd);
int as3722_sd_set_voltage(struct udevice *pmic, unsigned int sd, u8 value);
int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo);
int as3722_ldo_set_voltage(struct udevice *pmic, unsigned int ldo, u8 value);
int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
unsigned long flags);
int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio,
unsigned int level);
int as3722_read(struct udevice *pmic, u8 reg, u8 *value);
int as3722_write(struct udevice *pmic, u8 reg, u8 value);
int as3722_get(struct udevice **devp);
#endif /* __POWER_AS3722_H__ */

22
u-boot/include/power/battery.h Normal file
View File

@@ -0,0 +1,22 @@
/*
* Copyright (C) 2012 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __POWER_BATTERY_H_
#define __POWER_BATTERY_H_
struct battery {
unsigned int version;
unsigned int state_of_chrg;
unsigned int time_to_empty;
unsigned int capacity;
unsigned int voltage_uV;
unsigned int state;
};
int power_bat_init(unsigned char bus);
#endif /* __POWER_BATTERY_H_ */

74
u-boot/include/power/fg_battery_cell_params.h Normal file
View File

@@ -0,0 +1,74 @@
/*
* Copyright (C) 2012 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FG_BATTERY_CELL_PARAMS_H_
#define __FG_BATTERY_CELL_PARAMS_H_
#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TRATS)
/* Cell characteristics - Exynos4 TRATS development board */
/* Shall be written to addr 0x80h */
u16 cell_character0[16] = {
0xA2A0,
0xB6E0,
0xB850,
0xBAD0,
0xBB20,
0xBB70,
0xBBC0,
0xBC20,
0xBC80,
0xBCE0,
0xBD80,
0xBE20,
0xC090,
0xC420,
0xC910,
0xD070
};
/* Shall be written to addr 0x90h */
u16 cell_character1[16] = {
0x0090,
0x1A50,
0x02F0,
0x2060,
0x2060,
0x2E60,
0x26A0,
0x2DB0,
0x2DB0,
0x1870,
0x2A20,
0x16F0,
0x08F0,
0x0D40,
0x08C0,
0x08C0
};
/* Shall be written to addr 0xA0h */
u16 cell_character2[16] = {
0x0100,
0x0100,
0x0100,
0x0100,
0x0100,
0x0100,
0x0100,
0x0100,
0x0100,
0x0100,
0x0100,
0x0100,
0x0100,
0x0100,
0x0100,
0x0100
};
#endif
#endif /* __FG_BATTERY_CELL_PARAMS_H_ */

79
u-boot/include/power/hi6553_pmic.h Normal file
View File

@@ -0,0 +1,79 @@
/*
* (C) Copyright 2015 Linaro
* Peter Griffin <peter.griffin@linaro.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __HI6553_PMIC_H__
#define __HI6553_PMIC_H__
/* Registers */
enum {
HI6553_VERSION_REG = 0x000,
HI6553_ENABLE2_LDO1_8 = 0x029,
HI6553_DISABLE2_LDO1_8,
HI6553_ONOFF_STATUS2_LDO1_8,
HI6553_ENABLE3_LDO9_16,
HI6553_DISABLE3_LDO9_16,
HI6553_ONOFF_STATUS3_LDO9_16,
HI6553_DISABLE6_XO_CLK = 0x036,
HI6553_PERI_EN_MARK = 0x040,
HI6553_BUCK2_REG1 = 0x04a,
HI6553_BUCK2_REG5 = 0x04e,
HI6553_BUCK2_REG6,
HI6553_BUCK3_REG3 = 0x054,
HI6553_BUCK3_REG5 = 0x056,
HI6553_BUCK3_REG6,
HI6553_BUCK4_REG2 = 0x05b,
HI6553_BUCK4_REG5 = 0x05e,
HI6553_BUCK4_REG6,
HI6553_CLK_TOP0 = 0x063,
HI6553_CLK_TOP3 = 0x066,
HI6553_CLK_TOP4,
HI6553_VSET_BUCK2_ADJ = 0x06d,
HI6553_VSET_BUCK3_ADJ,
HI6553_LDO7_REG_ADJ = 0x078,
HI6553_LDO10_REG_ADJ = 0x07b,
HI6553_LDO19_REG_ADJ = 0x084,
HI6553_LDO20_REG_ADJ,
HI6553_DR_LED_CTRL = 0x098,
HI6553_DR_OUT_CTRL,
HI6553_DR3_ISET,
HI6553_DR3_START_DEL,
HI6553_DR4_ISET,
HI6553_DR4_START_DEL,
HI6553_DR345_TIM_CONF0 = 0x0a0,
HI6553_NP_REG_ADJ1 = 0x0be,
HI6553_NP_REG_CHG = 0x0c0,
HI6553_BUCK01_CTRL2 = 0x0d9,
HI6553_BUCK0_CTRL1 = 0x0dd,
HI6553_BUCK0_CTRL5 = 0x0e1,
HI6553_BUCK0_CTRL7 = 0x0e3,
HI6553_BUCK1_CTRL1 = 0x0e8,
HI6553_BUCK1_CTRL5 = 0x0ec,
HI6553_BUCK1_CTRL7 = 0x0ef,
HI6553_CLK19M2_600_586_EN = 0x0fe,
};
#define HI6553_DISABLE6_XO_CLK_BB (1 << 0)
#define HI6553_DISABLE6_XO_CLK_CONN (1 << 1)
#define HI6553_DISABLE6_XO_CLK_NFC (1 << 2)
#define HI6553_DISABLE6_XO_CLK_RF1 (1 << 3)
#define HI6553_DISABLE6_XO_CLK_RF2 (1 << 4)
#define HI6553_LED_START_DELAY_TIME 0x00
#define HI6553_LED_ELEC_VALUE 0x07
#define HI6553_LED_LIGHT_TIME 0xf0
#define HI6553_LED_GREEN_ENABLE (1 << 1)
#define HI6553_LED_OUT_CTRL 0x00
#define HI6553_PMU_V300 0x30
#define HI6553_PMU_V310 0x31
int power_hi6553_init(u8 *base);
#endif /* __HI6553_PMIC_H__ */

51
u-boot/include/power/ltc3676_pmic.h Normal file
View File

@@ -0,0 +1,51 @@
/*
* Copyright (C) 2014 Gateworks Corporation
* Tim Harvey <tharvey@gateworks.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LTC3676_PMIC_H_
#define __LTC3676_PMIC_H_
/* LTC3676 registers */
enum {
LTC3676_BUCK1 = 0x01,
LTC3676_BUCK2 = 0x02,
LTC3676_BUCK3 = 0x03,
LTC3676_BUCK4 = 0x04,
LTC3676_LDOA = 0x05,
LTC3676_LDOB = 0x06,
LTC3676_SQD1 = 0x07,
LTC3676_SQD2 = 0x08,
LTC3676_CNTRL = 0x09,
LTC3676_DVB1A = 0x0A,
LTC3676_DVB1B = 0x0B,
LTC3676_DVB2A = 0x0C,
LTC3676_DVB2B = 0x0D,
LTC3676_DVB3A = 0x0E,
LTC3676_DVB3B = 0x0F,
LTC3676_DVB4A = 0x10,
LTC3676_DVB4B = 0x11,
LTC3676_MSKIRQ = 0x12,
LTC3676_MSKPG = 0x13,
LTC3676_USER = 0x14,
LTC3676_HRST = 0x1E,
LTC3676_CLIRQ = 0x1F,
LTC3676_IRQSTAT = 0x15,
LTC3676_PGSTATL = 0x16,
LTC3676_PGSTATR = 0x17,
LTC3676_NUM_OF_REGS = 0x20,
};
/*
* SW Configuration
*/
#define LTC3676_DVB_MASK 0x1f
#define LTC3676_PGOOD_MASK (1<<5)
#define LTC3676_REF_SELA (0<<5)
#define LTC3676_REF_SELB (1<<5)
int power_ltc3676_init(unsigned char bus);
#endif

58
u-boot/include/power/max17042_fg.h Normal file
View File

@@ -0,0 +1,58 @@
/*
* Copyright (C) 2012 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MAX17042_FG_H_
#define __MAX17042_FG_H_
/* MAX 17042 registers */
enum {
MAX17042_STATUS = 0x00,
MAX17042_SOCREP = 0x06,
MAX17042_VCELL = 0x09,
MAX17042_CURRENT = 0x0A,
MAX17042_AVG_CURRENT = 0x0B,
MAX17042_SOCMIX = 0x0D,
MAX17042_SOCAV = 0x0E,
MAX17042_DESIGN_CAP = 0x18,
MAX17042_AVG_VCELL = 0x19,
MAX17042_CONFIG = 0x1D,
MAX17042_VERSION = 0x21,
MAX17042_LEARNCFG = 0x28,
MAX17042_FILTERCFG = 0x29,
MAX17042_RELAXCFG = 0x2A,
MAX17042_MISCCFG = 0x2B,
MAX17042_CGAIN = 0x2E,
MAX17042_COFF = 0x2F,
MAX17042_RCOMP0 = 0x38,
MAX17042_TEMPCO = 0x39,
MAX17042_FSTAT = 0x3D,
MAX17042_MLOCKReg1 = 0x62,
MAX17042_MLOCKReg2 = 0x63,
MAX17042_MODEL1 = 0x80,
MAX17042_MODEL2 = 0x90,
MAX17042_MODEL3 = 0xA0,
MAX17042_VFOCV = 0xFB,
MAX17042_VFSOC = 0xFF,
FG_NUM_OF_REGS = 0x100,
};
#define RCOMP0 0x0060
#define TempCo 0x1015
#define MAX17042_POR (1 << 1)
#define MODEL_UNLOCK1 0x0059
#define MODEL_UNLOCK2 0x00c4
#define MODEL_LOCK1 0x0000
#define MODEL_LOCK2 0x0000
#define MAX17042_I2C_ADDR (0x6C >> 1)
int power_fg_init(unsigned char bus);
#endif /* __MAX17042_FG_H_ */

228
u-boot/include/power/max77686_pmic.h Normal file
View File

@@ -0,0 +1,228 @@
/*
* Copyright (C) 2012 Samsung Electronics
* Rajeshwari Shinde <rajeshwari.s@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MAX77686_H_
#define __MAX77686_H_
#include <power/pmic.h>
enum {
MAX77686_REG_PMIC_ID = 0x0,
MAX77686_REG_PMIC_INTSRC,
MAX77686_REG_PMIC_INT1,
MAX77686_REG_PMIC_INT2,
MAX77686_REG_PMIC_INT1MSK,
MAX77686_REG_PMIC_INT2MSK,
MAX77686_REG_PMIC_STATUS1,
MAX77686_REG_PMIC_STATUS2,
MAX77686_REG_PMIC_PWRON,
MAX77686_REG_PMIC_ONOFFDELAY,
MAX77686_REG_PMIC_MRSTB,
MAX77686_REG_PMIC_BUCK1CRTL = 0x10,
MAX77686_REG_PMIC_BUCK1OUT,
MAX77686_REG_PMIC_BUCK2CTRL1,
MAX77686_REG_PMIC_BUCK234FREQ,
MAX77686_REG_PMIC_BUCK2DVS1,
MAX77686_REG_PMIC_BUCK2DVS2,
MAX77686_REG_PMIC_BUCK2DVS3,
MAX77686_REG_PMIC_BUCK2DVS4,
MAX77686_REG_PMIC_BUCK2DVS5,
MAX77686_REG_PMIC_BUCK2DVS6,
MAX77686_REG_PMIC_BUCK2DVS7,
MAX77686_REG_PMIC_BUCK2DVS8,
MAX77686_REG_PMIC_BUCK3CTRL,
MAX77686_REG_PMIC_BUCK3DVS1 = 0x1e,
MAX77686_REG_PMIC_BUCK3DVS2,
MAX77686_REG_PMIC_BUCK3DVS3,
MAX77686_REG_PMIC_BUCK3DVS4,
MAX77686_REG_PMIC_BUCK3DVS5,
MAX77686_REG_PMIC_BUCK3DVS6,
MAX77686_REG_PMIC_BUCK3DVS7,
MAX77686_REG_PMIC_BUCK3DVS8,
MAX77686_REG_PMIC_BUCK4CTRL1,
MAX77686_REG_PMIC_BUCK4DVS1 = 0x28,
MAX77686_REG_PMIC_BUCK4DVS2,
MAX77686_REG_PMIC_BUCK4DVS3,
MAX77686_REG_PMIC_BUCK4DVS4,
MAX77686_REG_PMIC_BUCK4DVS5,
MAX77686_REG_PMIC_BUCK4DVS6,
MAX77686_REG_PMIC_BUCK4DVS7,
MAX77686_REG_PMIC_BUCK4DVS8,
MAX77686_REG_PMIC_BUCK5CTRL,
MAX77686_REG_PMIC_BUCK5OUT,
MAX77686_REG_PMIC_BUCK6CRTL,
MAX77686_REG_PMIC_BUCK6OUT,
MAX77686_REG_PMIC_BUCK7CRTL,
MAX77686_REG_PMIC_BUCK7OUT,
MAX77686_REG_PMIC_BUCK8CRTL,
MAX77686_REG_PMIC_BUCK8OUT,
MAX77686_REG_PMIC_BUCK9CRTL,
MAX77686_REG_PMIC_BUCK9OUT,
MAX77686_REG_PMIC_LDO1CTRL1 = 0x40,
MAX77686_REG_PMIC_LDO2CTRL1,
MAX77686_REG_PMIC_LDO3CTRL1,
MAX77686_REG_PMIC_LDO4CTRL1,
MAX77686_REG_PMIC_LDO5CTRL1,
MAX77686_REG_PMIC_LDO6CTRL1,
MAX77686_REG_PMIC_LDO7CTRL1,
MAX77686_REG_PMIC_LDO8CTRL1,
MAX77686_REG_PMIC_LDO9CTRL1,
MAX77686_REG_PMIC_LDO10CTRL1,
MAX77686_REG_PMIC_LDO11CTRL1,
MAX77686_REG_PMIC_LDO12CTRL1,
MAX77686_REG_PMIC_LDO13CTRL1,
MAX77686_REG_PMIC_LDO14CTRL1,
MAX77686_REG_PMIC_LDO15CTRL1,
MAX77686_REG_PMIC_LDO16CTRL1,
MAX77686_REG_PMIC_LDO17CTRL1,
MAX77686_REG_PMIC_LDO18CTRL1,
MAX77686_REG_PMIC_LDO19CTRL1,
MAX77686_REG_PMIC_LDO20CTRL1,
MAX77686_REG_PMIC_LDO21CTRL1,
MAX77686_REG_PMIC_LDO22CTRL1,
MAX77686_REG_PMIC_LDO23CTRL1,
MAX77686_REG_PMIC_LDO24CTRL1,
MAX77686_REG_PMIC_LDO25CTRL1,
MAX77686_REG_PMIC_LDO26CTRL1,
MAX77686_REG_PMIC_LDO1CTRL2,
MAX77686_REG_PMIC_LDO2CTRL2,
MAX77686_REG_PMIC_LDO3CTRL2,
MAX77686_REG_PMIC_LDO4CTRL2,
MAX77686_REG_PMIC_LDO5CTRL2,
MAX77686_REG_PMIC_LDO6CTRL2,
MAX77686_REG_PMIC_LDO7CTRL2,
MAX77686_REG_PMIC_LDO8CTRL2,
MAX77686_REG_PMIC_LDO9CTRL2,
MAX77686_REG_PMIC_LDO10CTRL2,
MAX77686_REG_PMIC_LDO11CTRL2,
MAX77686_REG_PMIC_LDO12CTRL2,
MAX77686_REG_PMIC_LDO13CTRL2,
MAX77686_REG_PMIC_LDO14CTRL2,
MAX77686_REG_PMIC_LDO15CTRL2,
MAX77686_REG_PMIC_LDO16CTRL2,
MAX77686_REG_PMIC_LDO17CTRL2,
MAX77686_REG_PMIC_LDO18CTRL2,
MAX77686_REG_PMIC_LDO19CTRL2,
MAX77686_REG_PMIC_LDO20CTRL2,
MAX77686_REG_PMIC_LDO21CTRL2,
MAX77686_REG_PMIC_LDO22CTRL2,
MAX77686_REG_PMIC_LDO23CTRL2,
MAX77686_REG_PMIC_LDO24CTRL2,
MAX77686_REG_PMIC_LDO25CTRL2,
MAX77686_REG_PMIC_LDO26CTRL2,
MAX77686_REG_PMIC_BBAT = 0x7e,
MAX77686_REG_PMIC_32KHZ,
MAX77686_NUM_OF_REGS,
};
/* I2C device address for pmic max77686 */
#define MAX77686_I2C_ADDR (0x12 >> 1)
#define MAX77686_LDO_NUM 26
#define MAX77686_BUCK_NUM 9
/* Drivers name */
#define MAX77686_LDO_DRIVER "max77686_ldo"
#define MAX77686_BUCK_DRIVER "max77686_buck"
enum {
REG_DISABLE = 0,
REG_ENABLE
};
enum {
LDO_OFF = 0,
LDO_ON,
DIS_LDO = (0x00 << 6),
EN_LDO = (0x3 << 6),
};
enum {
OPMODE_OFF = 0,
OPMODE_LPM,
OPMODE_STANDBY,
OPMODE_STANDBY_LPM,
OPMODE_ON,
};
#ifdef CONFIG_POWER
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
#endif
#define MAX77686_LDO_VOLT_MAX_HEX 0x3f
#define MAX77686_LDO_VOLT_MASK 0x3f
#define MAX77686_LDO_MODE_MASK 0xc0
#define MAX77686_LDO_MODE_OFF (0x00 << 0x06)
#define MAX77686_LDO_MODE_LPM (0x01 << 0x06)
#define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06)
#define MAX77686_LDO_MODE_STANDBY_LPM (0x02 << 0x06)
#define MAX77686_LDO_MODE_ON (0x03 << 0x06)
#define MAX77686_BUCK234_VOLT_MAX_HEX 0xff
#define MAX77686_BUCK234_VOLT_MASK 0xff
#define MAX77686_BUCK_VOLT_MAX_HEX 0x3f
#define MAX77686_BUCK_VOLT_MASK 0x3f
#define MAX77686_BUCK_MODE_MASK 0x03
#define MAX77686_BUCK_MODE_SHIFT_1 0x00
#define MAX77686_BUCK_MODE_SHIFT_2 0x04
#define MAX77686_BUCK_MODE_OFF 0x00
#define MAX77686_BUCK_MODE_STANDBY 0x01
#define MAX77686_BUCK_MODE_LPM 0x02
#define MAX77686_BUCK_MODE_ON 0x03
/* For regulator hex<->volt conversion */
#define MAX77686_LDO_UV_MIN 800000 /* Minimum LDO uV value */
#define MAX77686_LDO_UV_LSTEP 25000 /* uV lower value step */
#define MAX77686_LDO_UV_HSTEP 50000 /* uV higher value step */
#define MAX77686_BUCK_UV_LMIN 600000 /* Lower minimun BUCK value */
#define MAX77686_BUCK_UV_HMIN 750000 /* Higher minimun BUCK value */
#define MAX77686_BUCK_UV_LSTEP 12500 /* uV lower value step */
#define MAX77686_BUCK_UV_HSTEP 50000 /* uV higher value step */
/* Buck1 1 volt value */
#define MAX77686_BUCK1OUT_1V 0x5
/* Buck1 1.05 volt value */
#define MAX77686_BUCK1OUT_1_05V 0x6
#define MAX77686_BUCK1CTRL_EN (3 << 0)
/* Buck2 1.3 volt value */
#define MAX77686_BUCK2DVS1_1_3V 0x38
#define MAX77686_BUCK2CTRL_ON (1 << 4)
/* Buck3 1.0125 volt value */
#define MAX77686_BUCK3DVS1_1_0125V 0x21
#define MAX77686_BUCK3CTRL_ON (1 << 4)
/* Buck4 1.2 volt value */
#define MAX77686_BUCK4DVS1_1_2V 0x30
#define MAX77686_BUCK4CTRL_ON (1 << 4)
/* LDO2 1.5 volt value */
#define MAX77686_LD02CTRL1_1_5V 0x1c
/* LDO3 1.8 volt value */
#define MAX77686_LD03CTRL1_1_8V 0x14
/* LDO5 1.8 volt value */
#define MAX77686_LD05CTRL1_1_8V 0x14
/* LDO10 1.8 volt value */
#define MAX77686_LD10CTRL1_1_8V 0x14
/*
* MAX77686_REG_PMIC_32KHZ set to 32KH CP
* output is activated
*/
#define MAX77686_32KHCP_EN (1 << 1)
/*
* MAX77686_REG_PMIC_BBAT set to
* Back up batery charger on and
* limit voltage setting to 3.5v
*/
#define MAX77686_BBCHOSTEN (1 << 0)
#define MAX77686_BBCVS_3_5V (3 << 3)
#endif /* __MAX77686_PMIC_H_ */

49
u-boot/include/power/max77693_fg.h Normal file
View File

@@ -0,0 +1,49 @@
/*
* Copyright (C) 2013 Samsung Electronics
* Piotr Wilczek <p.wilczek@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MAX77693_FG_H_
#define __MAX77693_FG_H_
/* MAX 77693 registers */
enum {
MAX77693_STATUS = 0x00,
MAX77693_SOCREP = 0x06,
MAX77693_VCELL = 0x09,
MAX77693_CURRENT = 0x0A,
MAX77693_AVG_CURRENT = 0x0B,
MAX77693_SOCMIX = 0x0D,
MAX77693_SOCAV = 0x0E,
MAX77693_DESIGN_CAP = 0x18,
MAX77693_AVG_VCELL = 0x19,
MAX77693_CONFIG = 0x1D,
MAX77693_VERSION = 0x21,
MAX77693_LEARNCFG = 0x28,
MAX77693_FILTERCFG = 0x29,
MAX77693_RELAXCFG = 0x2A,
MAX77693_MISCCFG = 0x2B,
MAX77693_CGAIN = 0x2E,
MAX77693_COFF = 0x2F,
MAX77693_RCOMP0 = 0x38,
MAX77693_TEMPCO = 0x39,
MAX77693_FSTAT = 0x3D,
MAX77693_VFOCV = 0xEE,
MAX77693_VFSOC = 0xFF,
FG_NUM_OF_REGS = 0x100,
};
#define MAX77693_POR (1 << 1)
#define MODEL_UNLOCK1 0x0059
#define MODEL_UNLOCK2 0x00c4
#define MODEL_LOCK1 0x0000
#define MODEL_LOCK2 0x0000
#define MAX77693_FUEL_I2C_ADDR (0x6C >> 1)
int power_fg_init(unsigned char bus);
#endif /* __MAX77693_FG_H_ */

74
u-boot/include/power/max77693_muic.h Normal file
View File

@@ -0,0 +1,74 @@
/*
* Copyright (C) 2013 Samsung Electronics
* Piotr Wilczek <p.wilczek@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MAX77693_MUIC_H_
#define __MAX77693_MUIC_H_
#include <power/power_chrg.h>
/*
* MUIC REGISTER
*/
#define MAX77693_MUIC_PREFIX "max77693-muic:"
/* MAX77693_MUIC_STATUS1 */
#define MAX77693_MUIC_ADC_MASK 0x1F
/* MAX77693_MUIC_STATUS2 */
#define MAX77693_MUIC_CHG_NO 0x00
#define MAX77693_MUIC_CHG_USB 0x01
#define MAX77693_MUIC_CHG_USB_D 0x02
#define MAX77693_MUIC_CHG_TA 0x03
#define MAX77693_MUIC_CHG_TA_500 0x04
#define MAX77693_MUIC_CHG_TA_1A 0x05
#define MAX77693_MUIC_CHG_MASK 0x07
/* MAX77693_MUIC_CONTROL1 */
#define MAX77693_MUIC_CTRL1_DN1DP2 ((0x1 << 3) | 0x1)
#define MAX77693_MUIC_CTRL1_UT1UR2 ((0x3 << 3) | 0x3)
#define MAX77693_MUIC_CTRL1_ADN1ADP2 ((0x4 << 3) | 0x4)
#define MAX77693_MUIC_CTRL1_AUT1AUR2 ((0x5 << 3) | 0x5)
#define MAX77693_MUIC_CTRL1_MASK 0xC0
#define MUIC_PATH_USB 0
#define MUIC_PATH_UART 1
#define MUIC_PATH_CP 0
#define MUIC_PATH_AP 1
enum muic_path {
MUIC_PATH_USB_CP,
MUIC_PATH_USB_AP,
MUIC_PATH_UART_CP,
MUIC_PATH_UART_AP,
};
/* MAX 777693 MUIC registers */
enum {
MAX77693_MUIC_ID = 0x00,
MAX77693_MUIC_INT1 = 0x01,
MAX77693_MUIC_INT2 = 0x02,
MAX77693_MUIC_INT3 = 0x03,
MAX77693_MUIC_STATUS1 = 0x04,
MAX77693_MUIC_STATUS2 = 0x05,
MAX77693_MUIC_STATUS3 = 0x06,
MAX77693_MUIC_INTMASK1 = 0x07,
MAX77693_MUIC_INTMASK2 = 0x08,
MAX77693_MUIC_INTMASK3 = 0x09,
MAX77693_MUIC_CDETCTRL = 0x0A,
MAX77693_MUIC_CONTROL1 = 0x0C,
MAX77693_MUIC_CONTROL2 = 0x0D,
MAX77693_MUIC_CONTROL3 = 0x0E,
MUIC_NUM_OF_REGS = 0x0F,
};
#define MAX77693_MUIC_I2C_ADDR (0x4A >> 1)
int power_muic_init(unsigned int bus);
#endif /* __MAX77693_MUIC_H_ */

41
u-boot/include/power/max77693_pmic.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* Copyright (C) 2013 Samsung Electronics
* Piotr Wilczek <p.wilczek@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MAX77693_PMIC_H_
#define __MAX77693_PMIC_H_
#include <power/power_chrg.h>
#define CHARGER_MIN_CURRENT 200
#define CHARGER_MAX_CURRENT 2000
#define MAX77693_CHG_PREFIX "max77693-chg:"
/* Registers */
#define MAX77693_CHG_BASE 0xB0
#define MAX77693_CHG_INT_OK 0xB2
#define MAX77693_CHG_CNFG_00 0xB7
#define MAX77693_CHG_CNFG_02 0xB9
#define MAX77693_CHG_CNFG_06 0xBD
#define MAX77693_SAFEOUT 0xC6
#define PMIC_NUM_OF_REGS 0xC7
#define MAX77693_CHG_DETBAT (0x1 << 7) /* MAX77693_CHG_INT_OK */
#define MAX77693_CHG_MODE_ON 0x05 /* MAX77693_CHG_CNFG_00 */
#define MAX77693_CHG_CC 0x3F /* MAX77693_CHG_CNFG_02 */
#define MAX77693_CHG_LOCK (0x0 << 2) /* MAX77693_CHG_CNFG_06 */
#define MAX77693_CHG_UNLOCK (0x3 << 2) /* MAX77693_CHG_CNFG_06 */
#define MAX77693_ENSAFEOUT1 (1 << 6)
#define MAX77693_ENSAFEOUT2 (1 << 7)
#define MAX77693_PMIC_I2C_ADDR (0xCC >> 1)
int pmic_init_max77693(unsigned char bus);
#endif /* __MAX77693_PMIC_H_ */

60
u-boot/include/power/max77696_pmic.h Normal file
View File

@@ -0,0 +1,60 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Fabio Estevam <fabio.estevam@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MAX77696_PMIC_H__
#define __MAX77696_PMIC_H__
#define CONFIG_POWER_MAX77696_I2C_ADDR 0x3C
enum {
L01_CNFG1 = 0x43,
L01_CNFG2,
L02_CNFG1,
L02_CNFG2,
L03_CNFG1,
L03_CNFG2,
L04_CNFG1,
L04_CNFG2,
L05_CNFG1,
L05_CNFG2,
L06_CNFG1,
L06_CNFG2,
L07_CNFG1,
L07_CNFG2,
L08_CNFG1,
L08_CNFG2,
L09_CNFG1,
L09_CNFG2,
L10_CNFG1,
L10_CNFG2,
LDO_INT1,
LDO_INT2,
LDO_INT1M,
LDO_INT2M,
LDO_CNFG3,
SW1_CNTRL,
SW2_CNTRL,
SW3_CNTRL,
SW4_CNTRL,
EPDCNFG,
EPDINTS,
EPDINT,
EPDINTM,
EPDVCOM,
EPDVEE,
EPDVNEG,
EPDVPOS,
EPDVDDH,
EPDSEQ,
EPDOKINTS,
CID = 0x9c,
PMIC_NUM_OF_REGS,
};
int power_max77696_init(unsigned char bus);
#endif

45
u-boot/include/power/max8997_muic.h Normal file
View File

@@ -0,0 +1,45 @@
/*
* Copyright (C) 2012 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MAX8997_MUIC_H_
#define __MAX8997_MUIC_H_
#include <power/power_chrg.h>
/* MAX8997_MUIC_STATUS2 */
#define MAX8997_MUIC_CHG_NO 0x00
#define MAX8997_MUIC_CHG_USB 0x01
#define MAX8997_MUIC_CHG_USB_D 0x02
#define MAX8997_MUIC_CHG_TA 0x03
#define MAX8997_MUIC_CHG_TA_500 0x04
#define MAX8997_MUIC_CHG_TA_1A 0x05
#define MAX8997_MUIC_CHG_MASK 0x07
/* MAX 8997 MUIC registers */
enum {
MAX8997_MUIC_ID = 0x00,
MAX8997_MUIC_INT1 = 0x01,
MAX8997_MUIC_INT2 = 0x02,
MAX8997_MUIC_INT3 = 0x03,
MAX8997_MUIC_STATUS1 = 0x04,
MAX8997_MUIC_STATUS2 = 0x05,
MAX8997_MUIC_STATUS3 = 0x06,
MAX8997_MUIC_INTMASK1 = 0x07,
MAX8997_MUIC_INTMASK2 = 0x08,
MAX8997_MUIC_INTMASK3 = 0x09,
MAX8997_MUIC_CDETCTRL = 0x0A,
MAX8997_MUIC_CONTROL1 = 0x0C,
MAX8997_MUIC_CONTROL2 = 0x0D,
MAX8997_MUIC_CONTROL3 = 0x0E,
MUIC_NUM_OF_REGS = 0x0F,
};
#define MAX8997_MUIC_I2C_ADDR (0x4A >> 1)
int power_muic_init(unsigned int bus);
#endif /* __MAX8997_MUIC_H_ */

197
u-boot/include/power/max8997_pmic.h Normal file
View File

@@ -0,0 +1,197 @@
/*
* Copyright (C) 2011 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MAX8997_PMIC_H_
#define __MAX8997_PMIC_H_
/* MAX 8997 registers */
enum {
MAX8997_REG_PMIC_ID0 = 0x00,
MAX8997_REG_PMIC_ID1 = 0x01,
MAX8997_REG_INTSRC = 0x02,
MAX8997_REG_INT1 = 0x03,
MAX8997_REG_INT2 = 0x04,
MAX8997_REG_INT3 = 0x05,
MAX8997_REG_INT4 = 0x06,
MAX8997_REG_INT1MSK = 0x08,
MAX8997_REG_INT2MSK = 0x09,
MAX8997_REG_INT3MSK = 0x0a,
MAX8997_REG_INT4MSK = 0x0b,
MAX8997_REG_STATUS1 = 0x0d,
MAX8997_REG_STATUS2 = 0x0e,
MAX8997_REG_STATUS3 = 0x0f,
MAX8997_REG_STATUS4 = 0x10,
MAX8997_REG_MAINCON1 = 0x13,
MAX8997_REG_MAINCON2 = 0x14,
MAX8997_REG_BUCKRAMP = 0x15,
MAX8997_REG_BUCK1CTRL = 0x18,
MAX8997_REG_BUCK1DVS1 = 0x19,
MAX8997_REG_BUCK1DVS2 = 0x1a,
MAX8997_REG_BUCK1DVS3 = 0x1b,
MAX8997_REG_BUCK1DVS4 = 0x1c,
MAX8997_REG_BUCK1DVS5 = 0x1d,
MAX8997_REG_BUCK1DVS6 = 0x1e,
MAX8997_REG_BUCK1DVS7 = 0x1f,
MAX8997_REG_BUCK1DVS8 = 0x20,
MAX8997_REG_BUCK2CTRL = 0x21,
MAX8997_REG_BUCK2DVS1 = 0x22,
MAX8997_REG_BUCK2DVS2 = 0x23,
MAX8997_REG_BUCK2DVS3 = 0x24,
MAX8997_REG_BUCK2DVS4 = 0x25,
MAX8997_REG_BUCK2DVS5 = 0x26,
MAX8997_REG_BUCK2DVS6 = 0x27,
MAX8997_REG_BUCK2DVS7 = 0x28,
MAX8997_REG_BUCK2DVS8 = 0x29,
MAX8997_REG_BUCK3CTRL = 0x2a,
MAX8997_REG_BUCK3DVS = 0x2b,
MAX8997_REG_BUCK4CTRL = 0x2c,
MAX8997_REG_BUCK4DVS = 0x2d,
MAX8997_REG_BUCK5CTRL = 0x2e,
MAX8997_REG_BUCK5DVS1 = 0x2f,
MAX8997_REG_BUCK5DVS2 = 0x30,
MAX8997_REG_BUCK5DVS3 = 0x31,
MAX8997_REG_BUCK5DVS4 = 0x32,
MAX8997_REG_BUCK5DVS5 = 0x33,
MAX8997_REG_BUCK5DVS6 = 0x34,
MAX8997_REG_BUCK5DVS7 = 0x35,
MAX8997_REG_BUCK5DVS8 = 0x36,
MAX8997_REG_BUCK6CTRL = 0x37,
MAX8997_REG_BUCK6BPSKIPCTRL = 0x38,
MAX8997_REG_BUCK7CTRL = 0x39,
MAX8997_REG_BUCK7DVS = 0x3a,
MAX8997_REG_LDO1CTRL = 0x3b,
MAX8997_REG_LDO2CTRL = 0x3c,
MAX8997_REG_LDO3CTRL = 0x3d,
MAX8997_REG_LDO4CTRL = 0x3e,
MAX8997_REG_LDO5CTRL = 0x3f,
MAX8997_REG_LDO6CTRL = 0x40,
MAX8997_REG_LDO7CTRL = 0x41,
MAX8997_REG_LDO8CTRL = 0x42,
MAX8997_REG_LDO9CTRL = 0x43,
MAX8997_REG_LDO10CTRL = 0x44,
MAX8997_REG_LDO11CTRL = 0x45,
MAX8997_REG_LDO12CTRL = 0x46,
MAX8997_REG_LDO13CTRL = 0x47,
MAX8997_REG_LDO14CTRL = 0x48,
MAX8997_REG_LDO15CTRL = 0x49,
MAX8997_REG_LDO16CTRL = 0x4a,
MAX8997_REG_LDO17CTRL = 0x4b,
MAX8997_REG_LDO18CTRL = 0x4c,
MAX8997_REG_LDO21CTRL = 0x4d,
MAX8997_REG_MBCCTRL1 = 0x50,
MAX8997_REG_MBCCTRL2 = 0x51,
MAX8997_REG_MBCCTRL3 = 0x52,
MAX8997_REG_MBCCTRL4 = 0x53,
MAX8997_REG_MBCCTRL5 = 0x54,
MAX8997_REG_MBCCTRL6 = 0x55,
MAX8997_REG_OTPCGHCVS = 0x56,
MAX8997_REG_SAFEOUTCTRL = 0x5a,
MAX8997_REG_LBCNFG1 = 0x5e,
MAX8997_REG_LBCNFG2 = 0x5f,
MAX8997_REG_BBCCTRL = 0x60,
MAX8997_REG_FLASH1_CUR = 0x63, /* 0x63 ~ 0x6e for FLASH */
MAX8997_REG_FLASH2_CUR = 0x64,
MAX8997_REG_MOVIE_CUR = 0x65,
MAX8997_REG_GSMB_CUR = 0x66,
MAX8997_REG_BOOST_CNTL = 0x67,
MAX8997_REG_LEN_CNTL = 0x68,
MAX8997_REG_FLASH_CNTL = 0x69,
MAX8997_REG_WDT_CNTL = 0x6a,
MAX8997_REG_MAXFLASH1 = 0x6b,
MAX8997_REG_MAXFLASH2 = 0x6c,
MAX8997_REG_FLASHSTATUS = 0x6d,
MAX8997_REG_FLASHSTATUSMASK = 0x6e,
MAX8997_REG_GPIOCNTL1 = 0x70,
MAX8997_REG_GPIOCNTL2 = 0x71,
MAX8997_REG_GPIOCNTL3 = 0x72,
MAX8997_REG_GPIOCNTL4 = 0x73,
MAX8997_REG_GPIOCNTL5 = 0x74,
MAX8997_REG_GPIOCNTL6 = 0x75,
MAX8997_REG_GPIOCNTL7 = 0x76,
MAX8997_REG_GPIOCNTL8 = 0x77,
MAX8997_REG_GPIOCNTL9 = 0x78,
MAX8997_REG_GPIOCNTL10 = 0x79,
MAX8997_REG_GPIOCNTL11 = 0x7a,
MAX8997_REG_GPIOCNTL12 = 0x7b,
MAX8997_REG_LDO1CONFIG = 0x80,
MAX8997_REG_LDO2CONFIG = 0x81,
MAX8997_REG_LDO3CONFIG = 0x82,
MAX8997_REG_LDO4CONFIG = 0x83,
MAX8997_REG_LDO5CONFIG = 0x84,
MAX8997_REG_LDO6CONFIG = 0x85,
MAX8997_REG_LDO7CONFIG = 0x86,
MAX8997_REG_LDO8CONFIG = 0x87,
MAX8997_REG_LDO9CONFIG = 0x88,
MAX8997_REG_LDO10CONFIG = 0x89,
MAX8997_REG_LDO11CONFIG = 0x8a,
MAX8997_REG_LDO12CONFIG = 0x8b,
MAX8997_REG_LDO13CONFIG = 0x8c,
MAX8997_REG_LDO14CONFIG = 0x8d,
MAX8997_REG_LDO15CONFIG = 0x8e,
MAX8997_REG_LDO16CONFIG = 0x8f,
MAX8997_REG_LDO17CONFIG = 0x90,
MAX8997_REG_LDO18CONFIG = 0x91,
MAX8997_REG_LDO21CONFIG = 0x92,
MAX8997_REG_DVSOKTIMER1 = 0x97,
MAX8997_REG_DVSOKTIMER2 = 0x98,
MAX8997_REG_DVSOKTIMER4 = 0x99,
MAX8997_REG_DVSOKTIMER5 = 0x9a,
PMIC_NUM_OF_REGS = 0x9b,
};
#define ACTDISSAFEO1 (1 << 4)
#define ACTDISSAFEO2 (1 << 5)
#define ENSAFEOUT1 (1 << 6)
#define ENSAFEOUT2 (1 << 7)
#define ENBUCK (1 << 0)
#define ACTIVE_DISCHARGE (1 << 3)
#define GNSLCT (1 << 2)
#define LDO_ADE (1 << 1)
#define SAFEOUT_4_85V 0x00
#define SAFEOUT_4_90V 0x01
#define SAFEOUT_4_95V 0x02
#define SAFEOUT_3_30V 0x03
/* Charger */
#define DETBAT (1 << 2)
#define MBCICHFCSET (1 << 4)
#define MBCHOSTEN (1 << 6)
#define VCHGR_FC (1 << 7)
#define CHARGER_MIN_CURRENT 200
#define CHARGER_MAX_CURRENT 950
#define CHARGER_CURRENT_RESOLUTION 50
#define MAX8997_I2C_ADDR (0xCC >> 1)
#define MAX8997_RTC_ADDR (0x0C >> 1)
#define MAX8997_MUIC_ADDR (0x4A >> 1)
#define MAX8997_FG_ADDR (0x6C >> 1)
enum {
LDO_OFF = 0,
LDO_ON = 1,
DIS_LDO = (0x00 << 6),
EN_LDO = (0x3 << 6),
};
#define MAX8997_LDO_MAX_VAL 0x3F
unsigned char max8997_reg_ldo(int uV);
#endif /* __MAX8997_PMIC_H_ */

72
u-boot/include/power/max8998_pmic.h Normal file
View File

@@ -0,0 +1,72 @@
/*
* Copyright (C) 2011 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MAX8998_PMIC_H_
#define __MAX8998_PMIC_H_
/* MAX 8998 registers */
enum {
MAX8998_REG_IRQ1,
MAX8998_REG_IRQ2,
MAX8998_REG_IRQ3,
MAX8998_REG_IRQ4,
MAX8998_REG_IRQM1,
MAX8998_REG_IRQM2,
MAX8998_REG_IRQM3,
MAX8998_REG_IRQM4,
MAX8998_REG_STATUS1,
MAX8998_REG_STATUS2,
MAX8998_REG_STATUSM1,
MAX8998_REG_STATUSM2,
MAX8998_REG_CHGR1,
MAX8998_REG_CHGR2,
MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
MAX8998_REG_ONOFF1,
MAX8998_REG_ONOFF2,
MAX8998_REG_ONOFF3,
MAX8998_REG_ONOFF4,
MAX8998_REG_BUCK1_VOLTAGE1,
MAX8998_REG_BUCK1_VOLTAGE2,
MAX8998_REG_BUCK1_VOLTAGE3,
MAX8998_REG_BUCK1_VOLTAGE4,
MAX8998_REG_BUCK2_VOLTAGE1,
MAX8998_REG_BUCK2_VOLTAGE2,
MAX8998_REG_BUCK3,
MAX8998_REG_BUCK4,
MAX8998_REG_LDO2_LDO3,
MAX8998_REG_LDO4,
MAX8998_REG_LDO5,
MAX8998_REG_LDO6,
MAX8998_REG_LDO7,
MAX8998_REG_LDO8_LDO9,
MAX8998_REG_LDO10_LDO11,
MAX8998_REG_LDO12,
MAX8998_REG_LDO13,
MAX8998_REG_LDO14,
MAX8998_REG_LDO15,
MAX8998_REG_LDO16,
MAX8998_REG_LDO17,
MAX8998_REG_BKCHR,
MAX8998_REG_LBCNFG1,
MAX8998_REG_LBCNFG2,
PMIC_NUM_OF_REGS,
};
#define MAX8998_LDO3 (1 << 2)
#define MAX8998_LDO4 (1 << 1)
#define MAX8998_LDO7 (1 << 6)
#define MAX8998_LDO8 (1 << 5)
#define MAX8998_LDO17 (1 << 4)
#define MAX8998_SAFEOUT1 (1 << 4)
#define MAX8998_I2C_ADDR (0xCC >> 1)
enum { LDO_OFF, LDO_ON };
#endif /* __MAX8998_PMIC_H_ */

259
u-boot/include/power/pfuze100_pmic.h Normal file
View File

@@ -0,0 +1,259 @@
/*
* Copyright (C) 2014 Gateworks Corporation
* Tim Harvey <tharvey@gateworks.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PFUZE100_PMIC_H_
#define __PFUZE100_PMIC_H_
/* Device ID */
enum {PFUZE100 = 0x10, PFUZE200 = 0x11, PFUZE3000 = 0x30};
#define PFUZE100_REGULATOR_DRIVER "pfuze100_regulator"
/* PFUZE100 registers */
enum {
PFUZE100_DEVICEID = 0x00,
PFUZE100_REVID = 0x03,
PFUZE100_FABID = 0x04,
PFUZE100_SW1ABVOL = 0x20,
PFUZE100_SW1ABSTBY = 0x21,
PFUZE100_SW1ABOFF = 0x22,
PFUZE100_SW1ABMODE = 0x23,
PFUZE100_SW1ABCONF = 0x24,
PFUZE100_SW1CVOL = 0x2e,
PFUZE100_SW1CSTBY = 0x2f,
PFUZE100_SW1COFF = 0x30,
PFUZE100_SW1CMODE = 0x31,
PFUZE100_SW1CCONF = 0x32,
PFUZE100_SW2VOL = 0x35,
PFUZE100_SW2STBY = 0x36,
PFUZE100_SW2OFF = 0x37,
PFUZE100_SW2MODE = 0x38,
PFUZE100_SW2CONF = 0x39,
PFUZE100_SW3AVOL = 0x3c,
PFUZE100_SW3ASTBY = 0x3D,
PFUZE100_SW3AOFF = 0x3E,
PFUZE100_SW3AMODE = 0x3F,
PFUZE100_SW3ACONF = 0x40,
PFUZE100_SW3BVOL = 0x43,
PFUZE100_SW3BSTBY = 0x44,
PFUZE100_SW3BOFF = 0x45,
PFUZE100_SW3BMODE = 0x46,
PFUZE100_SW3BCONF = 0x47,
PFUZE100_SW4VOL = 0x4a,
PFUZE100_SW4STBY = 0x4b,
PFUZE100_SW4OFF = 0x4c,
PFUZE100_SW4MODE = 0x4d,
PFUZE100_SW4CONF = 0x4e,
PFUZE100_SWBSTCON1 = 0x66,
PFUZE100_VREFDDRCON = 0x6a,
PFUZE100_VSNVSVOL = 0x6b,
PFUZE100_VGEN1VOL = 0x6c,
PFUZE100_VGEN2VOL = 0x6d,
PFUZE100_VGEN3VOL = 0x6e,
PFUZE100_VGEN4VOL = 0x6f,
PFUZE100_VGEN5VOL = 0x70,
PFUZE100_VGEN6VOL = 0x71,
PFUZE100_NUM_OF_REGS = 0x7f,
};
/* Registor offset based on VOLT register */
#define PFUZE100_VOL_OFFSET 0
#define PFUZE100_STBY_OFFSET 1
#define PFUZE100_OFF_OFFSET 2
#define PFUZE100_MODE_OFFSET 3
#define PFUZE100_CONF_OFFSET 4
/*
* Buck Regulators
*/
#define PFUZE100_SW1ABC_SETP(x) ((x - 3000) / 250)
/* SW1A/B/C Output Voltage Configuration */
#define SW1x_0_300V 0
#define SW1x_0_325V 1
#define SW1x_0_350V 2
#define SW1x_0_375V 3
#define SW1x_0_400V 4
#define SW1x_0_425V 5
#define SW1x_0_450V 6
#define SW1x_0_475V 7
#define SW1x_0_500V 8
#define SW1x_0_525V 9
#define SW1x_0_550V 10
#define SW1x_0_575V 11
#define SW1x_0_600V 12
#define SW1x_0_625V 13
#define SW1x_0_650V 14
#define SW1x_0_675V 15
#define SW1x_0_700V 16
#define SW1x_0_725V 17
#define SW1x_0_750V 18
#define SW1x_0_775V 19
#define SW1x_0_800V 20
#define SW1x_0_825V 21
#define SW1x_0_850V 22
#define SW1x_0_875V 23
#define SW1x_0_900V 24
#define SW1x_0_925V 25
#define SW1x_0_950V 26
#define SW1x_0_975V 27
#define SW1x_1_000V 28
#define SW1x_1_025V 29
#define SW1x_1_050V 30
#define SW1x_1_075V 31
#define SW1x_1_100V 32
#define SW1x_1_125V 33
#define SW1x_1_150V 34
#define SW1x_1_175V 35
#define SW1x_1_200V 36
#define SW1x_1_225V 37
#define SW1x_1_250V 38
#define SW1x_1_275V 39
#define SW1x_1_300V 40
#define SW1x_1_325V 41
#define SW1x_1_350V 42
#define SW1x_1_375V 43
#define SW1x_1_400V 44
#define SW1x_1_425V 45
#define SW1x_1_450V 46
#define SW1x_1_475V 47
#define SW1x_1_500V 48
#define SW1x_1_525V 49
#define SW1x_1_550V 50
#define SW1x_1_575V 51
#define SW1x_1_600V 52
#define SW1x_1_625V 53
#define SW1x_1_650V 54
#define SW1x_1_675V 55
#define SW1x_1_700V 56
#define SW1x_1_725V 57
#define SW1x_1_750V 58
#define SW1x_1_775V 59
#define SW1x_1_800V 60
#define SW1x_1_825V 61
#define SW1x_1_850V 62
#define SW1x_1_875V 63
#define SW1x_NORMAL_MASK 0x3f
#define SW1x_STBY_MASK 0x3f
#define SW1x_OFF_MASK 0x3f
#define SW_MODE_MASK 0xf
#define SW_MODE_SHIFT 0
#define SW1xCONF_DVSSPEED_MASK 0xc0
#define SW1xCONF_DVSSPEED_2US 0x00
#define SW1xCONF_DVSSPEED_4US 0x40
#define SW1xCONF_DVSSPEED_8US 0x80
#define SW1xCONF_DVSSPEED_16US 0xc0
/*
* LDO Configuration
*/
/* VGEN1/2 Voltage Configuration */
#define LDOA_0_80V 0
#define LDOA_0_85V 1
#define LDOA_0_90V 2
#define LDOA_0_95V 3
#define LDOA_1_00V 4
#define LDOA_1_05V 5
#define LDOA_1_10V 6
#define LDOA_1_15V 7
#define LDOA_1_20V 8
#define LDOA_1_25V 9
#define LDOA_1_30V 10
#define LDOA_1_35V 11
#define LDOA_1_40V 12
#define LDOA_1_45V 13
#define LDOA_1_50V 14
#define LDOA_1_55V 15
/* VGEN3/4/5/6 Voltage Configuration */
#define LDOB_1_80V 0
#define LDOB_1_90V 1
#define LDOB_2_00V 2
#define LDOB_2_10V 3
#define LDOB_2_20V 4
#define LDOB_2_30V 5
#define LDOB_2_40V 6
#define LDOB_2_50V 7
#define LDOB_2_60V 8
#define LDOB_2_70V 9
#define LDOB_2_80V 10
#define LDOB_2_90V 11
#define LDOB_3_00V 12
#define LDOB_3_10V 13
#define LDOB_3_20V 14
#define LDOB_3_30V 15
#define LDO_VOL_MASK 0xf
#define LDO_EN (1 << 4)
#define LDO_MODE_SHIFT 4
#define LDO_MODE_MASK (1 << 4)
#define LDO_MODE_OFF 0
#define LDO_MODE_ON 1
#define VREFDDRCON_EN (1 << 4)
/*
* Boost Regulator
*/
/* SWBST Output Voltage */
#define SWBST_5_00V 0
#define SWBST_5_05V 1
#define SWBST_5_10V 2
#define SWBST_5_15V 3
#define SWBST_VOL_MASK 0x3
#define SWBST_MODE_MASK 0xC
#define SWBST_MODE_SHIFT 0x2
#define SWBST_MODE_OFF 0
#define SWBST_MODE_PFM 1
#define SWBST_MODE_AUTO 2
#define SWBST_MODE_APS 3
/*
* Regulator Mode Control
*
* OFF: The regulator is switched off and the output voltage is discharged.
* PFM: In this mode, the regulator is always in PFM mode, which is useful
* at light loads for optimized efficiency.
* PWM: In this mode, the regulator is always in PWM mode operation
* regardless of load conditions.
* APS: In this mode, the regulator moves automatically between pulse
* skipping mode and PWM mode depending on load conditions.
*
* SWxMODE[3:0]
* Normal Mode | Standby Mode | value
* OFF OFF 0x0
* PWM OFF 0x1
* PFM OFF 0x3
* APS OFF 0x4
* PWM PWM 0x5
* PWM APS 0x6
* APS APS 0x8
* APS PFM 0xc
* PWM PFM 0xd
*/
#define OFF_OFF 0x0
#define PWM_OFF 0x1
#define PFM_OFF 0x3
#define APS_OFF 0x4
#define PWM_PWM 0x5
#define PWM_APS 0x6
#define APS_APS 0x8
#define APS_PFM 0xc
#define PWM_PFM 0xd
#define SWITCH_SIZE 0x7
int power_pfuze100_init(unsigned char bus);
#endif

78
u-boot/include/power/pfuze3000_pmic.h Normal file
View File

@@ -0,0 +1,78 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc
* Peng Fan <Peng.Fan@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PFUZE3000_PMIC_H_
#define __PFUZE3000_PMIC_H_
/* PFUZE3000 registers */
enum {
PFUZE3000_DEVICEID = 0x00,
PFUZE3000_REVID = 0x03,
PFUZE3000_FABID = 0x04,
PFUZE3000_INTSTAT0 = 0x05,
PFUZE3000_INTMASK0 = 0x06,
PFUZE3000_INTSENSE0 = 0x07,
PFUZE3000_INTSTAT1 = 0x08,
PFUZE3000_INTMASK1 = 0x09,
PFUZE3000_INTSENSE1 = 0x0A,
PFUZE3000_INTSTAT3 = 0x0E,
PFUZE3000_INTMASK3 = 0x0F,
PFUZE3000_INTSENSE3 = 0x10,
PFUZE3000_INTSTAT4 = 0x11,
PFUZE3000_INTMASK4 = 0x12,
PFUZE3000_INTSENSE4 = 0x13,
PFUZE3000_COINCTL = 0x1A,
PFUZE3000_PWRCTL = 0x1B,
PFUZE3000_MEMA = 0x1C,
PFUZE3000_MEMB = 0x1D,
PFUZE3000_MEMC = 0x1E,
PFUZE3000_MEMD = 0x1F,
PFUZE3000_SW1AVOLT = 0x20,
PFUZE3000_SW1ASTBY = 0x21,
PFUZE3000_SW1AOFF = 0x22,
PFUZE3000_SW1AMODE = 0x23,
PFUZE3000_SW1ACONF = 0x24,
PFUZE3000_SW1BVOLT = 0x2E,
PFUZE3000_SW1BSTBY = 0x2F,
PFUZE3000_SW1BOFF = 0x30,
PFUZE3000_SW1BMODE = 0x31,
PFUZE3000_SW1BCONF = 0x32,
PFUZE3000_SW2VOLT = 0x35,
PFUZE3000_SW2STBY = 0x36,
PFUZE3000_SW2OFF = 0x37,
PFUZE3000_SW2MODE = 0x38,
PFUZE3000_SW2CONF = 0x39,
PFUZE3000_SW3VOLT = 0x3C,
PFUZE3000_SW3STBY = 0x3D,
PFUZE3000_SW3OFF = 0x3E,
PFUZE3000_SW3MODE = 0x3F,
PFUZE3000_SW3CONF = 0x40,
PFUZE3000_SWBSTCTL = 0x66,
PFUZE3000_LDOGCTL = 0x69,
PFUZE3000_VREFDDRCTL = 0x6A,
PFUZE3000_VSNVSCTL = 0x6B,
PFUZE3000_VLDO1CTL = 0x6C,
PFUZE3000_VLDO2CTL = 0x6D,
PFUZE3000_VCC_SDCTL = 0x6E,
PFUZE3000_V33CTL = 0x6F,
PFUZE3000_VLDO3CTL = 0x70,
PFUZE3000_VLD4CTL = 0x71,
PMIC_NUM_OF_REGS = 0x7F,
};
int power_pfuze3000_init(unsigned char bus);
#endif

321
u-boot/include/power/pmic.h Normal file
View File

@@ -0,0 +1,321 @@
/*
* Copyright (C) 2014-2015 Samsung Electronics
* Przemyslaw Marczak <p.marczak@samsung.com>
*
* Copyright (C) 2011-2012 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CORE_PMIC_H_
#define __CORE_PMIC_H_
#include <i2c.h>
#include <linux/list.h>
#include <power/power_chrg.h>
enum { PMIC_I2C, PMIC_SPI, PMIC_NONE};
#ifdef CONFIG_POWER
enum { I2C_PMIC, I2C_NUM, };
enum { PMIC_READ, PMIC_WRITE, };
enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, };
enum {
PMIC_CHARGER_DISABLE,
PMIC_CHARGER_ENABLE,
};
struct p_i2c {
unsigned char addr;
unsigned char *buf;
unsigned char tx_num;
};
struct p_spi {
unsigned int cs;
unsigned int mode;
unsigned int bitlen;
unsigned int clk;
unsigned int flags;
u32 (*prepare_tx)(u32 reg, u32 *val, u32 write);
};
struct pmic;
struct power_fg {
int (*fg_battery_check) (struct pmic *p, struct pmic *bat);
int (*fg_battery_update) (struct pmic *p, struct pmic *bat);
};
struct power_chrg {
int (*chrg_type) (struct pmic *p);
int (*chrg_bat_present) (struct pmic *p);
int (*chrg_state) (struct pmic *p, int state, int current);
};
struct power_battery {
struct battery *bat;
int (*battery_init) (struct pmic *bat, struct pmic *p1,
struct pmic *p2, struct pmic *p3);
int (*battery_charge) (struct pmic *bat);
/* Keep info about power devices involved with battery operation */
struct pmic *chrg, *fg, *muic;
};
struct pmic {
const char *name;
unsigned char bus;
unsigned char interface;
unsigned char sensor_byte_order;
unsigned int number_of_regs;
union hw {
struct p_i2c i2c;
struct p_spi spi;
} hw;
void (*low_power_mode) (void);
struct power_battery *pbat;
struct power_chrg *chrg;
struct power_fg *fg;
struct pmic *parent;
struct list_head list;
};
#endif /* CONFIG_POWER */
#ifdef CONFIG_DM_PMIC
/**
* U-Boot PMIC Framework
* =====================
*
* UCLASS_PMIC - This is designed to provide an I/O interface for PMIC devices.
*
* For the multi-function PMIC devices, this can be used as parent I/O device
* for each IC's interface. Then, each child uses its parent for read/write.
*
* The driver model tree could look like this:
*
*_ root device
* |_ BUS 0 device (e.g. I2C0) - UCLASS_I2C/SPI/...
* | |_ PMIC device (READ/WRITE ops) - UCLASS_PMIC
* | |_ REGULATOR device (ldo/buck/... ops) - UCLASS_REGULATOR
* | |_ CHARGER device (charger ops) - UCLASS_CHARGER (in the future)
* | |_ MUIC device (microUSB connector ops) - UCLASS_MUIC (in the future)
* | |_ ...
* |
* |_ BUS 1 device (e.g. I2C1) - UCLASS_I2C/SPI/...
* |_ PMIC device (READ/WRITE ops) - UCLASS_PMIC
* |_ RTC device (rtc ops) - UCLASS_RTC (in the future)
*
* We can find two PMIC cases in boards design:
* - single I/O interface
* - multiple I/O interfaces
* We bind a single PMIC device for each interface, to provide an I/O for
* its child devices. And each child usually implements a different function,
* controlled by the same interface.
*
* The binding should be done automatically. If device tree nodes/subnodes are
* proper defined, then:
*
* |_ the ROOT driver will bind the device for I2C/SPI node:
* |_ the I2C/SPI driver should bind a device for pmic node:
* |_ the PMIC driver should bind devices for its childs:
* |_ regulator (child)
* |_ charger (child)
* |_ other (child)
*
* The same for other device nodes, for multi-interface PMIC.
*
* Note:
* Each PMIC interface driver should use a different compatible string.
*
* If a PMIC child device driver needs access the PMIC-specific registers,
* it need know only the register address and the access can be done through
* the parent pmic driver. Like in the example:
*
*_ root driver
* |_ dev: bus I2C0 - UCLASS_I2C
* | |_ dev: my_pmic (read/write) (is parent) - UCLASS_PMIC
* | |_ dev: my_regulator (set value/etc..) (is child) - UCLASS_REGULATOR
*
* To ensure such device relationship, the pmic device driver should also bind
* all its child devices, like in the example below. It can be done by calling
* the 'pmic_bind_children()' - please refer to the function description, which
* can be found in this header file. This function, should be called inside the
* driver's bind() method.
*
* For the example driver, please refer the MAX77686 driver:
* - 'drivers/power/pmic/max77686.c'
*/
/**
* struct dm_pmic_ops - PMIC device I/O interface
*
* Should be implemented by UCLASS_PMIC device drivers. The standard
* device operations provides the I/O interface for it's childs.
*
* @reg_count: device's register count
* @read: read 'len' bytes at "reg" and store it into the 'buffer'
* @write: write 'len' bytes from the 'buffer' to the register at 'reg' address
*/
struct dm_pmic_ops {
int (*reg_count)(struct udevice *dev);
int (*read)(struct udevice *dev, uint reg, uint8_t *buffer, int len);
int (*write)(struct udevice *dev, uint reg, const uint8_t *buffer,
int len);
};
/**
* enum pmic_op_type - used for various pmic devices operation calls,
* for reduce a number of lines with the same code for read/write or get/set.
*
* @PMIC_OP_GET - get operation
* @PMIC_OP_SET - set operation
*/
enum pmic_op_type {
PMIC_OP_GET,
PMIC_OP_SET,
};
/**
* struct pmic_child_info - basic device's child info for bind child nodes with
* the driver by the node name prefix and driver name. This is a helper struct
* for function: pmic_bind_children().
*
* @prefix - child node name prefix (or its name if is unique or single)
* @driver - driver name for the sub-node with prefix
*/
struct pmic_child_info {
const char *prefix;
const char *driver;
};
/* drivers/power/pmic-uclass.c */
/**
* pmic_bind_children() - bind drivers for given parent pmic, using child info
* found in 'child_info' array.
*
* @pmic - pmic device - the parent of found child's
* @child_info - N-childs info array
* @return a positive number of childs, or 0 if no child found (error)
*
* Note: For N-childs the child_info array should have N+1 entries and the last
* entry prefix should be NULL - the same as for drivers compatible.
*
* For example, a single prefix info (N=1):
* static const struct pmic_child_info bind_info[] = {
* { .prefix = "ldo", .driver = "ldo_driver" },
* { },
* };
*
* This function is useful for regulator sub-nodes:
* my_regulator@0xa {
* reg = <0xa>;
* (pmic - bind automatically by compatible)
* compatible = "my_pmic";
* ...
* (pmic's childs - bind by pmic_bind_children())
* (nodes prefix: "ldo", driver: "my_regulator_ldo")
* ldo1 { ... };
* ldo2 { ... };
*
* (nodes prefix: "buck", driver: "my_regulator_buck")
* buck1 { ... };
* buck2 { ... };
* };
*/
int pmic_bind_children(struct udevice *pmic, int offset,
const struct pmic_child_info *child_info);
/**
* pmic_get: get the pmic device using its name
*
* @name - device name
* @devp - returned pointer to the pmic device
* @return 0 on success or negative value of errno.
*
* The returned devp device can be used with pmic_read/write calls
*/
int pmic_get(const char *name, struct udevice **devp);
/**
* pmic_reg_count: get the pmic register count
*
* The required pmic device can be obtained by 'pmic_get()'
*
* @dev - pointer to the UCLASS_PMIC device
* @return register count value on success or negative value of errno.
*/
int pmic_reg_count(struct udevice *dev);
/**
* pmic_read/write: read/write to the UCLASS_PMIC device
*
* The required pmic device can be obtained by 'pmic_get()'
*
* @pmic - pointer to the UCLASS_PMIC device
* @reg - device register offset
* @buffer - pointer to read/write buffer
* @len - byte count for read/write
* @return 0 on success or negative value of errno.
*/
int pmic_read(struct udevice *dev, uint reg, uint8_t *buffer, int len);
int pmic_write(struct udevice *dev, uint reg, const uint8_t *buffer, int len);
/**
* pmic_reg_read() - read a PMIC register value
*
* @dev: PMIC device to read
* @reg: Register to read
* @return value read on success or negative value of errno.
*/
int pmic_reg_read(struct udevice *dev, uint reg);
/**
* pmic_reg_write() - write a PMIC register value
*
* @dev: PMIC device to write
* @reg: Register to write
* @value: Value to write
* @return 0 on success or negative value of errno.
*/
int pmic_reg_write(struct udevice *dev, uint reg, uint value);
/**
* pmic_clrsetbits() - clear and set bits in a PMIC register
*
* This reads a register, optionally clears some bits, optionally sets some
* bits, then writes the register.
*
* @dev: PMIC device to update
* @reg: Register to update
* @clr: Bit mask to clear (set those bits that you want cleared)
* @set: Bit mask to set (set those bits that you want set)
* @return 0 on success or negative value of errno.
*/
int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set);
#endif /* CONFIG_DM_PMIC */
#ifdef CONFIG_POWER
int pmic_init(unsigned char bus);
int power_init_board(void);
int pmic_dialog_init(unsigned char bus);
int check_reg(struct pmic *p, u32 reg);
struct pmic *pmic_alloc(void);
struct pmic *pmic_get(const char *s);
int pmic_probe(struct pmic *p);
int pmic_reg_read(struct pmic *p, u32 reg, u32 *val);
int pmic_reg_write(struct pmic *p, u32 reg, u32 val);
int pmic_set_output(struct pmic *p, u32 reg, int ldo, int on);
#endif
#define pmic_i2c_addr (p->hw.i2c.addr)
#define pmic_i2c_tx_num (p->hw.i2c.tx_num)
#define pmic_spi_bitlen (p->hw.spi.bitlen)
#define pmic_spi_flags (p->hw.spi.flags)
#endif /* __CORE_PMIC_H_ */

27
u-boot/include/power/power_chrg.h Normal file
View File

@@ -0,0 +1,27 @@
/*
* Copyright (C) 2012 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __POWER_CHARGER_H_
#define __POWER_CHARGER_H_
/* Type of available chargers */
enum {
CHARGER_NO = 0,
CHARGER_TA,
CHARGER_USB,
CHARGER_TA_500,
CHARGER_UNKNOWN,
};
enum {
UNKNOWN,
EXT_SOURCE,
CHARGE,
NORMAL,
};
#endif /* __POWER_CHARGER_H_ */

438
u-boot/include/power/regulator.h Normal file
View File

@@ -0,0 +1,438 @@
/*
* Copyright (C) 2014-2015 Samsung Electronics
* Przemyslaw Marczak <p.marczak@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _INCLUDE_REGULATOR_H_
#define _INCLUDE_REGULATOR_H_
/**
* U-Boot Voltage/Current Regulator
* ================================
*
* The regulator API is based on a driver model, with the device tree support.
* And this header describes the functions and data types for the uclass id:
* 'UCLASS_REGULATOR' and the regulator driver API.
*
* The regulator uclass - is based on uclass platform data which is allocated,
* automatically for each regulator device on bind and 'dev->uclass_platdata'
* points to it. The data type is: 'struct dm_regulator_uclass_platdata'.
* The uclass file: 'drivers/power/regulator/regulator-uclass.c'
*
* The regulator device - is based on driver's model 'struct udevice'.
* The API can use regulator name in two meanings:
* - devname - the regulator device's name: 'dev->name'
* - platname - the device's platdata's name. So in the code it looks like:
* 'uc_pdata = dev->uclass_platdata'; 'name = uc_pdata->name'.
*
* The regulator device driver - provide an implementation of uclass operations
* pointed by 'dev->driver->ops' as a struct of type 'struct dm_regulator_ops'.
*
* To proper bind the regulator device, the device tree node should provide
* regulator constraints, like in the example below:
*
* ldo1 {
* regulator-name = "VDD_MMC_1.8V"; (must be unique for proper bind)
* regulator-min-microvolt = <1000000>; (optional)
* regulator-max-microvolt = <1000000>; (optional)
* regulator-min-microamp = <1000>; (optional)
* regulator-max-microamp = <1000>; (optional)
* regulator-always-on; (optional)
* regulator-boot-on; (optional)
* };
*
* Note: For the proper operation, at least name constraint is needed, since
* it can be used when calling regulator_get_by_platname(). And the mandatory
* rule for this name is, that it must be globally unique for the single dts.
* If regulator-name property is not provided, node name will be chosen.
*
* Regulator bind:
* For each regulator device, the device_bind() should be called with passed
* device tree offset. This is required for this uclass's '.post_bind' method,
* which does the scan on the device node, for the 'regulator-name' constraint.
* If the parent is not a PMIC device, and the child is not bind by function:
* 'pmic_bind_childs()', then it's recommended to bind the device by call to
* dm_scan_fdt_node() - this is usually done automatically for bus devices,
* as a post bind method.
*
* Regulator get:
* Having the device's name constraint, we can call regulator_by_platname(),
* to find the required regulator. Before return, the regulator is probed,
* and the rest of its constraints are put into the device's uclass platform
* data, by the uclass regulator '.pre_probe' method.
*
* For more info about PMIC bind, please refer to file: 'include/power/pmic.h'
*
* Note:
* Please do not use the device_bind_by_name() function, since it pass '-1' as
* device node offset - and the bind will fail on uclass .post_bind method,
* because of missing 'regulator-name' constraint.
*
*
* Fixed Voltage/Current Regulator
* ===============================
*
* When fixed voltage regulator is needed, then enable the config:
* - CONFIG_DM_REGULATOR_FIXED
*
* The driver file: 'drivers/power/regulator/fixed.c', provides basic support
* for control the GPIO, and return the device tree constraint values.
*
* To bind the fixed voltage regulator device, we usually use a 'simple-bus'
* node as a parent. And 'regulator-fixed' for the driver compatible. This is
* the same as in the kernel. The example node of fixed regulator:
*
* simple-bus {
* compatible = "simple-bus";
* #address-cells = <1>;
* #size-cells = <0>;
*
* blue_led {
* compatible = "regulator-fixed";
* regulator-name = "VDD_LED_3.3V";
* regulator-min-microvolt = <3300000>;
* regulator-max-microvolt = <3300000>;
* gpio = <&gpc1 0 GPIO_ACTIVE_LOW>;
* };
* };
*
* The fixed regulator devices also provide regulator uclass platform data. And
* devices bound from such node, can use the regulator drivers API.
*/
/* enum regulator_type - used for regulator_*() variant calls */
enum regulator_type {
REGULATOR_TYPE_LDO = 0,
REGULATOR_TYPE_BUCK,
REGULATOR_TYPE_DVS,
REGULATOR_TYPE_FIXED,
REGULATOR_TYPE_OTHER,
};
/**
* struct dm_regulator_mode - this structure holds an information about
* each regulator operation mode. Probably in most cases - an array.
* This will be probably a driver-static data, since it is device-specific.
*
* @id - a driver-specific mode id
* @register_value - a driver-specific value for its mode id
* @name - the name of mode - used for regulator command
* Note:
* The field 'id', should be always a positive number, since the negative values
* are reserved for the errno numbers when returns the mode id.
*/
struct dm_regulator_mode {
int id; /* Set only as >= 0 (negative value is reserved for errno) */
int register_value;
const char *name;
};
enum regulator_flag {
REGULATOR_FLAG_AUTOSET_UV = 1 << 0,
REGULATOR_FLAG_AUTOSET_UA = 1 << 1,
};
/**
* struct dm_regulator_uclass_platdata - pointed by dev->uclass_platdata, and
* allocated on each regulator bind. This structure holds an information
* about each regulator's constraints and supported operation modes.
* There is no "step" voltage value - so driver should take care of this.
*
* @type - one of 'enum regulator_type'
* @mode - pointer to the regulator mode (array if more than one)
* @mode_count - number of '.mode' entries
* @min_uV* - minimum voltage (micro Volts)
* @max_uV* - maximum voltage (micro Volts)
* @min_uA* - minimum amperage (micro Amps)
* @max_uA* - maximum amperage (micro Amps)
* @always_on* - bool type, true or false
* @boot_on* - bool type, true or false
* TODO(sjg@chromium.org): Consider putting the above two into @flags
* @flags: - flags value (see REGULATOR_FLAG_...)
* @name** - fdt regulator name - should be taken from the device tree
*
* Note:
* * - set automatically on device probe by the uclass's '.pre_probe' method.
* ** - set automatically on device bind by the uclass's '.post_bind' method.
* The constraints: type, mode, mode_count, can be set by device driver, e.g.
* by the driver '.probe' method.
*/
struct dm_regulator_uclass_platdata {
enum regulator_type type;
struct dm_regulator_mode *mode;
int mode_count;
int min_uV;
int max_uV;
int min_uA;
int max_uA;
bool always_on;
bool boot_on;
const char *name;
int flags;
};
/* Regulator device operations */
struct dm_regulator_ops {
/**
* The regulator output value function calls operates on a micro Volts.
*
* get/set_value - get/set output value of the given output number
* @dev - regulator device
* Sets:
* @uV - set the output value [micro Volts]
* @return output value [uV] on success or negative errno if fail.
*/
int (*get_value)(struct udevice *dev);
int (*set_value)(struct udevice *dev, int uV);
/**
* The regulator output current function calls operates on a micro Amps.
*
* get/set_current - get/set output current of the given output number
* @dev - regulator device
* Sets:
* @uA - set the output current [micro Amps]
* @return output value [uA] on success or negative errno if fail.
*/
int (*get_current)(struct udevice *dev);
int (*set_current)(struct udevice *dev, int uA);
/**
* The most basic feature of the regulator output is its enable state.
*
* get/set_enable - get/set enable state of the given output number
* @dev - regulator device
* Sets:
* @enable - set true - enable or false - disable
* @return true/false for get; or 0 / -errno for set.
*/
bool (*get_enable)(struct udevice *dev);
int (*set_enable)(struct udevice *dev, bool enable);
/**
* The 'get/set_mode()' function calls should operate on a driver-
* specific mode id definitions, which should be found in:
* field 'id' of struct dm_regulator_mode.
*
* get/set_mode - get/set operation mode of the given output number
* @dev - regulator device
* Sets
* @mode_id - set output mode id (struct dm_regulator_mode->id)
* @return id/0 for get/set on success or negative errno if fail.
* Note:
* The field 'id' of struct type 'dm_regulator_mode', should be always
* a positive number, since the negative is reserved for the error.
*/
int (*get_mode)(struct udevice *dev);
int (*set_mode)(struct udevice *dev, int mode_id);
};
/**
* regulator_mode: returns a pointer to the array of regulator mode info
*
* @dev - pointer to the regulator device
* @modep - pointer to the returned mode info array
* @return - count of modep entries on success or negative errno if fail.
*/
int regulator_mode(struct udevice *dev, struct dm_regulator_mode **modep);
/**
* regulator_get_value: get microvoltage voltage value of a given regulator
*
* @dev - pointer to the regulator device
* @return - positive output value [uV] on success or negative errno if fail.
*/
int regulator_get_value(struct udevice *dev);
/**
* regulator_set_value: set the microvoltage value of a given regulator.
*
* @dev - pointer to the regulator device
* @uV - the output value to set [micro Volts]
* @return - 0 on success or -errno val if fails
*/
int regulator_set_value(struct udevice *dev, int uV);
/**
* regulator_get_current: get microampere value of a given regulator
*
* @dev - pointer to the regulator device
* @return - positive output current [uA] on success or negative errno if fail.
*/
int regulator_get_current(struct udevice *dev);
/**
* regulator_set_current: set the microampere value of a given regulator.
*
* @dev - pointer to the regulator device
* @uA - set the output current [micro Amps]
* @return - 0 on success or -errno val if fails
*/
int regulator_set_current(struct udevice *dev, int uA);
/**
* regulator_get_enable: get regulator device enable state.
*
* @dev - pointer to the regulator device
* @return - true/false of enable state
*/
bool regulator_get_enable(struct udevice *dev);
/**
* regulator_set_enable: set regulator enable state
*
* @dev - pointer to the regulator device
* @enable - set true or false
* @return - 0 on success or -errno val if fails
*/
int regulator_set_enable(struct udevice *dev, bool enable);
/**
* regulator_get_mode: get active operation mode id of a given regulator
*
* @dev - pointer to the regulator device
* @return - positive mode 'id' number on success or -errno val if fails
* Note:
* The device can provide an array of operating modes, which is type of struct
* dm_regulator_mode. Each mode has it's own 'id', which should be unique inside
* that array. By calling this function, the driver should return an active mode
* id of the given regulator device.
*/
int regulator_get_mode(struct udevice *dev);
/**
* regulator_set_mode: set the given regulator's, active mode id
*
* @dev - pointer to the regulator device
* @mode_id - mode id to set ('id' field of struct type dm_regulator_mode)
* @return - 0 on success or -errno value if fails
* Note:
* The device can provide an array of operating modes, which is type of struct
* dm_regulator_mode. Each mode has it's own 'id', which should be unique inside
* that array. By calling this function, the driver should set the active mode
* of a given regulator to given by "mode_id" argument.
*/
int regulator_set_mode(struct udevice *dev, int mode_id);
/**
* regulators_enable_boot_on() - enable regulators needed for boot
*
* This enables all regulators which are marked to be on at boot time. This
* only works for regulators which don't have a range for voltage/current,
* since in that case it is not possible to know which value to use.
*
* This effectively calls regulator_autoset() for every regulator.
*/
int regulators_enable_boot_on(bool verbose);
/**
* regulator_autoset: setup the voltage/current on a regulator
*
* The setup depends on constraints found in device's uclass's platform data
* (struct dm_regulator_uclass_platdata):
*
* - Enable - will set - if any of: 'always_on' or 'boot_on' is set to true,
* or if both are unset, then the function returns
* - Voltage value - will set - if '.min_uV' and '.max_uV' values are equal
* - Current limit - will set - if '.min_uA' and '.max_uA' values are equal
*
* The function returns on the first-encountered error.
*
* @platname - expected string for dm_regulator_uclass_platdata .name field
* @devp - returned pointer to the regulator device - if non-NULL passed
* @return: 0 on success or negative value of errno.
*/
int regulator_autoset(struct udevice *dev);
/**
* regulator_autoset_by_name: setup the regulator given by its uclass's
* platform data name field. The setup depends on constraints found in device's
* uclass's platform data (struct dm_regulator_uclass_platdata):
* - Enable - will set - if any of: 'always_on' or 'boot_on' is set to true,
* or if both are unset, then the function returns
* - Voltage value - will set - if '.min_uV' and '.max_uV' values are equal
* - Current limit - will set - if '.min_uA' and '.max_uA' values are equal
*
* The function returns on first encountered error.
*
* @platname - expected string for dm_regulator_uclass_platdata .name field
* @devp - returned pointer to the regulator device - if non-NULL passed
* @return: 0 on success or negative value of errno.
*
* The returned 'regulator' device can be used with:
* - regulator_get/set_*
*/
int regulator_autoset_by_name(const char *platname, struct udevice **devp);
/**
* regulator_list_autoset: setup the regulators given by list of their uclass's
* platform data name field. The setup depends on constraints found in device's
* uclass's platform data. The function loops with calls to:
* regulator_autoset_by_name() for each name from the list.
*
* @list_platname - an array of expected strings for .name field of each
* regulator's uclass platdata
* @list_devp - an array of returned pointers to the successfully setup
* regulator devices if non-NULL passed
* @verbose - (true/false) print each regulator setup info, or be quiet
* @return 0 on successfully setup of all list entries, otherwise first error.
*
* The returned 'regulator' devices can be used with:
* - regulator_get/set_*
*
* Note: The list must ends with NULL entry, like in the "platname" list below:
* char *my_regulators[] = {
* "VCC_3.3V",
* "VCC_1.8V",
* NULL,
* };
*/
int regulator_list_autoset(const char *list_platname[],
struct udevice *list_devp[],
bool verbose);
/**
* regulator_get_by_devname: returns the pointer to the pmic regulator device.
* Search by name, found in regulator device's name.
*
* @devname - expected string for 'dev->name' of regulator device
* @devp - returned pointer to the regulator device
* @return 0 on success or negative value of errno.
*
* The returned 'regulator' device is probed and can be used with:
* - regulator_get/set_*
*/
int regulator_get_by_devname(const char *devname, struct udevice **devp);
/**
* regulator_get_by_platname: returns the pointer to the pmic regulator device.
* Search by name, found in regulator uclass platdata.
*
* @platname - expected string for uc_pdata->name of regulator uclass platdata
* @devp - returns pointer to the regulator device or NULL on error
* @return 0 on success or negative value of errno.
*
* The returned 'regulator' device is probed and can be used with:
* - regulator_get/set_*
*/
int regulator_get_by_platname(const char *platname, struct udevice **devp);
/**
* device_get_supply_regulator: returns the pointer to the supply regulator.
* Search by phandle, found in device's node.
*
* Note: Please pay attention to proper order of device bind sequence.
* The regulator device searched by the phandle, must be binded before
* this function call.
*
* @dev - device with supply phandle
* @supply_name - phandle name of regulator
* @devp - returned pointer to the supply device
* @return 0 on success or negative value of errno.
*/
int device_get_supply_regulator(struct udevice *dev, const char *supply_name,
struct udevice **devp);
#endif /* _INCLUDE_REGULATOR_H_ */

77
u-boot/include/power/rk808_pmic.h Normal file
View File

@@ -0,0 +1,77 @@
/*
* Copyright (C) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PMIC_RK808_H_
#define _PMIC_RK808_H_
enum {
REG_DCDC_EN = 0x23,
REG_LDO_EN,
REG_SLEEP_SET_OFF1,
REG_SLEEP_SET_OFF2,
REG_DCDC_UV_STS,
REG_DCDC_UV_ACT,
REG_LDO_UV_STS,
REG_LDO_UV_ACT,
REG_DCDC_PG,
REG_LDO_PG,
REG_VOUT_MON_TDB,
REG_BUCK1_CONFIG,
REG_BUCK1_ON_VSEL,
REG_BUCK1_SLP_VSEL,
REG_BUCK1_DVS_VSEL,
REG_BUCK2_CONFIG,
REG_BUCK2_ON_VSEL,
REG_BUCK2_SLP_VSEL,
REG_BUCK2_DVS_VSEL,
REG_BUCK3_CONFIG,
REG_BUCK4_CONFIG,
REG_BUCK4_ON_VSEL,
REG_BUCK4_SLP_VSEL,
LDO1_ON_VSEL = 0x3b,
LDO1_SLP_VSEL,
LDO2_ON_VSEL,
LDO2_SLP_VSEL,
LDO3_ON_VSEL,
LDO3_SLP_VSEL,
LDO4_ON_VSEL,
LDO4_SLP_VSEL,
LDO5_ON_VSEL,
LDO5_SLP_VSEL,
LDO6_ON_VSEL,
LDO6_SLP_VSEL,
LDO7_ON_VSEL,
LDO7_SLP_VSEL,
LDO8_ON_VSEL,
LDO8_SLP_VSEL,
DEVCTRL,
INT_STS1,
INT_STS_MSK1,
INT_STS2,
INT_STS_MSK2,
IO_POL,
/* Not sure what this does */
DCDC_ILMAX = 0x90,
RK808_NUM_OF_REGS,
};
struct rk808_reg_table {
char *name;
u8 reg_ctl;
u8 reg_vol;
};
int rk808_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
#endif

109
u-boot/include/power/s2mps11.h Normal file
View File

@@ -0,0 +1,109 @@
#ifndef __S2MPS11__H__
#define __S2MPS11__H__
enum s2mps11_reg {
S2MPS11_REG_ID = 0,
S2MPS11_REG_INT1,
S2MPS11_REG_INT2,
S2MPS11_REG_INT3,
S2MPS11_REG_INT1M,
S2MPS11_REG_INT2M,
S2MPS11_REG_INT3M,
S2MPS11_REG_STATUS1,
S2MPS11_REG_STATUS2,
S2MPS11_REG_OFFSRC,
S2MPS11_REG_PWRONSRC,
S2MPS11_REG_RTC_CTRL,
S2MPS11_REG_CTRL1,
S2MPS11_REG_ETC_TEST,
S2MPS11_REG_RSVD3,
S2MPS11_REG_BU_CHG,
S2MPS11_REG_RAMP,
S2MPS11_REG_RAMP_BUCK,
S2MPS11_REG_LDO1_8,
S2MPS11_REG_LDO9_16,
S2MPS11_REG_LDO17_24,
S2MPS11_REG_LDO25_32,
S2MPS11_REG_LDO33_38,
S2MPS11_REG_LDO1_8_OVC,
S2MPS11_REG_LDO9_16_OVC,
S2MPS11_REG_LDO17_24_OVC,
S2MPS11_REG_LDO25_32_OVC,
S2MPS11_REG_LDO33_38_OVC,
S2MPS11_REG_RESERVED1,
S2MPS11_REG_RESERVED2,
S2MPS11_REG_RESERVED3,
S2MPS11_REG_RESERVED4,
S2MPS11_REG_RESERVED5,
S2MPS11_REG_RESERVED6,
S2MPS11_REG_RESERVED7,
S2MPS11_REG_RESERVED8,
S2MPS11_REG_WDRSTEN_CTRL,
S2MPS11_REG_B1CTRL1,
S2MPS11_REG_B1CTRL2,
S2MPS11_REG_B2CTRL1,
S2MPS11_REG_B2CTRL2,
S2MPS11_REG_B3CTRL1,
S2MPS11_REG_B3CTRL2,
S2MPS11_REG_B4CTRL1,
S2MPS11_REG_B4CTRL2,
S2MPS11_REG_B5CTRL1,
S2MPS11_REG_BUCK5_SW,
S2MPS11_REG_B5CTRL2,
S2MPS11_REG_B5CTRL3,
S2MPS11_REG_B5CTRL4,
S2MPS11_REG_B5CTRL5,
S2MPS11_REG_B6CTRL1,
S2MPS11_REG_B6CTRL2,
S2MPS11_REG_B7CTRL1,
S2MPS11_REG_B7CTRL2,
S2MPS11_REG_B8CTRL1,
S2MPS11_REG_B8CTRL2,
S2MPS11_REG_B9CTRL1,
S2MPS11_REG_B9CTRL2,
S2MPS11_REG_B10CTRL1,
S2MPS11_REG_B10CTRL2,
S2MPS11_REG_L1CTRL,
S2MPS11_REG_L2CTRL,
S2MPS11_REG_L3CTRL,
S2MPS11_REG_L4CTRL,
S2MPS11_REG_L5CTRL,
S2MPS11_REG_L6CTRL,
S2MPS11_REG_L7CTRL,
S2MPS11_REG_L8CTRL,
S2MPS11_REG_L9CTRL,
S2MPS11_REG_L10CTRL,
S2MPS11_REG_L11CTRL,
S2MPS11_REG_L12CTRL,
S2MPS11_REG_L13CTRL,
S2MPS11_REG_L14CTRL,
S2MPS11_REG_L15CTRL,
S2MPS11_REG_L16CTRL,
S2MPS11_REG_L17CTRL,
S2MPS11_REG_L18CTRL,
S2MPS11_REG_L19CTRL,
S2MPS11_REG_L20CTRL,
S2MPS11_REG_L21CTRL,
S2MPS11_REG_L22CTRL,
S2MPS11_REG_L23CTRL,
S2MPS11_REG_L24CTRL,
S2MPS11_REG_L25CTRL,
S2MPS11_REG_L26CTRL,
S2MPS11_REG_L27CTRL,
S2MPS11_REG_L28CTRL,
S2MPS11_REG_L29CTRL,
S2MPS11_REG_L30CTRL,
S2MPS11_REG_L31CTRL,
S2MPS11_REG_L32CTRL,
S2MPS11_REG_L33CTRL,
S2MPS11_REG_L34CTRL,
S2MPS11_REG_L35CTRL,
S2MPS11_REG_L36CTRL,
S2MPS11_REG_L37CTRL,
S2MPS11_REG_L38CTRL,
S2MPS11_REG_COUNT,
};
#define S2MPS11_LDO26_ENABLE 0xec
#endif

85
u-boot/include/power/s5m8767.h Normal file
View File

@@ -0,0 +1,85 @@
/*
* Copyright (c) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __S5M8767_H_
#define __S5M8767_H_
enum s5m8767_regnum {
S5M8767_BUCK1 = 0,
S5M8767_BUCK2,
S5M8767_BUCK3,
S5M8767_BUCK4,
S5M8767_BUCK5,
S5M8767_BUCK6,
S5M8767_BUCK7,
S5M8767_BUCK8,
S5M8767_BUCK9,
S5M8767_LDO1,
S5M8767_LDO2,
S5M8767_LDO3,
S5M8767_LDO4,
S5M8767_LDO5,
S5M8767_LDO6,
S5M8767_LDO7,
S5M8767_LDO8,
S5M8767_LDO9,
S5M8767_LDO10,
S5M8767_LDO11,
S5M8767_LDO12,
S5M8767_LDO13,
S5M8767_LDO14,
S5M8767_LDO15,
S5M8767_LDO16,
S5M8767_LDO17,
S5M8767_LDO18,
S5M8767_LDO19,
S5M8767_LDO20,
S5M8767_LDO21,
S5M8767_LDO22,
S5M8767_LDO23,
S5M8767_LDO24,
S5M8767_LDO25,
S5M8767_LDO26,
S5M8767_LDO27,
S5M8767_LDO28,
S5M8767_EN32KHZ_CP,
S5M8767_NUM_OF_REGS,
};
struct sec_voltage_desc {
int max;
int min;
int step;
};
/**
* struct s5m8767_para - s5m8767 register parameters
* @param vol_addr i2c address of the given buck/ldo register
* @param vol_bitpos bit position to be set or clear within register
* @param vol_bitmask bit mask value
* @param reg_enaddr control register address, which enable the given
* given buck/ldo.
* @param reg_enbiton value to be written to buck/ldo to make it ON
* @param vol Voltage information
*/
struct s5m8767_para {
enum s5m8767_regnum regnum;
u8 vol_addr;
u8 vol_bitpos;
u8 vol_bitmask;
u8 reg_enaddr;
u8 reg_enbiton;
const struct sec_voltage_desc *vol;
};
/* Drivers name */
#define S5M8767_LDO_DRIVER "s5m8767_ldo"
#define S5M8767_BUCK_DRIVER "s5m8767_buck"
int s5m8767_enable_32khz_cp(struct udevice *dev);
#endif /* __S5M8767_PMIC_H_ */

142
u-boot/include/power/sandbox_pmic.h Normal file
View File

@@ -0,0 +1,142 @@
/*
* Copyright (C) 2015 Samsung Electronics
* Przemyslaw Marczak <p.marczak@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SANDBOX_PMIC_H_
#define _SANDBOX_PMIC_H_
#define SANDBOX_LDO_DRIVER "sandbox_ldo"
#define SANDBOX_OF_LDO_PREFIX "ldo"
#define SANDBOX_BUCK_DRIVER "sandbox_buck"
#define SANDBOX_OF_BUCK_PREFIX "buck"
#define SANDBOX_BUCK_COUNT 2
#define SANDBOX_LDO_COUNT 2
/*
* Sandbox PMIC registers:
* We have only 12 significant registers, but we alloc 16 for padding.
*/
enum {
SANDBOX_PMIC_REG_BUCK1_UV = 0,
SANDBOX_PMIC_REG_BUCK1_UA,
SANDBOX_PMIC_REG_BUCK1_OM,
SANDBOX_PMIC_REG_BUCK2_UV,
SANDBOX_PMIC_REG_BUCK2_UA,
SANDBOX_PMIC_REG_BUCK2_OM,
SANDBOX_PMIC_REG_LDO_OFFSET,
SANDBOX_PMIC_REG_LDO1_UV = SANDBOX_PMIC_REG_LDO_OFFSET,
SANDBOX_PMIC_REG_LDO1_UA,
SANDBOX_PMIC_REG_LDO1_OM,
SANDBOX_PMIC_REG_LDO2_UV,
SANDBOX_PMIC_REG_LDO2_UA,
SANDBOX_PMIC_REG_LDO2_OM,
SANDBOX_PMIC_REG_COUNT = 16,
};
/* Register offset for output: micro Volts, micro Amps, Operation Mode */
enum {
OUT_REG_UV = 0,
OUT_REG_UA,
OUT_REG_OM,
OUT_REG_COUNT,
};
/* Buck operation modes */
enum {
BUCK_OM_OFF = 0,
BUCK_OM_ON,
BUCK_OM_PWM,
BUCK_OM_COUNT,
};
/* Ldo operation modes */
enum {
LDO_OM_OFF = 0,
LDO_OM_ON,
LDO_OM_SLEEP,
LDO_OM_STANDBY,
LDO_OM_COUNT,
};
/* BUCK1 Voltage: min: 0.8V, step: 25mV, max 2.4V */
#define OUT_BUCK1_UV_MIN 800000
#define OUT_BUCK1_UV_MAX 2400000
#define OUT_BUCK1_UV_STEP 25000
/* BUCK1 Amperage: min: 150mA, step: 25mA, max: 250mA */
#define OUT_BUCK1_UA_MIN 150000
#define OUT_BUCK1_UA_MAX 250000
#define OUT_BUCK1_UA_STEP 25000
/* BUCK2 Voltage: min: 0.75V, step: 50mV, max 3.95V */
#define OUT_BUCK2_UV_MIN 750000
#define OUT_BUCK2_UV_MAX 3950000
#define OUT_BUCK2_UV_STEP 50000
/* LDO1 Voltage: min: 0.8V, step: 25mV, max 2.4V */
#define OUT_LDO1_UV_MIN 800000
#define OUT_LDO1_UV_MAX 2400000
#define OUT_LDO1_UV_STEP 25000
/* LDO1 Amperage: min: 100mA, step: 50mA, max: 200mA */
#define OUT_LDO1_UA_MIN 100000
#define OUT_LDO1_UA_MAX 200000
#define OUT_LDO1_UA_STEP 50000
/* LDO2 Voltage: min: 0.75V, step: 50mV, max 3.95V */
#define OUT_LDO2_UV_MIN 750000
#define OUT_LDO2_UV_MAX 3950000
#define OUT_LDO2_UV_STEP 50000
/* register <-> value conversion */
#define REG2VAL(min, step, reg) ((min) + ((step) * (reg)))
#define VAL2REG(min, step, val) (((val) - (min)) / (step))
/* Operation mode id -> register value conversion */
#define OM2REG(x) (x)
/* Test data for: test/dm/power.c */
/* BUCK names */
#define SANDBOX_BUCK1_DEVNAME "buck1"
#define SANDBOX_BUCK1_PLATNAME "SUPPLY_1.2V"
#define SANDBOX_BUCK2_DEVNAME "buck2"
#define SANDBOX_BUCK2_PLATNAME "SUPPLY_3.3V"
/* LDO names */
#define SANDBOX_LDO1_DEVNAME "ldo1"
#define SANDBOX_LDO1_PLATNAME "VDD_EMMC_1.8V"
#define SANDBOX_LDO2_DEVNAME "ldo2"
#define SANDBOX_LDO2_PLATNAME "VDD_LCD_3.3V"
/*
* Expected regulators setup after call of:
* - regulator_autoset_by_name()
* - regulator_list_autoset()
*/
/* BUCK1: for testing regulator_autoset_by_name() */
#define SANDBOX_BUCK1_AUTOSET_EXPECTED_UV 1200000
#define SANDBOX_BUCK1_AUTOSET_EXPECTED_UA 200000
#define SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE true
/* BUCK2: for testing sandbox ADC's supply */
#define SANDBOX_BUCK2_INITIAL_EXPECTED_UV 3000000
#define SANDBOX_BUCK2_SET_UV 3300000
/* LDO1/2 for testing regulator_list_autoset() */
#define SANDBOX_LDO1_AUTOSET_EXPECTED_UV 1800000
#define SANDBOX_LDO1_AUTOSET_EXPECTED_UA 100000
#define SANDBOX_LDO1_AUTOSET_EXPECTED_ENABLE true
#define SANDBOX_LDO2_AUTOSET_EXPECTED_UV 3000000
#define SANDBOX_LDO2_AUTOSET_EXPECTED_UA -ENOSYS
#define SANDBOX_LDO2_AUTOSET_EXPECTED_ENABLE false
#endif

29
u-boot/include/power/tps62362.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
* Author: Felipe Balbi <balbi@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __POWER_TPS62362_H__
#define __POWER_TPS62362_H__
/* I2C chip address */
#define TPS62362_I2C_ADDR 0x60
/* Registers */
#define TPS62362_SET0 0x00
#define TPS62362_SET1 0x01
#define TPS62362_SET2 0x02
#define TPS62362_SET3 0x03
#define TPS62362_NUM_REGS 4
#define TPS62362_DCDC_VOLT_SEL_0950MV 0x12
#define TPS62362_DCDC_VOLT_SEL_1100MV 0x21
#define TPS62362_DCDC_VOLT_SEL_1200MV 0x2b
#define TPS62362_DCDC_VOLT_SEL_1260MV 0x31
#define TPS62362_DCDC_VOLT_SEL_1330MV 0x38
int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel);
int power_tps62362_init(unsigned char bus);
#endif /* __POWER_TPS62362_H__ */

56
u-boot/include/power/tps65090.h Normal file
View File

@@ -0,0 +1,56 @@
/*
* Copyright (c) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __TPS65090_PMIC_H_
#define __TPS65090_PMIC_H_
/* I2C device address for TPS65090 PMU */
#define TPS65090_I2C_ADDR 0x48
/* TPS65090 register addresses */
enum {
REG_IRQ1 = 0,
REG_CG_CTRL0 = 4,
REG_CG_STATUS1 = 0xa,
REG_FET_BASE = 0xe, /* Not a real register, FETs count from here */
REG_FET1_CTRL,
REG_FET2_CTRL,
REG_FET3_CTRL,
REG_FET4_CTRL,
REG_FET5_CTRL,
REG_FET6_CTRL,
REG_FET7_CTRL,
TPS65090_NUM_REGS,
};
enum {
IRQ1_VBATG = 1 << 3,
CG_CTRL0_ENC_MASK = 0x01,
MAX_FET_NUM = 7,
MAX_CTRL_READ_TRIES = 5,
/* TPS65090 FET_CTRL register values */
FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */
FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */
FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */
FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */
FET_CTRL_ENFET = 1 << 0, /* Enable FET */
};
enum {
/* Status register fields */
TPS65090_ST1_OTC = 1 << 0,
TPS65090_ST1_OCC = 1 << 1,
TPS65090_ST1_STATE_SHIFT = 4,
TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT,
};
/* Drivers name */
#define TPS65090_FET_DRIVER "tps65090_fet"
#endif /* __TPS65090_PMIC_H_ */

87
u-boot/include/power/tps65217.h Normal file
View File

@@ -0,0 +1,87 @@
/*
* (C) Copyright 2011-2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* For more details, please see the TRM at http://www.ti.com/product/tps65217a
*/
#ifndef __POWER_TPS65217_H__
#define __POWER_TPS65217_H__
/* I2C chip address */
#define TPS65217_CHIP_PM 0x24
/* Registers */
enum {
TPS65217_CHIPID = 0x00,
TPS65217_POWER_PATH,
TPS65217_INTERRUPT,
TPS65217_CHGCONFIG0,
TPS65217_CHGCONFIG1,
TPS65217_CHGCONFIG2,
TPS65217_CHGCONFIG3,
TPS65217_WLEDCTRL1,
TPS65217_WLEDCTRL2,
TPS65217_MUXCTRL,
TPS65217_STATUS,
TPS65217_PASSWORD,
TPS65217_PGOOD,
TPS65217_DEFPG,
TPS65217_DEFDCDC1,
TPS65217_DEFDCDC2,
TPS65217_DEFDCDC3,
TPS65217_DEFSLEW,
TPS65217_DEFLDO1,
TPS65217_DEFLDO2,
TPS65217_DEFLS1,
TPS65217_DEFLS2,
TPS65217_ENABLE,
TPS65217_DEFUVLO,
TPS65217_SEQ1,
TPS65217_SEQ2,
TPS65217_SEQ3,
TPS65217_SEQ4,
TPS65217_SEQ5,
TPS65217_SEQ6,
TPS65217_PMIC_NUM_OF_REGS,
};
#define TPS65217_PROT_LEVEL_NONE 0x00
#define TPS65217_PROT_LEVEL_1 0x01
#define TPS65217_PROT_LEVEL_2 0x02
#define TPS65217_PASSWORD_LOCK_FOR_WRITE 0x00
#define TPS65217_PASSWORD_UNLOCK 0x7D
#define TPS65217_DCDC_GO 0x80
#define TPS65217_MASK_ALL_BITS 0xFF
#define TPS65217_USB_INPUT_CUR_LIMIT_MASK 0x03
#define TPS65217_USB_INPUT_CUR_LIMIT_100MA 0x00
#define TPS65217_USB_INPUT_CUR_LIMIT_500MA 0x01
#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02
#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03
#define TPS65217_DCDC_VOLT_SEL_950MV 0x02
#define TPS65217_DCDC_VOLT_SEL_1100MV 0x08
#define TPS65217_DCDC_VOLT_SEL_1125MV 0x09
#define TPS65217_DCDC_VOLT_SEL_1200MV 0x0c
#define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F
#define TPS65217_DCDC_VOLT_SEL_1325MV 0x11
#define TPS65217_LDO_MASK 0x1F
#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06
#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F
#define TPS65217_PWR_OFF 0x80
#define TPS65217_PWR_SRC_USB_BITMASK 0x4
#define TPS65217_PWR_SRC_AC_BITMASK 0x8
int tps65217_reg_read(uchar src_reg, uchar *src_val);
int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
uchar mask);
int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
#endif /* __POWER_TPS65217_H__ */

79
u-boot/include/power/tps65218.h Normal file
View File

@@ -0,0 +1,79 @@
/*
* (C) Copyright 2014
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __POWER_TPS65218_H__
#define __POWER_TPS65218_H__
#include <linux/bitops.h>
/* I2C chip address */
#define TPS65218_CHIP_PM 0x24
/* Registers */
enum {
TPS65218_CHIPID = 0x00,
TPS65218_INT1,
TPS65218_INT2,
TPS65218_INT_MASK1,
TPS65218_INT_MASK2,
TPS65218_STATUS,
TPS65218_CONTROL,
TPS65218_FLAG,
TPS65218_PASSWORD = 0x10,
TPS65218_ENABLE1,
TPS65218_ENABLE2,
TPS65218_CONFIG1,
TPS65218_CONFIG2,
TPS65218_CONFIG3,
TPS65218_DCDC1,
TPS65218_DCDC2,
TPS65218_DCDC3,
TPS65218_DCDC4,
TPS65218_SLEW,
TPS65218_LDO1,
TPS65218_SEQ1 = 0x20,
TPS65218_SEQ2,
TPS65218_SEQ3,
TPS65218_SEQ4,
TPS65218_SEQ5,
TPS65218_SEQ6,
TPS65218_SEQ7,
TPS65218_PMIC_NUM_OF_REGS,
};
#define TPS65218_PROT_LEVEL_NONE 0x00
#define TPS65218_PROT_LEVEL_1 0x01
#define TPS65218_PROT_LEVEL_2 0x02
#define TPS65218_PASSWORD_LOCK_FOR_WRITE 0x00
#define TPS65218_PASSWORD_UNLOCK 0x7D
#define TPS65218_DCDC_GO 0x80
#define TPS65218_MASK_ALL_BITS 0xFF
#define TPS65218_DCDC_VOLT_SEL_0950MV 0x0a
#define TPS65218_DCDC_VOLT_SEL_1100MV 0x19
#define TPS65218_DCDC_VOLT_SEL_1200MV 0x23
#define TPS65218_DCDC_VOLT_SEL_1260MV 0x29
#define TPS65218_DCDC_VOLT_SEL_1330MV 0x30
#define TPS65218_CC_STAT (BIT(0) | BIT(1))
#define TPS65218_STATE (BIT(2) | BIT(3))
#define TPS65218_PB_STATE BIT(4)
#define TPS65218_AC_STATE BIT(5)
#define TPS65218_EE BIT(6)
#define TPS65218_FSEAL BIT(7)
int tps65218_reg_read(uchar dest_reg, uchar *dest_val);
int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
uchar mask);
int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
int tps65218_toggle_fseal(void);
int tps65218_lock_fseal(void);
int power_tps65218_init(unsigned char bus);
#endif /* __POWER_TPS65218_H__ */

77
u-boot/include/power/tps65910.h Normal file
View File

@@ -0,0 +1,77 @@
/*
* (C) Copyright 2011-2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* For more details, please see the TRM at http://www.ti.com/product/tps65910
*/
#ifndef __POWER_TPS65910_H__
#define __POWER_TPS65910_H__
#define MPU 0
#define CORE 1
#define TPS65910_SR_I2C_ADDR 0x12
#define TPS65910_CTRL_I2C_ADDR 0x2D
/* PMIC Register offsets */
enum {
TPS65910_VDD1_REG = 0x21,
TPS65910_VDD1_OP_REG = 0x22,
TPS65910_VDD2_REG = 0x24,
TPS65910_VDD2_OP_REG = 0x25,
TPS65910_DEVCTRL_REG = 0x3F,
};
/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
#define TPS65910_VGAIN_SEL_MASK (0x3 << 6)
#define TPS65910_ILMAX_MASK (0x1 << 5)
#define TPS65910_TSTEP_MASK (0x7 << 2)
#define TPS65910_ST_MASK (0x3)
#define TPS65910_REG_VGAIN_SEL_X1 (0x0 << 6)
#define TPS65910_REG_VGAIN_SEL_X1_0 (0x1 << 6)
#define TPS65910_REG_VGAIN_SEL_X3 (0x2 << 6)
#define TPS65910_REG_VGAIN_SEL_X4 (0x3 << 6)
#define TPS65910_REG_ILMAX_1_0_A (0x0 << 5)
#define TPS65910_REG_ILMAX_1_5_A (0x1 << 5)
#define TPS65910_REG_TSTEP_ (0x0 << 2)
#define TPS65910_REG_TSTEP_12_5 (0x1 << 2)
#define TPS65910_REG_TSTEP_9_4 (0x2 << 2)
#define TPS65910_REG_TSTEP_7_5 (0x3 << 2)
#define TPS65910_REG_TSTEP_6_25 (0x4 << 2)
#define TPS65910_REG_TSTEP_4_7 (0x5 << 2)
#define TPS65910_REG_TSTEP_3_12 (0x6 << 2)
#define TPS65910_REG_TSTEP_2_5 (0x7 << 2)
#define TPS65910_REG_ST_OFF (0x0)
#define TPS65910_REG_ST_ON_HI_POW (0x1)
#define TPS65910_REG_ST_OFF_1 (0x2)
#define TPS65910_REG_ST_ON_LOW_POW (0x3)
/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
#define TPS65910_OP_REG_SEL (0x7F)
#define TPS65910_OP_REG_CMD_MASK (0x1 << 7)
#define TPS65910_OP_REG_CMD_OP (0x0 << 7)
#define TPS65910_OP_REG_CMD_SR (0x1 << 7)
#define TPS65910_OP_REG_SEL_MASK (0x7F)
#define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */
#define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */
#define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */
#define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */
#define TPS65910_OP_REG_SEL_1_3_2_5 (0x3D) /* 1.3250 V */
/* Device control register . (DEVCTRL_REG) */
#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4)
#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4)
#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4)
int tps65910_set_i2c_control(void);
int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel);
#endif /* __POWER_TPS65910_H__ */