avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/include/.gitignore

@@ -0,0 +1,5 @@
+/autoconf.mk*
+/bmp_logo.h
+/bmp_logo_data.h
+/config.h
+/license.h

u-boot/include/ACEX1K.h

@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003
+ * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
+ *
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ACEX1K_H_
+#define _ACEX1K_H_
+
+#include <altera.h>
+
+extern int ACEX1K_load(Altera_desc *desc, const void *image, size_t size);
+extern int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int ACEX1K_info(Altera_desc *desc);
+
+extern int CYC2_load(Altera_desc *desc, const void *image, size_t size);
+extern int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int CYC2_info(Altera_desc *desc);
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	Altera_pre_fn		pre;
+	Altera_config_fn	config;
+	Altera_clk_fn		clk;
+	Altera_status_fn	status;
+	Altera_done_fn		done;
+	Altera_data_fn		data;
+	Altera_abort_fn		abort;
+	Altera_post_fn		post;
+} Altera_ACEX1K_Passive_Serial_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	Altera_pre_fn		pre;
+	Altera_config_fn	config;
+	Altera_status_fn	status;
+	Altera_done_fn		done;
+	Altera_write_fn		write;
+	Altera_abort_fn		abort;
+	Altera_post_fn		post;
+} Altera_CYC2_Passive_Serial_fns;
+
+/* Device Image Sizes
+ *********************************************************************/
+/* ACEX1K */
+/* FIXME: Which size do we mean?
+ * Datasheet says 1337000/8=167125Bytes,
+ * Filesize of an *.rbf file is 166965 Bytes
+ */
+#if 0
+#define Altera_EP1K100_SIZE	1337000/8	/* 167125 Bytes */
+#endif
+#define Altera_EP1K100_SIZE	(166965*8)
+
+#define Altera_EP2C8_SIZE	247942
+#define Altera_EP2C20_SIZE	586562
+#define Altera_EP2C35_SIZE	883905
+#define Altera_EP3C5_SIZE	368011		/* .rbf size in bytes */
+
+/* Descriptor Macros
+ *********************************************************************/
+/* ACEX1K devices */
+#define Altera_EP1K100_DESC(iface, fn_table, cookie) \
+{ Altera_ACEX1K, iface, Altera_EP1K100_SIZE, fn_table, cookie }
+
+#endif /* _ACEX1K_H_ */

u-boot/include/MCD_dma.h

@@ -0,0 +1,370 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MCD_API_H
+#define _MCD_API_H
+
+/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
+#undef MCD_INCLUDE_EU
+
+/* Number of DMA channels */
+#define NCHANNELS	16
+
+/* Total number of variants */
+#ifdef MCD_INCLUDE_EU
+#define NUMOFVARIANTS	6
+#else
+#define NUMOFVARIANTS	4
+#endif
+
+/* Define sizes of the various tables */
+#define TASK_TABLE_SIZE		(NCHANNELS*32)
+#define VAR_TAB_SIZE		(128)
+#define CONTEXT_SAVE_SIZE	(128)
+#define FUNCDESC_TAB_SIZE	(256)
+
+#ifdef MCD_INCLUDE_EU
+#define FUNCDESC_TAB_NUM	16
+#else
+#define FUNCDESC_TAB_NUM	1
+#endif
+
+#ifndef DEFINESONLY
+
+/* Portability typedefs */
+#if 1
+#include "common.h"
+#else
+#ifndef s32
+typedef int s32;
+#endif
+#ifndef u32
+typedef unsigned int u32;
+#endif
+#ifndef s16
+typedef short s16;
+#endif
+#ifndef u16
+typedef unsigned short u16;
+#endif
+#ifndef s8
+typedef char s8;
+#endif
+#ifndef u8
+typedef unsigned char u8;
+#endif
+#endif
+
+/*
+ * These structures represent the internal registers of the
+ * multi-channel DMA
+ */
+struct dmaRegs_s {
+	u32 taskbar;		/* task table base address */
+	u32 currPtr;
+	u32 endPtr;
+	u32 varTablePtr;
+	u16 dma_rsvd0;
+	u16 ptdControl;		/* ptd control */
+	u32 intPending;		/* interrupt pending */
+	u32 intMask;		/* interrupt mask */
+	u16 taskControl[16];	/* task control */
+	u8 priority[32];	/* priority */
+	u32 initiatorMux;	/* initiator mux control */
+	u32 taskSize0;		/* task size control 0. */
+	u32 taskSize1;		/* task size control 1. */
+	u32 dma_rsvd1;		/* reserved */
+	u32 dma_rsvd2;		/* reserved */
+	u32 debugComp1;		/* debug comparator 1 */
+	u32 debugComp2;		/* debug comparator 2 */
+	u32 debugControl;	/* debug control */
+	u32 debugStatus;	/* debug status */
+	u32 ptdDebug;		/* priority task decode debug */
+	u32 dma_rsvd3[31];	/* reserved */
+};
+typedef volatile struct dmaRegs_s dmaRegs;
+
+#endif
+
+/* PTD contrl reg bits */
+#define PTD_CTL_TSK_PRI		0x8000
+#define PTD_CTL_COMM_PREFETCH	0x0001
+
+/* Task Control reg bits and field masks */
+#define TASK_CTL_EN		0x8000
+#define TASK_CTL_VALID		0x4000
+#define TASK_CTL_ALWAYS		0x2000
+#define TASK_CTL_INIT_MASK	0x1f00
+#define TASK_CTL_ASTRT		0x0080
+#define TASK_CTL_HIPRITSKEN	0x0040
+#define TASK_CTL_HLDINITNUM	0x0020
+#define TASK_CTL_ASTSKNUM_MASK	0x000f
+
+/* Priority reg bits and field masks */
+#define PRIORITY_HLD		0x80
+#define PRIORITY_PRI_MASK	0x07
+
+/* Debug Control reg bits and field masks */
+#define DBG_CTL_BLOCK_TASKS_MASK	0xffff0000
+#define DBG_CTL_AUTO_ARM		0x00008000
+#define DBG_CTL_BREAK			0x00004000
+#define DBG_CTL_COMP1_TYP_MASK		0x00003800
+#define DBG_CTL_COMP2_TYP_MASK		0x00000070
+#define DBG_CTL_EXT_BREAK		0x00000004
+#define DBG_CTL_INT_BREAK		0x00000002
+
+/*
+ * PTD Debug reg selector addresses
+ * This reg must be written with a value to show the contents of
+ * one of the desired internal register.
+ */
+#define PTD_DBG_REQ		0x00	/* shows the state of 31 initiators */
+#define PTD_DBG_TSK_VLD_INIT	0x01	/* shows which 16 tasks are valid and
+					   have initiators asserted */
+
+/* General return values */
+#define MCD_OK			0
+#define MCD_ERROR		-1
+#define MCD_TABLE_UNALIGNED	-2
+#define MCD_CHANNEL_INVALID	-3
+
+/* MCD_initDma input flags */
+#define MCD_RELOC_TASKS		0x00000001
+#define MCD_NO_RELOC_TASKS	0x00000000
+#define MCD_COMM_PREFETCH_EN	0x00000002	/* MCF547x/548x ONLY */
+
+/*
+ * MCD_dmaStatus Status Values for each channel:
+ * MCD_NO_DMA	- No DMA has been requested since reset
+ * MCD_IDLE	- DMA active, but the initiator is currently inactive
+ * MCD_RUNNING	- DMA active, and the initiator is currently active
+ * MCD_PAUSED	- DMA active but it is currently paused
+ * MCD_HALTED	- the most recent DMA has been killed with MCD_killTask()
+ * MCD_DONE	- the most recent DMA has completed
+ */
+#define MCD_NO_DMA		1
+#define MCD_IDLE		2
+#define MCD_RUNNING		3
+#define MCD_PAUSED		4
+#define MCD_HALTED		5
+#define MCD_DONE		6
+
+/* MCD_startDma parameter defines */
+
+/* Constants for the funcDesc parameter */
+/*
+ * MCD_NO_BYTE_SWAP	- to disable byte swapping
+ * MCD_BYTE_REVERSE	- to reverse the bytes of each u32 of the DMAed data
+ * MCD_U16_REVERSE	- to reverse the 16-bit halves of each 32-bit data
+ *			  value being DMAed
+ * MCD_U16_BYTE_REVERSE	- to reverse the byte halves of each 16-bit half of
+ *			  each 32-bit data value DMAed
+ * MCD_NO_BIT_REV	- do not reverse the bits of each byte DMAed
+ * MCD_BIT_REV		- reverse the bits of each byte DMAed
+ * MCD_CRC16		- to perform CRC-16 on DMAed data
+ * MCD_CRCCCITT		- to perform CRC-CCITT on DMAed data
+ * MCD_CRC32		- to perform CRC-32 on DMAed data
+ * MCD_CSUMINET		- to perform internet checksums on DMAed data
+ * MCD_NO_CSUM		- to perform no checksumming
+ */
+#define MCD_NO_BYTE_SWAP	0x00045670
+#define MCD_BYTE_REVERSE	0x00076540
+#define MCD_U16_REVERSE		0x00067450
+#define MCD_U16_BYTE_REVERSE	0x00054760
+#define MCD_NO_BIT_REV		0x00000000
+#define MCD_BIT_REV		0x00088880
+/* CRCing: */
+#define MCD_CRC16		0xc0100000
+#define MCD_CRCCCITT		0xc0200000
+#define MCD_CRC32		0xc0300000
+#define MCD_CSUMINET		0xc0400000
+#define MCD_NO_CSUM		0xa0000000
+
+#define MCD_FUNC_NOEU1		(MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
+				 MCD_NO_CSUM)
+#define MCD_FUNC_NOEU2		(MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
+
+/* Constants for the flags parameter */
+#define MCD_TT_FLAGS_RL		0x00000001	/* Read line */
+#define MCD_TT_FLAGS_CW		0x00000002	/* Combine Writes */
+#define MCD_TT_FLAGS_SP		0x00000004	/* MCF547x/548x ONLY  */
+#define MCD_TT_FLAGS_MASK	0x000000ff
+#define MCD_TT_FLAGS_DEF	(MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
+
+#define MCD_SINGLE_DMA		0x00000100	/* Unchained DMA */
+#define MCD_CHAIN_DMA		/* TBD */
+#define MCD_EU_DMA		/* TBD */
+#define MCD_FECTX_DMA		0x00001000	/* FEC TX ring DMA */
+#define MCD_FECRX_DMA		0x00002000	/* FEC RX ring DMA */
+
+/* these flags are valid for MCD_startDma and the chained buffer descriptors */
+/*
+ * MCD_BUF_READY	- indicates that this buf is now under the DMA's ctrl
+ * MCD_WRAP		- to tell the FEC Dmas to wrap to the first BD
+ * MCD_INTERRUPT	- to generate an interrupt after completion of the DMA
+ * MCD_END_FRAME	- tell the DMA to end the frame when transferring
+ *			  last byte of data in buffer
+ * MCD_CRC_RESTART	- to empty out the accumulated checksum prior to
+ *			  performing the DMA
+ */
+#define MCD_BUF_READY		0x80000000
+#define MCD_WRAP		0x20000000
+#define MCD_INTERRUPT		0x10000000
+#define MCD_END_FRAME		0x08000000
+#define MCD_CRC_RESTART		0x40000000
+
+/* Defines for the FEC buffer descriptor control/status word*/
+#define MCD_FEC_BUF_READY	0x8000
+#define MCD_FEC_WRAP		0x2000
+#define MCD_FEC_INTERRUPT	0x1000
+#define MCD_FEC_END_FRAME	0x0800
+
+/* Defines for general intuitiveness */
+
+#define MCD_TRUE		1
+#define MCD_FALSE		0
+
+/* Three different cases for destination and source. */
+#define MINUS1			-1
+#define ZERO			0
+#define PLUS1			1
+
+#ifndef DEFINESONLY
+
+/* Task Table Entry struct*/
+typedef struct {
+	u32 TDTstart;		/* task descriptor table start */
+	u32 TDTend;		/* task descriptor table end */
+	u32 varTab;		/* variable table start */
+	u32 FDTandFlags;	/* function descriptor table start & flags */
+	volatile u32 descAddrAndStatus;
+	volatile u32 modifiedVarTab;
+	u32 contextSaveSpace;	/* context save space start */
+	u32 literalBases;
+} TaskTableEntry;
+
+/* Chained buffer descriptor:
+ * flags	- flags describing the DMA
+ * csumResult	- checksum performed since last checksum reset
+ * srcAddr	- the address to move data from
+ * destAddr	- the address to move data to
+ * lastDestAddr	- the last address written to
+ * dmaSize	- the no of bytes to xfer independent of the xfer sz
+ * next		- next buffer descriptor in chain
+ * info		- private info about this descriptor;  DMA does not affect it
+ */
+typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
+struct MCD_bufDesc_struct {
+	u32 flags;
+	u32 csumResult;
+	s8 *srcAddr;
+	s8 *destAddr;
+	s8 *lastDestAddr;
+	u32 dmaSize;
+	MCD_bufDesc *next;
+	u32 info;
+};
+
+/* Progress Query struct:
+ * lastSrcAddr	- the most-recent or last, post-increment source address
+ * lastDestAddr	- the most-recent or last, post-increment destination address
+ * dmaSize	- the amount of data transferred for the current buffer
+ * currBufDesc	- pointer to the current buffer descriptor being DMAed
+ */
+
+typedef volatile struct MCD_XferProg_struct {
+	s8 *lastSrcAddr;
+	s8 *lastDestAddr;
+	u32 dmaSize;
+	MCD_bufDesc *currBufDesc;
+} MCD_XferProg;
+
+/* FEC buffer descriptor */
+typedef volatile struct MCD_bufDescFec_struct {
+	u16 statCtrl;
+	u16 length;
+	u32 dataPointer;
+} MCD_bufDescFec;
+
+/*************************************************************************/
+/* API function Prototypes  - see MCD_dmaApi.c for further notes */
+
+/* MCD_startDma starts a particular kind of DMA:
+ * srcAddr	- the channel on which to run the DMA
+ * srcIncr	- the address to move data from, or buffer-descriptor address
+ * destAddr	- the amount to increment the source address per transfer
+ * destIncr	- the address to move data to
+ * dmaSize	- the amount to increment the destination address per transfer
+ * xferSize	- the number bytes in of each data movement (1, 2, or 4)
+ * initiator	- what device initiates the DMA
+ * priority	- priority of the DMA
+ * flags	- flags describing the DMA
+ * funcDesc	- description of byte swapping, bit swapping, and CRC actions
+ */
+int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
+		 s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
+		 int priority, u32 flags, u32 funcDesc);
+
+/*
+ * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
+ * registers, relocating and creating the appropriate task structures, and
+ * setting up some global settings
+ */
+int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
+
+/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
+int MCD_dmaStatus(int channel);
+
+/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
+int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
+
+/*
+ * MCD_killDma() halts the DMA on the requested channel, without any
+ * intention of resuming the DMA.
+ */
+int MCD_killDma(int channel);
+
+/*
+ * MCD_continDma() continues a DMA which as stopped due to encountering an
+ * unready buffer descriptor.
+ */
+int MCD_continDma(int channel);
+
+/*
+ * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
+ * running on that channel).
+ */
+int MCD_pauseDma(int channel);
+
+/*
+ * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
+ * running on that channel).
+ */
+int MCD_resumeDma(int channel);
+
+/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
+int MCD_csumQuery(int channel, u32 * csum);
+
+/*
+ * MCD_getCodeSize provides the packed size required by the microcoded task
+ * and structures.
+ */
+int MCD_getCodeSize(void);
+
+/*
+ * MCD_getVersion provides a pointer to a version string and returns a
+ * version number.
+ */
+int MCD_getVersion(char **longVersion);
+
+/* macro for setting a location in the variable table */
+#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
+/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
+   so I'm avoiding surrounding it with "do {} while(0)" */
+
+#endif				/* DEFINESONLY */
+
+#endif				/* _MCD_API_H */

u-boot/include/MCD_progCheck.h

@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+ /* This file is autogenerated. Do not change */
+#define CURRBD		4
+#define DCOUNT		6
+#define DESTPTR		5
+#define SRCPTR		7

u-boot/include/MCD_tasksInit.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef MCD_TSK_INIT_H
+#define MCD_TSK_INIT_H 1
+
+/*
+ * Do not edit!
+ */
+
+/* Task 0 */
+void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
+			   int xferSize, short xferSizeIncr, int *cSave,
+			   volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 1 */
+void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
+			    short destIncr, int dmaSize, short xferSizeIncr,
+			    int flags, int *currBD, int *cSave,
+			    volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 2 */
+void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
+			 int xferSize, short xferSizeIncr, int *cSave,
+			 volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 3 */
+void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
+			  short destIncr, int dmaSize, short xferSizeIncr,
+			  int flags, int *currBD, int *cSave,
+			  volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 4 */
+void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
+			 volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 5 */
+void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
+			  volatile TaskTableEntry * taskTable, int channel);
+
+#endif				/* MCD_TSK_INIT_H */

u-boot/include/_exports.h

@@ -0,0 +1,88 @@
+/*
+ * You need to use #ifdef around functions that may not exist
+ * in the final configuration (such as i2c).
+ * use a dummyfunction as first parameter to EXPORT_FUNC.
+ * As an example see the CONFIG_CMD_I2C section below
+ */
+#ifndef EXPORT_FUNC
+#define EXPORT_FUNC(a, b, c, ...)
+#endif
+	EXPORT_FUNC(get_version, unsigned long, get_version, void)
+	EXPORT_FUNC(getc, int, getc, void)
+	EXPORT_FUNC(tstc, int, tstc, void)
+	EXPORT_FUNC(putc, void, putc, const char)
+	EXPORT_FUNC(puts, void, puts, const char *)
+	EXPORT_FUNC(printf, int, printf, const char*, ...)
+#if defined(CONFIG_X86) || defined(CONFIG_PPC)
+	EXPORT_FUNC(irq_install_handler, void, install_hdlr,
+		    int, interrupt_handler_t, void*)
+
+	EXPORT_FUNC(irq_free_handler, void, free_hdlr, int)
+#else
+	EXPORT_FUNC(dummy, void, install_hdlr, void)
+	EXPORT_FUNC(dummy, void, free_hdlr, void)
+#endif
+	EXPORT_FUNC(malloc, void *, malloc, size_t)
+#if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE)
+	EXPORT_FUNC(free, void, free, void *)
+#endif
+	EXPORT_FUNC(udelay, void, udelay, unsigned long)
+	EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long)
+	EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list)
+	EXPORT_FUNC(do_reset, int, do_reset, cmd_tbl_t *,
+		    int , int , char * const [])
+	EXPORT_FUNC(getenv, char  *, getenv, const char*)
+	EXPORT_FUNC(setenv, int, setenv, const char *, const char *)
+	EXPORT_FUNC(simple_strtoul, unsigned long, simple_strtoul,
+		    const char *, char **, unsigned int)
+	EXPORT_FUNC(strict_strtoul, int, strict_strtoul,
+		    const char *, unsigned int , unsigned long *)
+	EXPORT_FUNC(simple_strtol, long, simple_strtol,
+		    const char *, char **, unsigned int)
+	EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct)
+#if defined(CONFIG_CMD_I2C) && \
+		(!defined(CONFIG_DM_I2C) || defined(CONFIG_DM_I2C_COMPAT))
+	EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int)
+	EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int)
+#else
+	EXPORT_FUNC(dummy, void, i2c_write, void)
+	EXPORT_FUNC(dummy, void, i2c_read, void)
+#endif
+
+#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI)
+	EXPORT_FUNC(dummy, void, spi_init, void)
+	EXPORT_FUNC(dummy, void, spi_setup_slave, void)
+	EXPORT_FUNC(dummy, void, spi_free_slave, void)
+#else
+	EXPORT_FUNC(spi_init, void, spi_init, void)
+	EXPORT_FUNC(spi_setup_slave, struct spi_slave *, spi_setup_slave,
+		    unsigned int, unsigned int, unsigned int, unsigned int)
+	EXPORT_FUNC(spi_free_slave, void, spi_free_slave, struct spi_slave *)
+#endif
+#ifndef CONFIG_CMD_SPI
+	EXPORT_FUNC(dummy, void, spi_claim_bus, void)
+	EXPORT_FUNC(dummy, void, spi_release_bus, void)
+	EXPORT_FUNC(dummy, void, spi_xfer, void)
+#else
+	EXPORT_FUNC(spi_claim_bus, int, spi_claim_bus, struct spi_slave *)
+	EXPORT_FUNC(spi_release_bus, void, spi_release_bus, struct spi_slave *)
+	EXPORT_FUNC(spi_xfer, int, spi_xfer, struct spi_slave *,
+		    unsigned int, const void *, void *, unsigned long)
+#endif
+	EXPORT_FUNC(ustrtoul, unsigned long, ustrtoul,
+		    const char *, char **, unsigned int)
+	EXPORT_FUNC(ustrtoull, unsigned long long, ustrtoull,
+		    const char *, char **, unsigned int)
+	EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src)
+	EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec)
+#ifdef CONFIG_PHY_AQUANTIA
+	EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *,
+		    mdio_get_current_dev, void)
+	EXPORT_FUNC(phy_find_by_mask, struct phy_device *, phy_find_by_mask,
+		    struct mii_dev *bus, unsigned phy_mask,
+		    phy_interface_t interface)
+	EXPORT_FUNC(mdio_phydev_for_ethname, struct phy_device *,
+		    mdio_phydev_for_ethname, const char *ethname)
+	EXPORT_FUNC(miiphy_set_current_dev, int, miiphy_set_current_dev,
+		    const char *devname)
+#endif

u-boot/include/adc.h

@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) 2015 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ADC_H_
+#define _ADC_H_
+
+/* ADC_CHANNEL() - ADC channel bit mask, to select only required channels */
+#define ADC_CHANNEL(x)		(1 << x)
+
+/* The last possible selected channel with 32-bit mask */
+#define ADC_MAX_CHANNEL		31
+
+/**
+ * adc_data_format: define the ADC output data format, can be useful when
+ * the device's input Voltage range is bipolar.
+ * - ADC_DATA_FORMAT_BIN - binary offset
+ * - ADC_DATA_FORMAT_2S  - two's complement
+ *
+ * Note: Device's driver should fill the 'data_format' field of its uclass's
+ * platform data using one of the above data format types.
+ */
+enum adc_data_format {
+	ADC_DATA_FORMAT_BIN,
+	ADC_DATA_FORMAT_2S,
+};
+
+/**
+ * struct adc_channel - structure to hold channel conversion data.
+ * Useful to keep the result of a multi-channel conversion output.
+ *
+ * @id   - channel id
+ * @data - channel conversion data
+ */
+struct adc_channel {
+	int id;
+	unsigned int data;
+};
+
+/**
+ * struct adc_uclass_platdata - basic ADC info
+ *
+ * Note: The positive/negative reference Voltage is only a name and it doesn't
+ * provide an information about the value polarity. It is possible, for both
+ * values to be a negative or positive. For this purpose the uclass's platform
+ * data provides a bool fields: 'vdd/vss_supply_is_negative'. This is useful,
+ * since the regulator API returns only a positive Voltage values.
+ *
+ * To get the reference Voltage values with polarity, use functions:
+ * - adc_vdd_value()
+ * - adc_vss_value()
+ * Those are useful for some cases of ADC's references, e.g.:
+ * * Vdd: +3.3V; Vss: -3.3V -> 6.6 Vdiff
+ * * Vdd: +3.3V; Vss: +0.3V -> 3.0 Vdiff
+ * * Vdd: +3.3V; Vss:  0.0V -> 3.3 Vdiff
+ * The last one is usually standard and doesn't require the fdt polarity info.
+ *
+ * For more informations read binding info:
+ * - doc/device-tree-bindings/adc/adc.txt
+ *
+ * @data_mask              - conversion output data mask
+ * @data_timeout_us        - single channel conversion timeout
+ * @multidata_timeout_us   - multi channel conversion timeout
+ * @channel_mask           - bit mask of available channels [0:31]
+ * @vdd_supply             - positive reference Voltage supply (regulator)
+ * @vss_supply             - negative reference Voltage supply (regulator)
+ * @vdd_polarity_negative  - positive reference Voltage has negative polarity
+ * @vss_polarity_negative  - negative reference Voltage has negative polarity
+ * @vdd_microvolts         - positive reference Voltage value
+ * @vss_microvolts         - negative reference Voltage value
+ */
+struct adc_uclass_platdata {
+	int data_format;
+	unsigned int data_mask;
+	unsigned int data_timeout_us;
+	unsigned int multidata_timeout_us;
+	unsigned int channel_mask;
+	struct udevice *vdd_supply;
+	struct udevice *vss_supply;
+	bool vdd_polarity_negative;
+	bool vss_polarity_negative;
+	int vdd_microvolts;
+	int vss_microvolts;
+};
+
+/**
+ * struct adc_ops - ADC device operations for single/multi-channel operation.
+ */
+struct adc_ops {
+	/**
+	 * start_channel() - start conversion with its default parameters
+	 *                   for the given channel number.
+	 *
+	 * @dev:          ADC device to init
+	 * @channel:      analog channel number
+	 * @return:       0 if OK, -ve on error
+	 */
+	int (*start_channel)(struct udevice *dev, int channel);
+
+	/**
+	 * start_channels() - start conversion with its default parameters
+	 *                    for the channel numbers selected by the bit mask.
+	 *
+	 * This is optional, useful when the hardware supports multichannel
+	 * conversion by the single software trigger.
+	 *
+	 * @dev:          ADC device to init
+	 * @channel_mask: bit mask of selected analog channels
+	 * @return:       0 if OK, -ve on error
+	 */
+	int (*start_channels)(struct udevice *dev, unsigned int channel_mask);
+
+	/**
+	 * channel_data() - get conversion output data for the given channel.
+	 *
+	 * Note: The implementation of this function should only check, that
+	 * the conversion data is available at the call time. If the hardware
+	 * requires some delay to get the data, then this function should
+	 * return with -EBUSY value. The ADC API will call it in a loop,
+	 * until the data is available or the timeout expires. The maximum
+	 * timeout for this operation is defined by the field 'data_timeout_us'
+	 * in ADC uclasses platform data structure.
+	 *
+	 * @dev:          ADC device to trigger
+	 * @channel:      selected analog channel number
+	 * @data:         returned pointer to selected channel's output data
+	 * @return:       0 if OK, -EBUSY if busy, and other negative on error
+	 */
+	int (*channel_data)(struct udevice *dev, int channel,
+			    unsigned int *data);
+
+	/**
+	 * channels_data() - get conversion data for the selected channels.
+	 *
+	 * This is optional, useful when multichannel conversion is supported
+	 * by the hardware, by the single software trigger.
+	 *
+	 * For the proper implementation, please look at the 'Note' for the
+	 * above method. The only difference is in used timeout value, which
+	 * is defined by field 'multidata_timeout_us'.
+	 *
+	 * @dev:          ADC device to trigger
+	 * @channel_mask: bit mask of selected analog channels
+	 * @channels:     returned pointer to array of output data for channels
+	 *                selected by the given mask
+	 * @return:       0 if OK, -ve on error
+	 */
+	int (*channels_data)(struct udevice *dev, unsigned int channel_mask,
+			     struct adc_channel *channels);
+
+	/**
+	 * stop() - stop conversion of the given ADC device
+	 *
+	 * @dev:          ADC device to stop
+	 * @return:       0 if OK, -ve on error
+	 */
+	int (*stop)(struct udevice *dev);
+};
+
+/**
+ * adc_start_channel() - start conversion for given device/channel and exit.
+ *
+ * @dev:     ADC device
+ * @channel: analog channel number
+ * @return:  0 if OK, -ve on error
+ */
+int adc_start_channel(struct udevice *dev, int channel);
+
+/**
+ * adc_start_channels() - start conversion for given device/channels and exit.
+ *
+ * Note:
+ * To use this function, device must implement method: start_channels().
+ *
+ * @dev:          ADC device to start
+ * @channel_mask: channel selection - a bit mask
+ * @channel_mask: bit mask of analog channels
+ * @return:       0 if OK, -ve on error
+ */
+int adc_start_channels(struct udevice *dev, unsigned int channel_mask);
+
+/**
+ * adc_channel_data() - get conversion data for the given device channel number.
+ *
+ * @dev:     ADC device to read
+ * @channel: analog channel number
+ * @data:    pointer to returned channel's data
+ * @return:  0 if OK, -ve on error
+ */
+int adc_channel_data(struct udevice *dev, int channel, unsigned int *data);
+
+/**
+ * adc_channels_data() - get conversion data for the channels selected by mask
+ *
+ * Note:
+ * To use this function, device must implement methods:
+ * - start_channels()
+ * - channels_data()
+ *
+ * @dev:          ADC device to read
+ * @channel_mask: channel selection - a bit mask
+ * @channels:     pointer to structure array of returned data for each channel
+ * @return:       0 if OK, -ve on error
+ */
+int adc_channels_data(struct udevice *dev, unsigned int channel_mask,
+		      struct adc_channel *channels);
+
+/**
+ * adc_data_mask() - get data mask (ADC resolution bitmask) for given ADC device
+ *
+ * This can be used if adc uclass platform data is filled.
+ *
+ * @dev:       ADC device to check
+ * @data_mask: pointer to the returned data bitmask
+ * @return: 0 if OK, -ve on error
+ */
+int adc_data_mask(struct udevice *dev, unsigned int *data_mask);
+
+/**
+ * adc_channel_single_shot() - get output data of conversion for the ADC
+ * device's channel. This function searches for the device with the given name,
+ * starts the given channel conversion and returns the output data.
+ *
+ * Note: To use this function, device must implement metods:
+ * - start_channel()
+ * - channel_data()
+ *
+ * @name:    device's name to search
+ * @channel: device's input channel to init
+ * @data:    pointer to conversion output data
+ * @return:  0 if OK, -ve on error
+ */
+int adc_channel_single_shot(const char *name, int channel, unsigned int *data);
+
+/**
+ * adc_channels_single_shot() - get ADC conversion output data for the selected
+ * device's channels. This function searches for the device by the given name,
+ * starts the selected channels conversion and returns the output data as array
+ * of type 'struct adc_channel'.
+ *
+ * Note: This function can be used if device implements one of ADC's single
+ * or multi-channel operation API. If multi-channel operation is not supported,
+ * then each selected channel is triggered by the sequence start/data in a loop.
+ *
+ * @name:         device's name to search
+ * @channel_mask: channel selection - a bit mask
+ * @channels:     pointer to conversion output data for the selected channels
+ * @return:       0 if OK, -ve on error
+ */
+int adc_channels_single_shot(const char *name, unsigned int channel_mask,
+			     struct adc_channel *channels);
+
+/**
+ * adc_vdd_value() - get the ADC device's positive reference Voltage value
+ *
+ * Note: Depending on bool value 'vdd_supply_is_negative' of platform data,
+ * the returned uV value can be negative, and it's not an error.
+ *
+ * @dev:     ADC device to check
+ * @uV:      Voltage value with polarization sign (uV)
+ * @return:  0 on success or -ve on error
+*/
+int adc_vdd_value(struct udevice *dev, int *uV);
+
+/**
+ * adc_vss_value() - get the ADC device's negative reference Voltage value
+ *
+ * Note: Depending on bool value 'vdd_supply_is_negative' of platform data,
+ * the returned uV value can be negative, and it's not an error.
+ *
+ * @dev:     ADC device to check
+ * @uV:      Voltage value with polarization sign (uV)
+ * @return:  0 on success or -ve on error
+*/
+int adc_vss_value(struct udevice *dev, int *uV);
+
+/**
+ * adc_stop() - stop operation for given ADC device.
+ *
+ * @dev:     ADC device to stop
+ * @return:  0 if OK, -ve on error
+ */
+int adc_stop(struct udevice *dev);
+
+#endif

u-boot/include/addr_map.h

@@ -0,0 +1,17 @@
+#ifndef __ADDR_MAP_H
+#define __ADDR_MAP_H
+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <asm/types.h>
+
+extern phys_addr_t addrmap_virt_to_phys(void *vaddr);
+extern void *addrmap_phys_to_virt(phys_addr_t paddr);
+extern void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,
+				phys_size_t size, int idx);
+
+#endif

u-boot/include/aes.h

@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _AES_REF_H_
+#define _AES_REF_H_
+
+#ifdef USE_HOSTCC
+/* Define compat stuff for use in fw_* tools. */
+typedef unsigned char u8;
+typedef unsigned int u32;
+#define debug(...) do {} while (0)
+#endif
+
+/*
+ * AES encryption library, with small code size, supporting only 128-bit AES
+ *
+ * AES is a stream cipher which works a block at a time, with each block
+ * in this case being AES_KEY_LENGTH bytes.
+ */
+
+enum {
+	AES_STATECOLS	= 4,	/* columns in the state & expanded key */
+	AES_KEYCOLS	= 4,	/* columns in a key */
+	AES_ROUNDS	= 10,	/* rounds in encryption */
+
+	AES_KEY_LENGTH	= 128 / 8,
+	AES_EXPAND_KEY_LENGTH	= 4 * AES_STATECOLS * (AES_ROUNDS + 1),
+};
+
+/**
+ * aes_expand_key() - Expand the AES key
+ *
+ * Expand a key into a key schedule, which is then used for the other
+ * operations.
+ *
+ * @key		Key, of length AES_KEY_LENGTH bytes
+ * @expkey	Buffer to place expanded key, AES_EXPAND_KEY_LENGTH
+ */
+void aes_expand_key(u8 *key, u8 *expkey);
+
+/**
+ * aes_encrypt() - Encrypt single block of data with AES 128
+ *
+ * @in		Input data
+ * @expkey	Expanded key to use for encryption (from aes_expand_key())
+ * @out		Output data
+ */
+void aes_encrypt(u8 *in, u8 *expkey, u8 *out);
+
+/**
+ * aes_decrypt() - Decrypt single block of data with AES 128
+ *
+ * @in		Input data
+ * @expkey	Expanded key to use for decryption (from aes_expand_key())
+ * @out		Output data
+ */
+void aes_decrypt(u8 *in, u8 *expkey, u8 *out);
+
+/**
+ * Apply chain data to the destination using EOR
+ *
+ * Each array is of length AES_KEY_LENGTH.
+ *
+ * @cbc_chain_data	Chain data
+ * @src			Source data
+ * @dst			Destination data, which is modified here
+ */
+void aes_apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst);
+
+/**
+ * aes_cbc_encrypt_blocks() - Encrypt multiple blocks of data with AES CBC.
+ *
+ * @key_exp		Expanded key to use
+ * @src			Source data to encrypt
+ * @dst			Destination buffer
+ * @num_aes_blocks	Number of AES blocks to encrypt
+ */
+void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks);
+
+/**
+ * Decrypt multiple blocks of data with AES CBC.
+ *
+ * @key_exp		Expanded key to use
+ * @src			Source data to decrypt
+ * @dst			Destination buffer
+ * @num_aes_blocks	Number of AES blocks to decrypt
+ */
+void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks);
+
+#endif /* _AES_REF_H_ */

u-boot/include/ahci.h

@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ * Author: Jason Jin<Jason.jin@freescale.com>
+ *         Zhang Wei<wei.zhang@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _AHCI_H_
+#define _AHCI_H_
+
+#include <pci.h>
+
+#define AHCI_PCI_BAR		0x24
+#define AHCI_MAX_SG		56 /* hardware max is 64K */
+#define AHCI_CMD_SLOT_SZ	32
+#define AHCI_MAX_CMD_SLOT	32
+#define AHCI_RX_FIS_SZ		256
+#define AHCI_CMD_TBL_HDR	0x80
+#define AHCI_CMD_TBL_CDB	0x40
+#define AHCI_CMD_TBL_SZ		AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
+#define AHCI_PORT_PRIV_DMA_SZ	(AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
+				AHCI_CMD_TBL_SZ	+ AHCI_RX_FIS_SZ)
+#define AHCI_CMD_ATAPI		(1 << 5)
+#define AHCI_CMD_WRITE		(1 << 6)
+#define AHCI_CMD_PREFETCH	(1 << 7)
+#define AHCI_CMD_RESET		(1 << 8)
+#define AHCI_CMD_CLR_BUSY	(1 << 10)
+
+#define RX_FIS_D2H_REG		0x40	/* offset of D2H Register FIS data */
+
+/* Global controller registers */
+#define HOST_CAP		0x00 /* host capabilities */
+#define HOST_CTL		0x04 /* global host control */
+#define HOST_IRQ_STAT		0x08 /* interrupt status */
+#define HOST_PORTS_IMPL		0x0c /* bitmap of implemented ports */
+#define HOST_VERSION		0x10 /* AHCI spec. version compliancy */
+#define HOST_CAP2		0x24 /* host capabilities, extended */
+
+/* HOST_CTL bits */
+#define HOST_RESET		(1 << 0)  /* reset controller; self-clear */
+#define HOST_IRQ_EN		(1 << 1)  /* global IRQ enable */
+#define HOST_AHCI_EN		(1 << 31) /* AHCI enabled */
+
+/* Registers for each SATA port */
+#define PORT_LST_ADDR		0x00 /* command list DMA addr */
+#define PORT_LST_ADDR_HI	0x04 /* command list DMA addr hi */
+#define PORT_FIS_ADDR		0x08 /* FIS rx buf addr */
+#define PORT_FIS_ADDR_HI	0x0c /* FIS rx buf addr hi */
+#define PORT_IRQ_STAT		0x10 /* interrupt status */
+#define PORT_IRQ_MASK		0x14 /* interrupt enable/disable mask */
+#define PORT_CMD		0x18 /* port command */
+#define PORT_TFDATA		0x20 /* taskfile data */
+#define PORT_SIG		0x24 /* device TF signature */
+#define PORT_CMD_ISSUE		0x38 /* command issue */
+#define PORT_SCR		0x28 /* SATA phy register block */
+#define PORT_SCR_STAT		0x28 /* SATA phy register: SStatus */
+#define PORT_SCR_CTL		0x2c /* SATA phy register: SControl */
+#define PORT_SCR_ERR		0x30 /* SATA phy register: SError */
+#define PORT_SCR_ACT		0x34 /* SATA phy register: SActive */
+
+#ifdef CONFIG_SUNXI_AHCI
+#define PORT_P0DMACR		0x70 /* SUNXI specific "DMA register" */
+#endif
+
+/* PORT_IRQ_{STAT,MASK} bits */
+#define PORT_IRQ_COLD_PRES	(1 << 31) /* cold presence detect */
+#define PORT_IRQ_TF_ERR		(1 << 30) /* task file error */
+#define PORT_IRQ_HBUS_ERR	(1 << 29) /* host bus fatal error */
+#define PORT_IRQ_HBUS_DATA_ERR	(1 << 28) /* host bus data error */
+#define PORT_IRQ_IF_ERR		(1 << 27) /* interface fatal error */
+#define PORT_IRQ_IF_NONFATAL	(1 << 26) /* interface non-fatal error */
+#define PORT_IRQ_OVERFLOW	(1 << 24) /* xfer exhausted available S/G */
+#define PORT_IRQ_BAD_PMP	(1 << 23) /* incorrect port multiplier */
+
+#define PORT_IRQ_PHYRDY		(1 << 22) /* PhyRdy changed */
+#define PORT_IRQ_DEV_ILCK	(1 << 7) /* device interlock */
+#define PORT_IRQ_CONNECT	(1 << 6) /* port connect change status */
+#define PORT_IRQ_SG_DONE	(1 << 5) /* descriptor processed */
+#define PORT_IRQ_UNK_FIS	(1 << 4) /* unknown FIS rx'd */
+#define PORT_IRQ_SDB_FIS	(1 << 3) /* Set Device Bits FIS rx'd */
+#define PORT_IRQ_DMAS_FIS	(1 << 2) /* DMA Setup FIS rx'd */
+#define PORT_IRQ_PIOS_FIS	(1 << 1) /* PIO Setup FIS rx'd */
+#define PORT_IRQ_D2H_REG_FIS	(1 << 0) /* D2H Register FIS rx'd */
+
+#define PORT_IRQ_FATAL		PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR	\
+				| PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
+
+#define DEF_PORT_IRQ		PORT_IRQ_FATAL | PORT_IRQ_PHYRDY	\
+				| PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE	\
+				| PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS	\
+				| PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS	\
+				| PORT_IRQ_D2H_REG_FIS
+
+/* PORT_SCR_STAT bits */
+#define PORT_SCR_STAT_DET_MASK	0x3
+#define PORT_SCR_STAT_DET_COMINIT 0x1
+#define PORT_SCR_STAT_DET_PHYRDY 0x3
+
+/* PORT_CMD bits */
+#define PORT_CMD_ATAPI		(1 << 24) /* Device is ATAPI */
+#define PORT_CMD_LIST_ON	(1 << 15) /* cmd list DMA engine running */
+#define PORT_CMD_FIS_ON		(1 << 14) /* FIS DMA engine running */
+#define PORT_CMD_FIS_RX		(1 << 4) /* Enable FIS receive DMA engine */
+#define PORT_CMD_CLO		(1 << 3) /* Command list override */
+#define PORT_CMD_POWER_ON	(1 << 2) /* Power up device */
+#define PORT_CMD_SPIN_UP	(1 << 1) /* Spin up device */
+#define PORT_CMD_START		(1 << 0) /* Enable port DMA engine */
+
+#define PORT_CMD_ICC_ACTIVE	(0x1 << 28) /* Put i/f in active state */
+#define PORT_CMD_ICC_PARTIAL	(0x2 << 28) /* Put i/f in partial state */
+#define PORT_CMD_ICC_SLUMBER	(0x6 << 28) /* Put i/f in slumber state */
+
+#define AHCI_MAX_PORTS		32
+
+#define ATA_FLAG_SATA		(1 << 3)
+#define ATA_FLAG_NO_LEGACY	(1 << 4) /* no legacy mode check */
+#define ATA_FLAG_MMIO		(1 << 6) /* use MMIO, not PIO */
+#define ATA_FLAG_SATA_RESET	(1 << 7) /* (obsolete) use COMRESET */
+#define ATA_FLAG_PIO_DMA	(1 << 8) /* PIO cmds via DMA */
+#define ATA_FLAG_NO_ATAPI	(1 << 11) /* No ATAPI support */
+
+struct ahci_cmd_hdr {
+	u32	opts;
+	u32	status;
+	u32	tbl_addr;
+	u32	tbl_addr_hi;
+	u32	reserved[4];
+};
+
+struct ahci_sg {
+	u32	addr;
+	u32	addr_hi;
+	u32	reserved;
+	u32	flags_size;
+};
+
+struct ahci_ioports {
+	void __iomem	*cmd_addr;
+	void __iomem	*scr_addr;
+	void __iomem	*port_mmio;
+	struct ahci_cmd_hdr	*cmd_slot;
+	struct ahci_sg		*cmd_tbl_sg;
+	ulong	cmd_tbl;
+	u32	rx_fis;
+};
+
+struct ahci_probe_ent {
+#ifdef CONFIG_DM_PCI
+	struct udevice *dev;
+#else
+	pci_dev_t	dev;
+#endif
+	struct ahci_ioports	port[AHCI_MAX_PORTS];
+	u32	n_ports;
+	u32	hard_port_no;
+	u32	host_flags;
+	u32	host_set_flags;
+	void __iomem *mmio_base;
+	u32     pio_mask;
+	u32	udma_mask;
+	u32	flags;
+	u32	cap;	/* cache of HOST_CAP register */
+	u32	port_map; /* cache of HOST_PORTS_IMPL reg */
+	u32	link_port_map; /*linkup port map*/
+};
+
+int ahci_init(void __iomem *base);
+int ahci_reset(void __iomem *base);
+
+#endif

u-boot/include/ali512x.h

@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_IC_ALI512X_H_
+#define __ASM_IC_ALI512X_H_
+
+# define ALI_INDEX    0x3f0
+# define ALI_DATA     0x3f1
+
+# define ALI_ENABLED  1
+# define ALI_DISABLED 0
+
+# define ALI_UART1    0
+# define ALI_UART2    1
+
+/* setup functions */
+void ali512x_init(void);
+void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel);
+void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel);
+void ali512x_set_uart(int enabled, int index, u16 io, u8 irq);
+void ali512x_set_rtc(int enabled, u16 io, u8 irq);
+void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq);
+void ali512x_set_cio(int enabled);
+
+
+/* common I/O functions */
+void ali512x_cio_function(int pin, int special, int inv, int input);
+void ali512x_cio_out(int pin, int value);
+int ali512x_cio_in(int pin);
+
+/* misc features */
+void ali512x_set_uart2_irda(int enabled);
+
+#endif

u-boot/include/altera.h

@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <fpga.h>
+
+#ifndef _ALTERA_H_
+#define _ALTERA_H_
+
+/*
+ * For the StratixV FPGA programming via SPI, the following
+ * information is coded in the 32bit cookie:
+ * Bit 31 ... Bit 0
+ * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
+ */
+#define FPGA_COOKIE(bus, dev, config, done)			\
+	(((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done))
+#define COOKIE2SPI_BUS(c)	(((c) >> 24) & 0xff)
+#define COOKIE2SPI_DEV(c)	(((c) >> 16) & 0xff)
+#define COOKIE2CONFIG(c)	(((c) >> 8) & 0xff)
+#define COOKIE2DONE(c)		((c) & 0xff)
+
+enum altera_iface {
+	/* insert all new types after this */
+	min_altera_iface_type,
+	/* serial data and external clock */
+	passive_serial,
+	/* parallel data */
+	passive_parallel_synchronous,
+	/* parallel data */
+	passive_parallel_asynchronous,
+	/* serial data w/ internal clock (not used) */
+	passive_serial_asynchronous,
+	/* jtag/tap serial (not used ) */
+	altera_jtag_mode,
+	/* fast passive parallel (FPP) */
+	fast_passive_parallel,
+	/* fast passive parallel with security (FPPS) */
+	fast_passive_parallel_security,
+	/* insert all new types before this */
+	max_altera_iface_type,
+};
+
+enum altera_family {
+	/* insert all new types after this */
+	min_altera_type,
+	/* ACEX1K Family */
+	Altera_ACEX1K,
+	/* CYCLONII Family */
+	Altera_CYC2,
+	/* StratixII Family */
+	Altera_StratixII,
+	/* StratixV Family */
+	Altera_StratixV,
+	/* SoCFPGA Family */
+	Altera_SoCFPGA,
+
+	/* Add new models here */
+
+	/* insert all new types before this */
+	max_altera_type,
+};
+
+typedef struct {
+	/* part type */
+	enum altera_family	family;
+	/* interface type */
+	enum altera_iface	iface;
+	/* bytes of data part can accept */
+	size_t			size;
+	/* interface function table */
+	void			*iface_fns;
+	/* base interface address */
+	void			*base;
+	/* implementation specific cookie */
+	int			cookie;
+} Altera_desc;
+
+/* Generic Altera Functions
+ *********************************************************************/
+extern int altera_load(Altera_desc *desc, const void *image, size_t size);
+extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int altera_info(Altera_desc *desc);
+
+/* Board specific implementation specific function types
+ *********************************************************************/
+typedef int (*Altera_pre_fn)( int cookie );
+typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
+typedef int (*Altera_status_fn)( int cookie );
+typedef int (*Altera_done_fn)( int cookie );
+typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
+typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
+typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie);
+typedef int (*Altera_abort_fn)( int cookie );
+typedef int (*Altera_post_fn)( int cookie );
+
+typedef struct {
+	Altera_pre_fn pre;
+	Altera_config_fn config;
+	Altera_status_fn status;
+	Altera_done_fn done;
+	Altera_clk_fn clk;
+	Altera_data_fn data;
+	Altera_write_fn write;
+	Altera_abort_fn abort;
+	Altera_post_fn post;
+} altera_board_specific_func;
+
+#ifdef CONFIG_FPGA_SOCFPGA
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+#endif
+
+#ifdef CONFIG_FPGA_STRATIX_V
+int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+#endif
+
+#endif /* _ALTERA_H_ */

u-boot/include/ambapp.h

@@ -0,0 +1,225 @@
+/* Interface for accessing Gaisler AMBA Plug&Play Bus.
+ * The AHB bus can be interfaced with a simpler bus -
+ * the APB bus, also freely available in GRLIB at
+ * www.gaisler.com.
+ *
+ * (C) Copyright 2009, 2015
+ * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AMBAPP_H__
+#define __AMBAPP_H__
+
+#include <ambapp_ids.h>
+
+#ifndef __ASSEMBLER__
+/* Structures used to access Plug&Play information directly */
+struct ambapp_pnp_ahb {
+	const unsigned int	id;		/* VENDOR, DEVICE, VER, IRQ, */
+	const unsigned int	custom[3];
+	const unsigned int	mbar[4];	/* MASK, ADDRESS, TYPE,
+						 * CACHABLE/PREFETCHABLE */
+};
+
+struct ambapp_pnp_apb {
+	const unsigned int	id;		/* VENDOR, DEVICE, VER, IRQ, */
+	const unsigned int	iobar;		/* MASK, ADDRESS, TYPE,
+						 * CACHABLE/PREFETCHABLE */
+};
+
+/* AMBA Plug&Play AHB Masters & Slaves information locations
+ * Max devices is 64 supported by HW, however often only 16
+ * are used.
+ */
+struct ambapp_pnp_info {
+	struct ambapp_pnp_ahb	masters[64];
+	struct ambapp_pnp_ahb	slaves[63];
+	const unsigned int	unused[4];
+	const unsigned int	systemid[4];
+};
+
+/* Describes a AMBA PnP bus */
+struct ambapp_bus {
+	int		buses;		/* Number of buses */
+	unsigned int	ioareas[6];	/* PnP I/O AREAs of AHB buses */
+	unsigned int	freq;		/* Frequency of bus0 [Hz] */
+};
+
+/* Processor Local AMBA bus */
+extern struct ambapp_bus ambapp_plb;
+
+/* Get Bus frequency of a certain AMBA bus */
+extern unsigned int ambapp_bus_freq(
+	struct ambapp_bus *abus,
+	int ahb_bus_index
+	);
+
+/* AMBA PnP information of a APB Device */
+typedef struct {
+	unsigned int vendor;
+	unsigned int device;
+	unsigned char irq;
+	unsigned char ver;
+	unsigned int address;
+	unsigned int mask;
+	int ahb_bus_index;
+} ambapp_apbdev;
+
+/* AMBA PnP information of a AHB Device */
+typedef struct {
+	unsigned int vendor;
+	unsigned int device;
+	unsigned char irq;
+	unsigned char ver;
+	unsigned int userdef[3];
+	unsigned int address[4];
+	unsigned int mask[4];
+	int type[4];
+	int ahb_bus_index;
+} ambapp_ahbdev;
+
+/* Scan AMBA Bus for AHB Bridges */
+extern void ambapp_bus_init(
+	unsigned int ioarea,
+	unsigned int freq,
+	struct ambapp_bus *abus);
+
+/* Find APB Slave device by index using breath first search.
+ *
+ * When vendor and device are both set to zero, any device
+ * with a non-zero device ID will match the search. It may be
+ * useful when processing all devices on a AMBA bus.
+ */
+extern int ambapp_apb_find(
+	struct ambapp_bus *abus,
+	int vendor,
+	int device,
+	int index,
+	ambapp_apbdev *dev
+	);
+
+/* Find AHB Master device by index using breath first search.
+ *
+ * When vendor and device are both set to zero, any device
+ * with a non-zero device ID will match the search. It may be
+ * useful when processing all devices on a AMBA bus.
+ */
+extern int ambapp_ahbmst_find(
+	struct ambapp_bus *abus,
+	int vendor,
+	int device,
+	int index,
+	ambapp_ahbdev *dev
+	);
+
+/* Find AHB Slave device by index using breath first search.
+ *
+ * When vendor and device are both set to zero, any device
+ * with a non-zero device ID will match the search. It may be
+ * useful when processing all devices on a AMBA bus.
+ */
+extern int ambapp_ahbslv_find(
+	struct ambapp_bus *abus,
+	int vendor,
+	int device,
+	int index,
+	ambapp_ahbdev *dev
+	);
+
+/* Return number of APB Slave devices of a certain ID (VENDOR:DEVICE)
+ * zero is returned if no devices was found.
+ */
+extern int ambapp_apb_count(struct ambapp_bus *abus, int vendor, int device);
+
+/* Return number of AHB Master devices of a certain ID (VENDOR:DEVICE)
+ * zero is returned if no devices was found.
+ */
+extern int ambapp_ahbmst_count(struct ambapp_bus *abus, int vendor, int device);
+
+/* Return number of AHB Slave devices of a certain ID (VENDOR:DEVICE)
+ * zero is returned if no devices was found.
+ */
+extern int ambapp_ahbslv_count(struct ambapp_bus *abus, int vendor, int device);
+
+#ifdef CONFIG_CMD_AMBAPP
+
+/* AMBA Plug&Play relocation & initialization */
+int ambapp_init_reloc(void);
+
+/* AMBA Plug&Play Name of Vendors and devices */
+
+/* Return name of device */
+char *ambapp_device_id2str(int vendor, int id);
+
+/* Return name of vendor */
+char *ambapp_vendor_id2str(int vendor);
+
+/* Return description of a device */
+char *ambapp_device_id2desc(int vendor, int id);
+
+#endif
+
+#endif /* defined(__ASSEMBLER__) */
+
+#define AMBA_DEFAULT_IOAREA 0xfff00000
+#define AMBA_CONF_AREA 0xff000
+#define AMBA_AHB_SLAVE_CONF_AREA 0x800
+
+#define DEV_NONE	0
+#define DEV_AHB_MST	1
+#define DEV_AHB_SLV	2
+#define DEV_APB_SLV	3
+
+#define AMBA_TYPE_APBIO 0x1
+#define AMBA_TYPE_MEM 0x2
+#define AMBA_TYPE_AHBIO 0x3
+
+/* ID layout for APB and AHB devices */
+#define AMBA_PNP_ID(vendor, device) (((vendor)<<24) | ((device)<<12))
+
+/* APB Slave PnP layout definitions */
+#define AMBA_APB_ID_OFS		(0*4)
+#define AMBA_APB_IOBAR_OFS	(1*4)
+#define AMBA_APB_CONF_LENGH	(2*4)
+
+/* AHB Master/Slave layout PnP definitions */
+#define AMBA_AHB_ID_OFS		(0*4)
+#define AMBA_AHB_CUSTOM0_OFS	(1*4)
+#define AMBA_AHB_CUSTOM1_OFS	(2*4)
+#define AMBA_AHB_CUSTOM2_OFS	(3*4)
+#define AMBA_AHB_MBAR0_OFS	(4*4)
+#define AMBA_AHB_MBAR1_OFS	(5*4)
+#define AMBA_AHB_MBAR2_OFS	(6*4)
+#define AMBA_AHB_MBAR3_OFS	(7*4)
+#define AMBA_AHB_CONF_LENGH	(8*4)
+
+/* Macros for extracting information from AMBA PnP information
+ * registers.
+ */
+
+#define amba_vendor(x) (((x) >> 24) & 0xff)
+
+#define amba_device(x) (((x) >> 12) & 0xfff)
+
+#define amba_irq(conf) ((conf) & 0x1f)
+
+#define amba_ver(conf) (((conf)>>5) & 0x1f)
+
+#define amba_iobar_start(base, iobar) \
+	((base) | ((((iobar) & 0xfff00000)>>12) & (((iobar) & 0xfff0)<<4)))
+
+#define amba_membar_start(mbar) \
+	(((mbar) & 0xfff00000) & (((mbar) & 0xfff0) << 16))
+
+#define amba_membar_type(mbar) ((mbar) & 0xf)
+
+#define amba_membar_mask(mbar) (((mbar) >> 4) & 0xfff)
+
+#define amba_ahbio_adr(addr, base_ioarea) \
+	((unsigned int)(base_ioarea) | ((addr) >> 12))
+
+#define amba_apb_mask(iobar) ((~(amba_membar_mask(iobar)<<8) & 0x000fffff) + 1)
+
+#endif

u-boot/include/ambapp_ids.h

@@ -0,0 +1,250 @@
+/* AMBA Plug & Play Bus Vendor and Device IDs.
+ *
+ * (C) Copyright 2010, 2015
+ * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __AMBAPP_IDS_H__
+#define __AMBAPP_IDS_H__
+
+/* Vendor ID defines */
+#define VENDOR_GAISLER       0x01
+#define VENDOR_PENDER        0x02
+#define VENDOR_ESA           0x04
+#define VENDOR_ASTRIUM       0x06
+#define VENDOR_OPENCHIP      0x07
+#define VENDOR_OPENCORES     0x08
+#define VENDOR_CONTRIB       0x09
+#define VENDOR_EONIC         0x0b
+#define VENDOR_RADIONOR      0x0f
+#define VENDOR_GLEICHMANN    0x10
+#define VENDOR_MENTA         0x11
+#define VENDOR_SUN           0x13
+#define VENDOR_MOVIDIA       0x14
+#define VENDOR_ORBITA        0x17
+#define VENDOR_SYNOPSYS      0x21
+#define VENDOR_NASA          0x22
+#define VENDOR_S3            0x31
+#define VENDOR_CAL           0xca
+#define VENDOR_EMBEDDIT      0xea
+#define VENDOR_CETON         0xcb
+#define VENDOR_ACTEL         0xac
+#define VENDOR_APPLECORE     0xae
+
+/* Aeroflex Gaisler device ID defines */
+#define GAISLER_LEON2DSU     0x002
+#define GAISLER_LEON3        0x003
+#define GAISLER_LEON3DSU     0x004
+#define GAISLER_ETHAHB       0x005
+#define GAISLER_APBMST       0x006
+#define GAISLER_AHBUART      0x007
+#define GAISLER_SRCTRL       0x008
+#define GAISLER_SDCTRL       0x009
+#define GAISLER_SSRCTRL      0x00a
+#define GAISLER_APBUART      0x00c
+#define GAISLER_IRQMP        0x00d
+#define GAISLER_AHBRAM       0x00e
+#define GAISLER_AHBDPRAM     0x00f
+#define GAISLER_GPTIMER      0x011
+#define GAISLER_PCITRG       0x012
+#define GAISLER_PCISBRG      0x013
+#define GAISLER_PCIFBRG      0x014
+#define GAISLER_PCITRACE     0x015
+#define GAISLER_DMACTRL      0x016
+#define GAISLER_AHBTRACE     0x017
+#define GAISLER_DSUCTRL      0x018
+#define GAISLER_CANAHB       0x019
+#define GAISLER_GPIO         0x01a
+#define GAISLER_AHBROM       0x01b
+#define GAISLER_AHBJTAG      0x01c
+#define GAISLER_ETHMAC       0x01d
+#define GAISLER_SWNODE       0x01e
+#define GAISLER_SPW          0x01f
+#define GAISLER_AHB2AHB      0x020
+#define GAISLER_USBDC        0x021
+#define GAISLER_USB_DCL      0x022
+#define GAISLER_DDRMP        0x023
+#define GAISLER_ATACTRL      0x024
+#define GAISLER_DDRSP        0x025
+#define GAISLER_EHCI         0x026
+#define GAISLER_UHCI         0x027
+#define GAISLER_I2CMST       0x028
+#define GAISLER_SPW2         0x029
+#define GAISLER_AHBDMA       0x02a
+#define GAISLER_NUHOSP3      0x02b
+#define GAISLER_CLKGATE      0x02c
+#define GAISLER_SPICTRL      0x02d
+#define GAISLER_DDR2SP       0x02e
+#define GAISLER_SLINK        0x02f
+#define GAISLER_GRTM         0x030
+#define GAISLER_GRTC         0x031
+#define GAISLER_GRPW         0x032
+#define GAISLER_GRCTM        0x033
+#define GAISLER_GRHCAN       0x034
+#define GAISLER_GRFIFO       0x035
+#define GAISLER_GRADCDAC     0x036
+#define GAISLER_GRPULSE      0x037
+#define GAISLER_GRTIMER      0x038
+#define GAISLER_AHB2PP       0x039
+#define GAISLER_GRVERSION    0x03a
+#define GAISLER_APB2PW       0x03b
+#define GAISLER_PW2APB       0x03c
+#define GAISLER_GRCAN        0x03d
+#define GAISLER_I2CSLV       0x03e
+#define GAISLER_U16550       0x03f
+#define GAISLER_AHBMST_EM    0x040
+#define GAISLER_AHBSLV_EM    0x041
+#define GAISLER_GRTESTMOD    0x042
+#define GAISLER_ASCS         0x043
+#define GAISLER_IPMVBCTRL    0x044
+#define GAISLER_SPIMCTRL     0x045
+#define GAISLER_L4STAT       0x047
+#define GAISLER_LEON4        0x048
+#define GAISLER_LEON4DSU     0x049
+#define GAISLER_PWM          0x04a
+#define GAISLER_L2CACHE      0x04b
+#define GAISLER_SDCTRL64     0x04c
+#define GAISLER_GR1553B      0x04d
+#define GAISLER_1553TST      0x04e
+#define GAISLER_GRIOMMU      0x04f
+#define GAISLER_FTAHBRAM     0x050
+#define GAISLER_FTSRCTRL     0x051
+#define GAISLER_AHBSTAT      0x052
+#define GAISLER_LEON3FT      0x053
+#define GAISLER_FTMCTRL      0x054
+#define GAISLER_FTSDCTRL     0x055
+#define GAISLER_FTSRCTRL8    0x056
+#define GAISLER_MEMSCRUB     0x057
+#define GAISLER_FTSDCTRL64   0x058
+#define GAISLER_APBPS2       0x060
+#define GAISLER_VGACTRL      0x061
+#define GAISLER_LOGAN        0x062
+#define GAISLER_SVGACTRL     0x063
+#define GAISLER_T1AHB        0x064
+#define GAISLER_MP7WRAP      0x065
+#define GAISLER_GRSYSMON     0x066
+#define GAISLER_GRACECTRL    0x067
+#define GAISLER_ATAHBSLV     0x068
+#define GAISLER_ATAHBMST     0x069
+#define GAISLER_ATAPBSLV     0x06a
+#define GAISLER_B1553BC      0x070
+#define GAISLER_B1553RT      0x071
+#define GAISLER_B1553BRM     0x072
+#define GAISLER_AES          0x073
+#define GAISLER_ECC          0x074
+#define GAISLER_PCIF         0x075
+#define GAISLER_CLKMOD       0x076
+#define GAISLER_HAPSTRAK     0x077
+#define GAISLER_TEST_1X2     0x078
+#define GAISLER_WILD2AHB     0x079
+#define GAISLER_BIO1         0x07a
+#define GAISLER_AESDMA       0x07b
+#define GAISLER_SATCAN       0x080
+#define GAISLER_CANMUX       0x081
+#define GAISLER_GRTMRX       0x082
+#define GAISLER_GRTCTX       0x083
+#define GAISLER_GRTMDESC     0x084
+#define GAISLER_GRTMVC       0x085
+#define GAISLER_GEFFE        0x086
+#define GAISLER_GPREG        0x087
+#define GAISLER_GRTMPAHB     0x088
+#define GAISLER_SPWCUC       0x089
+#define GAISLER_SPW2_DMA     0x08a
+#define GAISLER_SPWROUTER    0x08b
+
+/* European Space Agency device ID defines */
+#define ESA_LEON2            0x002
+#define ESA_LEON2APB         0x003
+#define ESA_IRQ              0x005
+#define ESA_TIMER            0x006
+#define ESA_UART             0x007
+#define ESA_CFG              0x008
+#define ESA_IO               0x009
+#define ESA_MCTRL            0x00f
+#define ESA_PCIARB           0x010
+#define ESA_HURRICANE        0x011
+#define ESA_SPW_RMAP         0x012
+#define ESA_AHBUART          0x013
+#define ESA_SPWA             0x014
+#define ESA_BOSCHCAN         0x015
+#define ESA_IRQ2             0x016
+#define ESA_AHBSTAT          0x017
+#define ESA_WPROT            0x018
+#define ESA_WPROT2           0x019
+#define ESA_PDEC3AMBA        0x020
+#define ESA_PTME3AMBA        0x021
+
+/* OpenChip device ID defines */
+#define OPENCHIP_APBGPIO     0x001
+#define OPENCHIP_APBI2C      0x002
+#define OPENCHIP_APBSPI      0x003
+#define OPENCHIP_APBCHARLCD  0x004
+#define OPENCHIP_APBPWM      0x005
+#define OPENCHIP_APBPS2      0x006
+#define OPENCHIP_APBMMCSD    0x007
+#define OPENCHIP_APBNAND     0x008
+#define OPENCHIP_APBLPC      0x009
+#define OPENCHIP_APBCF       0x00a
+#define OPENCHIP_APBSYSACE   0x00b
+#define OPENCHIP_APB1WIRE    0x00c
+#define OPENCHIP_APBJTAG     0x00d
+#define OPENCHIP_APBSUI      0x00e
+
+/* Various contributions device ID defines */
+#define CONTRIB_CORE1        0x001
+#define CONTRIB_CORE2        0x002
+
+/* Gleichmann Electronics device ID defines */
+#define GLEICHMANN_CUSTOM    0x001
+#define GLEICHMANN_GEOLCD01  0x002
+#define GLEICHMANN_DAC       0x003
+#define GLEICHMANN_HPI       0x004
+#define GLEICHMANN_SPI       0x005
+#define GLEICHMANN_HIFC      0x006
+#define GLEICHMANN_ADCDAC    0x007
+#define GLEICHMANN_SPIOC     0x008
+#define GLEICHMANN_AC97      0x009
+
+/* Sun Microsystems device ID defines */
+#define SUN_T1               0x001
+#define SUN_S1               0x011
+
+/* Orbita device ID defines */
+#define ORBITA_1553B         0x001
+#define ORBITA_429           0x002
+#define ORBITA_SPI           0x003
+#define ORBITA_I2C           0x004
+#define ORBITA_SMARTCARD     0x064
+#define ORBITA_SDCARD        0x065
+#define ORBITA_UART16550     0x066
+#define ORBITA_CRYPTO        0x067
+#define ORBITA_SYSIF         0x068
+#define ORBITA_PIO           0x069
+#define ORBITA_RTC           0x0c8
+#define ORBITA_COLORLCD      0x12c
+#define ORBITA_PCI           0x190
+#define ORBITA_DSP           0x1f4
+#define ORBITA_USBHOST       0x258
+#define ORBITA_USBDEV        0x2bc
+
+/* NASA device ID defines */
+#define NASA_EP32            0x001
+
+/* CAL device ID defines */
+#define CAL_DDRCTRL          0x188
+
+/* Actel Corporation device ID defines */
+#define ACTEL_COREMP7        0x001
+
+/* AppleCore device ID defines */
+#define APPLECORE_UTLEON3    0x001
+#define APPLECORE_UTLEON3DSU 0x002
+
+/* Opencores device id's */
+#define OPENCORES_PCIBR  0x4
+#define OPENCORES_ETHMAC 0x5
+
+#endif

u-boot/include/andestech/andes_pcu.h

@@ -0,0 +1,355 @@
+/*
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Andes Power Control Unit
+ */
+#ifndef __ANDES_PCU_H
+#define __ANDES_PCU_H
+
+#ifndef __ASSEMBLY__
+
+struct pcs {
+	unsigned int	cr;		/* PCSx Configuration (clock scaling) */
+	unsigned int	parm;		/* PCSx Parameter*/
+	unsigned int	stat1;		/* PCSx Status 1 */
+	unsigned int	stat2;		/* PCSx Stusts 2 */
+	unsigned int	pdd;		/* PCSx PDD */
+};
+
+struct andes_pcu {
+	unsigned int	rev;		/* 0x00 - PCU Revision */
+	unsigned int	spinfo;		/* 0x04 - Scratch Pad Info */
+	unsigned int	rsvd1[2];	/* 0x08-0x0C: Reserved */
+	unsigned int	soc_id;		/* 0x10 - SoC ID */
+	unsigned int	soc_ahb;	/* 0x14 - SoC AHB configuration */
+	unsigned int	soc_apb;	/* 0x18 - SoC APB configuration */
+	unsigned int	rsvd2;		/* 0x1C */
+	unsigned int	dcsrcr0;	/* 0x20 - Driving Capability
+						and Slew Rate Control 0 */
+	unsigned int	dcsrcr1;	/* 0x24 - Driving Capability
+						and Slew Rate Control 1 */
+	unsigned int	dcsrcr2;	/* 0x28 - Driving Capability
+						and Slew Rate Control 2 */
+	unsigned int	rsvd3;		/* 0x2C */
+	unsigned int	mfpsr0;		/* 0x30 - Multi-Func Port Setting 0 */
+	unsigned int	mfpsr1;		/* 0x34 - Multi-Func Port Setting 1 */
+	unsigned int	dmaes;		/* 0x38 - DMA Engine Selection */
+	unsigned int	rsvd4;		/* 0x3C */
+	unsigned int	oscc;		/* 0x40 - OSC Control */
+	unsigned int	pwmcd;		/* 0x44 - PWM Clock divider */
+	unsigned int	socmisc;	/* 0x48 - SoC Misc. */
+	unsigned int	rsvd5[13];	/* 0x4C-0x7C: Reserved */
+	unsigned int	bsmcr;		/* 0x80 - BSM Controrl */
+	unsigned int	bsmst;		/* 0x84 - BSM Status */
+	unsigned int	wes;		/* 0x88 - Wakeup Event Sensitivity*/
+	unsigned int	west;		/* 0x8C - Wakeup Event Status */
+	unsigned int	rsttiming;	/* 0x90 - Reset Timing  */
+	unsigned int	intr_st;	/* 0x94 - PCU Interrupt Status */
+	unsigned int	rsvd6[2];	/* 0x98-0x9C: Reserved */
+	struct pcs	pcs1;		/* 0xA0-0xB0: PCS1 (clock scaling) */
+	unsigned int	pcsrsvd1[3];	/* 0xB4-0xBC: Reserved */
+	struct pcs	pcs2;		/* 0xC0-0xD0: PCS2 (AHB clock gating) */
+	unsigned int	pcsrsvd2[3];	/* 0xD4-0xDC: Reserved */
+	struct pcs	pcs3;		/* 0xE0-0xF0: PCS3 (APB clock gating) */
+	unsigned int	pcsrsvd3[3];	/* 0xF4-0xFC: Reserved */
+	struct pcs	pcs4;		/* 0x100-0x110: PCS4 main PLL scaling */
+	unsigned int	pcsrsvd4[3];	/* 0x114-0x11C: Reserved */
+	struct pcs	pcs5;		/* 0x120-0x130: PCS5 PCI PLL scaling */
+	unsigned int	pcsrsvd5[3];	/* 0x134-0x13C: Reserved */
+	struct pcs	pcs6;		/* 0x140-0x150: PCS6 AC97 PLL scaling */
+	unsigned int	pcsrsvd6[3];	/* 0x154-0x15C: Reserved */
+	struct pcs	pcs7;		/* 0x160-0x170: PCS7 GMAC PLL scaling */
+	unsigned int	pcsrsvd7[3];	/* 0x174-0x17C: Reserved */
+	struct pcs	pcs8;		/* 0x180-0x190: PCS8 voltage scaling */
+	unsigned int	pcsrsvd8[3];	/* 0x194-0x19C: Reserved */
+	struct pcs	pcs9;		/* 0x1A0-0x1B0: PCS9 power control */
+	unsigned int	pcsrsvd9[93];	/* 0x1B4-0x3FC: Reserved */
+	unsigned int	pmspdm[40];	/* 0x400-0x4fC: Power Manager
+							Scratch Pad Memory 0 */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * PCU Revision Register (ro)
+ */
+#define ANDES_PCU_REV_NUMBER_PCS(x)	(((x) >> 0) & 0xff)
+#define ANDES_PCU_REV_VER(x)		(((x) >> 16) & 0xffff)
+
+/*
+ * Scratch Pad Info Register (ro)
+ */
+#define ANDES_PCU_SPINFO_SIZE(x)	(((x) >> 0) & 0xff)
+#define ANDES_PCU_SPINFO_OFFSET(x)	(((x) >> 8) & 0xf)
+
+/*
+ * SoC ID Register (ro)
+ */
+#define ANDES_PCU_SOC_ID_VER_MINOR(x)	(((x) >> 0) & 0xf)
+#define ANDES_PCU_SOC_ID_VER_MAJOR(x)	(((x) >> 4) & 0xfff)
+#define ANDES_PCU_SOC_ID_DEVICEID(x)	(((x) >> 16) & 0xffff)
+
+/*
+ * SoC AHB Configuration Register (ro)
+ */
+#define ANDES_PCU_SOC_AHB_AHBC(x)		((x) << 0)
+#define ANDES_PCU_SOC_AHB_APBREG(x)		((x) << 1)
+#define ANDES_PCU_SOC_AHB_APB(x)		((x) << 2)
+#define ANDES_PCU_SOC_AHB_DLM1(x)		((x) << 3)
+#define ANDES_PCU_SOC_AHB_SPIROM(x)		((x) << 4)
+#define ANDES_PCU_SOC_AHB_DDR2C(x)		((x) << 5)
+#define ANDES_PCU_SOC_AHB_DDR2MEM(x)		((x) << 6)
+#define ANDES_PCU_SOC_AHB_DMAC(x)		((x) << 7)
+#define ANDES_PCU_SOC_AHB_DLM2(x)		((x) << 8)
+#define ANDES_PCU_SOC_AHB_GPU(x)		((x) << 9)
+#define ANDES_PCU_SOC_AHB_GMAC(x)		((x) << 12)
+#define ANDES_PCU_SOC_AHB_IDE(x)		((x) << 13)
+#define ANDES_PCU_SOC_AHB_USBOTG(x)		((x) << 14)
+#define ANDES_PCU_SOC_AHB_INTC(x)		((x) << 15)
+#define ANDES_PCU_SOC_AHB_LPCIO(x)		((x) << 16)
+#define ANDES_PCU_SOC_AHB_LPCREG(x)		((x) << 17)
+#define ANDES_PCU_SOC_AHB_PCIIO(x)		((x) << 18)
+#define ANDES_PCU_SOC_AHB_PCIMEM(x)		((x) << 19)
+#define ANDES_PCU_SOC_AHB_L2CC(x)		((x) << 20)
+#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x)		((x) << 27)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x)	((x) << 28)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x)	((x) << 29)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x)	((x) << 30)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x)	((x) << 31)
+
+/*
+ * SoC APB Configuration Register (ro)
+ */
+#define ANDES_PCU_SOC_APB_CFC(x)	((x) << 1)
+#define ANDES_PCU_SOC_APB_SSP(x)	((x) << 2)
+#define ANDES_PCU_SOC_APB_UART1(x)	((x) << 3)
+#define ANDES_PCU_SOC_APB_SDC(x)	((x) << 5)
+#define ANDES_PCU_SOC_APB_AC97I2S(x)	((x) << 6)
+#define ANDES_PCU_SOC_APB_UART2(x)	((x) << 8)
+#define ANDES_PCU_SOC_APB_PCU(x)	((x) << 16)
+#define ANDES_PCU_SOC_APB_TMR(x)	((x) << 17)
+#define ANDES_PCU_SOC_APB_WDT(x)	((x) << 18)
+#define ANDES_PCU_SOC_APB_RTC(x)	((x) << 19)
+#define ANDES_PCU_SOC_APB_GPIO(x)	((x) << 20)
+#define ANDES_PCU_SOC_APB_I2C(x)	((x) << 22)
+#define ANDES_PCU_SOC_APB_PWM(x)	((x) << 23)
+
+/*
+ * Driving Capability and Slew Rate Control Register 0 (rw)
+ */
+#define ANDES_PCU_DCSRCR0_TRIAHB(x)	(((x) & 0x1f) << 0)
+#define ANDES_PCU_DCSRCR0_LPC(x)	(((x) & 0xf) << 8)
+#define ANDES_PCU_DCSRCR0_ULPI(x)	(((x) & 0xf) << 12)
+#define ANDES_PCU_DCSRCR0_GMAC(x)	(((x) & 0xf) << 16)
+#define ANDES_PCU_DCSRCR0_GPU(x)	(((x) & 0xf) << 20)
+
+/*
+ * Driving Capability and Slew Rate Control Register 1 (rw)
+ */
+#define ANDES_PCU_DCSRCR1_I2C(x)	(((x) & 0xf) << 0)
+
+/*
+ * Driving Capability and Slew Rate Control Register 2 (rw)
+ */
+#define ANDES_PCU_DCSRCR2_UART1(x)	(((x) & 0xf) << 0)
+#define ANDES_PCU_DCSRCR2_UART2(x)	(((x) & 0xf) << 4)
+#define ANDES_PCU_DCSRCR2_AC97(x)	(((x) & 0xf) << 8)
+#define ANDES_PCU_DCSRCR2_SPI(x)	(((x) & 0xf) << 12)
+#define ANDES_PCU_DCSRCR2_SD(x)		(((x) & 0xf) << 16)
+#define ANDES_PCU_DCSRCR2_CFC(x)	(((x) & 0xf) << 20)
+#define ANDES_PCU_DCSRCR2_GPIO(x)	(((x) & 0xf) << 24)
+#define ANDES_PCU_DCSRCR2_PCU(x)	(((x) & 0xf) << 28)
+
+/*
+ * Multi-function Port Setting Register 0 (rw)
+ */
+#define ANDES_PCU_MFPSR0_PCIMODE(x)		((x) << 0)
+#define ANDES_PCU_MFPSR0_IDEMODE(x)		((x) << 1)
+#define ANDES_PCU_MFPSR0_MINI_TC01(x)		((x) << 2)
+#define ANDES_PCU_MFPSR0_AHB_DEBUG(x)		((x) << 3)
+#define ANDES_PCU_MFPSR0_AHB_TARGET(x)		((x) << 4)
+#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x)		(((x) & 0x7) << 28)
+#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x)	((x) << 31)
+
+/*
+ * Multi-function Port Setting Register 1 (rw)
+ */
+#define ANDES_PCU_MFPSR1_SUSPEND(x)		((x) << 0)
+#define ANDES_PCU_MFPSR1_PWM0(x)		((x) << 1)
+#define ANDES_PCU_MFPSR1_PWM1(x)		((x) << 2)
+#define ANDES_PCU_MFPSR1_AC97CLKOUT(x)		((x) << 3)
+#define ANDES_PCU_MFPSR1_PWREN(x)		((x) << 4)
+#define ANDES_PCU_MFPSR1_PME(x)			((x) << 5)
+#define ANDES_PCU_MFPSR1_I2C(x)			((x) << 6)
+#define ANDES_PCU_MFPSR1_UART1(x)		((x) << 7)
+#define ANDES_PCU_MFPSR1_UART2(x)		((x) << 8)
+#define ANDES_PCU_MFPSR1_SPI(x)			((x) << 9)
+#define ANDES_PCU_MFPSR1_SD(x)			((x) << 10)
+#define ANDES_PCU_MFPSR1_GPUPLLSRC(x)		((x) << 27)
+#define ANDES_PCU_MFPSR1_DVOMODE(x)		((x) << 28)
+#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x)	((x) << 29)
+#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x)	((x) << 30)
+#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x)	((x) << 31)
+
+/*
+ * DMA Engine Selection Register (rw)
+ */
+#define ANDES_PCU_DMAES_AC97RX(x)		((x) << 2)
+#define ANDES_PCU_DMAES_AC97TX(x)		((x) << 3)
+#define ANDES_PCU_DMAES_UART1RX(x)		((x) << 4)
+#define ANDES_PCU_DMAES_UART1TX(x)		((x) << 5)
+#define ANDES_PCU_DMAES_UART2RX(x)		((x) << 6)
+#define ANDES_PCU_DMAES_UART2TX(x)		((x) << 7)
+#define ANDES_PCU_DMAES_SDDMA(x)		((x) << 8)
+#define ANDES_PCU_DMAES_CFCDMA(x)		((x) << 9)
+
+/*
+ * OSC Control Register (rw)
+ */
+#define ANDES_PCU_OSCC_OSCH_OFF(x)	((x) << 0)
+#define ANDES_PCU_OSCC_OSCH_STABLE(x)	((x) << 1)
+#define ANDES_PCU_OSCC_OSCH_TRI(x)	((x) << 2)
+#define ANDES_PCU_OSCC_OSCH_RANGE(x)	(((x) & 0x3) << 4)
+#define ANDES_PCU_OSCC_OSCH2_RANGE(x)	(((x) & 0x3) << 6)
+#define ANDES_PCU_OSCC_OSCH3_RANGE(x)	(((x) & 0x3) << 8)
+
+/*
+ * PWM Clock Divider Register (rw)
+ */
+#define ANDES_PCU_PWMCD_PWMDIV(x)	(((x) & 0xf) << 0)
+
+/*
+ * SoC Misc. Register (rw)
+ */
+#define ANDES_PCU_SOCMISC_RSCPUA(x)		((x) << 0)
+#define ANDES_PCU_SOCMISC_RSCPUB(x)		((x) << 1)
+#define ANDES_PCU_SOCMISC_RSPCI(x)		((x) << 2)
+#define ANDES_PCU_SOCMISC_USBWAKE(x)		((x) << 3)
+#define ANDES_PCU_SOCMISC_EXLM_WAITA(x)		(((x) & 0x3) << 4)
+#define ANDES_PCU_SOCMISC_EXLM_WAITB(x)		(((x) & 0x3) << 6)
+#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x)	(((x) << 8)
+#define ANDES_PCU_SOCMISC_300MHZSEL(x)		(((x) << 9)
+#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x)	(((x) << 10)
+#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x)	(((x) << 11)
+#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x)	(((x) << 12)
+#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x)	(((x) << 13)
+#define ANDES_PCU_SOCMISC_ENCPUA(x)		(((x) << 14)
+#define ANDES_PCU_SOCMISC_ENCPUB(x)		(((x) << 15)
+#define ANDES_PCU_SOCMISC_PWON_PWBTN(x)		(((x) << 16)
+#define ANDES_PCU_SOCMISC_PWON_GPIO1(x)		(((x) << 17)
+#define ANDES_PCU_SOCMISC_PWON_GPIO2(x)		(((x) << 18)
+#define ANDES_PCU_SOCMISC_PWON_GPIO3(x)		(((x) << 19)
+#define ANDES_PCU_SOCMISC_PWON_GPIO4(x)		(((x) << 20)
+#define ANDES_PCU_SOCMISC_PWON_GPIO5(x)		(((x) << 21)
+#define ANDES_PCU_SOCMISC_PWON_WOL(x)		(((x) << 22)
+#define ANDES_PCU_SOCMISC_PWON_RTC(x)		(((x) << 23)
+#define ANDES_PCU_SOCMISC_PWON_RTCALM(x)	(((x) << 24)
+#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x)	(((x) << 25)
+#define ANDES_PCU_SOCMISC_PWON_PME(x)		(((x) << 26)
+#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x)	(((x) << 27)
+#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x)	(((x) << 28)
+#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x)	(((x) << 29)
+#define ANDES_PCU_SOCMISC_WD_RESET(x)		(((x) << 30)
+#define ANDES_PCU_SOCMISC_HW_RESET(x)		(((x) << 31)
+
+/*
+ * BSM Control Register (rw)
+ */
+#define ANDES_PCU_BSMCR_LINK0(x)	(((x) & 0xf) << 0)
+#define ANDES_PCU_BSMCR_LINK1(x)	(((x) & 0xf) << 4)
+#define ANDES_PCU_BSMCR_SYNCSRC(x)	(((x) & 0xf) << 24)
+#define ANDES_PCU_BSMCR_CMD(x)		(((x) & 0x7) << 28)
+#define ANDES_PCU_BSMCR_IE(x)		((x) << 31)
+
+/*
+ * BSM Status Register
+ */
+#define ANDES_PCU_BSMSR_CI0(x)		(((x) & 0xf) << 0)
+#define ANDES_PCU_BSMSR_CI1(x)		(((x) & 0xf) << 4)
+#define ANDES_PCU_BSMSR_SYNCSRC(x)	(((x) & 0xf) << 24)
+#define ANDES_PCU_BSMSR_BSMST(x)	(((x) & 0xf) << 28)
+
+/*
+ * Wakeup Event Sensitivity Register (rw)
+ */
+#define ANDES_PCU_WESR_POLOR(x)		(((x) & 0xff) << 0)
+
+/*
+ * Wakeup Event Status Register (ro)
+ */
+#define ANDES_PCU_WEST_SIG(x)		(((x) & 0xff) << 0)
+
+/*
+ * Reset Timing Register
+ */
+#define ANDES_PCU_RSTTIMING_RG0(x)	(((x) & 0xff) << 0)
+#define ANDES_PCU_RSTTIMING_RG1(x)	(((x) & 0xff) << 8)
+#define ANDES_PCU_RSTTIMING_RG2(x)	(((x) & 0xff) << 16)
+#define ANDES_PCU_RSTTIMING_RG3(x)	(((x) & 0xff) << 24)
+
+/*
+ * PCU Interrupt Status Register
+ */
+#define ANDES_PCU_INTR_ST_BSM(x)	((x) << 0)
+#define ANDES_PCU_INTR_ST_PCS1(x)	((x) << 1)
+#define ANDES_PCU_INTR_ST_PCS2(x)	((x) << 2)
+#define ANDES_PCU_INTR_ST_PCS3(x)	((x) << 3)
+#define ANDES_PCU_INTR_ST_PCS4(x)	((x) << 4)
+#define ANDES_PCU_INTR_ST_PCS5(x)	((x) << 5)
+#define ANDES_PCU_INTR_ST_PCS6(x)	((x) << 6)
+#define ANDES_PCU_INTR_ST_PCS7(x)	((x) << 7)
+#define ANDES_PCU_INTR_ST_PCS8(x)	((x) << 8)
+#define ANDES_PCU_INTR_ST_PCS9(x)	((x) << 9)
+
+/*
+ * PCSx Configuration Register
+ */
+#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x)	(((x) & 0xff) << 0)
+#define ANDES_PCU_PCSX_CR_LW(x)		(((x) & 0xf) << 16)
+#define ANDES_PCU_PCSX_CR_LS(x)		(((x) & 0xf) << 20)
+#define ANDES_PCU_PCSX_CR_TYPE(x)	(((x) >> 28) & 0x7)	/* (ro) */
+
+/*
+ * PCSx Parameter Register (rw)
+ */
+#define ANDES_PCU_PCSX_PARM_NEXT(x)	(((x) & 0xffffff) << 0)
+#define ANDES_PCU_PCSX_PARM_SYNCSRC(x)	(((x) & 0xf) << 24)
+#define ANDES_PCU_PCSX_PARM_PCSCMD(x)	(((x) & 0x7) << 28)
+#define ANDES_PCU_PCSX_PARM_IE(x)	(((x) << 31)
+
+/*
+ * PCSx Status Register 1
+ */
+#define ANDES_PCU_PCSX_STAT1_ERRNO(x)	(((x) & 0xf) << 0)
+#define ANDES_PCU_PCSX_STAT1_ST(x)	(((x) & 0x7) << 28)
+
+/*
+ * PCSx Status Register 2
+ */
+#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x)	(((x) & 0xffffff) << 0)
+#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x)		(((x) & 0xf) << 24)
+
+/*
+ * PCSx PDD Register
+ * This is reserved for PCS(1-7)
+ */
+#define ANDES_PCU_PCS8_PDD_1BYTE(x)		(((x) & 0xff) << 0)
+#define ANDES_PCU_PCS8_PDD_2BYTE(x)		(((x) & 0xff) << 8)
+#define ANDES_PCU_PCS8_PDD_3BYTE(x)		(((x) & 0xff) << 16)
+#define ANDES_PCU_PCS8_PDD_4BYTE(x)		(((x) & 0xff) << 24)
+
+#define ANDES_PCU_PCS9_PDD_TIME1(x)		(((x) & 0x3f) << 0)
+#define ANDES_PCU_PCS9_PDD_TIME2(x)		(((x) & 0x3f) << 6)
+#define ANDES_PCU_PCS9_PDD_TIME3(x)		(((x) & 0x3f) << 12)
+#define ANDES_PCU_PCS9_PDD_TIME4(x)		(((x) & 0x3f) << 18)
+#define ANDES_PCU_PCS9_PDD_TICKTYPE(x)		((x) << 24)
+#define ANDES_PCU_PCS9_PDD_GPU_SRST(x)		((x) << 27)
+#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x)		(((x) & 0x3) << 28)
+#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x)		((x) << 30)
+#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x)	((x) << 31)
+
+#endif	/* __ANDES_PCU_H */

u-boot/include/android_image.h

@@ -0,0 +1,69 @@
+/*
+ * This is from the Android Project,
+ * Repository: https://android.googlesource.com/platform/bootable/bootloader/legacy
+ * File: include/boot/bootimg.h
+ * Commit: 4205b865141ff2e255fe1d3bd16de18e217ef06a
+ *
+ * Copyright (C) 2008 The Android Open Source Project
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#ifndef _ANDROID_IMAGE_H_
+#define _ANDROID_IMAGE_H_
+
+#define ANDR_BOOT_MAGIC "ANDROID!"
+#define ANDR_BOOT_MAGIC_SIZE 8
+#define ANDR_BOOT_NAME_SIZE 16
+#define ANDR_BOOT_ARGS_SIZE 512
+
+struct andr_img_hdr {
+	char magic[ANDR_BOOT_MAGIC_SIZE];
+
+	u32 kernel_size;	/* size in bytes */
+	u32 kernel_addr;	/* physical load addr */
+
+	u32 ramdisk_size;	/* size in bytes */
+	u32 ramdisk_addr;	/* physical load addr */
+
+	u32 second_size;	/* size in bytes */
+	u32 second_addr;	/* physical load addr */
+
+	u32 tags_addr;		/* physical addr for kernel tags */
+	u32 page_size;		/* flash page size we assume */
+	u32 unused[2];		/* future expansion: should be 0 */
+
+	char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */
+
+	char cmdline[ANDR_BOOT_ARGS_SIZE];
+
+	u32 id[8]; /* timestamp / checksum / sha1 / etc */
+};
+
+/*
+ * +-----------------+
+ * | boot header     | 1 page
+ * +-----------------+
+ * | kernel          | n pages
+ * +-----------------+
+ * | ramdisk         | m pages
+ * +-----------------+
+ * | second stage    | o pages
+ * +-----------------+
+ *
+ * n = (kernel_size + page_size - 1) / page_size
+ * m = (ramdisk_size + page_size - 1) / page_size
+ * o = (second_size + page_size - 1) / page_size
+ *
+ * 0. all entities are page_size aligned in flash
+ * 1. kernel and ramdisk are required (size != 0)
+ * 2. second is optional (second_size == 0 -> no second)
+ * 3. load each element (kernel, ramdisk, second) at
+ *    the specified physical address (kernel_addr, etc)
+ * 4. prepare tags at tag_addr.  kernel_args[] is
+ *    appended to the kernel commandline in the tags.
+ * 5. r0 = 0, r1 = MACHINE_TYPE, r2 = tags_addr
+ * 6. if second_size != 0: jump to second_addr
+ *    else: jump to kernel_addr
+ */
+#endif

u-boot/include/ansi.h

@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * ANSI terminal
+ */
+
+#define ANSI_CURSOR_UP			"\e[%dA"
+#define ANSI_CURSOR_DOWN		"\e[%dB"
+#define ANSI_CURSOR_FORWARD		"\e[%dC"
+#define ANSI_CURSOR_BACK		"\e[%dD"
+#define ANSI_CURSOR_NEXTLINE		"\e[%dE"
+#define ANSI_CURSOR_PREVIOUSLINE	"\e[%dF"
+#define ANSI_CURSOR_COLUMN		"\e[%dG"
+#define ANSI_CURSOR_POSITION		"\e[%d;%dH"
+#define ANSI_CURSOR_SHOW		"\e[?25h"
+#define ANSI_CURSOR_HIDE		"\e[?25l"
+#define ANSI_CLEAR_CONSOLE		"\e[2J"
+#define ANSI_CLEAR_LINE_TO_END		"\e[0K"
+#define ANSI_CLEAR_LINE			"\e[2K"
+#define ANSI_COLOR_RESET		"\e[0m"
+#define ANSI_COLOR_REVERSE		"\e[7m"

u-boot/include/api_public.h

@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2007-2008 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+	BSD-2-Clause
+ */
+
+#ifndef _API_PUBLIC_H_
+#define _API_PUBLIC_H_
+
+#define API_EINVAL		1	/* invalid argument(s)	*/
+#define API_ENODEV		2	/* no device		*/
+#define API_ENOMEM		3	/* no memory		*/
+#define API_EBUSY		4	/* busy, occupied etc.	*/
+#define API_EIO			5	/* I/O error		*/
+#define API_ESYSC		6	/* syscall error	*/
+
+typedef	int (*scp_t)(int, int *, ...);
+
+#define API_SIG_VERSION	1
+#define API_SIG_MAGIC	"UBootAPI"
+#define API_SIG_MAGLEN	8
+
+struct api_signature {
+	char		magic[API_SIG_MAGLEN];	/* magic string */
+	uint16_t	version;		/* API version */
+	uint32_t	checksum;		/* checksum of this sig struct */
+	scp_t		syscall;		/* entry point to the API */
+};
+
+enum {
+	API_RSVD = 0,
+	API_GETC,
+	API_PUTC,
+	API_TSTC,
+	API_PUTS,
+	API_RESET,
+	API_GET_SYS_INFO,
+	API_UDELAY,
+	API_GET_TIMER,
+	API_DEV_ENUM,
+	API_DEV_OPEN,
+	API_DEV_CLOSE,
+	API_DEV_READ,
+	API_DEV_WRITE,
+	API_ENV_ENUM,
+	API_ENV_GET,
+	API_ENV_SET,
+	API_DISPLAY_GET_INFO,
+	API_DISPLAY_DRAW_BITMAP,
+	API_DISPLAY_CLEAR,
+	API_MAXCALL
+};
+
+#define MR_ATTR_FLASH	0x0001
+#define MR_ATTR_DRAM	0x0002
+#define MR_ATTR_SRAM	0x0003
+
+struct mem_region {
+	unsigned long	start;
+	unsigned long	size;
+	int		flags;
+};
+
+struct sys_info {
+	unsigned long		clk_bus;
+	unsigned long		clk_cpu;
+	unsigned long		bar;
+	struct mem_region	*mr;
+	int			mr_no;	/* number of memory regions */
+};
+
+#undef CONFIG_SYS_64BIT_LBA
+#ifdef CONFIG_SYS_64BIT_LBA
+typedef	u_int64_t lbasize_t;
+#else
+typedef unsigned long lbasize_t;
+#endif
+typedef unsigned long lbastart_t;
+
+#define DEV_TYP_NONE	0x0000
+#define DEV_TYP_NET	0x0001
+
+#define DEV_TYP_STOR	0x0002
+#define DT_STOR_IDE	0x0010
+#define DT_STOR_SCSI	0x0020
+#define DT_STOR_USB	0x0040
+#define DT_STOR_MMC	0x0080
+#define DT_STOR_SATA	0x0100
+
+#define DEV_STA_CLOSED	0x0000		/* invalid, closed */
+#define DEV_STA_OPEN	0x0001		/* open i.e. active */
+
+struct device_info {
+	int	type;
+	void	*cookie;
+
+	union {
+		struct {
+			lbasize_t	block_count;	/* no of blocks */
+			unsigned long	block_size;	/* size of one block */
+		} storage;
+
+		struct {
+			unsigned char	hwaddr[6];
+		} net;
+	} info;
+#define di_stor info.storage
+#define di_net info.net
+
+	int	state;
+};
+
+#define DISPLAY_TYPE_LCD	0x0001
+#define DISPLAY_TYPE_VIDEO	0x0002
+
+struct display_info {
+	int type;
+	/* screen size in pixels */
+	int pixel_width;
+	int pixel_height;
+	/* screen size in rows and columns of text */
+	int screen_rows;
+	int screen_cols;
+};
+
+#endif /* _API_PUBLIC_H_ */

u-boot/include/armcoremodule.h

@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2005
+ * ARM Ltd.
+ * Peter Pearse, <Peter.Pearse@arm.com>
+ * Configuration for ARM Core Modules.
+ * No standalonw port yet available
+ * - this file is included by both integratorap.h & integratorcp.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARMCOREMODULE_H
+#define __ARMCOREMODULE_H
+
+#define CM_BASE			0x10000000
+
+/* CM registers common to all CMs */
+/* Note that observed values after reboot into the ARM Boot Monitor
+   have been used as defaults, rather than the POR values */
+#define OS_CTRL			0x0000000C
+#define CMMASK_REMAP		0x00000005	/* set remap & led           */
+#define CMMASK_RESET		0x00000008
+#define OS_LOCK			0x00000014
+#define CMVAL_LOCK1		0x0000A000	/* locking value             */
+#define CMVAL_LOCK2		0x0000005F	/* locking value             */
+#define CMVAL_UNLOCK		0x00000000	/* any value != CM_LOCKVAL   */
+#define OS_SDRAM		0x00000020
+#define OS_INIT			0x00000024
+#define CMMASK_MAP_SIMPLE	0xFFFDFFFF	/* simple mapping */
+#define CMMASK_TCRAM_DISABLE	0xFFFEFFFF	/* TCRAM disabled */
+#define CMMASK_LOWVEC		0x00000000	/* vectors @ 0x00000000 */
+#define CMMASK_LE		0xFFFFFFF7	/* little endian */
+#define CMMASK_CMxx6_COMMON	0x00000013      /* Common value for CMxx6 */
+						/* - observed reset value of */
+						/*   CM926EJ-S */
+						/*   CM1136-EJ-S */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+#define CMMASK_INIT_102	0x00000300		/* see CM102xx ref manual */
+						/* - PLL test clock bypassed */
+						/* - bus clock ratio 2 */
+						/* - little endian */
+						/* - vectors at zero */
+#endif /* CM1022xx */
+
+/* Determine CM characteristics */
+
+#undef	CONFIG_CM_MULTIPLE_SSRAM
+#undef	CONFIG_CM_SPD_DETECT
+#undef	CONFIG_CM_REMAP
+#undef	CONFIG_CM_INIT
+#undef	CONFIG_CM_TCRAM
+
+#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
+#define	CONFIG_CM_MULTIPLE_SSRAM	/* CM has multiple SSRAM mapping */
+#endif
+
+/* Excalibur core module has reduced functionality */
+#ifndef	CONFIG_CM922T_XA10
+#define CONFIG_CM_SPD_DETECT			/* CM supports SPD query      */
+#define OS_SPD			0x00000100	/* Address of SPD data        */
+#define CONFIG_CM_REMAP				/* CM supports remapping      */
+#define CONFIG_CM_INIT				/* CM has initialization reg  */
+#endif	/* NOT EXCALIBUR */
+
+#if defined(CONFIG_CM926EJ_S)   || defined (CONFIG_CM946E_S)	|| \
+    defined(CONFIG_CM966E_S)    || defined (CONFIG_CM1026EJ_S)	|| \
+    defined(CONFIG_CM1136JF_S)
+#define CONFIG_CM_TCRAM				/* CM has TCRAM  */
+#endif
+
+#ifdef CONFIG_CM_SPD_DETECT
+#define OS_SPD		0x00000100	/* The SDRAM SPD data is copied here */
+#endif
+
+#endif /* __ARMCOREMODULE_H */

u-boot/include/asm-generic/atomic-long.h

@@ -0,0 +1,260 @@
+#ifndef _ASM_GENERIC_ATOMIC_LONG_H
+#define _ASM_GENERIC_ATOMIC_LONG_H
+/*
+ * Copyright (C) 2005 Silicon Graphics, Inc.
+ *	Christoph Lameter
+ *
+ * Allows to provide arch independent atomic definitions without the need to
+ * edit all arch specific atomic.h files.
+ */
+
+#include <asm/types.h>
+
+/*
+ * Suppport for atomic_long_t
+ *
+ * Casts for parameters are avoided for existing atomic functions in order to
+ * avoid issues with cast-as-lval under gcc 4.x and other limitations that the
+ * macros of a platform may have.
+ */
+
+#if BITS_PER_LONG == 64
+
+typedef atomic64_t atomic_long_t;
+
+#define ATOMIC_LONG_INIT(i)	ATOMIC64_INIT(i)
+
+static inline long atomic_long_read(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_read(v);
+}
+
+static inline void atomic_long_set(atomic_long_t *l, long i)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	atomic64_set(v, i);
+}
+
+static inline void atomic_long_inc(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	atomic64_inc(v);
+}
+
+static inline void atomic_long_dec(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	atomic64_dec(v);
+}
+
+static inline void atomic_long_add(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	atomic64_add(i, v);
+}
+
+static inline void atomic_long_sub(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	atomic64_sub(i, v);
+}
+
+static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return atomic64_sub_and_test(i, v);
+}
+
+static inline int atomic_long_dec_and_test(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return atomic64_dec_and_test(v);
+}
+
+static inline int atomic_long_inc_and_test(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return atomic64_inc_and_test(v);
+}
+
+static inline int atomic_long_add_negative(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return atomic64_add_negative(i, v);
+}
+
+static inline long atomic_long_add_return(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_add_return(i, v);
+}
+
+static inline long atomic_long_sub_return(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_sub_return(i, v);
+}
+
+static inline long atomic_long_inc_return(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_inc_return(v);
+}
+
+static inline long atomic_long_dec_return(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_dec_return(v);
+}
+
+static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_add_unless(v, a, u);
+}
+
+#define atomic_long_inc_not_zero(l) atomic64_inc_not_zero((atomic64_t *)(l))
+
+#define atomic_long_cmpxchg(l, old, new) \
+	(atomic64_cmpxchg((atomic64_t *)(l), (old), (new)))
+#define atomic_long_xchg(v, new) \
+	(atomic64_xchg((atomic64_t *)(v), (new)))
+
+#else  /*  BITS_PER_LONG == 64  */
+
+typedef atomic_t atomic_long_t;
+
+#define ATOMIC_LONG_INIT(i)	ATOMIC_INIT(i)
+static inline long atomic_long_read(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_read(v);
+}
+
+static inline void atomic_long_set(atomic_long_t *l, long i)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	atomic_set(v, i);
+}
+
+static inline void atomic_long_inc(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	atomic_inc(v);
+}
+
+static inline void atomic_long_dec(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	atomic_dec(v);
+}
+
+static inline void atomic_long_add(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	atomic_add(i, v);
+}
+
+static inline void atomic_long_sub(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	atomic_sub(i, v);
+}
+
+#ifndef __UBOOT__
+static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return atomic_sub_and_test(i, v);
+}
+
+static inline int atomic_long_dec_and_test(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return atomic_dec_and_test(v);
+}
+
+static inline int atomic_long_inc_and_test(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return atomic_inc_and_test(v);
+}
+
+static inline int atomic_long_add_negative(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return atomic_add_negative(i, v);
+}
+
+static inline long atomic_long_add_return(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_add_return(i, v);
+}
+
+static inline long atomic_long_sub_return(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_sub_return(i, v);
+}
+
+static inline long atomic_long_inc_return(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_inc_return(v);
+}
+
+static inline long atomic_long_dec_return(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_dec_return(v);
+}
+
+static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_add_unless(v, a, u);
+}
+
+#define atomic_long_inc_not_zero(l) atomic_inc_not_zero((atomic_t *)(l))
+
+#define atomic_long_cmpxchg(l, old, new) \
+	(atomic_cmpxchg((atomic_t *)(l), (old), (new)))
+#define atomic_long_xchg(v, new) \
+	(atomic_xchg((atomic_t *)(v), (new)))
+#endif  /*  __UBOOT__ */
+
+#endif  /*  BITS_PER_LONG == 64  */
+
+#endif  /*  _ASM_GENERIC_ATOMIC_LONG_H  */

u-boot/include/asm-generic/bitops/__ffs.h

@@ -0,0 +1,43 @@
+#ifndef _ASM_GENERIC_BITOPS___FFS_H_
+#define _ASM_GENERIC_BITOPS___FFS_H_
+
+#include <asm/types.h>
+
+/**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static __always_inline unsigned long __ffs(unsigned long word)
+{
+	int num = 0;
+
+#if BITS_PER_LONG == 64
+	if ((word & 0xffffffff) == 0) {
+		num += 32;
+		word >>= 32;
+	}
+#endif
+	if ((word & 0xffff) == 0) {
+		num += 16;
+		word >>= 16;
+	}
+	if ((word & 0xff) == 0) {
+		num += 8;
+		word >>= 8;
+	}
+	if ((word & 0xf) == 0) {
+		num += 4;
+		word >>= 4;
+	}
+	if ((word & 0x3) == 0) {
+		num += 2;
+		word >>= 2;
+	}
+	if ((word & 0x1) == 0)
+		num += 1;
+	return num;
+}
+
+#endif /* _ASM_GENERIC_BITOPS___FFS_H_ */

u-boot/include/asm-generic/bitops/__fls.h

@@ -0,0 +1,43 @@
+#ifndef _ASM_GENERIC_BITOPS___FLS_H_
+#define _ASM_GENERIC_BITOPS___FLS_H_
+
+#include <asm/types.h>
+
+/**
+ * __fls - find last (most-significant) set bit in a long word
+ * @word: the word to search
+ *
+ * Undefined if no set bit exists, so code should check against 0 first.
+ */
+static __always_inline unsigned long __fls(unsigned long word)
+{
+	int num = BITS_PER_LONG - 1;
+
+#if BITS_PER_LONG == 64
+	if (!(word & (~0ul << 32))) {
+		num -= 32;
+		word <<= 32;
+	}
+#endif
+	if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
+		num -= 16;
+		word <<= 16;
+	}
+	if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
+		num -= 8;
+		word <<= 8;
+	}
+	if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
+		num -= 4;
+		word <<= 4;
+	}
+	if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
+		num -= 2;
+		word <<= 2;
+	}
+	if (!(word & (~0ul << (BITS_PER_LONG-1))))
+		num -= 1;
+	return num;
+}
+
+#endif /* _ASM_GENERIC_BITOPS___FLS_H_ */

u-boot/include/asm-generic/bitops/fls.h

@@ -0,0 +1,41 @@
+#ifndef _ASM_GENERIC_BITOPS_FLS_H_
+#define _ASM_GENERIC_BITOPS_FLS_H_
+
+/**
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+
+static __always_inline int fls(int x)
+{
+	int r = 32;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff0000u)) {
+		x <<= 16;
+		r -= 16;
+	}
+	if (!(x & 0xff000000u)) {
+		x <<= 8;
+		r -= 8;
+	}
+	if (!(x & 0xf0000000u)) {
+		x <<= 4;
+		r -= 4;
+	}
+	if (!(x & 0xc0000000u)) {
+		x <<= 2;
+		r -= 2;
+	}
+	if (!(x & 0x80000000u)) {
+		x <<= 1;
+		r -= 1;
+	}
+	return r;
+}
+
+#endif /* _ASM_GENERIC_BITOPS_FLS_H_ */

u-boot/include/asm-generic/bitops/fls64.h

@@ -0,0 +1,36 @@
+#ifndef _ASM_GENERIC_BITOPS_FLS64_H_
+#define _ASM_GENERIC_BITOPS_FLS64_H_
+
+#include <asm/types.h>
+
+/**
+ * fls64 - find last set bit in a 64-bit word
+ * @x: the word to search
+ *
+ * This is defined in a similar way as the libc and compiler builtin
+ * ffsll, but returns the position of the most significant set bit.
+ *
+ * fls64(value) returns 0 if value is 0 or the position of the last
+ * set bit if value is nonzero. The last (most significant) bit is
+ * at position 64.
+ */
+#if BITS_PER_LONG == 32
+static __always_inline int fls64(__u64 x)
+{
+	__u32 h = x >> 32;
+	if (h)
+		return fls(h) + 32;
+	return fls(x);
+}
+#elif BITS_PER_LONG == 64
+static __always_inline int fls64(__u64 x)
+{
+	if (x == 0)
+		return 0;
+	return __fls(x) + 1;
+}
+#else
+#error BITS_PER_LONG not 32 or 64
+#endif
+
+#endif /* _ASM_GENERIC_BITOPS_FLS64_H_ */

u-boot/include/asm-generic/bitsperlong.h

@@ -0,0 +1,8 @@
+#ifndef __ASM_GENERIC_BITS_PER_LONG
+#define __ASM_GENERIC_BITS_PER_LONG
+
+#ifndef BITS_PER_LONG_LONG
+#define BITS_PER_LONG_LONG 64
+#endif
+
+#endif /* __ASM_GENERIC_BITS_PER_LONG */

u-boot/include/asm-generic/errno.h

@@ -0,0 +1,139 @@
+/*
+ * U-Boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _GENERIC_ERRNO_H
+#define _GENERIC_ERRNO_H
+
+#define	EPERM		1	/* Operation not permitted */
+#define	ENOENT		2	/* No such file or directory */
+#define	ESRCH		3	/* No such process */
+#define	EINTR		4	/* Interrupted system call */
+#define	EIO		5	/* I/O error */
+#define	ENXIO		6	/* No such device or address */
+#define	E2BIG		7	/* Argument list too long */
+#define	ENOEXEC		8	/* Exec format error */
+#define	EBADF		9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+
+#define	EDEADLOCK	EDEADLK
+
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+#endif

u-boot/include/asm-generic/global_data.h

@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_GENERIC_GBL_DATA_H
+#define __ASM_GENERIC_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory which is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
+ *
+ * Each architecture has its own private fields. For now all are private
+ */
+
+#ifndef __ASSEMBLY__
+#include <membuff.h>
+#include <linux/list.h>
+
+typedef struct global_data {
+	bd_t *bd;
+	unsigned long flags;
+	unsigned int baudrate;
+	unsigned long cpu_clk;	/* CPU clock in Hz!		*/
+	unsigned long bus_clk;
+	/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
+	unsigned long pci_clk;
+	unsigned long mem_clk;
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
+	unsigned long fb_base;	/* Base address of framebuffer mem */
+#endif
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+	unsigned long post_log_word;  /* Record POST activities */
+	unsigned long post_log_res; /* success of POST test */
+	unsigned long post_init_f_time;  /* When post_init_f started */
+#endif
+#ifdef CONFIG_BOARD_TYPES
+	unsigned long board_type;
+#endif
+	unsigned long have_console;	/* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long precon_buf_idx;	/* Pre-Console buffer index */
+#endif
+	unsigned long env_addr;	/* Address  of Environment struct */
+	unsigned long env_valid;	/* Checksum of Environment valid? */
+
+	unsigned long ram_top;	/* Top address of RAM used by U-Boot */
+
+	unsigned long relocaddr;	/* Start address of U-Boot in RAM */
+	phys_size_t ram_size;	/* RAM size */
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#define MEM_RESERVE_SECURE_SECURED	0x1
+#define MEM_RESERVE_SECURE_MAINTAINED	0x2
+#define MEM_RESERVE_SECURE_ADDR_MASK	(~0x3)
+	/*
+	 * Secure memory addr
+	 * This variable needs maintenance if the RAM base is not zero,
+	 * or if RAM splits into non-consecutive banks. It also has a
+	 * flag indicating the secure memory is marked as secure by MMU.
+	 * Flags used: 0x1 secured
+	 *             0x2 maintained
+	 */
+	phys_addr_t secure_ram;
+#endif
+	unsigned long mon_len;	/* monitor len */
+	unsigned long irq_sp;		/* irq stack pointer */
+	unsigned long start_addr_sp;	/* start_addr_stackpointer */
+	unsigned long reloc_off;
+	struct global_data *new_gd;	/* relocated global data */
+
+#ifdef CONFIG_DM
+	struct udevice	*dm_root;	/* Root instance for Driver Model */
+	struct udevice	*dm_root_f;	/* Pre-relocation root instance */
+	struct list_head uclass_root;	/* Head of core tree */
+#endif
+#ifdef CONFIG_TIMER
+	struct udevice	*timer;	/* Timer instance for Driver Model */
+#endif
+
+	const void *fdt_blob;	/* Our device tree, NULL if none */
+	void *new_fdt;		/* Relocated FDT */
+	unsigned long fdt_size;	/* Space reserved for relocated FDT */
+	struct jt_funcs *jt;		/* jump table */
+	char env_buf[32];	/* buffer for getenv() before reloc. */
+#ifdef CONFIG_TRACE
+	void		*trace_buff;	/* The trace buffer */
+#endif
+#if defined(CONFIG_SYS_I2C)
+	int		cur_i2c_bus;	/* current used i2c bus */
+#endif
+#ifdef CONFIG_SYS_I2C_MXC
+	void *srdata[10];
+#endif
+	unsigned long timebase_h;
+	unsigned long timebase_l;
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	unsigned long malloc_base;	/* base address of early malloc() */
+	unsigned long malloc_limit;	/* limit address */
+	unsigned long malloc_ptr;	/* current address */
+#endif
+#ifdef CONFIG_PCI
+	struct pci_controller *hose;	/* PCI hose for early use */
+	phys_addr_t pci_ram_top;	/* top of region accessible to PCI */
+#endif
+#ifdef CONFIG_PCI_BOOTDELAY
+	int pcidelay_done;
+#endif
+	struct udevice *cur_serial_dev;	/* current serial device */
+	struct arch_global_data arch;	/* architecture-specific data */
+#ifdef CONFIG_CONSOLE_RECORD
+	struct membuff console_out;	/* console output */
+	struct membuff console_in;	/* console input */
+#endif
+#ifdef CONFIG_DM_VIDEO
+	ulong video_top;		/* Top of video frame buffer area */
+	ulong video_bottom;		/* Bottom of video frame buffer area */
+#endif
+} gd_t;
+#endif
+
+/*
+ * Global Data Flags - the top 16 bits are reserved for arch-specific flags
+ */
+#define GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	   */
+#define GD_FLG_DEVINIT		0x00002	/* Devices have been initialized   */
+#define GD_FLG_SILENT		0x00004	/* Silent mode			   */
+#define GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	   */
+#define GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	   */
+#define GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	   */
+#define GD_FLG_ENV_READY	0x00080	/* Env. imported into hash table   */
+#define GD_FLG_SERIAL_READY	0x00100	/* Pre-reloc serial console ready  */
+#define GD_FLG_FULL_MALLOC_INIT	0x00200	/* Full malloc() is ready	   */
+#define GD_FLG_SPL_INIT		0x00400	/* spl_init() has been called	   */
+#define GD_FLG_SKIP_RELOC	0x00800	/* Don't relocate */
+#define GD_FLG_RECORD		0x01000	/* Record console */
+#define GD_FLG_ENV_DEFAULT	0x02000 /* Default variable flag */
+
+#endif /* __ASM_GENERIC_GBL_DATA_H */

u-boot/include/asm-generic/gpio.h

@@ -0,0 +1,625 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2011, NVIDIA Corp. All rights reserved.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_GENERIC_GPIO_H_
+#define _ASM_GENERIC_GPIO_H_
+
+/*
+ * Generic GPIO API for U-Boot
+ *
+ * --
+ * NB: This is deprecated. Please use the driver model functions instead:
+ *
+ *    - gpio_request_by_name()
+ *    - dm_gpio_get_value() etc.
+ *
+ * For now we need a dm_ prefix on some functions to avoid name collision.
+ * --
+ *
+ * GPIOs are numbered from 0 to GPIO_COUNT-1 which value is defined
+ * by the SOC/architecture.
+ *
+ * Each GPIO can be an input or output. If an input then its value can
+ * be read as 0 or 1. If an output then its value can be set to 0 or 1.
+ * If you try to write an input then the value is undefined. If you try
+ * to read an output, barring something very unusual,  you will get
+ * back the value of the output that you previously set.
+ *
+ * In some cases the operation may fail, for example if the GPIO number
+ * is out of range, or the GPIO is not available because its pin is
+ * being used by another function. In that case, functions may return
+ * an error value of -1.
+ */
+
+/**
+ * @deprecated	Please use driver model instead
+ * Request a GPIO. This should be called before any of the other functions
+ * are used on this GPIO.
+ *
+ * Note: With driver model, the label is allocated so there is no need for
+ * the caller to preserve it.
+ *
+ * @param gpio	GPIO number
+ * @param label	User label for this GPIO
+ * @return 0 if ok, -1 on error
+ */
+int gpio_request(unsigned gpio, const char *label);
+
+/**
+ * @deprecated	Please use driver model instead
+ * Stop using the GPIO.  This function should not alter pin configuration.
+ *
+ * @param gpio	GPIO number
+ * @return 0 if ok, -1 on error
+ */
+int gpio_free(unsigned gpio);
+
+/**
+ * @deprecated	Please use driver model instead
+ * Make a GPIO an input.
+ *
+ * @param gpio	GPIO number
+ * @return 0 if ok, -1 on error
+ */
+int gpio_direction_input(unsigned gpio);
+
+/**
+ * @deprecated	Please use driver model instead
+ * Make a GPIO an output, and set its value.
+ *
+ * @param gpio	GPIO number
+ * @param value	GPIO value (0 for low or 1 for high)
+ * @return 0 if ok, -1 on error
+ */
+int gpio_direction_output(unsigned gpio, int value);
+
+/**
+ * @deprecated	Please use driver model instead
+ * Get a GPIO's value. This will work whether the GPIO is an input
+ * or an output.
+ *
+ * @param gpio	GPIO number
+ * @return 0 if low, 1 if high, -1 on error
+ */
+int gpio_get_value(unsigned gpio);
+
+/**
+ * @deprecated	Please use driver model instead
+ * Set an output GPIO's value. The GPIO must already be an output or
+ * this function may have no effect.
+ *
+ * @param gpio	GPIO number
+ * @param value	GPIO value (0 for low or 1 for high)
+ * @return 0 if ok, -1 on error
+ */
+int gpio_set_value(unsigned gpio, int value);
+
+/* State of a GPIO, as reported by get_function() */
+enum gpio_func_t {
+	GPIOF_INPUT = 0,
+	GPIOF_OUTPUT,
+	GPIOF_UNUSED,		/* Not claimed */
+	GPIOF_UNKNOWN,		/* Not known */
+	GPIOF_FUNC,		/* Not used as a GPIO */
+
+	GPIOF_COUNT,
+};
+
+struct udevice;
+
+struct gpio_desc {
+	struct udevice *dev;	/* Device, NULL for invalid GPIO */
+	unsigned long flags;
+#define GPIOD_REQUESTED		(1 << 0)	/* Requested/claimed */
+#define GPIOD_IS_OUT		(1 << 1)	/* GPIO is an output */
+#define GPIOD_IS_IN		(1 << 2)	/* GPIO is an input */
+#define GPIOD_ACTIVE_LOW	(1 << 3)	/* value has active low */
+#define GPIOD_IS_OUT_ACTIVE	(1 << 4)	/* set output active */
+
+	uint offset;		/* GPIO offset within the device */
+	/*
+	 * We could consider adding the GPIO label in here. Possibly we could
+	 * use this structure for internal GPIO information.
+	 */
+};
+
+/**
+ * dm_gpio_is_valid() - Check if a GPIO is valid
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return true if valid, false if not
+ */
+static inline bool dm_gpio_is_valid(const struct gpio_desc *desc)
+{
+	return desc->dev != NULL;
+}
+
+/**
+ * gpio_get_status() - get the current GPIO status as a string
+ *
+ * Obtain the current GPIO status as a string which can be presented to the
+ * user. A typical string is:
+ *
+ * "b4:  in: 1 [x] sdmmc_cd"
+ *
+ * which means this is GPIO bank b, offset 4, currently set to input, current
+ * value 1, [x] means that it is requested and the owner is 'sdmmc_cd'
+ *
+ * TODO(sjg@chromium.org): This should use struct gpio_desc
+ *
+ * @dev:	Device to check
+ * @offset:	Offset of device GPIO to check
+ * @buf:	Place to put string
+ * @buffsize:	Size of string including \0
+ */
+int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize);
+
+/**
+ * gpio_get_function() - get the current function for a GPIO pin
+ *
+ * Note this returns GPIOF_UNUSED if the GPIO is not requested.
+ *
+ * TODO(sjg@chromium.org): This should use struct gpio_desc
+ *
+ * @dev:	Device to check
+ * @offset:	Offset of device GPIO to check
+ * @namep:	If non-NULL, this is set to the name given when the GPIO
+ *		was requested, or -1 if it has not been requested
+ * @return  -ENODATA if the driver returned an unknown function,
+ * -ENODEV if the device is not active, -EINVAL if the offset is invalid.
+ * GPIOF_UNUSED if the GPIO has not been requested. Otherwise returns the
+ * function from enum gpio_func_t.
+ */
+int gpio_get_function(struct udevice *dev, int offset, const char **namep);
+
+/**
+ * gpio_get_raw_function() - get the current raw function for a GPIO pin
+ *
+ * Note this does not return GPIOF_UNUSED - it will always return the GPIO
+ * driver's view of a pin function, even if it is not correctly set up.
+ *
+ * TODO(sjg@chromium.org): This should use struct gpio_desc
+ *
+ * @dev:	Device to check
+ * @offset:	Offset of device GPIO to check
+ * @namep:	If non-NULL, this is set to the name given when the GPIO
+ *		was requested, or -1 if it has not been requested
+ * @return  -ENODATA if the driver returned an unknown function,
+ * -ENODEV if the device is not active, -EINVAL if the offset is invalid.
+ * Otherwise returns the function from enum gpio_func_t.
+ */
+int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep);
+
+/**
+ * gpio_requestf() - request a GPIO using a format string for the owner
+ *
+ * This is a helper function for gpio_request(). It allows you to provide
+ * a printf()-format string for the GPIO owner. It calls gpio_request() with
+ * the string that is created
+ */
+int gpio_requestf(unsigned gpio, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 2, 3)));
+
+struct fdtdec_phandle_args;
+
+/**
+ * gpio_xlate_offs_flags() - implementation for common use of dm_gpio_ops.xlate
+ *
+ * This routine sets the offset field to args[0] and the flags field to
+ * GPIOD_ACTIVE_LOW if the GPIO_ACTIVE_LOW flag is present in args[1].
+ *
+ */
+int gpio_xlate_offs_flags(struct udevice *dev, struct gpio_desc *desc,
+			  struct fdtdec_phandle_args *args);
+
+/**
+ * struct struct dm_gpio_ops - Driver model GPIO operations
+ *
+ * Refer to functions above for description. These function largely copy
+ * the old API.
+ *
+ * This is trying to be close to Linux GPIO API. Once the U-Boot uses the
+ * new DM GPIO API, this should be really easy to flip over to the Linux
+ * GPIO API-alike interface.
+ *
+ * Also it would be useful to standardise additional functions like
+ * pullup, slew rate and drive strength.
+ *
+ * gpio_request() and gpio_free() are optional - if NULL then they will
+ * not be called.
+ *
+ * Note that @offset is the offset from the base GPIO of the device. So
+ * offset 0 is the device's first GPIO and offset o-1 is the last GPIO,
+ * where o is the number of GPIO lines controlled by the device. A device
+ * is typically used to control a single bank of GPIOs. Within complex
+ * SoCs there may be many banks and therefore many devices all referring
+ * to the different IO addresses within the SoC.
+ *
+ * The uclass combines all GPIO devices together to provide a consistent
+ * numbering from 0 to n-1, where n is the number of GPIOs in total across
+ * all devices. Be careful not to confuse offset with gpio in the parameters.
+ */
+struct dm_gpio_ops {
+	int (*request)(struct udevice *dev, unsigned offset, const char *label);
+	int (*free)(struct udevice *dev, unsigned offset);
+	int (*direction_input)(struct udevice *dev, unsigned offset);
+	int (*direction_output)(struct udevice *dev, unsigned offset,
+				int value);
+	int (*get_value)(struct udevice *dev, unsigned offset);
+	int (*set_value)(struct udevice *dev, unsigned offset, int value);
+	int (*get_open_drain)(struct udevice *dev, unsigned offset);
+	int (*set_open_drain)(struct udevice *dev, unsigned offset, int value);
+	/**
+	 * get_function() Get the GPIO function
+	 *
+	 * @dev:     Device to check
+	 * @offset:  GPIO offset within that device
+	 * @return current function - GPIOF_...
+	 */
+	int (*get_function)(struct udevice *dev, unsigned offset);
+
+	/**
+	 * xlate() - Translate phandle arguments into a GPIO description
+	 *
+	 * This function should set up the fields in desc according to the
+	 * information in the arguments. The uclass will have set up:
+	 *
+	 *   @desc->dev to @dev
+	 *   @desc->flags to 0
+	 *   @desc->offset to 0
+	 *
+	 * This method is optional and defaults to gpio_xlate_offs_flags,
+	 * which will parse offset and the GPIO_ACTIVE_LOW flag in the first
+	 * two arguments.
+	 *
+	 * Note that @dev is passed in as a parameter to follow driver model
+	 * uclass conventions, even though it is already available as
+	 * desc->dev.
+	 *
+	 * @dev:	GPIO device
+	 * @desc:	Place to put GPIO description
+	 * @args:	Arguments provided in description
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*xlate)(struct udevice *dev, struct gpio_desc *desc,
+		     struct fdtdec_phandle_args *args);
+};
+
+/**
+ * struct gpio_dev_priv - information about a device used by the uclass
+ *
+ * The uclass combines all active GPIO devices into a unified numbering
+ * scheme. To do this it maintains some private information about each
+ * device.
+ *
+ * To implement driver model support in your GPIO driver, add a probe
+ * handler, and set @gpio_count and @bank_name correctly in that handler.
+ * This tells the uclass the name of the GPIO bank and the number of GPIOs
+ * it contains.
+ *
+ * @bank_name: Name of the GPIO device (e.g 'a' means GPIOs will be called
+ * 'A0', 'A1', etc.
+ * @gpio_count: Number of GPIOs in this device
+ * @gpio_base: Base GPIO number for this device. For the first active device
+ * this will be 0; the numbering for others will follow sequentially so that
+ * @gpio_base for device 1 will equal the number of GPIOs in device 0.
+ * @name: Array of pointers to the name for each GPIO in this bank. The
+ * value of the pointer will be NULL if the GPIO has not been claimed.
+ */
+struct gpio_dev_priv {
+	const char *bank_name;
+	unsigned gpio_count;
+	unsigned gpio_base;
+	char **name;
+};
+
+/* Access the GPIO operations for a device */
+#define gpio_get_ops(dev)	((struct dm_gpio_ops *)(dev)->driver->ops)
+
+/**
+ * gpio_get_bank_info - Return information about a GPIO bank/device
+ *
+ * This looks up a device and returns both its GPIO base name and the number
+ * of GPIOs it controls.
+ *
+ * @dev: Device to look up
+ * @offset_count: Returns number of GPIOs within this bank
+ * @return bank name of this device
+ */
+const char *gpio_get_bank_info(struct udevice *dev, int *offset_count);
+
+/**
+ * dm_gpio_lookup_name() - Look up a named GPIO and return its description
+ *
+ * The name of a GPIO is typically its bank name followed by a number from 0.
+ * For example A0 is the first GPIO in bank A. Each bank is a separate driver
+ * model device.
+ *
+ * @name:	Name to look up
+ * @desc:	Returns description, on success
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_lookup_name(const char *name, struct gpio_desc *desc);
+
+/**
+ * gpio_lookup_name - Look up a GPIO name and return its details
+ *
+ * This is used to convert a named GPIO into a device, offset and GPIO
+ * number.
+ *
+ * @name: GPIO name to look up
+ * @devp: Returns pointer to device which contains this GPIO
+ * @offsetp: Returns the offset number within this device
+ * @gpiop: Returns the absolute GPIO number, numbered from 0
+ */
+int gpio_lookup_name(const char *name, struct udevice **devp,
+		     unsigned int *offsetp, unsigned int *gpiop);
+
+/**
+ * gpio_get_values_as_int() - Turn the values of a list of GPIOs into an int
+ *
+ * This puts the value of the first GPIO into bit 0, the second into bit 1,
+ * etc. then returns the resulting integer.
+ *
+ * @gpio_list: List of GPIOs to collect
+ * @return resulting integer value, or -ve on error
+ */
+int gpio_get_values_as_int(const int *gpio_list);
+
+/**
+ * dm_gpio_get_values_as_int() - Turn the values of a list of GPIOs into an int
+ *
+ * This puts the value of the first GPIO into bit 0, the second into bit 1,
+ * etc. then returns the resulting integer.
+ *
+ * @desc_list: List of GPIOs to collect
+ * @count: Number of GPIOs
+ * @return resulting integer value, or -ve on error
+ */
+int dm_gpio_get_values_as_int(const struct gpio_desc *desc_list, int count);
+
+/**
+ * gpio_claim_vector() - claim a number of GPIOs for input
+ *
+ * @gpio_num_array:	array of gpios to claim, terminated by -1
+ * @fmt:		format string for GPIO names, e.g. "board_id%d"
+ * @return 0 if OK, -ve on error
+ */
+int gpio_claim_vector(const int *gpio_num_array, const char *fmt);
+
+/**
+ * gpio_request_by_name() - Locate and request a GPIO by name
+ *
+ * This operates by looking up the given list name in the device (device
+ * tree property) and requesting the GPIO for use. The property must exist
+ * in @dev's node.
+ *
+ * Use @flags to specify whether the GPIO should be an input or output. In
+ * principle this can also come from the device tree binding but most
+ * bindings don't provide this information. Specifically, when the GPIO uclass
+ * calls the xlate() method, it can return default flags, which are then
+ * ORed with this @flags.
+ *
+ * If we find that requesting the GPIO is not always needed we could add a
+ * new function or a new GPIOD_NO_REQUEST flag.
+ *
+ * At present driver model has no reference counting so if one device
+ * requests a GPIO which subsequently is unbound, the @desc->dev pointer
+ * will be invalid. However this will only happen if the GPIO device is
+ * unbound, not if it is removed, so this seems like a reasonable limitation
+ * for now. There is no real use case for unbinding drivers in normal
+ * operation.
+ *
+ * The device tree binding is doc/device-tree-bindings/gpio/gpio.txt in
+ * generate terms and each specific device may add additional details in
+ * a binding file in the same directory.
+ *
+ * @dev:	Device requesting the GPIO
+ * @list_name:	Name of GPIO list (e.g. "board-id-gpios")
+ * @index:	Index number of the GPIO in that list use request (0=first)
+ * @desc:	Returns GPIO description information. If there is no such
+ *		GPIO, dev->dev will be NULL.
+ * @flags:	Indicates the GPIO input/output settings (GPIOD_...)
+ * @return 0 if OK, -ENOENT if the GPIO does not exist, -EINVAL if there is
+ * something wrong with the list, or other -ve for another error (e.g.
+ * -EBUSY if a GPIO was already requested)
+ */
+int gpio_request_by_name(struct udevice *dev, const char *list_name,
+			 int index, struct gpio_desc *desc, int flags);
+
+/**
+ * gpio_request_list_by_name() - Request a list of GPIOs
+ *
+ * Reads all the GPIOs from a list and requests them. See
+ * gpio_request_by_name() for additional details. Lists should not be
+ * misused to hold unrelated or optional GPIOs. They should only be used
+ * for things like parallel data lines. A zero phandle terminates the list
+ * the list.
+ *
+ * This function will either succeed, and request all GPIOs in the list, or
+ * fail and request none (it will free already-requested GPIOs in case of
+ * an error part-way through).
+ *
+ * @dev:	Device requesting the GPIO
+ * @list_name:	Name of GPIO list (e.g. "board-id-gpios")
+ * @desc_list:	Returns a list of GPIO description information
+ * @max_count:	Maximum number of GPIOs to return (@desc_list must be at least
+ *		this big)
+ * @flags:	Indicates the GPIO input/output settings (GPIOD_...)
+ * @return number of GPIOs requested, or -ve on error
+ */
+int gpio_request_list_by_name(struct udevice *dev, const char *list_name,
+			      struct gpio_desc *desc_list, int max_count,
+			      int flags);
+
+/**
+ * dm_gpio_request() - manually request a GPIO
+ *
+ * Note: This function should only be used for testing / debugging. Instead.
+ * use gpio_request_by_name() to pull GPIOs from the device tree.
+ *
+ * @desc:	GPIO description of GPIO to request (see dm_gpio_lookup_name())
+ * @label:	Label to attach to the GPIO while claimed
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_request(struct gpio_desc *desc, const char *label);
+
+/**
+ * gpio_get_list_count() - Returns the number of GPIOs in a list
+ *
+ * Counts the GPIOs in a list. See gpio_request_by_name() for additional
+ * details.
+ *
+ * @dev:	Device requesting the GPIO
+ * @list_name:	Name of GPIO list (e.g. "board-id-gpios")
+ * @return number of GPIOs (0 for an empty property) or -ENOENT if the list
+ * does not exist
+ */
+int gpio_get_list_count(struct udevice *dev, const char *list_name);
+
+/**
+ * gpio_request_by_name_nodev() - request GPIOs without a device
+ *
+ * This is a version of gpio_request_list_by_name() that does not use a
+ * device. Avoid it unless the caller is not yet using driver model
+ */
+int gpio_request_by_name_nodev(const void *blob, int node,
+			       const char *list_name,
+			       int index, struct gpio_desc *desc, int flags);
+
+/**
+ * gpio_request_list_by_name_nodev() - request GPIOs without a device
+ *
+ * This is a version of gpio_request_list_by_name() that does not use a
+ * device. Avoid it unless the caller is not yet using driver model
+ */
+int gpio_request_list_by_name_nodev(const void *blob, int node,
+				    const char *list_name,
+				    struct gpio_desc *desc_list, int max_count,
+				    int flags);
+
+/**
+ * dm_gpio_free() - Free a single GPIO
+ *
+ * This frees a single GPIOs previously returned from gpio_request_by_name().
+ *
+ * @dev:	Device which requested the GPIO
+ * @desc:	GPIO to free
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc);
+
+/**
+ * gpio_free_list() - Free a list of GPIOs
+ *
+ * This frees a list of GPIOs previously returned from
+ * gpio_request_list_by_name().
+ *
+ * @dev:	Device which requested the GPIOs
+ * @desc:	List of GPIOs to free
+ * @count:	Number of GPIOs in the list
+ * @return 0 if OK, -ve on error
+ */
+int gpio_free_list(struct udevice *dev, struct gpio_desc *desc, int count);
+
+/**
+ * gpio_free_list_nodev() - free GPIOs without a device
+ *
+ * This is a version of gpio_free_list() that does not use a
+ * device. Avoid it unless the caller is not yet using driver model
+ */
+int gpio_free_list_nodev(struct gpio_desc *desc, int count);
+
+/**
+ * dm_gpio_get_value() - Get the value of a GPIO
+ *
+ * This is the driver model version of the existing gpio_get_value() function
+ * and should be used instead of that.
+ *
+ * For now, these functions have a dm_ prefix since they conflict with
+ * existing names.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return GPIO value (0 for inactive, 1 for active) or -ve on error
+ */
+int dm_gpio_get_value(const struct gpio_desc *desc);
+
+int dm_gpio_set_value(const struct gpio_desc *desc, int value);
+
+/**
+ * dm_gpio_get_open_drain() - Check if open-drain-mode of a GPIO is active
+ *
+ * This checks if open-drain-mode for a GPIO is enabled or not. This method is
+ * optional.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return Value of open drain mode for GPIO (0 for inactive, 1 for active) or
+ *	   -ve on error
+ */
+int dm_gpio_get_open_drain(struct gpio_desc *desc);
+
+/**
+ * dm_gpio_set_open_drain() - Switch open-drain-mode of a GPIO on or off
+ *
+ * This enables or disables open-drain mode for a GPIO. This method is
+ * optional; if the driver does not support it, nothing happens when the method
+ * is called.
+ *
+ * In open-drain mode, instead of actively driving the output (Push-pull
+ * output), the GPIO's pin is connected to the collector (for a NPN transistor)
+ * or the drain (for a MOSFET) of a transistor, respectively. The pin then
+ * either forms an open circuit or a connection to ground, depending on the
+ * state of the transistor.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_set_open_drain(struct gpio_desc *desc, int value);
+
+/**
+ * dm_gpio_set_dir() - Set the direction for a GPIO
+ *
+ * This sets up the direction according tot the provided flags. It will do
+ * nothing unless the direction is actually specified.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_set_dir(struct gpio_desc *desc);
+
+/**
+ * dm_gpio_set_dir_flags() - Set direction using specific flags
+ *
+ * This is like dm_gpio_set_dir() except that the flags value is provided
+ * instead of being used from desc->flags. This is needed because in many
+ * cases the GPIO description does not include direction information.
+ * Note that desc->flags is updated by this function.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @flags:	New flags to use
+ * @return 0 if OK, -ve on error, in which case desc->flags is not updated
+ */
+int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags);
+
+/**
+ * gpio_get_number() - Get the global GPIO number of a GPIO
+ *
+ * This should only be used for debugging or interest. It returns the number
+ * that should be used for gpio_get_value() etc. to access this GPIO.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return GPIO number, or -ve if not found
+ */
+int gpio_get_number(const struct gpio_desc *desc);
+
+#endif	/* _ASM_GENERIC_GPIO_H_ */

u-boot/include/asm-generic/ioctl.h

@@ -0,0 +1,105 @@
+#ifndef _ASM_GENERIC_IOCTL_H
+#define _ASM_GENERIC_IOCTL_H
+
+/* ioctl command encoding: 32 bits total, command in lower 16 bits,
+ * size of the parameter structure in the lower 14 bits of the
+ * upper 16 bits.
+ * Encoding the size of the parameter structure in the ioctl request
+ * is useful for catching programs compiled with old versions
+ * and to avoid overwriting user space outside the user buffer area.
+ * The highest 2 bits are reserved for indicating the ``access mode''.
+ * NOTE: This limits the max parameter size to 16kB -1 !
+ */
+
+/*
+ * The following is for compatibility across the various Linux
+ * platforms.  The generic ioctl numbering scheme doesn't really enforce
+ * a type field.  De facto, however, the top 8 bits of the lower 16
+ * bits are indeed used as a type field, so we might just as well make
+ * this explicit here.  Please be sure to use the decoding macros
+ * below from now on.
+ */
+#define _IOC_NRBITS	8
+#define _IOC_TYPEBITS	8
+
+/*
+ * Let any architecture override either of the following before
+ * including this file.
+ */
+
+#ifndef _IOC_SIZEBITS
+# define _IOC_SIZEBITS	14
+#endif
+
+#ifndef _IOC_DIRBITS
+# define _IOC_DIRBITS	2
+#endif
+
+#define _IOC_NRMASK	((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK	((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK	((1 << _IOC_SIZEBITS)-1)
+#define _IOC_DIRMASK	((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT	0
+#define _IOC_TYPESHIFT	(_IOC_NRSHIFT+_IOC_NRBITS)
+#define _IOC_SIZESHIFT	(_IOC_TYPESHIFT+_IOC_TYPEBITS)
+#define _IOC_DIRSHIFT	(_IOC_SIZESHIFT+_IOC_SIZEBITS)
+
+/*
+ * Direction bits, which any architecture can choose to override
+ * before including this file.
+ */
+
+#ifndef _IOC_NONE
+# define _IOC_NONE	0U
+#endif
+
+#ifndef _IOC_WRITE
+# define _IOC_WRITE	1U
+#endif
+
+#ifndef _IOC_READ
+# define _IOC_READ	2U
+#endif
+
+#define _IOC(dir,type,nr,size) \
+	(((dir)  << _IOC_DIRSHIFT) | \
+	 ((type) << _IOC_TYPESHIFT) | \
+	 ((nr)   << _IOC_NRSHIFT) | \
+	 ((size) << _IOC_SIZESHIFT))
+
+#ifdef __KERNEL__
+/* provoke compile error for invalid uses of size argument */
+extern unsigned int __invalid_size_argument_for_IOC;
+#define _IOC_TYPECHECK(t) \
+	((sizeof(t) == sizeof(t[1]) && \
+	  sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
+	  sizeof(t) : __invalid_size_argument_for_IOC)
+#else
+#define _IOC_TYPECHECK(t) (sizeof(t))
+#endif
+
+/* used to create numbers */
+#define _IO(type,nr)		_IOC(_IOC_NONE,(type),(nr),0)
+#define _IOR(type,nr,size)	_IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOW(type,nr,size)	_IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOWR(type,nr,size)	_IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOR_BAD(type,nr,size)	_IOC(_IOC_READ,(type),(nr),sizeof(size))
+#define _IOW_BAD(type,nr,size)	_IOC(_IOC_WRITE,(type),(nr),sizeof(size))
+#define _IOWR_BAD(type,nr,size)	_IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
+
+/* used to decode ioctl numbers.. */
+#define _IOC_DIR(nr)		(((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
+#define _IOC_TYPE(nr)		(((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr)		(((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr)		(((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
+
+/* ...and for the drivers/sound files... */
+
+#define IOC_IN		(_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT		(_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT	((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK	(_IOC_SIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT	(_IOC_SIZESHIFT)
+
+#endif /* _ASM_GENERIC_IOCTL_H */

u-boot/include/asm-generic/sections.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Taken from Linux kernel, commit f56c3196 */
+
+#ifndef _ASM_GENERIC_SECTIONS_H_
+#define _ASM_GENERIC_SECTIONS_H_
+
+/* References to section boundaries */
+
+extern char _text[], _stext[], _etext[];
+extern char _data[], _sdata[], _edata[];
+extern char __bss_start[], __bss_stop[];
+extern char __init_begin[], __init_end[];
+extern char _sinittext[], _einittext[];
+extern char _end[], _init[];
+extern char __per_cpu_load[], __per_cpu_start[], __per_cpu_end[];
+extern char __kprobes_text_start[], __kprobes_text_end[];
+extern char __entry_text_start[], __entry_text_end[];
+extern char __initdata_begin[], __initdata_end[];
+extern char __start_rodata[], __end_rodata[];
+
+/* Start and end of .ctors section - used for constructor calls. */
+extern char __ctors_start[], __ctors_end[];
+
+/* function descriptor handling (if any).  Override
+ * in asm/sections.h */
+#ifndef dereference_function_descriptor
+#define dereference_function_descriptor(p) (p)
+#endif
+
+/* random extra sections (if any).  Override
+ * in asm/sections.h */
+#ifndef arch_is_kernel_text
+static inline int arch_is_kernel_text(unsigned long addr)
+{
+	return 0;
+}
+#endif
+
+#ifndef arch_is_kernel_data
+static inline int arch_is_kernel_data(unsigned long addr)
+{
+	return 0;
+}
+#endif
+
+/* U-Boot-specific things begin here */
+
+/* Start of U-Boot text region */
+extern char __text_start[];
+
+/* This marks the end of the text region which must be relocated */
+extern char __image_copy_end[];
+
+/*
+ * This is the U-Boot entry point - prior to relocation it should be same
+ * as __text_start
+ */
+extern void _start(void);
+
+/*
+ * ARM defines its symbols as char[]. Other arches define them as ulongs.
+ */
+#ifdef CONFIG_ARM
+
+extern char __bss_start[];
+extern char __bss_end[];
+extern char __image_copy_start[];
+extern char __image_copy_end[];
+extern char _image_binary_end[];
+extern char __rel_dyn_start[];
+extern char __rel_dyn_end[];
+
+#else /* don't use offsets: */
+
+/* Exports from the Linker Script */
+extern ulong __data_end;
+extern ulong __rel_dyn_start;
+extern ulong __rel_dyn_end;
+extern ulong __bss_end;
+
+extern ulong _TEXT_BASE;	/* code start */
+
+#endif
+
+#endif /* _ASM_GENERIC_SECTIONS_H_ */

u-boot/include/asm-generic/signal.h

@@ -0,0 +1,101 @@
+#ifndef __ASM_GENERIC_SIGNAL_H
+#define __ASM_GENERIC_SIGNAL_H
+
+#include <linux/types.h>
+
+#define _NSIG		64
+#define _NSIG_BPW	BITS_PER_LONG
+#define _NSIG_WORDS	(_NSIG / _NSIG_BPW)
+
+#define SIGHUP		 1
+#define SIGINT		 2
+#define SIGQUIT		 3
+#define SIGILL		 4
+#define SIGTRAP		 5
+#define SIGABRT		 6
+#define SIGIOT		 6
+#define SIGBUS		 7
+#define SIGFPE		 8
+#define SIGKILL		 9
+#define SIGUSR1		10
+#define SIGSEGV		11
+#define SIGUSR2		12
+#define SIGPIPE		13
+#define SIGALRM		14
+#define SIGTERM		15
+#define SIGSTKFLT	16
+#define SIGCHLD		17
+#define SIGCONT		18
+#define SIGSTOP		19
+#define SIGTSTP		20
+#define SIGTTIN		21
+#define SIGTTOU		22
+#define SIGURG		23
+#define SIGXCPU		24
+#define SIGXFSZ		25
+#define SIGVTALRM	26
+#define SIGPROF		27
+#define SIGWINCH	28
+#define SIGIO		29
+#define SIGPOLL		SIGIO
+/*
+#define SIGLOST		29
+*/
+#define SIGPWR		30
+#define SIGSYS		31
+#define	SIGUNUSED	31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN	32
+#ifndef SIGRTMAX
+#define SIGRTMAX	_NSIG
+#endif
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP	0x00000001
+#define SA_NOCLDWAIT	0x00000002
+#define SA_SIGINFO	0x00000004
+#define SA_ONSTACK	0x08000000
+#define SA_RESTART	0x10000000
+#define SA_NODEFER	0x40000000
+#define SA_RESETHAND	0x80000000
+
+#define SA_NOMASK	SA_NODEFER
+#define SA_ONESHOT	SA_RESETHAND
+
+/*
+ * New architectures should not define the obsolete
+ *	SA_RESTORER	0x04000000
+ */
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK	1
+#define SS_DISABLE	2
+
+#define MINSIGSTKSZ	2048
+#define SIGSTKSZ	8192
+
+#ifndef __ASSEMBLY__
+typedef struct {
+	unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+/* not actually used, but required for linux/syscalls.h */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_GENERIC_SIGNAL_H */

u-boot/include/asm-generic/u-boot.h

@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * (C) Copyright 2000 - 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __ASM_GENERIC_U_BOOT_H__
+#define __ASM_GENERIC_U_BOOT_H__
+
+/*
+ * Board information passed to Linux kernel from U-Boot
+ *
+ * include/asm-ppc/u-boot.h
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef struct bd_info {
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	phys_size_t	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long	bi_sramstart;	/* start of SRAM memory */
+	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
+#ifdef CONFIG_AVR32
+	unsigned char   bi_phy_id[4];   /* PHY address for ATAG_ETHERNET */
+	unsigned long   bi_board_number;/* ATAG_BOARDINFO */
+#endif
+#ifdef CONFIG_ARM
+	unsigned long	bi_arm_freq; /* arm frequency */
+	unsigned long	bi_dsp_freq; /* dsp core frequency */
+	unsigned long	bi_ddr_freq; /* ddr frequency */
+#endif
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
+	|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+	unsigned long	bi_immr_base;	/* base of IMMR register */
+#endif
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
+	unsigned long	bi_mbar_base;	/* base of internal registers */
+#endif
+#if defined(CONFIG_MPC83xx)
+	unsigned long	bi_immrbar;
+#endif
+	unsigned long	bi_bootflags;	/* boot / reboot flag (Unused) */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6];	/* OLD: see README.enetaddr */
+	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
+	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
+	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
+#if defined(CONFIG_CPM2)
+	unsigned long	bi_cpmfreq;	/* CPM_CLK Freq, in MHz */
+	unsigned long	bi_brgfreq;	/* BRG_CLK Freq, in MHz */
+	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
+	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
+#endif
+#if defined(CONFIG_MPC512X)
+	unsigned long	bi_ipsfreq;	/* IPS Bus Freq, in MHz */
+#endif /* CONFIG_MPC512X */
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
+	unsigned long	bi_ipbfreq;	/* IPB Bus Freq, in MHz */
+	unsigned long	bi_pcifreq;	/* PCI Bus Freq, in MHz */
+#endif
+#if defined(CONFIG_EXTRA_CLOCK)
+	unsigned long bi_inpfreq;	/* input Freq in MHz */
+	unsigned long bi_vcofreq;	/* vco Freq in MHz */
+	unsigned long bi_flbfreq;	/* Flexbus Freq in MHz */
+#endif
+#if defined(CONFIG_405)   || \
+		defined(CONFIG_405GP) || \
+		defined(CONFIG_405EP) || \
+		defined(CONFIG_405EZ) || \
+		defined(CONFIG_405EX) || \
+		defined(CONFIG_440)
+	unsigned char	bi_s_version[4];	/* Version of this structure */
+	unsigned char	bi_r_version[32];	/* Version of the ROM (AMCC) */
+	unsigned int	bi_procfreq;	/* CPU (Internal) Freq, in Hz */
+	unsigned int	bi_plb_busfreq;	/* PLB Bus speed, in Hz */
+	unsigned int	bi_pci_busfreq;	/* PCI Bus speed, in Hz */
+	unsigned char	bi_pci_enetaddr[6];	/* PCI Ethernet MAC address */
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+	unsigned char   bi_enet1addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH2
+	unsigned char	bi_enet2addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH3
+	unsigned char   bi_enet3addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH4
+	unsigned char   bi_enet4addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH5
+	unsigned char   bi_enet5addr[6];	/* OLD: see README.enetaddr */
+#endif
+
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+		defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
+		defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+		defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+		defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
+	int		bi_iic_fast[2];		/* Use fast i2c mode */
+#endif
+#if defined(CONFIG_4xx)
+#if defined(CONFIG_440GX) || \
+		defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	int		bi_phynum[4];           /* Determines phy mapping */
+	int		bi_phymode[4];          /* Determines phy mode */
+#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440)
+	int		bi_phynum[2];           /* Determines phy mapping */
+	int		bi_phymode[2];          /* Determines phy mode */
+#else
+	int		bi_phynum[1];           /* Determines phy mapping */
+	int		bi_phymode[1];          /* Determines phy mode */
+#endif
+#endif /* defined(CONFIG_4xx) */
+	ulong	        bi_arch_number;	/* unique id for this board */
+	ulong	        bi_boot_params;	/* where this board expects params */
+#ifdef CONFIG_NR_DRAM_BANKS
+	struct {			/* RAM configuration */
+		phys_addr_t start;
+		phys_size_t size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+#endif /* CONFIG_NR_DRAM_BANKS */
+} bd_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif	/* __ASM_GENERIC_U_BOOT_H__ */

u-boot/include/asm-generic/unaligned.h

@@ -0,0 +1,23 @@
+#ifndef _GENERIC_UNALIGNED_H
+#define _GENERIC_UNALIGNED_H
+
+#include <asm/byteorder.h>
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+/*
+ * Select endianness
+ */
+#if defined(__LITTLE_ENDIAN)
+#define get_unaligned	__get_unaligned_le
+#define put_unaligned	__put_unaligned_le
+#elif defined(__BIG_ENDIAN)
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+#else
+#error invalid endian
+#endif
+
+#endif

u-boot/include/asm-offsets.h

@@ -0,0 +1,6 @@
+#ifndef	DO_DEPS_ONLY
+
+#include <generated/generic-asm-offsets.h>
+/* #include <generated/asm-offsets.h> */
+
+#endif

u-boot/include/ata.h

@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Most of the following information was derived from the document
+ * "Information Technology - AT Attachment-3 Interface (ATA-3)"
+ * which can be found at:
+ * http://www.dt.wdc.com/ata/ata-3/ata3r5v.zip
+ * ftp://poctok.iae.nsk.su/pub/asm/Documents/IDE/ATA3R5V.ZIP
+ * ftp://ftp.fee.vutbr.cz/pub/doc/io/ata/ata-3/ata3r5v.zip
+ */
+
+#ifndef	_ATA_H
+#define _ATA_H
+
+#include <libata.h>
+
+/* Register addressing depends on the hardware design; for instance,
+ * 8-bit (register) and 16-bit (data) accesses might use different
+ * address spaces. This is implemented by the following definitions.
+ */
+#ifndef CONFIG_SYS_ATA_STRIDE
+#define CONFIG_SYS_ATA_STRIDE	1
+#endif
+
+#define ATA_IO_DATA(x)	(CONFIG_SYS_ATA_DATA_OFFSET+((x) * CONFIG_SYS_ATA_STRIDE))
+#define ATA_IO_REG(x)	(CONFIG_SYS_ATA_REG_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
+#define ATA_IO_ALT(x)	(CONFIG_SYS_ATA_ALT_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
+
+/*
+ * I/O Register Descriptions
+ */
+#define ATA_DATA_REG	ATA_IO_DATA(0)
+#define ATA_ERROR_REG	ATA_IO_REG(1)
+#define ATA_SECT_CNT	ATA_IO_REG(2)
+#define ATA_SECT_NUM	ATA_IO_REG(3)
+#define ATA_CYL_LOW	ATA_IO_REG(4)
+#define ATA_CYL_HIGH	ATA_IO_REG(5)
+#define ATA_DEV_HD	ATA_IO_REG(6)
+#define ATA_COMMAND	ATA_IO_REG(7)
+#define ATA_DATA_EVEN	ATA_IO_REG(8)
+#define ATA_DATA_ODD	ATA_IO_REG(9)
+#define ATA_STATUS	ATA_COMMAND
+#define ATA_DEV_CTL	ATA_IO_ALT(6)
+#define ATA_LBA_LOW	ATA_SECT_NUM
+#define ATA_LBA_MID	ATA_CYL_LOW
+#define ATA_LBA_HIGH	ATA_CYL_HIGH
+#define ATA_LBA_SEL	ATA_DEV_CTL
+
+/*
+ * Status register bits
+ */
+#define ATA_STAT_BUSY	0x80	/* Device Busy			*/
+#define ATA_STAT_READY	0x40	/* Device Ready			*/
+#define ATA_STAT_FAULT	0x20	/* Device Fault			*/
+#define ATA_STAT_SEEK	0x10	/* Device Seek Complete		*/
+#define ATA_STAT_DRQ	0x08	/* Data Request (ready)		*/
+#define ATA_STAT_CORR	0x04	/* Corrected Data Error		*/
+#define ATA_STAT_INDEX	0x02	/* Vendor specific		*/
+#define ATA_STAT_ERR	0x01	/* Error			*/
+
+/*
+ * Device / Head Register Bits
+ */
+#ifndef ATA_DEVICE
+#define ATA_DEVICE(x)	((x & 1)<<4)
+#endif /* ATA_DEVICE */
+#define ATA_LBA		0xE0
+
+/*
+ * ATA Commands (only mandatory commands listed here)
+ */
+#define ATA_CMD_READ	0x20	/* Read Sectors (with retries)	*/
+#define ATA_CMD_READN	0x21	/* Read Sectors ( no  retries)	*/
+#define ATA_CMD_WRITE	0x30	/* Write Sectores (with retries)*/
+#define ATA_CMD_WRITEN	0x31	/* Write Sectors  ( no  retries)*/
+#define ATA_CMD_VRFY	0x40	/* Read Verify  (with retries)	*/
+#define ATA_CMD_VRFYN	0x41	/* Read verify  ( no  retries)	*/
+#define ATA_CMD_SEEK	0x70	/* Seek				*/
+#define ATA_CMD_DIAG	0x90	/* Execute Device Diagnostic	*/
+#define ATA_CMD_INIT	0x91	/* Initialize Device Parameters	*/
+#define ATA_CMD_RD_MULT	0xC4	/* Read Multiple		*/
+#define ATA_CMD_WR_MULT	0xC5	/* Write Multiple		*/
+#define ATA_CMD_SETMULT	0xC6	/* Set Multiple Mode		*/
+#define ATA_CMD_RD_DMA	0xC8	/* Read DMA (with retries)	*/
+#define ATA_CMD_RD_DMAN	0xC9	/* Read DMS ( no  retries)	*/
+#define ATA_CMD_WR_DMA	0xCA	/* Write DMA (with retries)	*/
+#define ATA_CMD_WR_DMAN	0xCB	/* Write DMA ( no  retires)	*/
+#define ATA_CMD_IDENT	0xEC	/* Identify Device		*/
+#define ATA_CMD_SETF	0xEF	/* Set Features			*/
+#define ATA_CMD_CHK_PWR	0xE5	/* Check Power Mode		*/
+
+#define ATA_CMD_READ_EXT 0x24	/* Read Sectors (with retries)	with 48bit addressing */
+#define ATA_CMD_WRITE_EXT	0x34	/* Write Sectores (with retries) with 48bit addressing */
+#define ATA_CMD_VRFY_EXT	0x42	/* Read Verify	(with retries)	with 48bit addressing */
+
+#define ATA_CMD_FLUSH 0xE7 /* Flush drive cache */
+#define ATA_CMD_FLUSH_EXT 0xEA /* Flush drive cache, with 48bit addressing */
+
+/*
+ * ATAPI Commands
+ */
+#define ATAPI_CMD_IDENT 0xA1 /* Identify AT Atachment Packed Interface Device */
+#define ATAPI_CMD_PACKET 0xA0 /* Packed Command */
+
+
+#define ATAPI_CMD_INQUIRY 0x12
+#define ATAPI_CMD_REQ_SENSE 0x03
+#define ATAPI_CMD_READ_CAP 0x25
+#define ATAPI_CMD_START_STOP 0x1B
+#define ATAPI_CMD_READ_12 0xA8
+
+
+#define ATA_GET_ERR()	inb(ATA_STATUS)
+#define ATA_GET_STAT()	inb(ATA_STATUS)
+#define ATA_OK_STAT(stat,good,bad)	(((stat)&((good)|(bad)))==(good))
+#define ATA_BAD_R_STAT	(ATA_STAT_BUSY	| ATA_STAT_ERR)
+#define ATA_BAD_W_STAT	(ATA_BAD_R_STAT	| ATA_STAT_FAULT)
+#define ATA_BAD_STAT	(ATA_BAD_R_STAT	| ATA_STAT_DRQ)
+#define ATA_DRIVE_READY	(ATA_READY_STAT	| ATA_STAT_SEEK)
+#define ATA_DATA_READY	(ATA_STAT_DRQ)
+
+#define ATA_BLOCKSIZE	512	/* bytes */
+#define ATA_BLOCKSHIFT	9	/* 2 ^ ATA_BLOCKSIZESHIFT = 512 */
+#define ATA_SECTORWORDS	(512 / sizeof(uint32_t))
+
+#ifndef ATA_RESET_TIME
+#define ATA_RESET_TIME	60	/* spec allows up to 31 seconds */
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * structure returned by ATA_CMD_IDENT, as per ANSI ATA2 rev.2f spec
+ */
+typedef struct hd_driveid {
+	unsigned short	config;		/* lots of obsolete bit flags */
+	unsigned short	cyls;		/* "physical" cyls */
+	unsigned short	reserved2;	/* reserved (word 2) */
+	unsigned short	heads;		/* "physical" heads */
+	unsigned short	track_bytes;	/* unformatted bytes per track */
+	unsigned short	sector_bytes;	/* unformatted bytes per sector */
+	unsigned short	sectors;	/* "physical" sectors per track */
+	unsigned short	vendor0;	/* vendor unique */
+	unsigned short	vendor1;	/* vendor unique */
+	unsigned short	vendor2;	/* vendor unique */
+	unsigned char	serial_no[20];	/* 0 = not_specified */
+	unsigned short	buf_type;
+	unsigned short	buf_size;	/* 512 byte increments; 0 = not_specified */
+	unsigned short	ecc_bytes;	/* for r/w long cmds; 0 = not_specified */
+	unsigned char	fw_rev[8];	/* 0 = not_specified */
+	unsigned char	model[40];	/* 0 = not_specified */
+	unsigned char	max_multsect;	/* 0=not_implemented */
+	unsigned char	vendor3;	/* vendor unique */
+	unsigned short	dword_io;	/* 0=not_implemented; 1=implemented */
+	unsigned char	vendor4;	/* vendor unique */
+	unsigned char	capability;	/* bits 0:DMA 1:LBA 2:IORDYsw 3:IORDYsup*/
+	unsigned short	reserved50;	/* reserved (word 50) */
+	unsigned char	vendor5;	/* vendor unique */
+	unsigned char	tPIO;		/* 0=slow, 1=medium, 2=fast */
+	unsigned char	vendor6;	/* vendor unique */
+	unsigned char	tDMA;		/* 0=slow, 1=medium, 2=fast */
+	unsigned short	field_valid;	/* bits 0:cur_ok 1:eide_ok */
+	unsigned short	cur_cyls;	/* logical cylinders */
+	unsigned short	cur_heads;	/* logical heads */
+	unsigned short	cur_sectors;	/* logical sectors per track */
+	unsigned short	cur_capacity0;	/* logical total sectors on drive */
+	unsigned short	cur_capacity1;	/*  (2 words, misaligned int)     */
+	unsigned char	multsect;	/* current multiple sector count */
+	unsigned char	multsect_valid;	/* when (bit0==1) multsect is ok */
+	unsigned int	lba_capacity;	/* total number of sectors */
+	unsigned short	dma_1word;	/* single-word dma info */
+	unsigned short	dma_mword;	/* multiple-word dma info */
+	unsigned short  eide_pio_modes; /* bits 0:mode3 1:mode4 */
+	unsigned short  eide_dma_min;	/* min mword dma cycle time (ns) */
+	unsigned short  eide_dma_time;	/* recommended mword dma cycle time (ns) */
+	unsigned short  eide_pio;       /* min cycle time (ns), no IORDY  */
+	unsigned short  eide_pio_iordy; /* min cycle time (ns), with IORDY */
+	unsigned short	words69_70[2];	/* reserved words 69-70 */
+	unsigned short	words71_74[4];	/* reserved words 71-74 */
+	unsigned short  queue_depth;	/*  */
+	unsigned short  words76_79[4];	/* reserved words 76-79 */
+	unsigned short  major_rev_num;	/*  */
+	unsigned short  minor_rev_num;	/*  */
+	unsigned short  command_set_1;	/* bits 0:Smart 1:Security 2:Removable 3:PM */
+	unsigned short	command_set_2;	/* bits 14:Smart Enabled 13:0 zero 10:lba48 support*/
+	unsigned short  cfsse;		/* command set-feature supported extensions */
+	unsigned short  cfs_enable_1;	/* command set-feature enabled */
+	unsigned short  cfs_enable_2;	/* command set-feature enabled */
+	unsigned short  csf_default;	/* command set-feature default */
+	unsigned short  dma_ultra;	/*  */
+	unsigned short	word89;		/* reserved (word 89) */
+	unsigned short	word90;		/* reserved (word 90) */
+	unsigned short	CurAPMvalues;	/* current APM values */
+	unsigned short	word92;		/* reserved (word 92) */
+	unsigned short	hw_config;	/* hardware config */
+	unsigned short	words94_99[6];/* reserved words 94-99 */
+	/*unsigned long long  lba48_capacity; /--* 4 16bit values containing lba 48 total number of sectors */
+	unsigned short	lba48_capacity[4]; /* 4 16bit values containing lba 48 total number of sectors */
+	unsigned short	words104_125[22];/* reserved words 104-125 */
+	unsigned short	last_lun;	/* reserved (word 126) */
+	unsigned short	word127;	/* reserved (word 127) */
+	unsigned short	dlf;		/* device lock function
+					 * 15:9	reserved
+					 * 8	security level 1:max 0:high
+					 * 7:6	reserved
+					 * 5	enhanced erase
+					 * 4	expire
+					 * 3	frozen
+					 * 2	locked
+					 * 1	en/disabled
+					 * 0	capability
+					 */
+	unsigned short  csfo;		/* current set features options
+					 * 15:4	reserved
+					 * 3	auto reassign
+					 * 2	reverting
+					 * 1	read-look-ahead
+					 * 0	write cache
+					 */
+	unsigned short	words130_155[26];/* reserved vendor words 130-155 */
+	unsigned short	word156;
+	unsigned short	words157_159[3];/* reserved vendor words 157-159 */
+	unsigned short	words160_162[3];/* reserved words 160-162 */
+	unsigned short	cf_advanced_caps;
+	unsigned short	words164_255[92];/* reserved words 164-255 */
+} hd_driveid_t;
+
+
+/*
+ * PIO Mode Configuration
+ *
+ * See ATA-3 (AT Attachment-3 Interface) documentation, Figure 14 / Table 21
+ */
+
+typedef struct {
+	unsigned int	t_setup;	/* Setup  Time in [ns] or clocks	*/
+	unsigned int	t_length;	/* Length Time in [ns] or clocks	*/
+	unsigned int	t_hold;		/* Hold   Time in [ns] or clocks	*/
+}
+pio_config_t;
+
+#define	IDE_MAX_PIO_MODE	4	/* max suppurted PIO mode		*/
+
+/* ------------------------------------------------------------------------- */
+
+#endif /* _ATA_H */

u-boot/include/atmel_hlcdc.h

@@ -0,0 +1,226 @@
+/*
+ *  Header file for AT91/AT32 MULTI LAYER LCD Controller
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2012 Atmel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ATMEL_HLCDC_H__
+#define __ATMEL_HLCDC_H__
+
+/* Atmel multi layer lcdc hardware registers */
+struct atmel_hlcd_regs {
+	u32	lcdc_lcdcfg0;
+	u32	lcdc_lcdcfg1;
+	u32	lcdc_lcdcfg2;
+	u32	lcdc_lcdcfg3;
+	u32	lcdc_lcdcfg4;
+	u32	lcdc_lcdcfg5;
+	u32	lcdc_lcdcfg6;
+	u32	res1;
+	u32	lcdc_lcden;
+	u32	lcdc_lcddis;
+	u32	lcdc_lcdsr;
+	u32	res2;
+	u32	lcdc_lcdidr;
+	u32	res3[3];
+	u32	lcdc_basecher;
+	u32	res4[3];
+	u32	lcdc_baseidr;
+	u32	res5[3];
+	u32	lcdc_baseaddr;
+	u32	lcdc_basectrl;
+	u32	lcdc_basenext;
+	u32	lcdc_basecfg0;
+	u32	lcdc_basecfg1;
+	u32	lcdc_basecfg2;
+	u32	lcdc_basecfg3;
+	u32	lcdc_basecfg4;
+};
+
+#define LCDC_LCDCFG0_CLKPOL	(0x1 << 0)
+#define LCDC_LCDCFG0_CLKSEL	(0x1 << 2)
+#define LCDC_LCDCFG0_CLKPWMSEL	(0x1 << 3)
+#define LCDC_LCDCFG0_CGDISBASE	(0x1 << 8)
+#define LCDC_LCDCFG0_CGDISOVR1	(0x1 << 9)
+#define LCDC_LCDCFG0_CGDISHEO	(0x1 << 11)
+#define LCDC_LCDCFG0_CGDISHCR	(0x1 << 12)
+#define LCDC_LCDCFG0_CLKDIV_Pos	16
+#define LCDC_LCDCFG0_CLKDIV_Msk	(0xff << LCDC_LCDCFG0_CLKDIV_Pos)
+#define LCDC_LCDCFG0_CLKDIV(value) \
+	((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
+
+#define LCDC_LCDCFG1_HSPW_Pos	0
+#define LCDC_LCDCFG1_HSPW_Msk	(0x3f << LCDC_LCDCFG1_HSPW_Pos)
+#define LCDC_LCDCFG1_HSPW(value) \
+	((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
+#define LCDC_LCDCFG1_VSPW_Pos	16
+#define LCDC_LCDCFG1_VSPW_Msk	(0x3f << LCDC_LCDCFG1_VSPW_Pos)
+#define LCDC_LCDCFG1_VSPW(value) \
+	((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
+
+#define LCDC_LCDCFG2_VFPW_Pos	0
+#define LCDC_LCDCFG2_VFPW_Msk	(0x3f << LCDC_LCDCFG2_VFPW_Pos)
+#define LCDC_LCDCFG2_VFPW(value) \
+	((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
+#define LCDC_LCDCFG2_VBPW_Pos	16
+#define LCDC_LCDCFG2_VBPW_Msk	(0x3f << LCDC_LCDCFG2_VBPW_Pos)
+#define LCDC_LCDCFG2_VBPW(value) \
+	((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
+
+#define LCDC_LCDCFG3_HFPW_Pos	0
+#define LCDC_LCDCFG3_HFPW_Msk	(0xff << LCDC_LCDCFG3_HFPW_Pos)
+#define LCDC_LCDCFG3_HFPW(value) \
+	((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
+#define LCDC_LCDCFG3_HBPW_Pos	16
+#define LCDC_LCDCFG3_HBPW_Msk	(0xff << LCDC_LCDCFG3_HBPW_Pos)
+#define LCDC_LCDCFG3_HBPW(value) \
+	((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
+
+#define LCDC_LCDCFG4_PPL_Pos	0
+#define LCDC_LCDCFG4_PPL_Msk	(0x7ff << LCDC_LCDCFG4_PPL_Pos)
+#define LCDC_LCDCFG4_PPL(value) \
+	((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
+#define LCDC_LCDCFG4_RPF_Pos	16
+#define LCDC_LCDCFG4_RPF_Msk	(0x7ff << LCDC_LCDCFG4_RPF_Pos)
+#define LCDC_LCDCFG4_RPF(value) \
+	((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
+
+#define LCDC_LCDCFG5_HSPOL	(0x1 << 0)
+#define LCDC_LCDCFG5_VSPOL	(0x1 << 1)
+#define LCDC_LCDCFG5_VSPDLYS	(0x1 << 2)
+#define LCDC_LCDCFG5_VSPDLYE	(0x1 << 3)
+#define LCDC_LCDCFG5_DISPPOL	(0x1 << 4)
+#define LCDC_LCDCFG5_SERIAL	(0x1 << 5)
+#define LCDC_LCDCFG5_DITHER	(0x1 << 6)
+#define LCDC_LCDCFG5_DISPDLY	(0x1 << 7)
+#define LCDC_LCDCFG5_MODE_Pos	8
+#define LCDC_LCDCFG5_MODE_Msk	(0x3 << LCDC_LCDCFG5_MODE_Pos)
+#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP	(0x0 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP	(0x1 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP	(0x2 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP	(0x3 << 8)
+#define LCDC_LCDCFG5_VSPSU		(0x1 << 12)
+#define LCDC_LCDCFG5_VSPHO		(0x1 << 13)
+#define LCDC_LCDCFG5_GUARDTIME_Pos	16
+#define LCDC_LCDCFG5_GUARDTIME_Msk	(0x1f << LCDC_LCDCFG5_GUARDTIME_Pos)
+#define LCDC_LCDCFG5_GUARDTIME(value) \
+	((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
+
+#define LCDC_LCDCFG6_PWMPS_Pos		0
+#define LCDC_LCDCFG6_PWMPS_Msk		(0x7 << LCDC_LCDCFG6_PWMPS_Pos)
+#define LCDC_LCDCFG6_PWMPS(value) \
+	((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
+#define LCDC_LCDCFG6_PWMPOL		(0x1 << 4)
+#define LCDC_LCDCFG6_PWMCVAL_Pos	8
+#define LCDC_LCDCFG6_PWMCVAL_Msk	(0xff << LCDC_LCDCFG6_PWMCVAL_Pos)
+#define LCDC_LCDCFG6_PWMCVAL(value) \
+	((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
+
+#define LCDC_LCDEN_CLKEN	(0x1 << 0)
+#define LCDC_LCDEN_SYNCEN	(0x1 << 1)
+#define LCDC_LCDEN_DISPEN	(0x1 << 2)
+#define LCDC_LCDEN_PWMEN	(0x1 << 3)
+
+#define LCDC_LCDDIS_CLKDIS	(0x1 << 0)
+#define LCDC_LCDDIS_SYNCDIS	(0x1 << 1)
+#define LCDC_LCDDIS_DISPDIS	(0x1 << 2)
+#define LCDC_LCDDIS_PWMDIS	(0x1 << 3)
+#define LCDC_LCDDIS_CLKRST	(0x1 << 8)
+#define LCDC_LCDDIS_SYNCRST	(0x1 << 9)
+#define LCDC_LCDDIS_DISPRST	(0x1 << 10)
+#define LCDC_LCDDIS_PWMRST	(0x1 << 11)
+
+#define LCDC_LCDSR_CLKSTS	(0x1 << 0)
+#define LCDC_LCDSR_LCDSTS	(0x1 << 1)
+#define LCDC_LCDSR_DISPSTS	(0x1 << 2)
+#define LCDC_LCDSR_PWMSTS	(0x1 << 3)
+#define LCDC_LCDSR_SIPSTS	(0x1 << 4)
+
+#define LCDC_LCDIDR_SOFID	(0x1 << 0)
+#define LCDC_LCDIDR_DISID	(0x1 << 1)
+#define LCDC_LCDIDR_DISPID	(0x1 << 2)
+#define LCDC_LCDIDR_FIFOERRID	(0x1 << 4)
+#define LCDC_LCDIDR_BASEID	(0x1 << 8)
+#define LCDC_LCDIDR_OVR1ID	(0x1 << 9)
+#define LCDC_LCDIDR_HEOID	(0x1 << 11)
+#define LCDC_LCDIDR_HCRID	(0x1 << 12)
+
+#define LCDC_BASECHER_CHEN	(0x1 << 0)
+#define LCDC_BASECHER_UPDATEEN	(0x1 << 1)
+#define LCDC_BASECHER_A2QEN	(0x1 << 2)
+
+#define LCDC_BASEIDR_DMA	(0x1 << 2)
+#define LCDC_BASEIDR_DSCR	(0x1 << 3)
+#define LCDC_BASEIDR_ADD	(0x1 << 4)
+#define LCDC_BASEIDR_DONE	(0x1 << 5)
+#define LCDC_BASEIDR_OVR	(0x1 << 6)
+
+#define LCDC_BASECTRL_DFETCH	(0x1 << 0)
+#define LCDC_BASECTRL_LFETCH	(0x1 << 1)
+#define LCDC_BASECTRL_DMAIEN	(0x1 << 2)
+#define LCDC_BASECTRL_DSCRIEN	(0x1 << 3)
+#define LCDC_BASECTRL_ADDIEN	(0x1 << 4)
+#define LCDC_BASECTRL_DONEIEN	(0x1 << 5)
+
+#define LCDC_BASECFG0_BLEN_Pos		4
+#define LCDC_BASECFG0_BLEN_AHB_SINGLE	(0x0 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR4	(0x1 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR8	(0x2 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR16	(0x3 << 4)
+#define LCDC_BASECFG0_DLBO		(0x1 << 8)
+
+#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444		(0x0 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444		(0x1 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444		(0x2 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565		(0x3 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555		(0x4 << 4)
+#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666		(0x5 << 4)
+#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
+#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666		(0x7 << 4)
+#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED		(0x8 << 4)
+#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888		(0x9 << 4)
+#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
+#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888		(0xB << 4)
+#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888		(0xC << 4)
+#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888		(0xD << 4)
+
+#define LCDC_BASECFG2_XSTRIDE_Pos 0
+#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos)
+#define LCDC_BASECFG2_XSTRIDE(value) \
+	((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
+
+#define LCDC_BASECFG3_BDEF_Pos	0
+#define LCDC_BASECFG3_BDEF_Msk	(0xff << LCDC_BASECFG3_BDEF_Pos)
+#define LCDC_BASECFG3_BDEF(value) \
+	((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
+#define LCDC_BASECFG3_GDEF_Pos	8
+#define LCDC_BASECFG3_GDEF_Msk	(0xff << LCDC_BASECFG3_GDEF_Pos)
+#define LCDC_BASECFG3_GDEF(value) \
+	((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
+#define LCDC_BASECFG3_RDEF_Pos	16
+#define LCDC_BASECFG3_RDEF_Msk	(0xff << LCDC_BASECFG3_RDEF_Pos)
+#define LCDC_BASECFG3_RDEF(value) \
+	((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
+
+#define LCDC_BASECLUT_BCLUT_Pos 0
+#define LCDC_BASECLUT_BCLUT_Msk (0xff << LCDC_BASECLUT_BCLUT_Pos)
+#define LCDC_BASECLUT_GCLUT_Pos 8
+#define LCDC_BASECLUT_GCLUT_Msk (0xff << LCDC_BASECLUT_GCLUT_Pos)
+#define LCDC_BASECLUT_RCLUT_Pos 16
+#define LCDC_BASECLUT_RCLUT_Msk (0xff << LCDC_BASECLUT_RCLUT_Pos)
+
+#define LCDC_BASECFG4_DMA	(0x1 << 8)
+#define LCDC_BASECFG4_REP	(0x1 << 9)
+
+struct lcd_dma_desc {
+	u32	address;
+	u32	control;
+	u32	next;
+};
+
+#define ATMEL_LCDC_LUT(n)	(0x0400 + ((n)*4))
+
+#endif /* __ATMEL_HLCDC_H__ */

u-boot/include/atmel_lcd.h

@@ -0,0 +1,48 @@
+/*
+ * atmel_lcd.h - Atmel LCD Controller structures
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ATMEL_LCD_H_
+#define _ATMEL_LCD_H_
+
+/**
+ * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model
+ *
+ * @timing_index:	Index of LCD timing to use in device tree node
+ */
+struct atmel_lcd_platdata {
+	int timing_index;
+};
+
+typedef struct vidinfo {
+	ushort vl_col;		/* Number of columns (i.e. 640) */
+	ushort vl_row;		/* Number of rows (i.e. 480) */
+	ushort vl_rot;		/* Rotation of Display (0, 1, 2, 3) */
+	u_long vl_clk;		/* pixel clock in ps    */
+
+	/* LCD configuration register */
+	u_long vl_sync;		/* Horizontal / vertical sync */
+	u_long vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
+	u_long vl_tft;		/* 0 = passive, 1 = TFT */
+	u_long vl_cont_pol_low;	/* contrast polarity is low */
+	u_long vl_clk_pol;	/* clock polarity */
+
+	/* Horizontal control register. */
+	u_long vl_hsync_len;	/* Length of horizontal sync */
+	u_long vl_left_margin;	/* Time from sync to picture */
+	u_long vl_right_margin;	/* Time from picture to sync */
+
+	/* Vertical control register. */
+	u_long vl_vsync_len;	/* Length of vertical sync */
+	u_long vl_upper_margin;	/* Time from sync to picture */
+	u_long vl_lower_margin;	/* Time from picture to sync */
+
+	u_long	mmio;		/* Memory mapped registers */
+} vidinfo_t;
+
+#endif

u-boot/include/atmel_lcdc.h

@@ -0,0 +1,165 @@
+/*
+ *  Header file for AT91/AT32 LCD Controller
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ATMEL_LCDC_H__
+#define __ATMEL_LCDC_H__
+
+#define ATMEL_LCDC_DMABADDR1	0x00
+#define ATMEL_LCDC_DMABADDR2	0x04
+#define ATMEL_LCDC_DMAFRMPT1	0x08
+#define ATMEL_LCDC_DMAFRMPT2	0x0c
+#define ATMEL_LCDC_DMAFRMADD1	0x10
+#define ATMEL_LCDC_DMAFRMADD2	0x14
+
+#define ATMEL_LCDC_DMAFRMCFG	0x18
+#define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
+#define	ATMEL_LCDC_BLENGTH_OFFSET	24
+#define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
+
+#define ATMEL_LCDC_DMACON	0x1c
+#define	ATMEL_LCDC_DMAEN	(0x1 << 0)
+#define	ATMEL_LCDC_DMARST	(0x1 << 1)
+#define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
+#define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
+#define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
+
+#define ATMEL_LCDC_DMA2DCFG	0x20
+#define		ATMEL_LCDC_ADDRINC_OFFSET	0
+#define		ATMEL_LCDC_ADDRINC		(0xffff)
+#define		ATMEL_LCDC_PIXELOFF_OFFSET	24
+#define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
+
+#define ATMEL_LCDC_LCDCON1	0x0800
+#define	ATMEL_LCDC_BYPASS	(1     <<  0)
+#define	ATMEL_LCDC_CLKVAL_OFFSET	12
+#define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
+#define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
+
+#define ATMEL_LCDC_LCDCON2	0x0804
+#define	ATMEL_LCDC_DISTYPE	(3 << 0)
+#define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
+#define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
+#define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
+#define	ATMEL_LCDC_SCANMOD	(1 << 2)
+#define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
+#define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
+#define	ATMEL_LCDC_IFWIDTH	(3 << 3)
+#define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
+#define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
+#define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
+#define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
+#define	ATMEL_LCDC_INVVD	(1 << 8)
+#define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
+#define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
+#define	ATMEL_LCDC_INVFRAME	(1 << 9 )
+#define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
+#define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
+#define	ATMEL_LCDC_INVLINE	(1 << 10)
+#define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
+#define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
+#define	ATMEL_LCDC_INVCLK	(1 << 11)
+#define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
+#define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
+#define	ATMEL_LCDC_INVDVAL	(1 << 12)
+#define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
+#define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
+#define	ATMEL_LCDC_CLKMOD	(1 << 15)
+#define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
+#define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
+#define	ATMEL_LCDC_MEMOR	(1 << 31)
+#define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
+#define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
+
+#define ATMEL_LCDC_TIM1		0x0808
+#define	ATMEL_LCDC_VFP		(0xffU <<  0)
+#define	ATMEL_LCDC_VBP_OFFSET		8
+#define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
+#define	ATMEL_LCDC_VPW_OFFSET		16
+#define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
+#define	ATMEL_LCDC_VHDLY_OFFSET		24
+#define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
+
+#define ATMEL_LCDC_TIM2		0x080c
+#define	ATMEL_LCDC_HBP		(0xffU  <<  0)
+#define	ATMEL_LCDC_HPW_OFFSET		8
+#define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
+#define	ATMEL_LCDC_HFP_OFFSET		21
+#define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
+
+#define ATMEL_LCDC_LCDFRMCFG	0x0810
+#define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
+#define	ATMEL_LCDC_HOZVAL_OFFSET	21
+#define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
+
+#define ATMEL_LCDC_FIFO		0x0814
+#define	ATMEL_LCDC_FIFOTH	(0xffff)
+
+#define ATMEL_LCDC_MVAL		0x0818
+
+#define ATMEL_LCDC_DP1_2	0x081c
+#define ATMEL_LCDC_DP4_7	0x0820
+#define ATMEL_LCDC_DP3_5	0x0824
+#define ATMEL_LCDC_DP2_3	0x0828
+#define ATMEL_LCDC_DP5_7	0x082c
+#define ATMEL_LCDC_DP3_4	0x0830
+#define ATMEL_LCDC_DP4_5	0x0834
+#define ATMEL_LCDC_DP6_7	0x0838
+#define	ATMEL_LCDC_DP1_2_VAL	(0xff)
+#define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
+#define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
+#define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
+#define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
+#define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
+#define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
+#define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
+
+#define ATMEL_LCDC_PWRCON	0x083c
+#define	ATMEL_LCDC_PWR		(1    <<  0)
+#define	ATMEL_LCDC_GUARDT_OFFSET	1
+#define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
+#define	ATMEL_LCDC_BUSY		(1    << 31)
+
+#define ATMEL_LCDC_CONTRAST_CTR	0x0840
+#define	ATMEL_LCDC_PS		(3 << 0)
+#define		ATMEL_LCDC_PS_DIV1		(0 << 0)
+#define		ATMEL_LCDC_PS_DIV2		(1 << 0)
+#define		ATMEL_LCDC_PS_DIV4		(2 << 0)
+#define		ATMEL_LCDC_PS_DIV8		(3 << 0)
+#define	ATMEL_LCDC_POL		(1 << 2)
+#define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
+#define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
+#define	ATMEL_LCDC_ENA		(1 << 3)
+#define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
+#define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
+
+#define ATMEL_LCDC_CONTRAST_VAL	0x0844
+#define	ATMEL_LCDC_CVAL	(0xff)
+
+#define ATMEL_LCDC_IER		0x0848
+#define ATMEL_LCDC_IDR		0x084c
+#define ATMEL_LCDC_IMR		0x0850
+#define ATMEL_LCDC_ISR		0x0854
+#define ATMEL_LCDC_ICR		0x0858
+#define	ATMEL_LCDC_LNI		(1 << 0)
+#define	ATMEL_LCDC_LSTLNI	(1 << 1)
+#define	ATMEL_LCDC_EOFI		(1 << 2)
+#define	ATMEL_LCDC_UFLWI	(1 << 4)
+#define	ATMEL_LCDC_OWRI		(1 << 5)
+#define	ATMEL_LCDC_MERI		(1 << 6)
+
+#define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
+
+#endif /* __ATMEL_LCDC_H__ */

u-boot/include/atmel_mci.h

@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ATMEL_MCI_H__
+#define __ATMEL_MCI_H__
+
+int atmel_mci_init(void *regs);
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Structure for struct SoC access.
+ * Names starting with '_' are fillers.
+ */
+typedef struct atmel_mci {
+	/*	reg	Offset */
+	u32	cr;	/* 0x00 */
+	u32	mr;	/* 0x04 */
+	u32	dtor;	/* 0x08 */
+	u32	sdcr;	/* 0x0c */
+	u32	argr;	/* 0x10 */
+	u32	cmdr;	/* 0x14 */
+	u32	blkr;	/* 0x18 */
+	u32	_1c;	/* 0x1c */
+	u32	rspr;	/* 0x20 */
+	u32	rspr1;	/* 0x24 */
+	u32	rspr2;	/* 0x28 */
+	u32	rspr3;	/* 0x2c */
+	u32	rdr;	/* 0x30 */
+	u32	tdr;	/* 0x34 */
+	u32	_38;	/* 0x38 */
+	u32	_3c;	/* 0x3c */
+	u32	sr;	/* 0x40 */
+	u32	ier;	/* 0x44 */
+	u32	idr;	/* 0x48 */
+	u32	imr;	/* 0x4c */
+	u32	dma;	/* 0x50 */
+	u32	cfg;	/* 0x54 */
+	u32	reserved[41];
+	u32	version;
+} atmel_mci_t;
+
+#endif /* __ASSEMBLY__ */
+
+/* Bitfields in CR */
+#define MMCI_MCIEN_OFFSET			0
+#define MMCI_MCIEN_SIZE				1
+#define MMCI_MCIDIS_OFFSET			1
+#define MMCI_MCIDIS_SIZE			1
+#define MMCI_PWSEN_OFFSET			2
+#define MMCI_PWSEN_SIZE				1
+#define MMCI_PWSDIS_OFFSET			3
+#define MMCI_PWSDIS_SIZE			1
+#define MMCI_SWRST_OFFSET			7
+#define MMCI_SWRST_SIZE				1
+
+/* Bitfields in MR */
+#define MMCI_CLKDIV_OFFSET			0
+#define MMCI_CLKDIV_SIZE			8
+#define MMCI_PWSDIV_OFFSET			8
+#define MMCI_PWSDIV_SIZE			3
+#define MMCI_RDPROOF_OFFSET			11
+#define MMCI_RDPROOF_SIZE			1
+#define MMCI_WRPROOF_OFFSET			12
+#define MMCI_WRPROOF_SIZE			1
+#define MMCI_PDCPADV_OFFSET			14
+#define MMCI_PDCPADV_SIZE			1
+#define MMCI_PDCMODE_OFFSET			15
+#define MMCI_PDCMODE_SIZE			1
+/* MCI IP version >= 0x500, MR bit 16 used for CLKODD */
+#define MMCI_CLKODD_OFFSET			16
+#define MMCI_CLKODD_SIZE			1
+/* MCI IP version < 0x200, MR higher 16bits for BLKLEN */
+#define MMCI_BLKLEN_OFFSET			16
+#define MMCI_BLKLEN_SIZE			16
+
+/* Bitfields in DTOR */
+#define MMCI_DTOCYC_OFFSET			0
+#define MMCI_DTOCYC_SIZE			4
+#define MMCI_DTOMUL_OFFSET			4
+#define MMCI_DTOMUL_SIZE			3
+
+/* Bitfields in SDCR */
+#define MMCI_SCDSEL_OFFSET			0
+#define MMCI_SCDSEL_SIZE			4
+#define MMCI_SCDBUS_OFFSET			7
+#define MMCI_SCDBUS_SIZE			1
+
+/* Bitfields in ARGR */
+#define MMCI_ARG_OFFSET				0
+#define MMCI_ARG_SIZE				32
+
+/* Bitfields in CMDR */
+#define MMCI_CMDNB_OFFSET			0
+#define MMCI_CMDNB_SIZE				6
+#define MMCI_RSPTYP_OFFSET			6
+#define MMCI_RSPTYP_SIZE			2
+#define MMCI_SPCMD_OFFSET			8
+#define MMCI_SPCMD_SIZE				3
+#define MMCI_OPDCMD_OFFSET			11
+#define MMCI_OPDCMD_SIZE			1
+#define MMCI_MAXLAT_OFFSET			12
+#define MMCI_MAXLAT_SIZE			1
+#define MMCI_TRCMD_OFFSET			16
+#define MMCI_TRCMD_SIZE				2
+#define MMCI_TRDIR_OFFSET			18
+#define MMCI_TRDIR_SIZE				1
+#define MMCI_TRTYP_OFFSET			19
+#define MMCI_TRTYP_SIZE				2
+
+/* Bitfields in BLKR */
+/* MMCI_BLKLEN_OFFSET/SIZE already defined in MR */
+#define MMCI_BCNT_OFFSET			0
+#define MMCI_BCNT_SIZE			16
+
+/* Bitfields in RSPRx */
+#define MMCI_RSP_OFFSET				0
+#define MMCI_RSP_SIZE				32
+
+/* Bitfields in SR/IER/IDR/IMR */
+#define MMCI_CMDRDY_OFFSET			0
+#define MMCI_CMDRDY_SIZE			1
+#define MMCI_RXRDY_OFFSET			1
+#define MMCI_RXRDY_SIZE				1
+#define MMCI_TXRDY_OFFSET			2
+#define MMCI_TXRDY_SIZE				1
+#define MMCI_BLKE_OFFSET			3
+#define MMCI_BLKE_SIZE				1
+#define MMCI_DTIP_OFFSET			4
+#define MMCI_DTIP_SIZE				1
+#define MMCI_NOTBUSY_OFFSET			5
+#define MMCI_NOTBUSY_SIZE			1
+#define MMCI_ENDRX_OFFSET			6
+#define MMCI_ENDRX_SIZE				1
+#define MMCI_ENDTX_OFFSET			7
+#define MMCI_ENDTX_SIZE				1
+#define MMCI_RXBUFF_OFFSET			14
+#define MMCI_RXBUFF_SIZE			1
+#define MMCI_TXBUFE_OFFSET			15
+#define MMCI_TXBUFE_SIZE			1
+#define MMCI_RINDE_OFFSET			16
+#define MMCI_RINDE_SIZE				1
+#define MMCI_RDIRE_OFFSET			17
+#define MMCI_RDIRE_SIZE				1
+#define MMCI_RCRCE_OFFSET			18
+#define MMCI_RCRCE_SIZE				1
+#define MMCI_RENDE_OFFSET			19
+#define MMCI_RENDE_SIZE				1
+#define MMCI_RTOE_OFFSET			20
+#define MMCI_RTOE_SIZE				1
+#define MMCI_DCRCE_OFFSET			21
+#define MMCI_DCRCE_SIZE				1
+#define MMCI_DTOE_OFFSET			22
+#define MMCI_DTOE_SIZE				1
+#define MMCI_OVRE_OFFSET			30
+#define MMCI_OVRE_SIZE				1
+#define MMCI_UNRE_OFFSET			31
+#define MMCI_UNRE_SIZE				1
+
+/* Constants for DTOMUL */
+#define MMCI_DTOMUL_1_CYCLE			0
+#define MMCI_DTOMUL_16_CYCLES			1
+#define MMCI_DTOMUL_128_CYCLES			2
+#define MMCI_DTOMUL_256_CYCLES			3
+#define MMCI_DTOMUL_1024_CYCLES			4
+#define MMCI_DTOMUL_4096_CYCLES			5
+#define MMCI_DTOMUL_65536_CYCLES		6
+#define MMCI_DTOMUL_1048576_CYCLES		7
+
+/* Constants for RSPTYP */
+#define MMCI_RSPTYP_NO_RESP			0
+#define MMCI_RSPTYP_48_BIT_RESP			1
+#define MMCI_RSPTYP_136_BIT_RESP		2
+
+/* Constants for SPCMD */
+#define MMCI_SPCMD_NO_SPEC_CMD			0
+#define MMCI_SPCMD_INIT_CMD			1
+#define MMCI_SPCMD_SYNC_CMD			2
+#define MMCI_SPCMD_INT_CMD			4
+#define MMCI_SPCMD_INT_RESP			5
+
+/* Constants for TRCMD */
+#define MMCI_TRCMD_NO_TRANS			0
+#define MMCI_TRCMD_START_TRANS			1
+#define MMCI_TRCMD_STOP_TRANS			2
+
+/* Constants for TRTYP */
+#define MMCI_TRTYP_BLOCK			0
+#define MMCI_TRTYP_MULTI_BLOCK			1
+#define MMCI_TRTYP_STREAM			2
+
+/* Bitfields in CFG */
+#define MMCI_FIFOMODE_OFFSET			0
+#define MMCI_FIFOMODE_SIZE			1
+#define MMCI_FERRCTRL_OFFSET			4
+#define MMCI_FERRCTRL_SIZE			1
+#define MMCI_HSMODE_OFFSET			8
+#define MMCI_HSMODE_SIZE			1
+#define MMCI_LSYNC_OFFSET			12
+#define MMCI_LSYNC_SIZE				1
+
+/* Bit manipulation macros */
+#define MMCI_BIT(name)					\
+	(1 << MMCI_##name##_OFFSET)
+#define MMCI_BF(name,value)				\
+	(((value) & ((1 << MMCI_##name##_SIZE) - 1))	\
+	 << MMCI_##name##_OFFSET)
+#define MMCI_BFEXT(name,value)				\
+	(((value) >> MMCI_##name##_OFFSET)\
+	 & ((1 << MMCI_##name##_SIZE) - 1))
+#define MMCI_BFINS(name,value,old)			\
+	(((old) & ~(((1 << MMCI_##name##_SIZE) - 1)	\
+		    << MMCI_##name##_OFFSET))		\
+	 | MMCI_BF(name,value))
+
+#endif /* __ATMEL_MCI_H__ */

u-boot/include/autoboot.h

@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Add to readline cmdline-editing by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AUTOBOOT_H
+#define __AUTOBOOT_H
+
+#ifdef CONFIG_AUTOBOOT
+/**
+ * bootdelay_process() - process the bootd delay
+ *
+ * Process the boot delay, boot limit, then get the value of either
+ * bootcmd, failbootcmd or altbootcmd depending on the current state.
+ * Return this command so it can be executed.
+ *
+ * @return command to executed
+ */
+const char *bootdelay_process(void);
+
+/**
+ * autoboot_command() - run the autoboot command
+ *
+ * If enabled, run the autoboot command returned from bootdelay_process().
+ * Also do the CONFIG_MENUKEY processing if enabled.
+ *
+ * @cmd: Command to run
+ */
+void autoboot_command(const char *cmd);
+#else
+static inline const char *bootdelay_process(void)
+{
+	return NULL;
+}
+
+static inline void autoboot_command(const char *s)
+{
+}
+#endif
+
+#endif

u-boot/include/axp152.h

@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+enum axp152_reg {
+	AXP152_CHIP_VERSION = 0x3,
+	AXP152_DCDC2_VOLTAGE = 0x23,
+	AXP152_DCDC3_VOLTAGE = 0x27,
+	AXP152_DCDC4_VOLTAGE = 0x2B,
+	AXP152_LDO2_VOLTAGE = 0x2A,
+	AXP152_SHUTDOWN = 0x32,
+};
+
+#define AXP152_POWEROFF			(1 << 7)
+
+/* For axp_gpio.c */
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x91
+#define AXP_GPIO2_CTRL			0x92
+#define AXP_GPIO3_CTRL			0x93
+#define AXP_GPIO_CTRL_OUTPUT_LOW		0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH		0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT			0x02 /* Input */
+#define AXP_GPIO_STATE			0x97
+#define AXP_GPIO_STATE_OFFSET			0

u-boot/include/axp209.h

@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+enum axp209_reg {
+	AXP209_POWER_STATUS = 0x00,
+	AXP209_CHIP_VERSION = 0x03,
+	AXP209_OUTPUT_CTRL = 0x12,
+	AXP209_DCDC2_VOLTAGE = 0x23,
+	AXP209_DCDC3_VOLTAGE = 0x27,
+	AXP209_LDO24_VOLTAGE = 0x28,
+	AXP209_LDO3_VOLTAGE = 0x29,
+	AXP209_IRQ_ENABLE1 = 0x40,
+	AXP209_IRQ_ENABLE2 = 0x41,
+	AXP209_IRQ_ENABLE3 = 0x42,
+	AXP209_IRQ_ENABLE4 = 0x43,
+	AXP209_IRQ_ENABLE5 = 0x44,
+	AXP209_IRQ_STATUS5 = 0x4c,
+	AXP209_SHUTDOWN = 0x32,
+};
+
+#define AXP209_POWER_STATUS_ON_BY_DC	(1 << 0)
+#define AXP209_POWER_STATUS_VBUS_USABLE	(1 << 4)
+
+#define AXP209_OUTPUT_CTRL_EXTEN	(1 << 0)
+#define AXP209_OUTPUT_CTRL_DCDC3	(1 << 1)
+#define AXP209_OUTPUT_CTRL_LDO2		(1 << 2)
+#define AXP209_OUTPUT_CTRL_LDO4		(1 << 3)
+#define AXP209_OUTPUT_CTRL_DCDC2	(1 << 4)
+#define AXP209_OUTPUT_CTRL_LDO3		(1 << 6)
+
+#define AXP209_IRQ5_PEK_UP		(1 << 6)
+#define AXP209_IRQ5_PEK_DOWN		(1 << 5)
+
+#define AXP209_POWEROFF			(1 << 7)
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO2_CTRL			0x93
+#define AXP_GPIO_CTRL_OUTPUT_LOW		0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH		0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT			0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET			4

u-boot/include/axp221.h

@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ *
+ * X-Powers AXP221 Power Management IC driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Page 0 addresses */
+#define AXP221_CHIP_ID		0x03
+#define AXP221_OUTPUT_CTRL1	0x10
+#define AXP221_OUTPUT_CTRL1_DCDC0_EN	(1 << 0)
+#define AXP221_OUTPUT_CTRL1_DCDC1_EN	(1 << 1)
+#define AXP221_OUTPUT_CTRL1_DCDC2_EN	(1 << 2)
+#define AXP221_OUTPUT_CTRL1_DCDC3_EN	(1 << 3)
+#define AXP221_OUTPUT_CTRL1_DCDC4_EN	(1 << 4)
+#define AXP221_OUTPUT_CTRL1_DCDC5_EN	(1 << 5)
+#define AXP221_OUTPUT_CTRL1_ALDO1_EN	(1 << 6)
+#define AXP221_OUTPUT_CTRL1_ALDO2_EN	(1 << 7)
+#define AXP221_OUTPUT_CTRL2	0x12
+#define AXP221_OUTPUT_CTRL2_ELDO1_EN	(1 << 0)
+#define AXP221_OUTPUT_CTRL2_ELDO2_EN	(1 << 1)
+#define AXP221_OUTPUT_CTRL2_ELDO3_EN	(1 << 2)
+#define AXP221_OUTPUT_CTRL2_DLDO1_EN	(1 << 3)
+#define AXP221_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
+#define AXP221_OUTPUT_CTRL2_DLDO3_EN	(1 << 5)
+#define AXP221_OUTPUT_CTRL2_DLDO4_EN	(1 << 6)
+#define AXP221_OUTPUT_CTRL2_DCDC1SW_EN	(1 << 7)
+#define AXP221_OUTPUT_CTRL3	0x13
+#define AXP221_OUTPUT_CTRL3_ALDO3_EN	(1 << 7)
+#define AXP221_DLDO1_CTRL	0x15
+#define AXP221_DLDO2_CTRL	0x16
+#define AXP221_DLDO3_CTRL	0x17
+#define AXP221_DLDO4_CTRL	0x18
+#define AXP221_ELDO1_CTRL	0x19
+#define AXP221_ELDO2_CTRL	0x1a
+#define AXP221_ELDO3_CTRL	0x1b
+#define AXP221_DCDC1_CTRL	0x21
+#define AXP221_DCDC2_CTRL	0x22
+#define AXP221_DCDC3_CTRL	0x23
+#define AXP221_DCDC4_CTRL	0x24
+#define AXP221_DCDC5_CTRL	0x25
+#define AXP221_ALDO1_CTRL	0x28
+#define AXP221_ALDO2_CTRL	0x29
+#define AXP221_ALDO3_CTRL	0x2a
+#define AXP221_SHUTDOWN		0x32
+#define AXP221_SHUTDOWN_POWEROFF	(1 << 7)
+#define AXP221_PAGE		0xff
+
+/* Page 1 addresses */
+#define AXP221_SID		0x20
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
+#define AXP_VBUS_IPSOUT			0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+#define AXP_MISC_CTRL			0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW		0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH		0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT			0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET			0

u-boot/include/axp809.h

@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * X-Powers AXP809 Power Management IC driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define AXP809_CHIP_ID		0x03
+
+#define AXP809_OUTPUT_CTRL1	0x10
+#define AXP809_OUTPUT_CTRL1_DC5LDO_EN	(1 << 0)
+#define AXP809_OUTPUT_CTRL1_DCDC1_EN	(1 << 1)
+#define AXP809_OUTPUT_CTRL1_DCDC2_EN	(1 << 2)
+#define AXP809_OUTPUT_CTRL1_DCDC3_EN	(1 << 3)
+#define AXP809_OUTPUT_CTRL1_DCDC4_EN	(1 << 4)
+#define AXP809_OUTPUT_CTRL1_DCDC5_EN	(1 << 5)
+#define AXP809_OUTPUT_CTRL1_ALDO1_EN	(1 << 6)
+#define AXP809_OUTPUT_CTRL1_ALDO2_EN	(1 << 7)
+#define AXP809_OUTPUT_CTRL2	0x12
+#define AXP809_OUTPUT_CTRL2_ELDO1_EN	(1 << 0)
+#define AXP809_OUTPUT_CTRL2_ELDO2_EN	(1 << 1)
+#define AXP809_OUTPUT_CTRL2_ELDO3_EN	(1 << 2)
+#define AXP809_OUTPUT_CTRL2_DLDO1_EN	(1 << 3)
+#define AXP809_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
+#define AXP809_OUTPUT_CTRL2_ALDO3_EN	(1 << 5)
+#define AXP809_OUTPUT_CTRL2_SWOUT_EN	(1 << 6)
+#define AXP809_OUTPUT_CTRL2_DC1SW_EN	(1 << 7)
+
+#define AXP809_DLDO1_CTRL	0x15
+#define AXP809_DLDO2_CTRL	0x16
+#define AXP809_ELDO1_CTRL	0x19
+#define AXP809_ELDO2_CTRL	0x1a
+#define AXP809_ELDO3_CTRL	0x1b
+#define AXP809_DC5LDO_CTRL	0x1c
+#define AXP809_DCDC1_CTRL	0x21
+#define AXP809_DCDC2_CTRL	0x22
+#define AXP809_DCDC3_CTRL	0x23
+#define AXP809_DCDC4_CTRL	0x24
+#define AXP809_DCDC5_CTRL	0x25
+#define AXP809_ALDO1_CTRL	0x28
+#define AXP809_ALDO2_CTRL	0x29
+#define AXP809_ALDO3_CTRL	0x2a
+#define AXP809_SHUTDOWN		0x32
+#define AXP809_SHUTDOWN_POWEROFF	(1 << 7)
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
+#define AXP_VBUS_IPSOUT			0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+#define AXP_MISC_CTRL			0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET		0

u-boot/include/axp818.h

@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * X-Powers AXP818 Power Management IC driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define AXP818_CHIP_ID		0x03
+
+#define AXP818_OUTPUT_CTRL1	0x10
+#define AXP818_OUTPUT_CTRL1_DCDC1_EN	(1 << 0)
+#define AXP818_OUTPUT_CTRL1_DCDC2_EN	(1 << 1)
+#define AXP818_OUTPUT_CTRL1_DCDC3_EN	(1 << 2)
+#define AXP818_OUTPUT_CTRL1_DCDC4_EN	(1 << 3)
+#define AXP818_OUTPUT_CTRL1_DCDC5_EN	(1 << 4)
+#define AXP818_OUTPUT_CTRL1_DCDC6_EN	(1 << 5)
+#define AXP818_OUTPUT_CTRL1_DCDC7_EN	(1 << 6)
+#define AXP818_OUTPUT_CTRL2	0x12
+#define AXP818_OUTPUT_CTRL2_ELDO1_EN	(1 << 0)
+#define AXP818_OUTPUT_CTRL2_ELDO2_EN	(1 << 1)
+#define AXP818_OUTPUT_CTRL2_ELDO3_EN	(1 << 2)
+#define AXP818_OUTPUT_CTRL2_DLDO1_EN	(1 << 3)
+#define AXP818_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
+#define AXP818_OUTPUT_CTRL2_DLDO3_EN	(1 << 5)
+#define AXP818_OUTPUT_CTRL2_DLDO4_EN	(1 << 6)
+#define AXP818_OUTPUT_CTRL2_SW_EN	(1 << 7)
+#define AXP818_OUTPUT_CTRL3	0x13
+#define AXP818_OUTPUT_CTRL3_FLDO1_EN	(1 << 2)
+#define AXP818_OUTPUT_CTRL3_FLDO2_EN	(1 << 3)
+#define AXP818_OUTPUT_CTRL3_FLDO3_EN	(1 << 4)
+#define AXP818_OUTPUT_CTRL3_ALDO1_EN	(1 << 5)
+#define AXP818_OUTPUT_CTRL3_ALDO2_EN	(1 << 6)
+#define AXP818_OUTPUT_CTRL3_ALDO3_EN	(1 << 7)
+
+#define AXP818_DLDO1_CTRL	0x15
+#define AXP818_DLDO2_CTRL	0x16
+#define AXP818_DLDO3_CTRL	0x17
+#define AXP818_DLDO4_CTRL	0x18
+#define AXP818_ELDO1_CTRL	0x19
+#define AXP818_ELDO2_CTRL	0x1a
+#define AXP818_ELDO3_CTRL	0x1b
+#define AXP818_FLDO1_CTRL	0x1c
+#define AXP818_FLDO2_3_CTRL	0x1d
+#define AXP818_FLDO2_3_CTRL_FLDO3_VOL	(1 << 4)
+#define AXP818_DCDC1_CTRL	0x20
+#define AXP818_DCDC2_CTRL	0x21
+#define AXP818_DCDC3_CTRL	0x22
+#define AXP818_DCDC4_CTRL	0x23
+#define AXP818_DCDC5_CTRL	0x24
+#define AXP818_DCDC6_CTRL	0x25
+#define AXP818_DCDC7_CTRL	0x26
+
+#define AXP818_ALDO1_CTRL	0x28
+#define AXP818_ALDO2_CTRL	0x29
+#define AXP818_ALDO3_CTRL	0x2a
+
+#define AXP818_SHUTDOWN		0x32
+#define AXP818_SHUTDOWN_POWEROFF	(1 << 7)
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
+#define AXP_VBUS_IPSOUT			0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+#define AXP_MISC_CTRL			0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET		0

u-boot/include/axp_pmic.h

@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * X-Powers AX Power Management IC support header
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _AXP_PMIC_H_
+
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#endif
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
+#ifdef CONFIG_AXP221_POWER
+#include <axp221.h>
+#endif
+#ifdef CONFIG_AXP809_POWER
+#include <axp809.h>
+#endif
+#ifdef CONFIG_AXP818_POWER
+#include <axp818.h>
+#endif
+
+int axp_set_dcdc1(unsigned int mvolt);
+int axp_set_dcdc2(unsigned int mvolt);
+int axp_set_dcdc3(unsigned int mvolt);
+int axp_set_dcdc4(unsigned int mvolt);
+int axp_set_dcdc5(unsigned int mvolt);
+int axp_set_aldo1(unsigned int mvolt);
+int axp_set_aldo2(unsigned int mvolt);
+int axp_set_aldo3(unsigned int mvolt);
+int axp_set_aldo4(unsigned int mvolt);
+int axp_set_dldo(int dldo_num, unsigned int mvolt);
+int axp_set_eldo(int eldo_num, unsigned int mvolt);
+int axp_set_fldo(int fldo_num, unsigned int mvolt);
+int axp_set_sw(bool on);
+int axp_init(void);
+int axp_get_sid(unsigned int *sid);
+
+#endif

u-boot/include/backlight.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BACKLIGHT_H
+#define _BACKLIGHT_H
+
+struct backlight_ops {
+	/**
+	 * enable() - Enable a backlight
+	 *
+	 * @dev:	Backlight device to enable
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*enable)(struct udevice *dev);
+};
+
+#define backlight_get_ops(dev)	((struct backlight_ops *)(dev)->driver->ops)
+
+/**
+ * backlight_enable() - Enable a backlight
+ *
+ * @dev:	Backlight device to enable
+ * @return 0 if OK, -ve on error
+ */
+int backlight_enable(struct udevice *dev);
+
+#endif

u-boot/include/bcd.h

@@ -0,0 +1,23 @@
+/* Permission is hereby granted to copy, modify and redistribute this code
+ * in terms of the GNU Library General Public License, Version 2 or later,
+ * at your option.
+ */
+
+/* inline functions to translate to/from binary and binary-coded decimal
+ * (frequently found in RTC chips).
+ */
+
+#ifndef _BCD_H
+#define _BCD_H
+
+static inline unsigned int bcd2bin(unsigned int val)
+{
+	return ((val) & 0x0f) + ((val & 0xff) >> 4) * 10;
+}
+
+static inline unsigned int bin2bcd(unsigned int val)
+{
+	return (((val / 10) << 4) | (val % 10));
+}
+
+#endif /* _BCD_H */

u-boot/include/bedbug/bedbug.h

@@ -0,0 +1,40 @@
+/* $Id$ */
+
+#ifndef _BEDBUG_H
+#define _BEDBUG_H
+
+#ifndef NULL
+#define NULL	0
+#endif
+
+#define _USE_PROTOTYPES
+
+#ifndef isblank
+#define isblank(c) isspace((int)(c))
+#endif
+
+#ifndef __P
+#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus))
+#define __P(protos)	protos		/* full-blown ANSI C */
+#else
+#define __P(protos)	()		/* traditional C preprocessor */
+#endif
+#endif
+
+#endif /* _BEDBUG_H */
+
+
+/*
+ * Copyright (c) 2001 William L. Pitts
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */

u-boot/include/bedbug/ppc.h

@@ -0,0 +1,408 @@
+/* $Id$ */
+
+#ifndef _PPC_H
+#define _PPC_H
+
+/*======================================================================
+ *
+ *  OPERANDS
+ *
+ *======================================================================*/
+
+enum OP_FIELD {
+  O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD,
+  O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD,
+  O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr,
+  O_cr2 };
+
+struct operand {
+  enum OP_FIELD	field;		/* The operand identifier from the
+				   enum above */
+
+  char *	name;		/* Symbolic name of this operand */
+
+  unsigned int	bits;		/* The number of bits used by this
+				   operand */
+
+  unsigned int	shift;		/* How far to the right the operand
+				   should be shifted so that it is
+				   aligned at the beginning of the
+				   word */
+
+  unsigned int	hint;		/* A bitwise-inclusive-OR of the
+				   values shown below.  These are used
+				   tell the disassembler how to print
+				   this operand */
+};
+
+/* Values for operand hint */
+#define OH_SILENT	0x01	/* dont print this operand */
+#define OH_ADDR		0x02	/* this operand is an address */
+#define OH_REG		0x04	/* this operand is a register */
+#define OH_SPR		0x08	/* this operand is an SPR */
+#define OH_TBR		0x10	/* this operand is a TBR */
+#define OH_OFFSET	0x20	/* this operand is an offset */
+#define OH_LITERAL      0x40    /* a literal string */
+
+
+/*======================================================================
+ *
+ *  OPCODES
+ *
+ *======================================================================*/
+
+/* From the MPCxxx instruction set documentation, all instructions are
+ * 32 bits long and word aligned.  Bits 0-5 always specify the primary
+ * opcode.  Many instructions also have an extended opcode.
+ */
+
+#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f)
+#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26)
+
+/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the
+ * instruction forms
+ */
+
+
+/*-------------------------------------------------
+ *              I-Form Instructions:
+ * bX
+ *-------------------------------------------------
+ * OPCD |           LI                       |AA|LK
+ *-------------------------------------------------*/
+
+#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
+#define I_MASK I_OPCODE(0x3f,0x1,0x1)
+
+
+/*-------------------------------------------------
+ *              B-Form Instructions:
+ * bcX
+ *-------------------------------------------------
+ * OPCD |    BO   |  BI  |   BD              |AA|LK
+ *-------------------------------------------------*/
+
+#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
+#define B_MASK B_OPCODE(0x3f,0x1,0x1)
+
+
+/*-------------------------------------------------
+ *             SC-Form Instructions:
+ * sc
+ *-------------------------------------------------
+ * OPCD | 00000 | 00000 | 00000000000000       |1|0
+ *-------------------------------------------------*/
+
+#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2)
+#define SC_MASK SC_OPCODE(0x3f)
+
+
+/*-------------------------------------------------
+ *             D-Form Instructions:
+ * addi addic addic. addis andi. andis. cmpi cmpli
+ * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli
+ * ori oris stb stbu sth sthu stmw stw stwu subfic
+ * twi xori xoris
+ *-------------------------------------------------
+ * OPCD |   D    |   A   |            d
+ * OPCD |   D    |   A   |           SIMM
+ * OPCD |   S    |   A   |            d
+ * OPCD |   S    |   A   |           UIMM
+ * OPCD |crfD|0|L|   A   |           SIMM
+ * OPCD |crfD|0|L|   A   |           UIMM
+ * OPCD |   TO   |   A   |           SIMM
+ *-------------------------------------------------*/
+
+#define D_OPCODE(i) MAKE_OPCODE(i)
+#define D_MASK MAKE_OPCODE(0x3f)
+
+
+/*-------------------------------------------------
+ *            DS-Form Instructions:
+ * (none supported by MPC860)
+ *-------------------------------------------------
+ * OPCD |   D    |   A   |          ds          |XO
+ * OPCD |   S    |   A   |          ds          |XO
+ *-------------------------------------------------*/
+
+#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3))
+#define DS_MASK DS_OPCODE(0x3f,0x1)
+
+
+/*---------------------------------------------------
+ *            X-Form Instructions:
+ * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt
+ * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX
+ * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi
+ * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr
+ * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX
+ * orX orcX slwX srawX srawiX srwX stbux stbx
+ * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux
+ * stwx sync tlbie tlbld tlbli tlbsync tw xorX
+ *---------------------------------------------------
+ * OPCD |   D    |    A   |    B   |      XO      |0
+ * OPCD |   D    |    A   |   NB   |      XO      |0
+ * OPCD |   D    |  00000 |    B   |      XO      |0
+ * OPCD |   D    |  00000 |  00000 |      XO      |0
+ * OPCD |   D    |0|  SR  |  00000 |      XO      |0
+ * OPCD |   S    |    A   |    B   |      XO      |Rc
+ * OPCD |   S    |    A   |    B   |      XO      |1
+ * OPCD |   S    |    A   |    B   |      XO      |0
+ * OPCD |   S    |    A   |   NB   |      XO      |0
+ * OPCD |   S    |    A   |  00000 |      XO      |Rc
+ * OPCD |   S    |  00000 |    B   |      XO      |0
+ * OPCD |   S    |  00000 |  00000 |      XO      |0
+ * OPCD |   S    |0|  SR  |  00000 |      XO      |0
+ * OPCD |   S    |    A   |   SH   |      XO      |Rc
+ * OPCD |crfD|0|L|    A   |   SH   |      XO      |0
+ * OPCD |crfD |00|    A   |    B   |      XO      |0
+ * OPCD |crfD |00|crfS |00|  00000 |      XO      |0
+ * OPCD |crfD |00|  00000 |  00000 |      XO      |0
+ * OPCD |crfD |00|  00000 | IMM  |0|      XO      |Rc
+ * OPCD |   TO   |    A   |    B   |      XO      |0
+ * OPCD |   D    |  00000 |    B   |      XO      |Rc
+ * OPCD |   D    |  00000 |  00000 |      XO      |Rc
+ * OPCD |  crbD  |  00000 |  00000 |      XO      |Rc
+ * OPCD |  00000 |    A   |    B   |      XO      |0
+ * OPCD |  00000 |  00000 |    B   |      XO      |0
+ * OPCD |  00000 |  00000 |  00000 |      XO      |0
+ *---------------------------------------------------*/
+
+#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			   ((rc) & 0x1))
+#define X_MASK X_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XL-Form Instructions:
+ * bcctrX bclrX crand crandc creqv crnand crnor cror
+ * croc crxorisync mcrf rfi
+ *---------------------------------------------------
+ * OPCD |   BO   |  BI    |  00000 |      XO      |LK
+ * OPCD |  crbD  | crbA   |  crbB  |      XO      |0
+ * OPCD |crfD |00|crfS |00|  00000 |      XO      |0
+ * OPCD |  00000 |  00000 |  00000 |      XO      |0
+ *---------------------------------------------------*/
+
+#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			    ((lk) & 0x1))
+#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XFX-Form Instructions:
+ * mfspr mftb mtcrf mtspr
+ *---------------------------------------------------
+ * OPCD |   D    |      spr        |      XO       |0
+ * OPCD |   D    |0|    CRM      |0|      XO       |0
+ * OPCD |   S    |      spr        |      XO       |0
+ * OPCD |   D    |      tbr        |      XO       |0
+ *---------------------------------------------------*/
+
+#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			     ((rc) & 0x1))
+#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XFL-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |0|      FM     |0|   B    |      XO       |0
+ *---------------------------------------------------*/
+
+#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			     ((rc) & 0x1))
+#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XS-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |   sh   |      XO   |sh|LK
+ *---------------------------------------------------*/
+
+#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \
+			     ((rc) & 0x1))
+#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XO-Form Instructions:
+ * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX
+ * mulhwuX mullwX negX subfX subfcX subfeX subfmeX
+ * subfzeX
+ *---------------------------------------------------
+ * OPCD |    D   |   A    |    B   |OE|     XO    |Rc
+ * OPCD |    D   |   A    |    B   |0 |     XO    |Rc
+ * OPCD |    D   |   A    |  00000 |OE|     XO    |Rc
+ *---------------------------------------------------*/
+
+#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \
+			       (((xo) & 0x1ff) << 1) | ((rc) & 0x1))
+#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1)
+
+
+/*---------------------------------------------------
+ *            A-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    D   |   A    |    B   |00000|  XO    |Rc
+ * OPCD |    D   |   A    |    B   |  C  |  XO    |Rc
+ * OPCD |    D   |   A    |  00000 |  C  |  XO    |Rc
+ * OPCD |    D   |  00000 |    B   |00000|  XO    |Rc
+ *---------------------------------------------------*/
+
+#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \
+			   ((rc) & 0x1))
+#define A_MASK A_OPCODE(0x3f,0x1f,0x1)
+
+
+/*---------------------------------------------------
+ *            M-Form Instructions:
+ * rlwimiX rlwinmX rlwnmX
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    SH   |  MB |  ME   |Rc
+ * OPCD |    S   |   A    |     B   |  MB |  ME   |Rc
+ *---------------------------------------------------*/
+
+#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1))
+#define M_MASK M_OPCODE(0x3f,0x1)
+
+
+/*---------------------------------------------------
+ *            MD-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    sh   |  mb | XO |sh|Rc
+ * OPCD |    S   |   A    |    sh   |  me | XO |sh|Rc
+ *---------------------------------------------------*/
+
+#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \
+			   ((rc) & 0x1))
+#define MD_MASK MD_OPCODE(0x3f,0x7,0x1)
+
+
+/*---------------------------------------------------
+ *            MDS-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    B    |  mb | XO    |Rc
+ * OPCD |    S   |   A    |    B    |  me | XO    |Rc
+ *---------------------------------------------------*/
+
+#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \
+			   ((rc) & 0x1))
+#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1)
+
+#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr))
+
+#define MAX_OPERANDS  8
+
+struct ppc_ctx;
+
+struct opcode {
+  unsigned long	opcode;		/* The complete opcode as produced by
+				   one of the XXX_OPCODE macros above */
+
+  unsigned long	mask;		/* The mask to use on an instruction
+				   before comparing with the opcode
+				   field to see if it matches */
+
+  enum OP_FIELD	fields[MAX_OPERANDS];
+				/* An array defining the operands for
+				   this opcode.  The values of the
+				   array are the operand identifiers */
+
+  int (*hfunc)(struct ppc_ctx *);
+				/* Address of a function to handle the given
+				   mnemonic */
+
+  char *	name;		/* The symbolic name of this opcode */
+
+  unsigned int	hint;		/* A bitwise-inclusive-OR of the
+				   values shown below.  These are used
+				   tell the disassembler how to print
+				   some operands for this opcode */
+};
+
+/* values for opcode hints */
+#define H_RELATIVE	0x1	/* The address operand is relative */
+#define H_IMM_HIGH	0x2	/* [U|S]IMM field shifted high */
+#define H_RA0_IS_0	0x4	/* If rA = 0 then treat as literal 0 */
+
+struct ppc_ctx {
+  struct opcode *	op;
+  unsigned long		instr;
+  unsigned int		flags;
+  int			datalen;
+  char			data[ 256 ];
+  char			radix_fmt[ 8 ];
+  unsigned char *	virtual;
+};
+
+
+/*======================================================================
+ *
+ *  FUNCTIONS
+ *
+ *======================================================================*/
+
+/* Values for flags as passed to various ppc routines */
+#define F_RADOCTAL	0x1	/* output radix = unsigned octal */
+#define F_RADUDECIMAL	0x2	/* output radix = unsigned decimal */
+#define F_RADSDECIMAL	0x4	/* output radix = signed decimal */
+#define F_RADHEX	0x8	/* output radix = unsigned hex */
+#define F_SIMPLE	0x10	/* use simplified mnemonics */
+#define F_SYMBOL	0x20	/* use symbol lookups for addresses */
+#define F_INSTR		0x40	/* output the raw instruction */
+#define F_LOCALMEM	0x80	/* retrieve opcodes from local memory
+				   rather than from the HMI */
+#define F_LINENO	0x100	/* show line number info if available */
+#define F_VALIDONLY	0x200	/* cache: valid entries only */
+
+/* Values for assembler error codes */
+#define E_ASM_BAD_OPCODE	1
+#define E_ASM_NUM_OPERANDS	2
+#define E_ASM_BAD_REGISTER	3
+#define E_ASM_BAD_SPR		4
+#define E_ASM_BAD_TBR		5
+
+extern int disppc __P((unsigned char *,unsigned char *,int,
+		       int (*)(const char *), unsigned long));
+extern int print_source_line __P((char *,char *,int,
+				  int (*pfunc)(const char *)));
+extern int find_next_address __P((unsigned char *,int,struct pt_regs *));
+extern int handle_bc __P((struct ppc_ctx *));
+extern unsigned long asmppc __P((unsigned long,char*,int*));
+extern char *asm_error_str __P((int));
+
+/*======================================================================
+ *
+ *  GLOBAL VARIABLES
+ *
+ *======================================================================*/
+
+extern struct operand operands[];
+extern const unsigned int n_operands;
+extern struct opcode opcodes[];
+extern const unsigned int n_opcodes;
+
+#endif /* _PPC_H */
+
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */

u-boot/include/bedbug/regs.h

@@ -0,0 +1,402 @@
+/* $Id$ */
+
+#ifndef _REGS_H
+#define _REGS_H
+
+/* Special Purpose Registers */
+
+#define SPR_CR		-1
+#define SPR_MSR		-2
+
+#define SPR_XER		1
+#define SPR_LR		8
+#define SPR_CTR		9
+#define SPR_DSISR	18
+#define SPR_DAR		19
+#define SPR_DEC		22
+#define SPR_SRR0	26
+#define SPR_SRR1	27
+#define SPR_EIE		80
+#define SPR_EID		81
+#define SPR_CMPA	144
+#define SPR_CMPB	145
+#define SPR_CMPC	146
+#define SPR_CMPD	147
+#define SPR_ICR		148
+#define SPR_DER		149
+#define SPR_COUNTA	150
+#define SPR_COUNTB	151
+#define SPR_CMPE	152
+#define SPR_CMPF	153
+#define SPR_CMPG	154
+#define SPR_CMPH	155
+#define SPR_LCTRL1	156
+#define SPR_LCTRL2	157
+#define SPR_ICTRL	158
+#define SPR_BAR		159
+#define SPR_USPRG0      256
+#define SPR_SPRG4_RO    260
+#define SPR_SPRG5_RO    261
+#define SPR_SPRG6_RO    262
+#define SPR_SPRG7_RO    263
+#define SPR_SPRG0	272
+#define SPR_SPRG1	273
+#define SPR_SPRG2	274
+#define SPR_SPRG3	275
+#define SPR_SPRG4       276
+#define SPR_SPRG5       277
+#define SPR_SPRG6       278
+#define SPR_SPRG7       279
+#define SPR_EAR         282	/* MPC603e core */
+#define SPR_TBL         284
+#define SPR_TBU         285
+#define SPR_PVR		287
+#define SPR_IC_CST	560
+#define SPR_IC_ADR	561
+#define SPR_IC_DAT	562
+#define SPR_DC_CST	568
+#define SPR_DC_ADR	569
+#define SPR_DC_DAT	570
+#define SPR_DPDR	630
+#define SPR_IMMR	638
+#define SPR_MI_CTR	784
+#define SPR_MI_AP	786
+#define SPR_MI_EPN	787
+#define SPR_MI_TWC	789
+#define SPR_MI_RPN	790
+#define SPR_MD_CTR	792
+#define SPR_M_CASID	793
+#define SPR_MD_AP	794
+#define SPR_MD_EPN	795
+#define SPR_M_TWB	796
+#define SPR_MD_TWC	797
+#define SPR_MD_RPN	798
+#define SPR_M_TW	799
+#define SPR_MI_DBCAM	816
+#define SPR_MI_DBRAM0	817
+#define SPR_MI_DBRAM1	818
+#define SPR_MD_DBCAM	824
+#define SPR_MD_DBRAM0	825
+#define SPR_MD_DBRAM1	826
+#define SPR_ZPR         944
+#define SPR_PID         945
+#define SPR_CCR0        947
+#define SPR_IAC3        948
+#define SPR_IAC4        949
+#define SPR_DVC1        950
+#define SPR_DVC2        951
+#define SPR_SGR         953
+#define SPR_DCWR        954
+#define SPR_SLER        955
+#define SPR_SU0R        956
+#define SPR_DBCR1       957
+#define SPR_ICDBDR      979
+#define SPR_ESR         980
+#define SPR_DEAR        981
+#define SPR_EVPR        982
+#define SPR_TSR         984
+#define SPR_TCR         986
+#define SPR_PIT         987
+#define SPR_SRR2        990
+#define SPR_SRR3        991
+#define SPR_DBSR        1008
+#define SPR_DBCR0       1010
+#define SPR_IABR        1010	/* MPC603e core */
+#define SPR_IAC1        1012
+#define SPR_IAC2        1013
+#define SPR_DAC1        1014
+#define SPR_DAC2        1015
+#define SPR_DCCR        1018
+#define SPR_ICCR        1019
+
+/* Bits for the DBCR0 register */
+#define DBCR0_EDM	0x80000000
+#define DBCR0_IDM	0x40000000
+#define DBCR0_RST	0x30000000
+#define DBCR0_IC	0x08000000
+#define DBCR0_BT	0x04000000
+#define DBCR0_EDE	0x02000000
+#define DBCR0_TDE	0x01000000
+#define DBCR0_IA1	0x00800000
+#define DBCR0_IA2	0x00400000
+#define DBCR0_IA12	0x00200000
+#define DBCR0_IA12X	0x00100000
+#define DBCR0_IA3	0x00080000
+#define DBCR0_IA4	0x00040000
+#define DBCR0_IA34	0x00020000
+#define DBCR0_IA34X	0x00010000
+#define DBCR0_IA12T	0x00008000
+#define DBCR0_IA34T	0x00004000
+#define DBCR0_FT	0x00000001
+
+/* Bits for the DBCR1 register */
+#define DBCR1_D1R	0x80000000
+#define DBCR1_D2R	0x40000000
+#define DBCR1_D1W	0x20000000
+#define DBCR1_D2W	0x10000000
+#define DBCR1_D1S	0x0C000000
+#define DBCR1_D2S	0x03000000
+#define DBCR1_DA12	0x00800000
+#define DBCR1_DA12X	0x00400000
+#define DBCR1_DV1M	0x000C0000
+#define DBCR1_DV2M	0x00030000
+#define DBCR1_DV1BE	0x0000F000
+#define DBCR1_DV2BE	0x00000F00
+
+/*
+ * DBSR bits which have conflicting definitions on true Book E versus PPC40x
+ */
+#ifdef CONFIG_BOOKE
+#define DBSR_IA1	0x00800000	/* Instr Address Compare 1 Event */
+#define DBSR_IA2	0x00400000	/* Instr Address Compare 2 Event */
+#define DBSR_IA3	0x00200000	/* Instr Address Compare 3 Event */
+#define DBSR_IA4	0x00100000	/* Instr Address Compare 4 Event */
+#endif
+#ifndef CONFIG_440
+#define DBSR_IA1	0x04000000	/* Instr Address Compare 1 Event */
+#define DBSR_IA2	0x02000000	/* Instr Address Compare 2 Event */
+#define DBSR_IA3	0x00080000	/* Instr Address Compare 3 Event */
+#define DBSR_IA4	0x00040000	/* Instr Address Compare 4 Event */
+#endif
+
+struct spr_info {
+  int  spr_val;
+  char spr_name[ 10 ];
+};
+
+extern struct spr_info spr_map[];
+extern const unsigned int n_sprs;
+
+
+#define SET_REGISTER( str, val ) \
+({ unsigned long __value = (val); \
+  asm volatile( str : : "r" (__value)); \
+  __value; })
+
+#define	GET_REGISTER( str ) \
+({ unsigned long __value; \
+  asm volatile( str : "=r" (__value) : ); \
+  __value; })
+
+#define	 GET_CR()	     GET_REGISTER( "mfcr %0" )
+#define	 SET_CR(val)	     SET_REGISTER( "mtcr %0", val )
+#define	 GET_MSR()	     GET_REGISTER( "mfmsr %0" )
+#define	 SET_MSR(val)	     SET_REGISTER( "mtmsr %0", val )
+#define	 GET_XER()	     GET_REGISTER( "mfspr %0,1" )
+#define	 SET_XER(val)	     SET_REGISTER( "mtspr 1,%0", val )
+#define	 GET_LR()	     GET_REGISTER( "mfspr %0,8" )
+#define	 SET_LR(val)	     SET_REGISTER( "mtspr 8,%0", val )
+#define	 GET_CTR()	     GET_REGISTER( "mfspr %0,9" )
+#define	 SET_CTR(val)	     SET_REGISTER( "mtspr 9,%0", val )
+#define	 GET_DSISR()	     GET_REGISTER( "mfspr %0,18" )
+#define	 SET_DSISR(val)	     SET_REGISTER( "mtspr 18,%0", val )
+#define	 GET_DAR()	     GET_REGISTER( "mfspr %0,19" )
+#define	 SET_DAR(val)	     SET_REGISTER( "mtspr 19,%0", val )
+#define	 GET_DEC()	     GET_REGISTER( "mfspr %0,22" )
+#define	 SET_DEC(val)	     SET_REGISTER( "mtspr 22,%0", val )
+#define	 GET_SRR0()	     GET_REGISTER( "mfspr %0,26" )
+#define	 SET_SRR0(val)       SET_REGISTER( "mtspr 26,%0", val )
+#define	 GET_SRR1()	     GET_REGISTER( "mfspr %0,27" )
+#define	 SET_SRR1(val)	     SET_REGISTER( "mtspr 27,%0", val )
+#define	 GET_EIE()	     GET_REGISTER( "mfspr %0,80" )
+#define	 SET_EIE(val)	     SET_REGISTER( "mtspr 80,%0", val )
+#define	 GET_EID()	     GET_REGISTER( "mfspr %0,81" )
+#define	 SET_EID(val)	     SET_REGISTER( "mtspr 81,%0", val )
+#define	 GET_CMPA()	     GET_REGISTER( "mfspr %0,144" )
+#define	 SET_CMPA(val)	     SET_REGISTER( "mtspr 144,%0", val )
+#define	 GET_CMPB()	     GET_REGISTER( "mfspr %0,145" )
+#define	 SET_CMPB(val)	     SET_REGISTER( "mtspr 145,%0", val )
+#define	 GET_CMPC()	     GET_REGISTER( "mfspr %0,146" )
+#define	 SET_CMPC(val)	     SET_REGISTER( "mtspr 146,%0", val )
+#define	 GET_CMPD()	     GET_REGISTER( "mfspr %0,147" )
+#define	 SET_CMPD(val)	     SET_REGISTER( "mtspr 147,%0", val )
+#define	 GET_ICR()	     GET_REGISTER( "mfspr %0,148" )
+#define	 SET_ICR(val)	     SET_REGISTER( "mtspr 148,%0", val )
+#define	 GET_DER()	     GET_REGISTER( "mfspr %0,149" )
+#define	 SET_DER(val)	     SET_REGISTER( "mtspr 149,%0", val )
+#define	 GET_COUNTA()	     GET_REGISTER( "mfspr %0,150" )
+#define	 SET_COUNTA(val)     SET_REGISTER( "mtspr 150,%0", val )
+#define	 GET_COUNTB()	     GET_REGISTER( "mfspr %0,151" )
+#define	 SET_COUNTB(val)     SET_REGISTER( "mtspr 151,%0", val )
+#define	 GET_CMPE()	     GET_REGISTER( "mfspr %0,152" )
+#define	 SET_CMPE(val)	     SET_REGISTER( "mtspr 152,%0", val )
+#define	 GET_CMPF()	     GET_REGISTER( "mfspr %0,153" )
+#define	 SET_CMPF(val)	     SET_REGISTER( "mtspr 153,%0", val )
+#define	 GET_CMPG()	     GET_REGISTER( "mfspr %0,154" )
+#define	 SET_CMPG(val)	     SET_REGISTER( "mtspr 154,%0", val )
+#define	 GET_CMPH()	     GET_REGISTER( "mfspr %0,155" )
+#define	 SET_CMPH(val)	     SET_REGISTER( "mtspr 155,%0", val )
+#define  GET_LCTRL1()	     GET_REGISTER( "mfspr %0,156" )
+#define	 SET_LCTRL1(val)     SET_REGISTER( "mtspr 156,%0", val )
+#define  GET_LCTRL2()	     GET_REGISTER( "mfspr %0,157" )
+#define	 SET_LCTRL2(val)     SET_REGISTER( "mtspr 157,%0", val )
+#define  GET_ICTRL()	     GET_REGISTER( "mfspr %0,158" )
+#define	 SET_ICTRL(val)	     SET_REGISTER( "mtspr 158,%0", val )
+#define  GET_BAR()	     GET_REGISTER( "mfspr %0,159" )
+#define	 SET_BAR(val)	     SET_REGISTER( "mtspr 159,%0", val )
+#define  GET_USPRG0()	     GET_REGISTER( "mfspr %0,256" )
+#define	 SET_USPRG0(val)     SET_REGISTER( "mtspr 256,%0", val )
+#define  GET_SPRG4_RO()	     GET_REGISTER( "mfspr %0,260" )
+#define	 SET_SPRG4_RO(val)   SET_REGISTER( "mtspr 260,%0", val )
+#define  GET_SPRG5_RO()	     GET_REGISTER( "mfspr %0,261" )
+#define	 SET_SPRG5_RO(val)   SET_REGISTER( "mtspr 261,%0", val )
+#define  GET_SPRG6_RO()	     GET_REGISTER( "mfspr %0,262" )
+#define	 SET_SPRG6_RO(val)   SET_REGISTER( "mtspr 262,%0", val )
+#define  GET_SPRG7_RO()	     GET_REGISTER( "mfspr %0,263" )
+#define	 SET_SPRG7_RO(val)   SET_REGISTER( "mtspr 263,%0", val )
+#define  GET_SPRG0()	     GET_REGISTER( "mfspr %0,272" )
+#define	 SET_SPRG0(val)	     SET_REGISTER( "mtspr 272,%0", val )
+#define  GET_SPRG1()	     GET_REGISTER( "mfspr %0,273" )
+#define	 SET_SPRG1(val)	     SET_REGISTER( "mtspr 273,%0", val )
+#define  GET_SPRG2()	     GET_REGISTER( "mfspr %0,274" )
+#define	 SET_SPRG2(val)	     SET_REGISTER( "mtspr 274,%0", val )
+#define  GET_SPRG3()	     GET_REGISTER( "mfspr %0,275" )
+#define	 SET_SPRG3(val)	     SET_REGISTER( "mtspr 275,%0", val )
+#define  GET_SPRG4()	     GET_REGISTER( "mfspr %0,276" )
+#define	 SET_SPRG4(val)      SET_REGISTER( "mtspr 276,%0", val )
+#define  GET_SPRG5()	     GET_REGISTER( "mfspr %0,277" )
+#define	 SET_SPRG5(val)	     SET_REGISTER( "mtspr 277,%0", val )
+#define  GET_SPRG6()	     GET_REGISTER( "mfspr %0,278" )
+#define	 SET_SPRG6(val)	     SET_REGISTER( "mtspr 278,%0", val )
+#define  GET_SPRG7()	     GET_REGISTER( "mfspr %0,279" )
+#define	 SET_SPRG7(val)	     SET_REGISTER( "mtspr 279,%0", val )
+#define  GET_EAR()	     GET_REGISTER( "mfspr %0,282" )
+#define	 SET_EAR(val)	     SET_REGISTER( "mtspr 282,%0", val )
+#define  GET_TBL()	     GET_REGISTER( "mfspr %0,284" )
+#define	 SET_TBL(val)	     SET_REGISTER( "mtspr 284,%0", val )
+#define  GET_TBU()	     GET_REGISTER( "mfspr %0,285" )
+#define	 SET_TBU(val)	     SET_REGISTER( "mtspr 285,%0", val )
+#define  GET_PVR()	     GET_REGISTER( "mfspr %0,287" )
+#define	 SET_PVR(val)	     SET_REGISTER( "mtspr 287,%0", val )
+#define  GET_IC_CST()	     GET_REGISTER( "mfspr %0,560" )
+#define	 SET_IC_CST(val)     SET_REGISTER( "mtspr 560,%0", val )
+#define  GET_IC_ADR()	     GET_REGISTER( "mfspr %0,561" )
+#define	 SET_IC_ADR(val)     SET_REGISTER( "mtspr 561,%0", val )
+#define  GET_IC_DAT()	     GET_REGISTER( "mfspr %0,562" )
+#define	 SET_IC_DAT(val)     SET_REGISTER( "mtspr 562,%0", val )
+#define  GET_DC_CST()	     GET_REGISTER( "mfspr %0,568" )
+#define	 SET_DC_CST(val)     SET_REGISTER( "mtspr 568,%0", val )
+#define  GET_DC_ADR()	     GET_REGISTER( "mfspr %0,569" )
+#define	 SET_DC_ADR(val)     SET_REGISTER( "mtspr 569,%0", val )
+#define  GET_DC_DAT()	     GET_REGISTER( "mfspr %0,570" )
+#define	 SET_DC_DAT(val)     SET_REGISTER( "mtspr 570,%0", val )
+#define  GET_DPDR()	     GET_REGISTER( "mfspr %0,630" )
+#define	 SET_DPDR(val)	     SET_REGISTER( "mtspr 630,%0", val )
+#define  GET_IMMR()	     GET_REGISTER( "mfspr %0,638" )
+#define	 SET_IMMR(val)	     SET_REGISTER( "mtspr 638,%0", val )
+#define  GET_MI_CTR()	     GET_REGISTER( "mfspr %0,784" )
+#define	 SET_MI_CTR(val)     SET_REGISTER( "mtspr 784,%0", val )
+#define  GET_MI_AP()	     GET_REGISTER( "mfspr %0,786" )
+#define	 SET_MI_AP(val)	     SET_REGISTER( "mtspr 786,%0", val )
+#define  GET_MI_EPN()	     GET_REGISTER( "mfspr %0,787" )
+#define	 SET_MI_EPN(val)     SET_REGISTER( "mtspr 787,%0", val )
+#define  GET_MI_TWC()	     GET_REGISTER( "mfspr %0,789" )
+#define	 SET_MI_TWC(val)     SET_REGISTER( "mtspr 789,%0", val )
+#define  GET_MI_RPN()	     GET_REGISTER( "mfspr %0,790" )
+#define	 SET_MI_RPN(val)     SET_REGISTER( "mtspr 790,%0", val )
+#define  GET_MD_CTR()	     GET_REGISTER( "mfspr %0,792" )
+#define	 SET_MD_CTR(val)     SET_REGISTER( "mtspr 792,%0", val )
+#define  GET_M_CASID()	     GET_REGISTER( "mfspr %0,793" )
+#define	 SET_M_CASID(val)    SET_REGISTER( "mtspr 793,%0", val )
+#define  GET_MD_AP()	     GET_REGISTER( "mfspr %0,794" )
+#define	 SET_MD_AP(val)	     SET_REGISTER( "mtspr ,794%0", val )
+#define  GET_MD_EPN()	     GET_REGISTER( "mfspr %0,795" )
+#define	 SET_MD_EPN(val)     SET_REGISTER( "mtspr 795,%0", val )
+#define  GET_M_TWB()	     GET_REGISTER( "mfspr %0,796" )
+#define	 SET_M_TWB(val)	     SET_REGISTER( "mtspr 796,%0", val )
+#define  GET_MD_TWC()	     GET_REGISTER( "mfspr %0,797" )
+#define	 SET_MD_TWC(val)     SET_REGISTER( "mtspr 797,%0", val )
+#define  GET_MD_RPN()	     GET_REGISTER( "mfspr %0,798" )
+#define	 SET_MD_RPN(val)     SET_REGISTER( "mtspr 798,%0", val )
+#define  GET_M_TW()	     GET_REGISTER( "mfspr %0,799" )
+#define	 SET_M_TW(val)	     SET_REGISTER( "mtspr 799,%0", val )
+#define  GET_MI_DBCAM()      GET_REGISTER( "mfspr %0,816" )
+#define	 SET_MI_DBCAM(val)   SET_REGISTER( "mtspr 816,%0", val )
+#define  GET_MI_DBRAM0()     GET_REGISTER( "mfspr %0,817" )
+#define	 SET_MI_DBRAM0(val)  SET_REGISTER( "mtspr 817,%0", val )
+#define  GET_MI_DBRAM1()     GET_REGISTER( "mfspr %0,818" )
+#define	 SET_MI_DBRAM1(val)  SET_REGISTER( "mtspr 818,%0", val )
+#define  GET_MD_DBCAM()      GET_REGISTER( "mfspr %0,824" )
+#define	 SET_MD_DBCA(val)    SET_REGISTER( "mtspr 824,%0", val )
+#define  GET_MD_DBRAM0()     GET_REGISTER( "mfspr %0,825" )
+#define	 SET_MD_DBRAM0(val)  SET_REGISTER( "mtspr 825,%0", val )
+#define  GET_MD_DBRAM1()     GET_REGISTER( "mfspr %0,826" )
+#define	 SET_MD_DBRAM1(val)  SET_REGISTER( "mtspr 826,%0", val )
+#define  GET_ZPR()           GET_REGISTER( "mfspr %0,944" )
+#define	 SET_ZPR(val)        SET_REGISTER( "mtspr 944,%0", val )
+#define  GET_PID()	     GET_REGISTER( "mfspr %0,945" )
+#define	 SET_PID(val)	     SET_REGISTER( "mtspr 945,%0", val )
+#define  GET_CCR0()	     GET_REGISTER( "mfspr %0,947" )
+#define	 SET_CCR0(val)	     SET_REGISTER( "mtspr 947,%0", val )
+#define	 GET_IAC3()	     GET_REGISTER( "mfspr %0,948" )
+#define	 SET_IAC3(val)	     SET_REGISTER( "mtspr 948,%0", val )
+#define	 GET_IAC4()	     GET_REGISTER( "mfspr %0,949" )
+#define	 SET_IAC4(val)	     SET_REGISTER( "mtspr 949,%0", val )
+#define	 GET_DVC1()	     GET_REGISTER( "mfspr %0,950" )
+#define	 SET_DVC1(val)	     SET_REGISTER( "mtspr 950,%0", val )
+#define	 GET_DVC2()	     GET_REGISTER( "mfspr %0,951" )
+#define	 SET_DVC2(val)	     SET_REGISTER( "mtspr 951,%0", val )
+#define	 GET_SGR()	     GET_REGISTER( "mfspr %0,953" )
+#define	 SET_SGR(val)	     SET_REGISTER( "mtspr 953,%0", val )
+#define	 GET_DCWR()	     GET_REGISTER( "mfspr %0,954" )
+#define	 SET_DCWR(val)	     SET_REGISTER( "mtspr 954,%0", val )
+#define	 GET_SLER()	     GET_REGISTER( "mfspr %0,955" )
+#define	 SET_SLER(val)	     SET_REGISTER( "mtspr 955,%0", val )
+#define	 GET_SU0R()	     GET_REGISTER( "mfspr %0,956" )
+#define	 SET_SU0R(val)	     SET_REGISTER( "mtspr 956,%0", val )
+#define	 GET_DBCR1()	     GET_REGISTER( "mfspr %0,957" )
+#define	 SET_DBCR1(val)	     SET_REGISTER( "mtspr 957,%0", val )
+#define	 GET_ICDBDR()	     GET_REGISTER( "mfspr %0,979" )
+#define	 SET_ICDBDR(val)     SET_REGISTER( "mtspr 979,%0", val )
+#define	 GET_ESR()	     GET_REGISTER( "mfspr %0,980" )
+#define	 SET_ESR(val)	     SET_REGISTER( "mtspr 980,%0", val )
+#define	 GET_DEAR()	     GET_REGISTER( "mfspr %0,981" )
+#define	 SET_DEAR(val)	     SET_REGISTER( "mtspr 981,%0", val )
+#define	 GET_EVPR()	     GET_REGISTER( "mfspr %0,982" )
+#define	 SET_EVPR(val)	     SET_REGISTER( "mtspr 982,%0", val )
+#define	 GET_TSR()	     GET_REGISTER( "mfspr %0,984" )
+#define	 SET_TSR(val)	     SET_REGISTER( "mtspr 984,%0", val )
+#define	 GET_TCR()	     GET_REGISTER( "mfspr %0,986" )
+#define	 SET_TCR(val)	     SET_REGISTER( "mtspr 986,%0", val )
+#define	 GET_PIT()	     GET_REGISTER( "mfspr %0,987" )
+#define	 SET_PIT(val)	     SET_REGISTER( "mtspr 987,%0", val )
+#define	 GET_SRR2()	     GET_REGISTER( "mfspr %0,990" )
+#define	 SET_SRR2(val)	     SET_REGISTER( "mtspr 990,%0", val )
+#define	 GET_SRR3()	     GET_REGISTER( "mfspr %0,991" )
+#define	 SET_SRR3(val)	     SET_REGISTER( "mtspr 991,%0", val )
+#define	 GET_DBSR()	     GET_REGISTER( "mfspr %0,1008" )
+#define	 SET_DBSR(val)	     SET_REGISTER( "mtspr 1008,%0", val )
+#define	 GET_DBCR0()	     GET_REGISTER( "mfspr %0,1010" )
+#define	 SET_DBCR0(val)	     SET_REGISTER( "mtspr 1010,%0", val )
+#define	 GET_IABR()	     GET_REGISTER( "mfspr %0,1010" )
+#define	 SET_IABR(val)	     SET_REGISTER( "mtspr 1010,%0", val )
+#define	 GET_IAC1()	     GET_REGISTER( "mfspr %0,1012" )
+#define	 SET_IAC1(val)	     SET_REGISTER( "mtspr 1012,%0", val )
+#define	 GET_IAC2()	     GET_REGISTER( "mfspr %0,1013" )
+#define	 SET_IAC2(val)	     SET_REGISTER( "mtspr 1013,%0", val )
+#define	 GET_DAC1()	     GET_REGISTER( "mfspr %0,1014" )
+#define	 SET_DAC1(val)	     SET_REGISTER( "mtspr 1014,%0", val )
+#define	 GET_DAC2()	     GET_REGISTER( "mfspr %0,1015" )
+#define	 SET_DAC2(val)	     SET_REGISTER( "mtspr 1015,%0", val )
+#define	 GET_DCCR()	     GET_REGISTER( "mfspr %0,1018" )
+#define	 SET_DCCR(val)	     SET_REGISTER( "mtspr 1018,%0", val )
+#define	 GET_ICCR()	     GET_REGISTER( "mfspr %0,1019" )
+#define	 SET_ICCR(val)	     SET_REGISTER( "mtspr 1019,%0", val )
+
+#endif /* _REGS_H */
+
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */

u-boot/include/bedbug/tables.h

@@ -0,0 +1,601 @@
+/* $Id$ */
+
+#ifndef TABLES_H
+#define TABLES_H
+
+/* This is only included by common/bedbug.c, and depends on the following
+ * files to already be included
+ *   common.h
+ *   bedbug/bedbug.h
+ *   bedbug/ppc.h
+ *   bedbug/regs.h
+ */
+
+struct operand operands[] = {
+  /*Field    Name     Bits  Shift  Hint			   Position	*/
+  /*-----    ------   ----- -----  ----			   ------------ */
+  { O_AA,    "O_AA",	1,     1,  OH_SILENT },		/*   30		*/
+  { O_BD,    "O_BD",   14,     2,  OH_ADDR },		/* 16-29	*/
+  { O_BI,    "O_BI",	5,    16,  0 },			/* 11-15	*/
+  { O_BO,    "O_BO",	5,    21,  0 },			/*  6-10	*/
+  { O_crbD,  "O_crbD",	5,    21,  0 },			/*  6-10	*/
+  { O_crbA,  "O_crbA",	5,    16,  0 },			/* 11-15	*/
+  { O_crbB,  "O_crbB",	5,    11,  0 },			/* 16-20	*/
+  { O_CRM,   "O_CRM",	8,    12,  0 },			/* 12-19	*/
+  { O_d,     "O_d",    15,     0,  OH_OFFSET },		/* 16-31	*/
+  { O_frC,   "O_frC",	5,     6,  0 },			/* 21-25	*/
+  { O_frD,   "O_frD",	5,    21,  0 },			/*  6-10	*/
+  { O_frS,   "O_frS",	5,    21,  0 },			/*  6-10	*/
+  { O_IMM,   "O_IMM",	4,    12,  0 },			/* 16-19	*/
+  { O_LI,    "O_LI",   24,     2,  OH_ADDR },		/*  6-29	*/
+  { O_LK,    "O_LK",	1,     0,  OH_SILENT },		/*   31		*/
+  { O_MB,    "O_MB",	5,     6,  0 },			/* 21-25	*/
+  { O_ME,    "O_ME",	5,     1,  0 },			/* 26-30	*/
+  { O_NB,    "O_NB",	5,    11,  0 },			/* 16-20	*/
+  { O_OE,    "O_OE",	1,    10,  OH_SILENT },		/*   21		*/
+  { O_rA,    "O_rA",	5,    16,  OH_REG },		/* 11-15	*/
+  { O_rB,    "O_rB",	5,    11,  OH_REG },		/* 16-20	*/
+  { O_Rc,    "O_Rc",	1,     0,  OH_SILENT },		/*   31		*/
+  { O_rD,    "O_rD",	5,    21,  OH_REG },		/*  6-10	*/
+  { O_rS,    "O_rS",	5,    21,  OH_REG },		/*  6-10	*/
+  { O_SH,    "O_SH",	5,    11,  0 },			/* 16-20	*/
+  { O_SIMM,  "O_SIMM", 16,     0,  0 },			/* 16-31	*/
+  { O_SR,    "O_SR",	4,    16,  0 },			/* 12-15	*/
+  { O_TO,    "O_TO",	5,    21,  0 },			/*  6-10	*/
+  { O_UIMM,  "O_UIMM", 16,     0,  0 },			/* 16-31	*/
+  { O_crfD,  "O_crfD",	3,    23,  0 },			/*  6- 8	*/
+  { O_crfS,  "O_crfS",	3,    18,  0 },			/* 11-13	*/
+  { O_L,     "O_L",	1,    21,  0 },			/*   10		*/
+  { O_spr,   "O_spr",  10,    11,  OH_SPR },		/* 11-20	*/
+  { O_tbr,   "O_tbr",  10,    11,  OH_TBR },		/* 11-20	*/
+  { O_cr2,   "O_cr2",	0,     0,  OH_LITERAL },	/* "cr2"	*/
+};
+
+const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
+
+/* A note about the fields array in the opcodes structure:
+   The operands are listed in the order they appear in the output.
+
+   This table is arranged in numeric order of the opcode.  Note that some
+   opcodes have defined bits in odd places so not all forms of a command
+   will be in the same place.  This is done so that a binary search can be
+   done to find the opcodes.  Note that table D.2 in the MPC860 User's
+   Manual "Instructions Sorted by Opcode" does not account for these
+   bit locations */
+
+struct opcode opcodes[] = {
+  { D_OPCODE(3),	   D_MASK,   {O_TO, O_rA, O_SIMM, 0},
+    0,		     "twi",	     0 },
+  { D_OPCODE(7),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "mulli",	     0 },
+  { D_OPCODE(8),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "subfic",	     0 },
+  { D_OPCODE(10),	   D_MASK,   {O_crfD, O_L, O_rA, O_UIMM, 0},
+    0,		     "cmpli",	     0 },
+  { D_OPCODE(11),	   D_MASK,   {O_crfD, O_L, O_rA, O_SIMM, 0},
+    0,		     "cmpi",	     0 },
+  { D_OPCODE(12),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addic",	     0 },
+  { D_OPCODE(13),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addic.",	     0 },
+  { D_OPCODE(14),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addi",	     H_RA0_IS_0 },
+  { D_OPCODE(15),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addis",	     H_RA0_IS_0|H_IMM_HIGH },
+  { B_OPCODE(16,0,0),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    handle_bc,	     "bc",	     H_RELATIVE },
+  { B_OPCODE(16,0,1),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bcl",	     H_RELATIVE },
+  { B_OPCODE(16,1,0),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bca",	     0 },
+  { B_OPCODE(16,1,1),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bcla",	     0 },
+  { SC_OPCODE(17),	   SC_MASK,  {0},
+    0,		     "sc",	     0 },
+  { I_OPCODE(18,0,0),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "b",	     H_RELATIVE },
+  { I_OPCODE(18,0,1),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "bl",	     H_RELATIVE },
+  { I_OPCODE(18,1,0),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "ba",	     0 },
+  { I_OPCODE(18,1,1),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "bla",	     0 },
+  { XL_OPCODE(19,0,0),	   XL_MASK,  {O_crfD, O_crfS},
+    0,		     "mcrf",	     0 },
+  { XL_OPCODE(19,16,0),    XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bclr",	     0 },
+  { XL_OPCODE(19,16,1),    XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bclrl",	     0 },
+  { XL_OPCODE(19,33,0),    XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crnor",	     0 },
+  { XL_OPCODE(19,50,0),    XL_MASK,  {0},
+    0,		     "rfi",	     0 },
+  { XL_OPCODE(19,129,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crandc",	     0 },
+  { XL_OPCODE(19,150,0),   XL_MASK,  {0},
+    0,		     "isync",	     0 },
+  { XL_OPCODE(19,193,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crxor",	     0 },
+  { XL_OPCODE(19,225,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crnand",	     0 },
+  { XL_OPCODE(19,257,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crand",	     0 },
+  { XL_OPCODE(19,289,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "creqv",	     0 },
+  { XL_OPCODE(19,417,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crorc",	     0 },
+  { XL_OPCODE(19,449,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "cror",	     0 },
+  { XL_OPCODE(19,528,0),   XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bcctr",	     0 },
+  { XL_OPCODE(19,528,1),   XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bcctrl",	     0 },
+  { M_OPCODE(20,0),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwimi",	     0 },
+  { M_OPCODE(20,1),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwimi.",      0 },
+  { M_OPCODE(21,0),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwinm",	     0 },
+  { M_OPCODE(21,1),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwinm.",      0 },
+  { M_OPCODE(23,0),	   M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwnm",	     0 },
+  { M_OPCODE(23,1),	   M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwnm.",	     0 },
+  { D_OPCODE(24),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "ori",	     0 },
+  { D_OPCODE(25),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "oris",	     H_IMM_HIGH },
+  { D_OPCODE(26),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "xori",	     0 },
+  { D_OPCODE(27),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "xoris",	     H_IMM_HIGH },
+  { D_OPCODE(28),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "andi.",	     0 },
+  { D_OPCODE(29),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "andis.",	     H_IMM_HIGH },
+  { X_OPCODE(31,0,0),	   X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
+    0,		     "cmp",	     0 },
+  { X_OPCODE(31,4,0),	   X_MASK,   {O_TO, O_rA, O_rB, 0},
+    0,		     "tw",	     0 },
+  { XO_OPCODE(31,8,0,0),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfc",	     0 },
+  { XO_OPCODE(31,8,0,1),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfc.",	     0 },
+  { XO_OPCODE(31,10,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addc",	     0 },
+  { XO_OPCODE(31,10,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addc.",	     0 },
+  { XO_OPCODE(31,11,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhwu",	     0 },
+  { XO_OPCODE(31,11,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhwu.",      0 },
+  { X_OPCODE(31,19,0),	   X_MASK,   {O_rD, 0},
+    0,		     "mfcr",	     0 },
+  { X_OPCODE(31,20,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwarx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,23,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwzx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,24,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "slw",	     0 },
+  { X_OPCODE(31,24,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "slw.",	     0 },
+  { X_OPCODE(31,26,0),	   X_MASK,   {O_rA, O_rS, O_Rc, 0 },
+    0,		     "cntlzw",	     0 },
+  { X_OPCODE(31,26,1),	   X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "cntlzw.",      0 },
+  { X_OPCODE(31,28,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "and",	     0 },
+  { X_OPCODE(31,28,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "and.",	     0 },
+  { X_OPCODE(31,32,0),	   X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
+    0,		     "cmpl",	     0 },
+  { XO_OPCODE(31,40,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subf",	     0 },
+  { XO_OPCODE(31,40,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subf.",	     0 },
+  { X_OPCODE(31,54,0),	   X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbst",	     H_RA0_IS_0 },
+  { X_OPCODE(31,55,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwzux",	     0 },
+  { X_OPCODE(31,60,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "andc",	     0 },
+  { X_OPCODE(31,60,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "andc.",	     0 },
+  { XO_OPCODE(31,75,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhw",	     0 },
+  { XO_OPCODE(31,75,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhw.",	     0 },
+  { X_OPCODE(31,83,0),	   X_MASK,   {O_rD, 0},
+    0,		     "mfmsr",	     0 },
+  { X_OPCODE(31,86,0),	   X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbf",	     H_RA0_IS_0 },
+  { X_OPCODE(31,87,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lbzx",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,104,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "neg",	     0 },
+  { XO_OPCODE(31,104,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "neg.",	     0 },
+  { X_OPCODE(31,119,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lbzux",	     0 },
+  { X_OPCODE(31,124,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "nor",	     0 },
+  { X_OPCODE(31,124,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "nor.",	     0 },
+  { XO_OPCODE(31,136,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfe",	     0 },
+  { XO_OPCODE(31,136,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfe.",	     0 },
+  { XO_OPCODE(31,138,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "adde",	     0 },
+  { XO_OPCODE(31,138,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "adde.",	     0 },
+  { XFX_OPCODE(31,144,0),  XFX_MASK, {O_CRM, O_rS, 0},
+    0,		     "mtcrf",	     0 },
+  { X_OPCODE(31,146,0),    X_MASK,   {O_rS, 0},
+    0,		     "mtmsr",	     0 },
+  { X_OPCODE(31,150,1),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwcx.",	     0 },
+  { X_OPCODE(31,151,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwx",	     0 },
+  { X_OPCODE(31,183,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwux",	     0 },
+  { XO_OPCODE(31,200,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfze",	     0 },
+  { XO_OPCODE(31,200,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfze.",      0 },
+  { XO_OPCODE(31,202,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addze",	     0 },
+  { XO_OPCODE(31,202,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addze.",	     0 },
+  { X_OPCODE(31,210,0),    X_MASK,   {O_SR, O_rS, 0},
+    0,		     "mtsr",	     0 },
+  { X_OPCODE(31,215,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stbx",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,232,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfme",	     0 },
+  { XO_OPCODE(31,232,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfme.",      0 },
+  { XO_OPCODE(31,234,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addme",	     0 },
+  { XO_OPCODE(31,234,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addme.",	     0 },
+  { XO_OPCODE(31,235,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullw",	     0 },
+  { XO_OPCODE(31,235,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullw.",	     0 },
+  { X_OPCODE(31,242,0),    X_MASK,   {O_rS, O_rB, 0},
+    0,		     "mtsrin",	     0 },
+  { X_OPCODE(31,246,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbtst",	     H_RA0_IS_0 },
+  { X_OPCODE(31,247,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stbux",	     0 },
+  { XO_OPCODE(31,266,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "add",	     0 },
+  { XO_OPCODE(31,266,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "add.",	     0 },
+  { X_OPCODE(31,278,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbt",	     H_RA0_IS_0 },
+  { X_OPCODE(31,279,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhzx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,284,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "eqv",	     0 },
+  { X_OPCODE(31,284,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "eqv.",	     0 },
+  { X_OPCODE(31,306,0),    X_MASK,   {O_rB, 0},
+    0,		     "tlbie",	     0 },
+  { X_OPCODE(31,310,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "eciwx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,311,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhzux",	     0 },
+  { X_OPCODE(31,316,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "xor",	     0 },
+  { X_OPCODE(31,316,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "xor.",	     0 },
+  { XFX_OPCODE(31,339,0),  XFX_MASK, {O_rD, O_spr, 0},
+    0,		     "mfspr",	     0 },
+  { X_OPCODE(31,343,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhax",	     H_RA0_IS_0 },
+  { X_OPCODE(31,370,0),    X_MASK,   {0},
+    0,		     "tlbia",	     0 },
+  { XFX_OPCODE(31,371,0),  XFX_MASK, {O_rD, O_tbr, 0},
+    0,		     "mftb",	     0 },
+  { X_OPCODE(31,375,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhaux",	     0 },
+  { X_OPCODE(31,407,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "sthx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,412,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "orc",	     0 },
+  { X_OPCODE(31,412,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "orc.",	     0 },
+  { X_OPCODE(31,438,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "ecowx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,439,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "sthux",	     0 },
+  { X_OPCODE(31,444,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "or",	     0 },
+  { X_OPCODE(31,444,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "or.",	     0 },
+  { XO_OPCODE(31,459,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwu",	     0 },
+  { XO_OPCODE(31,459,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwu.",	     0 },
+  { XFX_OPCODE(31,467,0),  XFX_MASK, {O_spr, O_rS, 0},
+    0,		     "mtspr",	     0 },
+  { X_OPCODE(31,470,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbi",	     H_RA0_IS_0 },
+  { X_OPCODE(31,476,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "nand",	     0 },
+  { X_OPCODE(31,476,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc,0},
+    0,		     "nand.",	     0 },
+  { XO_OPCODE(31,491,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divw",	     0 },
+  { XO_OPCODE(31,491,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divw.",	     0 },
+  { X_OPCODE(31,512,0),    X_MASK,   {O_crfD, 0},
+    0,		     "mcrxr",	     0 },
+  { XO_OPCODE(31,8,1,0),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfco",	     0 },
+  { XO_OPCODE(31,8,1,1),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfco.",      0 },
+  { XO_OPCODE(31,10,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addco",	     0 },
+  { XO_OPCODE(31,10,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addco.",	     0 },
+  { X_OPCODE(31,533,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lswx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,534,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwbrx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,536,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "srw",	     0 },
+  { X_OPCODE(31,536,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "srw.",	     0 },
+  { XO_OPCODE(31,40,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfo",	     0 },
+  { XO_OPCODE(31,40,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfo.",	     0 },
+  { X_OPCODE(31,566,0),    X_MASK,   {0},
+    0,		     "tlbsync",      0 },
+  { X_OPCODE(31,595,0),    X_MASK,   {O_rD, O_SR, 0},
+    0,		     "mfsr",	     0 },
+  { X_OPCODE(31,597,0),    X_MASK,   {O_rD, O_rA, O_NB, 0},
+    0,		     "lswi",	     H_RA0_IS_0 },
+  { X_OPCODE(31,598,0),    X_MASK,   {0},
+    0,		     "sync",	     0 },
+  { XO_OPCODE(31,104,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "nego",	     0 },
+  { XO_OPCODE(31,104,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "nego.",	     0 },
+  { XO_OPCODE(31,136,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfeo",	     0 },
+  { XO_OPCODE(31,136,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfeo.",      0 },
+  { XO_OPCODE(31,138,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addeo",	     0 },
+  { XO_OPCODE(31,138,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addeo.",	     0 },
+  { X_OPCODE(31,659,0),    X_MASK,   {O_rD, O_rB, 0},
+    0,		     "mfsrin",	     0 },
+  { X_OPCODE(31,661,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stswx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,662,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwbrx",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,200,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfzeo",      0 },
+  { XO_OPCODE(31,200,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfzeo.",     0 },
+  { XO_OPCODE(31,202,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addzeo",	     0 },
+  { XO_OPCODE(31,202,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addzeo.",      0 },
+  { X_OPCODE(31,725,0),    X_MASK,   {O_rS, O_rA, O_NB, 0},
+    0,		     "stswi",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,232,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfmeo",      0 },
+  { XO_OPCODE(31,232,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfmeo.",     0 },
+  { XO_OPCODE(31,234,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addmeo",	     0 },
+  { XO_OPCODE(31,234,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addmeo.",      0 },
+  { XO_OPCODE(31,235,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullwo",	     0 },
+  { XO_OPCODE(31,235,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullwo.",      0 },
+  { XO_OPCODE(31,266,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addo",	     0 },
+  { XO_OPCODE(31,266,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addo.",	     0 },
+  { X_OPCODE(31,790,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhbrx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,792,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "sraw",	     0 },
+  { X_OPCODE(31,792,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "sraw.",	     0 },
+  { X_OPCODE(31,824,0),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
+    0,		     "srawi",	     0 },
+  { X_OPCODE(31,824,1),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
+    0,		     "srawi.",	     0 },
+  { X_OPCODE(31,854,0),    X_MASK,   {0},
+    0,		     "eieio",	     0 },
+  { X_OPCODE(31,918,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "sthbrx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,922,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsh",	     0 },
+  { X_OPCODE(31,922,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsh.",	     0 },
+  { X_OPCODE(31,954,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsb",	     0 },
+  { X_OPCODE(31,954,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsb.",	     0 },
+  { XO_OPCODE(31,459,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwuo",	     0 },
+  { XO_OPCODE(31,459,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwuo.",      0 },
+  { X_OPCODE(31,978,0),    X_MASK,   {O_rB, 0},
+    0,		     "tlbld",	     0 },
+  { X_OPCODE(31,982,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "icbi",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,491,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwo",	     0 },
+  { XO_OPCODE(31,491,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwo.",	     0 },
+  { X_OPCODE(31,1010,0),   X_MASK,   {O_rB, 0},
+    0,		     "tlbli",	     0 },
+  { X_OPCODE(31,1014,0),   X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbz",	     H_RA0_IS_0 },
+  { D_OPCODE(32),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lwz",	     H_RA0_IS_0 },
+  { D_OPCODE(33),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lwzu",	     0 },
+  { D_OPCODE(34),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lbz",	     H_RA0_IS_0 },
+  { D_OPCODE(35),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lbzu",	     0 },
+  { D_OPCODE(36),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stw",	     H_RA0_IS_0 },
+  { D_OPCODE(37),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stwu",	     0 },
+  { D_OPCODE(38),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stb",	     H_RA0_IS_0 },
+  { D_OPCODE(39),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stbu",	     0 },
+  { D_OPCODE(40),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhz",	     H_RA0_IS_0 },
+  { D_OPCODE(41),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhzu",	     0 },
+  { D_OPCODE(42),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lha",	     H_RA0_IS_0 },
+  { D_OPCODE(43),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhau",	     0 },
+  { D_OPCODE(44),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "sth",	     H_RA0_IS_0 },
+  { D_OPCODE(45),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "sthu",	     0 },
+  { D_OPCODE(46),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lmw",	     H_RA0_IS_0 },
+  { D_OPCODE(47),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stmw",	     H_RA0_IS_0 },
+};
+
+const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);
+
+struct spr_info spr_map[] = {
+  { SPR_XER,	"XER" },
+  { SPR_LR,	"LR" },
+  { SPR_CTR,	"CTR" },
+  { SPR_DSISR,	"DSISR" },
+  { SPR_DAR,	"DAR" },
+  { SPR_DEC,	"DEC" },
+  { SPR_SRR0,	"SRR0" },
+  { SPR_SRR1,	"SRR1" },
+  { SPR_EIE,	"EIE" },
+  { SPR_EID,	"EID" },
+  { SPR_CMPA,	"CMPA" },
+  { SPR_CMPB,	"CMPB" },
+  { SPR_CMPC,	"CMPC" },
+  { SPR_CMPD,	"CMPD" },
+  { SPR_ICR,	"ICR" },
+  { SPR_DER,	"DER" },
+  { SPR_COUNTA,	"COUNTA" },
+  { SPR_COUNTB,	"COUNTB" },
+  { SPR_CMPE,	"CMPE" },
+  { SPR_CMPF,	"CMPF" },
+  { SPR_CMPG,	"CMPG" },
+  { SPR_CMPH,	"CMPH" },
+  { SPR_LCTRL1,	"LCTRL1" },
+  { SPR_LCTRL2,	"LCTRL2" },
+  { SPR_ICTRL,	"ICTRL" },
+  { SPR_BAR,	"BAR" },
+  { SPR_USPRG0,	"USPRG0" },
+  { SPR_SPRG4_RO,	"SPRG4_RO" },
+  { SPR_SPRG5_RO,	"SPRG5_RO" },
+  { SPR_SPRG6_RO,	"SPRG6_RO" },
+  { SPR_SPRG7_RO,	"SPRG7_RO" },
+  { SPR_SPRG0,	"SPRG0" },
+  { SPR_SPRG1,	"SPRG1" },
+  { SPR_SPRG2,	"SPRG2" },
+  { SPR_SPRG3,	"SPRG3" },
+  { SPR_SPRG4,	"SPRG4" },
+  { SPR_SPRG5,	"SPRG5" },
+  { SPR_SPRG6,	"SPRG6" },
+  { SPR_SPRG7,	"SPRG7" },
+  { SPR_EAR,	"EAR" },
+  { SPR_TBL,	"TBL" },
+  { SPR_TBU,	"TBU" },
+  { SPR_IC_CST,	"IC_CST" },
+  { SPR_IC_ADR,	"IC_ADR" },
+  { SPR_IC_DAT,	"IC_DAT" },
+  { SPR_DC_CST,	"DC_CST" },
+  { SPR_DC_ADR,	"DC_ADR" },
+  { SPR_DC_DAT,	"DC_DAT" },
+  { SPR_DPDR,	"DPDR" },
+  { SPR_IMMR,	"IMMR" },
+  { SPR_MI_CTR,	"MI_CTR" },
+  { SPR_MI_AP,	"MI_AP" },
+  { SPR_MI_EPN,	"MI_EPN" },
+  { SPR_MI_TWC,	"MI_TWC" },
+  { SPR_MI_RPN,	"MI_RPN" },
+  { SPR_MD_CTR,	"MD_CTR" },
+  { SPR_M_CASID,	"M_CASID" },
+  { SPR_MD_AP,	"MD_AP" },
+  { SPR_MD_EPN,	"MD_EPN" },
+  { SPR_M_TWB,	"M_TWB" },
+  { SPR_MD_TWC,	"MD_TWC" },
+  { SPR_MD_RPN,	"MD_RPN" },
+  { SPR_M_TW,	"M_TW" },
+  { SPR_MI_DBCAM,	"MI_DBCAM" },
+  { SPR_MI_DBRAM0,	"MI_DBRAM0" },
+  { SPR_MI_DBRAM1,	"MI_DBRAM1" },
+  { SPR_MD_DBCAM,	"MD_DBCAM" },
+  { SPR_MD_DBRAM0,	"MD_DBRAM0" },
+  { SPR_MD_DBRAM1,	"MD_DBRAM1" },
+  { SPR_ZPR,	"ZPR" },
+  { SPR_PID,	"PID" },
+  { SPR_CCR0,	"CCR0" },
+  { SPR_IAC3,	"IAC3" },
+  { SPR_IAC4,	"IAC4" },
+  { SPR_DVC1,	"DVC1" },
+  { SPR_DVC2,	"DVC2" },
+  { SPR_SGR,	"SGR" },
+  { SPR_DCWR,	"DCWR" },
+  { SPR_SLER,	"SLER" },
+  { SPR_SU0R,	"SU0R" },
+  { SPR_DBCR1,	"DBCR1" },
+  { SPR_ICDBDR,	"ICDBDR" },
+  { SPR_ESR,	"ESR" },
+  { SPR_DEAR,	"DEAR" },
+  { SPR_EVPR,	"EVPR" },
+  { SPR_TSR,	"TSR" },
+  { SPR_TCR,	"TCR" },
+  { SPR_PIT,	"PIT" },
+  { SPR_SRR2,	"SRR2" },
+  { SPR_SRR3,	"SRR3" },
+  { SPR_DBSR,	"DBSR" },
+  { SPR_DBCR0,	"DBCR0" },
+  { SPR_IAC1,	"IAC1" },
+  { SPR_IAC2,	"IAC2" },
+  { SPR_DAC1,	"DAC1" },
+  { SPR_DAC2,	"DAC2" },
+  { SPR_DCCR,	"DCCR" },
+  { SPR_ICCR,	"ICCR" },
+};
+
+const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]);
+
+#endif
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */

u-boot/include/bedbug/type.h

@@ -0,0 +1,26 @@
+#ifndef _TYPE_BEDBUG_H
+#define _TYPE_BEDBUG_H
+
+/* Supporting routines */
+int bedbug_puts (const char *);
+void bedbug_init (void);
+void bedbug860_init (void);
+void do_bedbug_breakpoint (struct pt_regs *);
+void bedbug_main_loop (unsigned long, struct pt_regs *);
+
+
+typedef struct {
+	int hw_debug_enabled;
+	int stopped;
+	int current_bp;
+	struct pt_regs *regs;
+
+	void (*do_break) (cmd_tbl_t *, int, int, char * const []);
+	void (*break_isr) (struct pt_regs *);
+	int (*find_empty) (void);
+	int (*set) (int, unsigned long);
+	int (*clear) (int);
+} CPU_DEBUG_CTX;
+
+
+#endif /* _TYPE_BEDBUG_H  */

u-boot/include/bios_emul.h

@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 1996-1999 SciTech Software, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _BIOS_EMUL_H
+#define _BIOS_EMUL_H
+
+/* Include the register header directly here */
+#include "../drivers/bios_emulator/include/x86emu/regs.h"
+#include <pci.h>
+
+/****************************************************************************
+REMARKS:
+Data structure used to describe the details for the BIOS emulator system
+environment as used by the X86 emulator library.
+
+HEADER:
+biosemu.h
+
+MEMBERS:
+vgaInfo         - VGA BIOS information structure
+biosmem_base    - Base of the BIOS image
+biosmem_limit   - Limit of the BIOS image
+busmem_base     - Base of the VGA bus memory
+****************************************************************************/
+typedef struct {
+	int function;
+	int device;
+	int bus;
+	u32 VendorID;
+	u32 DeviceID;
+#ifdef CONFIG_DM_PCI
+	struct udevice *pcidev;
+#else
+	pci_dev_t pcidev;
+#endif
+	void *BIOSImage;
+	u32 BIOSImageLen;
+	u8 LowMem[1536];
+} BE_VGAInfo;
+
+struct vbe_mode_info;
+
+#ifdef CONFIG_DM_PCI
+int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
+		      int clean_up);
+#else
+int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up);
+#endif
+
+/* Run a BIOS ROM natively (only supported on x86 machines) */
+void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
+		     struct vbe_mode_info *mode_info);
+
+/**
+ * bios_set_interrupt_handler() - Install an interrupt handler for the BIOS
+ *
+ * This installs an interrupt handler that the BIOS will call when needed.
+ *
+ * @intnum:		Interrupt number to install a handler for
+ * @int_handler_func:	Function to call to handle interrupt
+ */
+void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void));
+
+void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void));
+
+#ifdef CONFIG_DM_PCI
+int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **pVGAInfo);
+
+int biosemu_run(struct udevice *dev, uchar *bios_rom, int bios_len,
+		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+		struct vbe_mode_info *mode_info);
+#else
+int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo);
+
+int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
+		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+		struct vbe_mode_info *mode_info);
+#endif
+
+#endif

u-boot/include/bitfield.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+/*
+ * Bitfield operations
+ *
+ * These are generic bitfield operations which allow manipulation of variable
+ * width bitfields within a word. One use of this would be to use data tables
+ * to determine how to reprogram fields within R/W hardware registers.
+ *
+ * Example:
+ *
+ *            old_reg_val
+ * +--------+----+---+--+-----+----------+
+ * |        |    |   |  | old |          |
+ * +--------+----+---+--+-----+----------+
+ *
+ *            new_reg_val
+ * +--------+----+---+--+-----+----------+
+ * |        |    |   |  | new |          |
+ * +--------+----+---+--+-----+----------+
+ *
+ * mask = bitfield_mask(10, 5);
+ * old = bitfield_extract(old_reg_val, 10, 5);
+ * new_reg_val = bitfield_replace(old_reg_val, 10, 5, new);
+ *
+ * or
+ *
+ * mask = bitfield_mask(10, 5);
+ * old = bitfield_extract_by_mask(old_reg_val, mask);
+ * new_reg_val = bitfield_replace_by_mask(old_reg_val, mask, new);
+ *
+ * The numbers 10 and 5 could for example come from data
+ * tables which describe all bitfields in all registers.
+ */
+
+#include <linux/types.h>
+
+/* Produces a mask of set bits covering a range of a uint value */
+static inline uint bitfield_mask(uint shift, uint width)
+{
+	return ((1 << width) - 1) << shift;
+}
+
+/* Extract the value of a bitfield found within a given register value */
+static inline uint bitfield_extract(uint reg_val, uint shift, uint width)
+{
+	return (reg_val & bitfield_mask(shift, width)) >> shift;
+}
+
+/*
+ * Replace the value of a bitfield found within a given register value
+ * Returns the newly modified uint value with the replaced field.
+ */
+static inline uint bitfield_replace(uint reg_val, uint shift, uint width,
+				    uint bitfield_val)
+{
+	uint mask = bitfield_mask(shift, width);
+
+	return (reg_val & ~mask) | ((bitfield_val << shift) & mask);
+}
+
+/* Produces a shift of the bitfield given a mask */
+static inline uint bitfield_shift(uint mask)
+{
+	return mask ? ffs(mask) - 1 : 0;
+}
+
+/* Extract the value of a bitfield found within a given register value */
+static inline uint bitfield_extract_by_mask(uint reg_val, uint mask)
+{
+	uint shift = bitfield_shift(mask);
+
+	return (reg_val & mask) >> shift;
+}
+
+/*
+ * Replace the value of a bitfield found within a given register value
+ * Returns the newly modified uint value with the replaced field.
+ */
+static inline uint bitfield_replace_by_mask(uint reg_val, uint mask,
+					    uint bitfield_val)
+{
+	uint shift = bitfield_shift(mask);
+
+	return (reg_val & ~mask) | ((bitfield_val << shift) & mask);
+}

u-boot/include/blk.h

@@ -0,0 +1,606 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef BLK_H
+#define BLK_H
+
+#ifdef CONFIG_SYS_64BIT_LBA
+typedef uint64_t lbaint_t;
+#define LBAFlength "ll"
+#else
+typedef ulong lbaint_t;
+#define LBAFlength "l"
+#endif
+#define LBAF "%" LBAFlength "x"
+#define LBAFU "%" LBAFlength "u"
+
+/* Interface types: */
+enum if_type {
+	IF_TYPE_UNKNOWN = 0,
+	IF_TYPE_IDE,
+	IF_TYPE_SCSI,
+	IF_TYPE_ATAPI,
+	IF_TYPE_USB,
+	IF_TYPE_DOC,
+	IF_TYPE_MMC,
+	IF_TYPE_SD,
+	IF_TYPE_SATA,
+	IF_TYPE_HOST,
+	IF_TYPE_SYSTEMACE,
+
+	IF_TYPE_COUNT,			/* Number of interface types */
+};
+
+/*
+ * With driver model (CONFIG_BLK) this is uclass platform data, accessible
+ * with dev_get_uclass_platdata(dev)
+ */
+struct blk_desc {
+	/*
+	 * TODO: With driver model we should be able to use the parent
+	 * device's uclass instead.
+	 */
+	enum if_type	if_type;	/* type of the interface */
+	int		devnum;		/* device number */
+	unsigned char	part_type;	/* partition type */
+	unsigned char	target;		/* target SCSI ID */
+	unsigned char	lun;		/* target LUN */
+	unsigned char	hwpart;		/* HW partition, e.g. for eMMC */
+	unsigned char	type;		/* device type */
+	unsigned char	removable;	/* removable device */
+#ifdef CONFIG_LBA48
+	/* device can use 48bit addr (ATA/ATAPI v7) */
+	unsigned char	lba48;
+#endif
+	lbaint_t	lba;		/* number of blocks */
+	unsigned long	blksz;		/* block size */
+	int		log2blksz;	/* for convenience: log2(blksz) */
+	char		vendor[40+1];	/* IDE model, SCSI Vendor */
+	char		product[20+1];	/* IDE Serial no, SCSI product */
+	char		revision[8+1];	/* firmware revision */
+#ifdef CONFIG_BLK
+	/*
+	 * For now we have a few functions which take struct blk_desc as a
+	 * parameter. This field allows them to look up the associated
+	 * device. Once these functions are removed we can drop this field.
+	 */
+	struct udevice *bdev;
+#else
+	unsigned long	(*block_read)(struct blk_desc *block_dev,
+				      lbaint_t start,
+				      lbaint_t blkcnt,
+				      void *buffer);
+	unsigned long	(*block_write)(struct blk_desc *block_dev,
+				       lbaint_t start,
+				       lbaint_t blkcnt,
+				       const void *buffer);
+	unsigned long	(*block_erase)(struct blk_desc *block_dev,
+				       lbaint_t start,
+				       lbaint_t blkcnt);
+	void		*priv;		/* driver private struct pointer */
+#endif
+};
+
+#define BLOCK_CNT(size, blk_desc) (PAD_COUNT(size, blk_desc->blksz))
+#define PAD_TO_BLOCKSIZE(size, blk_desc) \
+	(PAD_SIZE(size, blk_desc->blksz))
+
+#ifdef CONFIG_BLOCK_CACHE
+/**
+ * blkcache_read() - attempt to read a set of blocks from cache
+ *
+ * @param iftype - IF_TYPE_x for type of device
+ * @param dev - device index of particular type
+ * @param start - starting block number
+ * @param blkcnt - number of blocks to read
+ * @param blksz - size in bytes of each block
+ * @param buf - buffer to contain cached data
+ *
+ * @return - '1' if block returned from cache, '0' otherwise.
+ */
+int blkcache_read(int iftype, int dev,
+		  lbaint_t start, lbaint_t blkcnt,
+		  unsigned long blksz, void *buffer);
+
+/**
+ * blkcache_fill() - make data read from a block device available
+ * to the block cache
+ *
+ * @param iftype - IF_TYPE_x for type of device
+ * @param dev - device index of particular type
+ * @param start - starting block number
+ * @param blkcnt - number of blocks available
+ * @param blksz - size in bytes of each block
+ * @param buf - buffer containing data to cache
+ *
+ */
+void blkcache_fill(int iftype, int dev,
+		   lbaint_t start, lbaint_t blkcnt,
+		   unsigned long blksz, void const *buffer);
+
+/**
+ * blkcache_invalidate() - discard the cache for a set of blocks
+ * because of a write or device (re)initialization.
+ *
+ * @param iftype - IF_TYPE_x for type of device
+ * @param dev - device index of particular type
+ */
+void blkcache_invalidate(int iftype, int dev);
+
+/**
+ * blkcache_configure() - configure block cache
+ *
+ * @param blocks - maximum blocks per entry
+ * @param entries - maximum entries in cache
+ */
+void blkcache_configure(unsigned blocks, unsigned entries);
+
+/*
+ * statistics of the block cache
+ */
+struct block_cache_stats {
+	unsigned hits;
+	unsigned misses;
+	unsigned entries; /* current entry count */
+	unsigned max_blocks_per_entry;
+	unsigned max_entries;
+};
+
+/**
+ * get_blkcache_stats() - return statistics and reset
+ *
+ * @param stats - statistics are copied here
+ */
+void blkcache_stats(struct block_cache_stats *stats);
+
+#else
+
+static inline int blkcache_read(int iftype, int dev,
+				lbaint_t start, lbaint_t blkcnt,
+				unsigned long blksz, void *buffer)
+{
+	return 0;
+}
+
+static inline void blkcache_fill(int iftype, int dev,
+				 lbaint_t start, lbaint_t blkcnt,
+				 unsigned long blksz, void const *buffer) {}
+
+static inline void blkcache_invalidate(int iftype, int dev) {}
+
+#endif
+
+#ifdef CONFIG_BLK
+struct udevice;
+
+/* Operations on block devices */
+struct blk_ops {
+	/**
+	 * read() - read from a block device
+	 *
+	 * @dev:	Device to read from
+	 * @start:	Start block number to read (0=first)
+	 * @blkcnt:	Number of blocks to read
+	 * @buffer:	Destination buffer for data read
+	 * @return number of blocks read, or -ve error number (see the
+	 * IS_ERR_VALUE() macro
+	 */
+	unsigned long (*read)(struct udevice *dev, lbaint_t start,
+			      lbaint_t blkcnt, void *buffer);
+
+	/**
+	 * write() - write to a block device
+	 *
+	 * @dev:	Device to write to
+	 * @start:	Start block number to write (0=first)
+	 * @blkcnt:	Number of blocks to write
+	 * @buffer:	Source buffer for data to write
+	 * @return number of blocks written, or -ve error number (see the
+	 * IS_ERR_VALUE() macro
+	 */
+	unsigned long (*write)(struct udevice *dev, lbaint_t start,
+			       lbaint_t blkcnt, const void *buffer);
+
+	/**
+	 * erase() - erase a section of a block device
+	 *
+	 * @dev:	Device to (partially) erase
+	 * @start:	Start block number to erase (0=first)
+	 * @blkcnt:	Number of blocks to erase
+	 * @return number of blocks erased, or -ve error number (see the
+	 * IS_ERR_VALUE() macro
+	 */
+	unsigned long (*erase)(struct udevice *dev, lbaint_t start,
+			       lbaint_t blkcnt);
+
+	/**
+	 * select_hwpart() - select a particular hardware partition
+	 *
+	 * Some devices (e.g. MMC) can support partitioning at the hardware
+	 * level. This is quite separate from the normal idea of
+	 * software-based partitions. MMC hardware partitions must be
+	 * explicitly selected. Once selected only the region of the device
+	 * covered by that partition is accessible.
+	 *
+	 * The MMC standard provides for two boot partitions (numbered 1 and 2),
+	 * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
+	 *
+	 * @desc:	Block device to update
+	 * @hwpart:	Hardware partition number to select. 0 means the raw
+	 *		device, 1 is the first partition, 2 is the second, etc.
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*select_hwpart)(struct udevice *dev, int hwpart);
+};
+
+#define blk_get_ops(dev)	((struct blk_ops *)(dev)->driver->ops)
+
+/*
+ * These functions should take struct udevice instead of struct blk_desc,
+ * but this is convenient for migration to driver model. Add a 'd' prefix
+ * to the function operations, so that blk_read(), etc. can be reserved for
+ * functions with the correct arguments.
+ */
+unsigned long blk_dread(struct blk_desc *block_dev, lbaint_t start,
+			lbaint_t blkcnt, void *buffer);
+unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start,
+			 lbaint_t blkcnt, const void *buffer);
+unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start,
+			 lbaint_t blkcnt);
+
+/**
+ * blk_get_device() - Find and probe a block device ready for use
+ *
+ * @if_type:	Interface type (enum if_type_t)
+ * @devnum:	Device number (specific to each interface type)
+ * @devp:	the device, if found
+ * @return - if found, -ENODEV if no device found, or other -ve error value
+ */
+int blk_get_device(int if_type, int devnum, struct udevice **devp);
+
+/**
+ * blk_first_device() - Find the first device for a given interface
+ *
+ * The device is probed ready for use
+ *
+ * @devnum:	Device number (specific to each interface type)
+ * @devp:	the device, if found
+ * @return 0 if found, -ENODEV if no device, or other -ve error value
+ */
+int blk_first_device(int if_type, struct udevice **devp);
+
+/**
+ * blk_next_device() - Find the next device for a given interface
+ *
+ * This can be called repeatedly after blk_first_device() to iterate through
+ * all devices of the given interface type.
+ *
+ * The device is probed ready for use
+ *
+ * @devp:	On entry, the previous device returned. On exit, the next
+ *		device, if found
+ * @return 0 if found, -ENODEV if no device, or other -ve error value
+ */
+int blk_next_device(struct udevice **devp);
+
+/**
+ * blk_create_device() - Create a new block device
+ *
+ * @parent:	Parent of the new device
+ * @drv_name:	Driver name to use for the block device
+ * @name:	Name for the device
+ * @if_type:	Interface type (enum if_type_t)
+ * @devnum:	Device number, specific to the interface type, or -1 to
+ *		allocate the next available number
+ * @blksz:	Block size of the device in bytes (typically 512)
+ * @size:	Total size of the device in bytes
+ * @devp:	the new device (which has not been probed)
+ */
+int blk_create_device(struct udevice *parent, const char *drv_name,
+		      const char *name, int if_type, int devnum, int blksz,
+		      lbaint_t size, struct udevice **devp);
+
+/**
+ * blk_create_devicef() - Create a new named block device
+ *
+ * @parent:	Parent of the new device
+ * @drv_name:	Driver name to use for the block device
+ * @name:	Name for the device (parent name is prepended)
+ * @if_type:	Interface type (enum if_type_t)
+ * @devnum:	Device number, specific to the interface type, or -1 to
+ *		allocate the next available number
+ * @blksz:	Block size of the device in bytes (typically 512)
+ * @size:	Total size of the device in bytes
+ * @devp:	the new device (which has not been probed)
+ */
+int blk_create_devicef(struct udevice *parent, const char *drv_name,
+		       const char *name, int if_type, int devnum, int blksz,
+		       lbaint_t size, struct udevice **devp);
+
+/**
+ * blk_prepare_device() - Prepare a block device for use
+ *
+ * This reads partition information from the device if supported.
+ *
+ * @dev:	Device to prepare
+ * @return 0 if ok, -ve on error
+ */
+int blk_prepare_device(struct udevice *dev);
+
+/**
+ * blk_unbind_all() - Unbind all device of the given interface type
+ *
+ * The devices are removed and then unbound.
+ *
+ * @if_type:	Interface type to unbind
+ * @return 0 if OK, -ve on error
+ */
+int blk_unbind_all(int if_type);
+
+/**
+ * blk_find_max_devnum() - find the maximum device number for an interface type
+ *
+ * Finds the last allocated device number for an interface type @if_type. The
+ * next number is safe to use for a newly allocated device.
+ *
+ * @if_type:	Interface type to scan
+ * @return maximum device number found, or -ENODEV if none, or other -ve on
+ * error
+ */
+int blk_find_max_devnum(enum if_type if_type);
+
+/**
+ * blk_select_hwpart() - select a hardware partition
+ *
+ * Select a hardware partition if the device supports it (typically MMC does)
+ *
+ * @dev:	Device to update
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_select_hwpart(struct udevice *dev, int hwpart);
+
+#else
+#include <errno.h>
+/*
+ * These functions should take struct udevice instead of struct blk_desc,
+ * but this is convenient for migration to driver model. Add a 'd' prefix
+ * to the function operations, so that blk_read(), etc. can be reserved for
+ * functions with the correct arguments.
+ */
+static inline ulong blk_dread(struct blk_desc *block_dev, lbaint_t start,
+			      lbaint_t blkcnt, void *buffer)
+{
+	ulong blks_read;
+	if (blkcache_read(block_dev->if_type, block_dev->devnum,
+			  start, blkcnt, block_dev->blksz, buffer))
+		return blkcnt;
+
+	/*
+	 * We could check if block_read is NULL and return -ENOSYS. But this
+	 * bloats the code slightly (cause some board to fail to build), and
+	 * it would be an error to try an operation that does not exist.
+	 */
+	blks_read = block_dev->block_read(block_dev, start, blkcnt, buffer);
+	if (blks_read == blkcnt)
+		blkcache_fill(block_dev->if_type, block_dev->devnum,
+			      start, blkcnt, block_dev->blksz, buffer);
+
+	return blks_read;
+}
+
+static inline ulong blk_dwrite(struct blk_desc *block_dev, lbaint_t start,
+			       lbaint_t blkcnt, const void *buffer)
+{
+	blkcache_invalidate(block_dev->if_type, block_dev->devnum);
+	return block_dev->block_write(block_dev, start, blkcnt, buffer);
+}
+
+static inline ulong blk_derase(struct blk_desc *block_dev, lbaint_t start,
+			       lbaint_t blkcnt)
+{
+	blkcache_invalidate(block_dev->if_type, block_dev->devnum);
+	return block_dev->block_erase(block_dev, start, blkcnt);
+}
+
+/**
+ * struct blk_driver - Driver for block interface types
+ *
+ * This provides access to the block devices for each interface type. One
+ * driver should be provided using U_BOOT_LEGACY_BLK() for each interface
+ * type that is to be supported.
+ *
+ * @if_typename:	Interface type name
+ * @if_type:		Interface type
+ * @max_devs:		Maximum number of devices supported
+ * @desc:		Pointer to list of devices for this interface type,
+ *			or NULL to use @get_dev() instead
+ */
+struct blk_driver {
+	const char *if_typename;
+	enum if_type if_type;
+	int max_devs;
+	struct blk_desc *desc;
+	/**
+	 * get_dev() - get a pointer to a block device given its number
+	 *
+	 * Each interface allocates its own devices and typically
+	 * struct blk_desc is contained with the interface's data structure.
+	 * There is no global numbering for block devices. This method allows
+	 * the device for an interface type to be obtained when @desc is NULL.
+	 *
+	 * @devnum:	Device number (0 for first device on that interface,
+	 *		1 for second, etc.
+	 * @descp:	Returns pointer to the block device on success
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_dev)(int devnum, struct blk_desc **descp);
+
+	/**
+	 * select_hwpart() - Select a hardware partition
+	 *
+	 * Some devices (e.g. MMC) can support partitioning at the hardware
+	 * level. This is quite separate from the normal idea of
+	 * software-based partitions. MMC hardware partitions must be
+	 * explicitly selected. Once selected only the region of the device
+	 * covered by that partition is accessible.
+	 *
+	 * The MMC standard provides for two boot partitions (numbered 1 and 2),
+	 * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
+	 * Partition 0 is the main user-data partition.
+	 *
+	 * @desc:	Block device descriptor
+	 * @hwpart:	Hardware partition number to select. 0 means the main
+	 *		user-data partition, 1 is the first partition, 2 is
+	 *		the second, etc.
+	 * @return 0 if OK, other value for an error
+	 */
+	int (*select_hwpart)(struct blk_desc *desc, int hwpart);
+};
+
+/*
+ * Declare a new U-Boot legacy block driver. New drivers should use driver
+ * model (UCLASS_BLK).
+ */
+#define U_BOOT_LEGACY_BLK(__name)					\
+	ll_entry_declare(struct blk_driver, __name, blk_driver)
+
+struct blk_driver *blk_driver_lookup_type(int if_type);
+
+#endif /* !CONFIG_BLK */
+
+/**
+ * blk_get_devnum_by_typename() - Get a block device by type and number
+ *
+ * This looks through the available block devices of the given type, returning
+ * the one with the given @devnum.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return point to block device descriptor, or NULL if not found
+ */
+struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum);
+
+/**
+ * blk_get_devnum_by_type() - Get a block device by type name, and number
+ *
+ * This looks up the block device type based on @if_typename, then calls
+ * blk_get_devnum_by_type().
+ *
+ * @if_typename:	Block device type name
+ * @devnum:		Device number
+ * @return point to block device descriptor, or NULL if not found
+ */
+struct blk_desc *blk_get_devnum_by_typename(const char *if_typename,
+					    int devnum);
+
+/**
+ * blk_dselect_hwpart() - select a hardware partition
+ *
+ * This selects a hardware partition (such as is supported by MMC). The block
+ * device size may change as this effectively points the block device to a
+ * partition at the hardware level. See the select_hwpart() method above.
+ *
+ * @desc:	Block device descriptor for the device to select
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_dselect_hwpart(struct blk_desc *desc, int hwpart);
+
+/**
+ * blk_list_part() - list the partitions for block devices of a given type
+ *
+ * This looks up the partition type for each block device of type @if_type,
+ * then displays a list of partitions.
+ *
+ * @if_type:	Block device type
+ * @return 0 if OK, -ENODEV if there is none of that type
+ */
+int blk_list_part(enum if_type if_type);
+
+/**
+ * blk_list_devices() - list the block devices of a given type
+ *
+ * This lists each block device of the type @if_type, showing the capacity
+ * as well as type-specific information.
+ *
+ * @if_type:	Block device type
+ */
+void blk_list_devices(enum if_type if_type);
+
+/**
+ * blk_show_device() - show information about a given block device
+ *
+ * This shows the block device capacity as well as type-specific information.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENODEV for invalid device number
+ */
+int blk_show_device(enum if_type if_type, int devnum);
+
+/**
+ * blk_print_device_num() - show information about a given block device
+ *
+ * This is similar to blk_show_device() but returns an error if the block
+ * device type is unknown.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENODEV for invalid device number, -ENOENT if the block
+ * device is not connected
+ */
+int blk_print_device_num(enum if_type if_type, int devnum);
+
+/**
+ * blk_print_part_devnum() - print the partition information for a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENOENT if the block device is not connected, -ENOSYS if
+ * the interface type is not supported, other -ve on other error
+ */
+int blk_print_part_devnum(enum if_type if_type, int devnum);
+
+/**
+ * blk_read_devnum() - read blocks from a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @blkcnt:	Number of blocks to read
+ * @buffer:	Address to write data to
+ * @return number of blocks read, or -ve error number on error
+ */
+ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		      lbaint_t blkcnt, void *buffer);
+
+/**
+ * blk_write_devnum() - write blocks to a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @blkcnt:	Number of blocks to write
+ * @buffer:	Address to read data from
+ * @return number of blocks written, or -ve error number on error
+ */
+ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		       lbaint_t blkcnt, const void *buffer);
+
+/**
+ * blk_select_hwpart_devnum() - select a hardware partition
+ *
+ * This is similar to blk_dselect_hwpart() but it looks up the interface and
+ * device number.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart);
+
+#endif

u-boot/include/bmp_layout.h

@@ -0,0 +1,60 @@
+/* (C) Copyright 2002
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************/
+/* ** Layout of a bmp file						*/
+/************************************************************************/
+
+#ifndef _BMP_H_
+#define _BMP_H_
+
+struct __packed bmp_color_table_entry {
+	__u8	blue;
+	__u8	green;
+	__u8	red;
+	__u8	reserved;
+};
+
+/* When accessing these fields, remember that they are stored in little
+   endian format, so use linux macros, e.g. le32_to_cpu(width)          */
+
+struct __packed bmp_header {
+	/* Header */
+	char signature[2];
+	__u32	file_size;
+	__u32	reserved;
+	__u32	data_offset;
+	/* InfoHeader */
+	__u32	size;
+	__u32	width;
+	__u32	height;
+	__u16	planes;
+	__u16	bit_count;
+	__u32	compression;
+	__u32	image_size;
+	__u32	x_pixels_per_m;
+	__u32	y_pixels_per_m;
+	__u32	colors_used;
+	__u32	colors_important;
+	/* ColorTable */
+};
+
+struct bmp_image {
+	struct bmp_header header;
+	/* We use a zero sized array just as a placeholder for variable
+	   sized array */
+	struct bmp_color_table_entry color_table[0];
+};
+
+/* Data in the bmp_image is aligned to this length */
+#define BMP_DATA_ALIGN	4
+
+/* Constants for the compression field */
+#define BMP_BI_RGB	0
+#define BMP_BI_RLE8	1
+#define BMP_BI_RLE4	2
+
+#endif							/* _BMP_H_ */

u-boot/include/bootcount.h

@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2012
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+
+#if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE)
+# if __BYTE_ORDER == __LITTLE_ENDIAN
+#  define CONFIG_SYS_BOOTCOUNT_LE
+# else
+#  define CONFIG_SYS_BOOTCOUNT_BE
+# endif
+#endif
+
+#ifdef CONFIG_SYS_BOOTCOUNT_LE
+static inline void raw_bootcount_store(volatile u32 *addr, u32 data)
+{
+	out_le32(addr, data);
+}
+
+static inline u32 raw_bootcount_load(volatile u32 *addr)
+{
+	return in_le32(addr);
+}
+#else
+static inline void raw_bootcount_store(volatile u32 *addr, u32 data)
+{
+	out_be32(addr, data);
+}
+
+static inline u32 raw_bootcount_load(volatile u32 *addr)
+{
+	return in_be32(addr);
+}
+#endif

u-boot/include/bootm.h

@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOOTM_H
+#define _BOOTM_H
+
+#include <command.h>
+#include <image.h>
+
+#define BOOTM_ERR_RESET		(-1)
+#define BOOTM_ERR_OVERLAP		(-2)
+#define BOOTM_ERR_UNIMPLEMENTED	(-3)
+
+/*
+ *  Continue booting an OS image; caller already has:
+ *  - copied image header to global variable `header'
+ *  - checked header magic number, checksums (both header & image),
+ *  - verified image architecture (PPC) and type (KERNEL or MULTI),
+ *  - loaded (first part of) image to header load address,
+ *  - disabled interrupts.
+ *
+ * @flag: Flags indicating what to do (BOOTM_STATE_...)
+ * @argc: Number of arguments. Note that the arguments are shifted down
+ *	 so that 0 is the first argument not processed by U-Boot, and
+ *	 argc is adjusted accordingly. This avoids confusion as to how
+ *	 many arguments are available for the OS.
+ * @images: Pointers to os/initrd/fdt
+ * @return 1 on error. On success the OS boots so this function does
+ * not return.
+ */
+typedef int boot_os_fn(int flag, int argc, char * const argv[],
+			bootm_headers_t *images);
+
+extern boot_os_fn do_bootm_linux;
+int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void lynxkdi_boot(image_header_t *hdr);
+
+boot_os_fn *bootm_os_get_boot_func(int os);
+
+int bootm_host_load_images(const void *fit, int cfg_noffset);
+
+int boot_selected_os(int argc, char * const argv[], int state,
+		     bootm_headers_t *images, boot_os_fn *boot_fn);
+
+ulong bootm_disable_interrupts(void);
+
+/* This is a special function used by booti/bootz */
+int bootm_find_images(int flag, int argc, char * const argv[]);
+
+int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		    int states, bootm_headers_t *images, int boot_progress);
+
+void arch_preboot_os(void);
+
+/**
+ * bootm_decomp_image() - decompress the operating system
+ *
+ * @comp:	Compression algorithm that is used (IH_COMP_...)
+ * @load:	Destination load address in U-Boot memory
+ * @image_start Image start address (where we are decompressing from)
+ * @type:	OS type (IH_OS_...)
+ * @load_bug:	Place to decompress to
+ * @image_buf:	Address to decompress from
+ * @image_len:	Number of bytes in @image_buf to decompress
+ * @unc_len:	Available space for decompression
+ * @return 0 if OK, -ve on error (BOOTM_ERR_...)
+ */
+int bootm_decomp_image(int comp, ulong load, ulong image_start, int type,
+		       void *load_buf, void *image_buf, ulong image_len,
+		       uint unc_len, ulong *load_end);
+
+#endif

u-boot/include/bootretry.h

@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOOTRETRY_H
+#define __BOOTRETRY_H
+
+#ifdef CONFIG_BOOT_RETRY_TIME
+/**
+ * bootretry_tstc_timeout() - ensure we get a keypress before timeout
+ *
+ * Check for a keypress repeatedly, resetting the watchdog each time. If a
+ * keypress is not received within the command timeout, return an error.
+ *
+ * @return 0 if a key is received in time, -ETIMEDOUT if not
+ */
+int bootretry_tstc_timeout(void);
+
+/**
+ * bootretry_init_cmd_timeout() - set up command timeout
+ *
+ * Get the required command timeout from the environment.
+ */
+void bootretry_init_cmd_timeout(void);
+
+/**
+ * bootretry_reset_cmd_timeout() - reset command timeout
+ *
+ * Reset the command timeout so that the user has a fresh start. This is
+ * typically used when input is received from the user.
+ */
+void bootretry_reset_cmd_timeout(void);
+
+/** bootretry_dont_retry() - Indicate that we should not retry the boot */
+void bootretry_dont_retry(void);
+#else
+static inline int bootretry_tstc_timeout(void)
+{
+	return 0;
+}
+
+static inline void bootretry_init_cmd_timeout(void)
+{
+}
+
+static inline void bootretry_reset_cmd_timeout(void)
+{
+}
+
+static inline void bootretry_dont_retry(void)
+{
+}
+
+#endif
+
+#endif

u-boot/include/bootstage.h

@@ -0,0 +1,399 @@
+/*
+ * This file implements recording of each stage of the boot process. It is
+ * intended to implement timing of each stage, reporting this information
+ * to the user and passing it to the OS for logging / further analysis.
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOOTSTAGE_H
+#define _BOOTSTAGE_H
+
+/* Define this for host tools */
+#ifndef CONFIG_BOOTSTAGE_USER_COUNT
+#define CONFIG_BOOTSTAGE_USER_COUNT	20
+#endif
+
+/* Flags for each bootstage record */
+enum bootstage_flags {
+	BOOTSTAGEF_ERROR	= 1 << 0,	/* Error record */
+	BOOTSTAGEF_ALLOC	= 1 << 1,	/* Allocate an id */
+};
+
+/* bootstate sub-IDs used for kernel and ramdisk ranges */
+enum {
+	BOOTSTAGE_SUB_FORMAT,
+	BOOTSTAGE_SUB_FORMAT_OK,
+	BOOTSTAGE_SUB_NO_UNIT_NAME,
+	BOOTSTAGE_SUB_UNIT_NAME,
+	BOOTSTAGE_SUB_SUBNODE,
+
+	BOOTSTAGE_SUB_CHECK,
+	BOOTSTAGE_SUB_HASH = 5,
+	BOOTSTAGE_SUB_CHECK_ARCH = 5,
+	BOOTSTAGE_SUB_CHECK_ALL,
+	BOOTSTAGE_SUB_GET_DATA,
+	BOOTSTAGE_SUB_CHECK_ALL_OK = 7,
+	BOOTSTAGE_SUB_GET_DATA_OK,
+	BOOTSTAGE_SUB_LOAD,
+};
+
+/*
+ * A list of boot stages that we know about. Each of these indicates the
+ * state that we are at, and the action that we are about to perform. For
+ * errors, we issue an error for an item when it fails. Therefore the
+ * normal sequence is:
+ *
+ * progress action1
+ * progress action2
+ * progress action3
+ *
+ * and an error condition where action 3 failed would be:
+ *
+ * progress action1
+ * progress action2
+ * progress action3
+ * error on action3
+ */
+enum bootstage_id {
+	BOOTSTAGE_ID_START = 0,
+	BOOTSTAGE_ID_CHECK_MAGIC,	/* Checking image magic */
+	BOOTSTAGE_ID_CHECK_HEADER,	/* Checking image header */
+	BOOTSTAGE_ID_CHECK_CHECKSUM,	/* Checking image checksum */
+	BOOTSTAGE_ID_CHECK_ARCH,	/* Checking architecture */
+
+	BOOTSTAGE_ID_CHECK_IMAGETYPE = 5,/* Checking image type */
+	BOOTSTAGE_ID_DECOMP_IMAGE,	/* Decompressing image */
+	BOOTSTAGE_ID_KERNEL_LOADED,	/* Kernel has been loaded */
+	BOOTSTAGE_ID_DECOMP_UNIMPL = 7,	/* Odd decompression algorithm */
+	BOOTSTAGE_ID_CHECK_BOOT_OS,	/* Calling OS-specific boot function */
+	BOOTSTAGE_ID_BOOT_OS_RETURNED,	/* Tried to boot OS, but it returned */
+	BOOTSTAGE_ID_CHECK_RAMDISK = 9,	/* Checking ram disk */
+
+	BOOTSTAGE_ID_RD_MAGIC,		/* Checking ram disk magic */
+	BOOTSTAGE_ID_RD_HDR_CHECKSUM,	/* Checking ram disk heder checksum */
+	BOOTSTAGE_ID_RD_CHECKSUM,	/* Checking ram disk checksum */
+	BOOTSTAGE_ID_COPY_RAMDISK = 12,	/* Copying ram disk into place */
+	BOOTSTAGE_ID_RAMDISK,		/* Checking for valid ramdisk */
+	BOOTSTAGE_ID_NO_RAMDISK,	/* No ram disk found (not an error) */
+
+	BOOTSTAGE_ID_RUN_OS	= 15,	/* Exiting U-Boot, entering OS */
+
+	BOOTSTAGE_ID_NEED_RESET = 30,
+	BOOTSTAGE_ID_POST_FAIL,		/* Post failure */
+	BOOTSTAGE_ID_POST_FAIL_R,	/* Post failure reported after reloc */
+
+	/*
+	 * This set is reported only by x86, and the meaning is different. In
+	 * this case we are reporting completion of a particular stage.
+	 * This should probably change in the x86 code (which doesn't report
+	 * errors in any case), but discussion this can perhaps wait until we
+	 * have a generic board implementation.
+	 */
+	BOOTSTAGE_ID_BOARD_INIT_R,	/* We have relocated */
+	BOOTSTAGE_ID_BOARD_GLOBAL_DATA,	/* Global data is set up */
+
+	BOOTSTAGE_ID_BOARD_INIT_SEQ,	/* We completed the init sequence */
+	BOOTSTAGE_ID_BOARD_FLASH,	/* We have configured flash banks */
+	BOOTSTAGE_ID_BOARD_FLASH_37,	/* In case you didn't hear... */
+	BOOTSTAGE_ID_BOARD_ENV,		/* Environment is relocated & ready */
+	BOOTSTAGE_ID_BOARD_PCI,		/* PCI is up */
+
+	BOOTSTAGE_ID_BOARD_INTERRUPTS,	/* Exceptions / interrupts ready */
+	BOOTSTAGE_ID_BOARD_DONE,	/* Board init done, off to main loop */
+	/* ^^^ here ends the x86 sequence */
+
+	/* Boot stages related to loading a kernel from an IDE device */
+	BOOTSTAGE_ID_IDE_START = 41,
+	BOOTSTAGE_ID_IDE_ADDR,
+	BOOTSTAGE_ID_IDE_BOOT_DEVICE,
+	BOOTSTAGE_ID_IDE_TYPE,
+
+	BOOTSTAGE_ID_IDE_PART,
+	BOOTSTAGE_ID_IDE_PART_INFO,
+	BOOTSTAGE_ID_IDE_PART_TYPE,
+	BOOTSTAGE_ID_IDE_PART_READ,
+	BOOTSTAGE_ID_IDE_FORMAT,
+
+	BOOTSTAGE_ID_IDE_CHECKSUM,	/* 50 */
+	BOOTSTAGE_ID_IDE_READ,
+
+	/* Boot stages related to loading a kernel from an NAND device */
+	BOOTSTAGE_ID_NAND_PART,
+	BOOTSTAGE_ID_NAND_SUFFIX,
+	BOOTSTAGE_ID_NAND_BOOT_DEVICE,
+	BOOTSTAGE_ID_NAND_HDR_READ = 55,
+	BOOTSTAGE_ID_NAND_AVAILABLE = 55,
+	BOOTSTAGE_ID_NAND_TYPE = 57,
+	BOOTSTAGE_ID_NAND_READ,
+
+	/* Boot stages related to loading a kernel from an network device */
+	BOOTSTAGE_ID_NET_CHECKSUM = 60,
+	BOOTSTAGE_ID_NET_ETH_START = 64,
+	BOOTSTAGE_ID_NET_ETH_INIT,
+
+	BOOTSTAGE_ID_NET_START = 80,
+	BOOTSTAGE_ID_NET_NETLOOP_OK,
+	BOOTSTAGE_ID_NET_LOADED,
+	BOOTSTAGE_ID_NET_DONE_ERR,
+	BOOTSTAGE_ID_NET_DONE,
+
+	BOOTSTAGE_ID_FIT_FDT_START = 90,
+	/*
+	 * Boot stages related to loading a FIT image. Some of these are a
+	 * bit wonky.
+	 */
+	BOOTSTAGE_ID_FIT_KERNEL_START = 100,
+
+	BOOTSTAGE_ID_FIT_CONFIG = 110,
+	BOOTSTAGE_ID_FIT_TYPE,
+	BOOTSTAGE_ID_FIT_KERNEL_INFO,
+
+	BOOTSTAGE_ID_FIT_COMPRESSION,
+	BOOTSTAGE_ID_FIT_OS,
+	BOOTSTAGE_ID_FIT_LOADADDR,
+	BOOTSTAGE_ID_OVERWRITTEN,
+
+	/* Next 10 IDs used by BOOTSTAGE_SUB_... */
+	BOOTSTAGE_ID_FIT_RD_START = 120,	/* Ramdisk stages */
+
+	/* Next 10 IDs used by BOOTSTAGE_SUB_... */
+	BOOTSTAGE_ID_FIT_SETUP_START = 130,	/* x86 setup stages */
+
+	BOOTSTAGE_ID_IDE_FIT_READ = 140,
+	BOOTSTAGE_ID_IDE_FIT_READ_OK,
+
+	BOOTSTAGE_ID_NAND_FIT_READ = 150,
+	BOOTSTAGE_ID_NAND_FIT_READ_OK,
+
+	BOOTSTAGE_ID_FIT_LOADABLE_START = 160,	/* for Loadable Images */
+	/*
+	 * These boot stages are new, higher level, and not directly related
+	 * to the old boot progress numbers. They are useful for recording
+	 * rough boot timing information.
+	 */
+	BOOTSTAGE_ID_AWAKE,
+	BOOTSTAGE_ID_START_SPL,
+	BOOTSTAGE_ID_START_UBOOT_F,
+	BOOTSTAGE_ID_START_UBOOT_R,
+	BOOTSTAGE_ID_USB_START,
+	BOOTSTAGE_ID_ETH_START,
+	BOOTSTAGE_ID_BOOTP_START,
+	BOOTSTAGE_ID_BOOTP_STOP,
+	BOOTSTAGE_ID_BOOTM_START,
+	BOOTSTAGE_ID_BOOTM_HANDOFF,
+	BOOTSTAGE_ID_MAIN_LOOP,
+	BOOTSTAGE_KERNELREAD_START,
+	BOOTSTAGE_KERNELREAD_STOP,
+	BOOTSTAGE_ID_BOARD_INIT,
+	BOOTSTAGE_ID_BOARD_INIT_DONE,
+
+	BOOTSTAGE_ID_CPU_AWAKE,
+	BOOTSTAGE_ID_MAIN_CPU_AWAKE,
+	BOOTSTAGE_ID_MAIN_CPU_READY,
+
+	BOOTSTAGE_ID_ACCUM_LCD,
+	BOOTSTAGE_ID_ACCUM_SCSI,
+	BOOTSTAGE_ID_ACCUM_SPI,
+	BOOTSTAGE_ID_ACCUM_DECOMP,
+	BOOTSTAGE_ID_FPGA_INIT,
+
+	/* a few spare for the user, from here */
+	BOOTSTAGE_ID_USER,
+	BOOTSTAGE_ID_COUNT = BOOTSTAGE_ID_USER + CONFIG_BOOTSTAGE_USER_COUNT,
+	BOOTSTAGE_ID_ALLOC,
+};
+
+/*
+ * Return the time since boot in microseconds, This is needed for bootstage
+ * and should be defined in CPU- or board-specific code. If undefined then
+ * millisecond resolution will be used (the standard get_timer()).
+ */
+ulong timer_get_boot_us(void);
+
+#if defined(USE_HOSTCC)
+#define show_boot_progress(val) do {} while (0)
+#else
+/*
+ * Board code can implement show_boot_progress() if needed.
+ *
+ * @param val	Progress state (enum bootstage_id), or -id if an error
+ *		has occurred.
+ */
+void show_boot_progress(int val);
+#endif
+
+#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD) && \
+	!defined(USE_HOSTCC)
+/* This is the full bootstage implementation */
+
+/**
+ * Relocate existing bootstage records
+ *
+ * Call this after relocation has happened and after malloc has been initted.
+ * We need to copy any pointers in bootstage records that were added pre-
+ * relocation, since memory can be overritten later.
+ * @return Always returns 0, to indicate success
+ */
+int bootstage_relocate(void);
+
+/**
+ * Add a new bootstage record
+ *
+ * @param id	Bootstage ID to use (ignored if flags & BOOTSTAGEF_ALLOC)
+ * @param name	Name of record, or NULL for none
+ * @param flags	Flags (BOOTSTAGEF_...)
+ * @param mark	Time to record in this record, in microseconds
+ */
+ulong bootstage_add_record(enum bootstage_id id, const char *name,
+			   int flags, ulong mark);
+
+/*
+ * Mark a time stamp for the current boot stage.
+ */
+ulong bootstage_mark(enum bootstage_id id);
+
+ulong bootstage_error(enum bootstage_id id);
+
+ulong bootstage_mark_name(enum bootstage_id id, const char *name);
+
+/**
+ * Mark a time stamp in the given function and line number
+ *
+ * See BOOTSTAGE_MARKER() for a convenient macro.
+ *
+ * @param file		Filename to record (NULL if none)
+ * @param func		Function name to record
+ * @param linenum	Line number to record
+ * @return recorded time stamp
+ */
+ulong bootstage_mark_code(const char *file, const char *func,
+			  int linenum);
+
+/**
+ * Mark the start of a bootstage activity. The end will be marked later with
+ * bootstage_accum() and at that point we accumulate the time taken. Calling
+ * this function turns the given id into a accumulator rather than and
+ * absolute mark in time. Accumulators record the total amount of time spent
+ * in an activty during boot.
+ *
+ * @param id	Bootstage id to record this timestamp against
+ * @param name	Textual name to display for this id in the report (maybe NULL)
+ * @return start timestamp in microseconds
+ */
+uint32_t bootstage_start(enum bootstage_id id, const char *name);
+
+/**
+ * Mark the end of a bootstage activity
+ *
+ * After previously marking the start of an activity with bootstage_start(),
+ * call this function to mark the end. You can call these functions in pairs
+ * as many times as you like.
+ *
+ * @param id	Bootstage id to record this timestamp against
+ * @return time spent in this iteration of the activity (i.e. the time now
+ *		less the start time recorded in the last bootstage_start() call
+ *		with this id.
+ */
+uint32_t bootstage_accum(enum bootstage_id id);
+
+/* Print a report about boot time */
+void bootstage_report(void);
+
+/**
+ * Add bootstage information to the device tree
+ *
+ * @return 0 if ok, -ve on error
+ */
+int bootstage_fdt_add_report(void);
+
+/*
+ * Stash bootstage data into memory
+ *
+ * @param base	Base address of memory buffer
+ * @param size	Size of memory buffer
+ * @return 0 if stashed ok, -1 if out of space
+ */
+int bootstage_stash(void *base, int size);
+
+/**
+ * Read bootstage data from memory
+ *
+ * Bootstage data is read from memory and placed in the bootstage table
+ * in the user records.
+ *
+ * @param base	Base address of memory buffer
+ * @param size	Size of memory buffer (-1 if unknown)
+ * @return 0 if unstashed ok, -1 if bootstage info not found, or out of space
+ */
+int bootstage_unstash(void *base, int size);
+
+#else
+static inline ulong bootstage_add_record(enum bootstage_id id,
+		const char *name, int flags, ulong mark)
+{
+	return 0;
+}
+
+/*
+ * This is a dummy implementation which just calls show_boot_progress(),
+ * and won't even do that unless CONFIG_SHOW_BOOT_PROGRESS is defined
+ */
+
+static inline int bootstage_relocate(void)
+{
+	return 0;
+}
+
+static inline ulong bootstage_mark(enum bootstage_id id)
+{
+	show_boot_progress(id);
+	return 0;
+}
+
+static inline ulong bootstage_error(enum bootstage_id id)
+{
+	show_boot_progress(-id);
+	return 0;
+}
+
+static inline ulong bootstage_mark_name(enum bootstage_id id, const char *name)
+{
+	show_boot_progress(id);
+	return 0;
+}
+
+static inline ulong bootstage_mark_code(const char *file, const char *func,
+					int linenum)
+{
+	return 0;
+}
+
+static inline uint32_t bootstage_start(enum bootstage_id id, const char *name)
+{
+	return 0;
+}
+
+static inline uint32_t bootstage_accum(enum bootstage_id id)
+{
+	return 0;
+}
+
+static inline int bootstage_stash(void *base, int size)
+{
+	return 0;	/* Pretend to succeed */
+}
+
+static inline int bootstage_unstash(void *base, int size)
+{
+	return 0;	/* Pretend to succeed */
+}
+#endif /* CONFIG_BOOTSTAGE */
+
+/* Helper macro for adding a bootstage to a line of code */
+#define BOOTSTAGE_MARKER()	\
+		bootstage_mark_code(__FILE__, __func__, __LINE__)
+
+#endif

u-boot/include/bouncebuf.h

@@ -0,0 +1,72 @@
+/*
+ * Generic bounce buffer implementation
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __INCLUDE_BOUNCEBUF_H__
+#define __INCLUDE_BOUNCEBUF_H__
+
+#include <linux/types.h>
+
+/*
+ * GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware.
+ * The source buffer is copied into the bounce buffer (if unaligned, otherwise
+ * the source buffer is used directly) upon start() call, then the operation
+ * requiring the aligned transfer happens, then the bounce buffer is lost upon
+ * stop() call.
+ */
+#define GEN_BB_READ	(1 << 0)
+/*
+ * GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware.
+ * The source buffer starts in an undefined state upon start() call, then the
+ * operation requiring the aligned transfer happens, then the bounce buffer is
+ * copied into the destination buffer (if unaligned, otherwise destination
+ * buffer is used directly) upon stop() call.
+ */
+#define GEN_BB_WRITE	(1 << 1)
+/*
+ * GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware.
+ * The source buffer is copied into the bounce buffer (if unaligned, otherwise
+ * the source buffer is used directly) upon start() call, then the  operation
+ * requiring the aligned transfer happens, then the bounce buffer is  copied
+ * into the destination buffer (if unaligned, otherwise destination buffer is
+ * used directly) upon stop() call.
+ */
+#define GEN_BB_RW	(GEN_BB_READ | GEN_BB_WRITE)
+
+struct bounce_buffer {
+	/* Copy of data parameter passed to start() */
+	void *user_buffer;
+	/*
+	 * DMA-aligned buffer. This field is always set to the value that
+	 * should be used for DMA; either equal to .user_buffer, or to a
+	 * freshly allocated aligned buffer.
+	 */
+	void *bounce_buffer;
+	/* Copy of len parameter passed to start() */
+	size_t len;
+	/* DMA-aligned buffer length */
+	size_t len_aligned;
+	/* Copy of flags parameter passed to start() */
+	unsigned int flags;
+};
+
+/**
+ * bounce_buffer_start() -- Start the bounce buffer session
+ * state:	stores state passed between bounce_buffer_{start,stop}
+ * data:	pointer to buffer to be aligned
+ * len:		length of the buffer
+ * flags:	flags describing the transaction, see above.
+ */
+int bounce_buffer_start(struct bounce_buffer *state, void *data,
+			size_t len, unsigned int flags);
+/**
+ * bounce_buffer_stop() -- Finish the bounce buffer session
+ * state:	stores state passed between bounce_buffer_{start,stop}
+ */
+int bounce_buffer_stop(struct bounce_buffer *state);
+
+#endif

u-boot/include/bus_vcxk.h

@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2005-2009
+ * Jens Scharsig @ BuS Elektronik GmbH & Co. KG, <esw@bus-elektronik.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BUS_VCXK_H_
+#define __BUS_VCXK_H_
+
+extern int vcxk_init(unsigned long width, unsigned long height);
+extern void vcxk_setpixel(int x, int y, unsigned long color);
+extern int vcxk_acknowledge_wait(void);
+extern int vcxk_request(void);
+extern void vcxk_loadimage(ulong source);
+extern int vcxk_display_bitmap(ulong addr, int x, int y);
+extern void vcxk_setbrightness(unsigned int side, short brightness);
+extern int video_display_bitmap(ulong addr, int x, int y);
+
+#endif

u-boot/include/bzlib.h

@@ -0,0 +1,332 @@
+/*
+ * This file is a modified version of bzlib.h from the bzip2-1.0.2
+ * distribution which can be found at http://sources.redhat.com/bzip2/
+ */
+
+/*-------------------------------------------------------------*/
+/*--- Public header file for the library.                   ---*/
+/*---                                               bzlib.h ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+  This file is a part of bzip2 and/or libbzip2, a program and
+  library for lossless, block-sorting data compression.
+
+  Copyright (C) 1996-2002 Julian R Seward.  All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+  1. Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+  2. The origin of this software must not be misrepresented; you must
+     not claim that you wrote the original software.  If you use this
+     software in a product, an acknowledgment in the product
+     documentation would be appreciated but is not required.
+
+  3. Altered source versions must be plainly marked as such, and must
+     not be misrepresented as being the original software.
+
+  4. The name of the author may not be used to endorse or promote
+     products derived from this software without specific prior written
+     permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  Julian Seward, Cambridge, UK.
+  jseward@acm.org
+  bzip2/libbzip2 version 1.0 of 21 March 2000
+
+  This program is based on (at least) the work of:
+     Mike Burrows
+     David Wheeler
+     Peter Fenwick
+     Alistair Moffat
+     Radford Neal
+     Ian H. Witten
+     Robert Sedgewick
+     Jon L. Bentley
+
+  For more information on these sources, see the manual.
+--*/
+
+
+#ifndef _BZLIB_H
+#define _BZLIB_H
+
+/* Configure for U-Boot environment */
+#define BZ_NO_STDIO
+
+#ifndef CONFIG_SANDBOX
+#define BZ_NO_COMPRESS
+#endif
+/* End of configuration for U-Boot environment */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BZ_RUN               0
+#define BZ_FLUSH             1
+#define BZ_FINISH            2
+
+#define BZ_OK                0
+#define BZ_RUN_OK            1
+#define BZ_FLUSH_OK          2
+#define BZ_FINISH_OK         3
+#define BZ_STREAM_END        4
+#define BZ_SEQUENCE_ERROR    (-1)
+#define BZ_PARAM_ERROR       (-2)
+#define BZ_MEM_ERROR         (-3)
+#define BZ_DATA_ERROR        (-4)
+#define BZ_DATA_ERROR_MAGIC  (-5)
+#define BZ_IO_ERROR          (-6)
+#define BZ_UNEXPECTED_EOF    (-7)
+#define BZ_OUTBUFF_FULL      (-8)
+#define BZ_CONFIG_ERROR      (-9)
+
+typedef
+   struct {
+      char *next_in;
+      unsigned int avail_in;
+      unsigned int total_in_lo32;
+      unsigned int total_in_hi32;
+
+      char *next_out;
+      unsigned int avail_out;
+      unsigned int total_out_lo32;
+      unsigned int total_out_hi32;
+
+      void *state;
+
+      void *(*bzalloc)(void *,int,int);
+      void (*bzfree)(void *,void *);
+      void *opaque;
+   }
+   bz_stream;
+
+
+#ifndef BZ_IMPORT
+#define BZ_EXPORT
+#endif
+
+#ifdef _WIN32
+#   include <windows.h>
+#   ifdef small
+      /* windows.h define small to char */
+#      undef small
+#   endif
+#   ifdef BZ_EXPORT
+#   define BZ_API(func) WINAPI func
+#   define BZ_EXTERN extern
+#   else
+   /* import windows dll dynamically */
+#   define BZ_API(func) (WINAPI * func)
+#   define BZ_EXTERN
+#   endif
+#else
+#   define BZ_API(func) func
+#   define BZ_EXTERN extern
+#endif
+
+
+/*-- Core (low-level) library functions --*/
+
+BZ_EXTERN int BZ_API(BZ2_bzCompressInit) (
+      bz_stream* strm,
+      int        blockSize100k,
+      int        verbosity,
+      int        workFactor
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzCompress) (
+      bz_stream* strm,
+      int action
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzCompressEnd) (
+      bz_stream* strm
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompressInit) (
+      bz_stream *strm,
+      int       verbosity,
+      int       small
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompress) (
+      bz_stream* strm
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) (
+      bz_stream *strm
+   );
+
+
+/*-- High(er) level library functions --*/
+
+#ifndef BZ_NO_STDIO
+#define BZ_MAX_UNUSED 5000
+
+/* Need a definitition for FILE */
+#include <stdio.h>
+
+typedef void BZFILE;
+
+BZ_EXTERN BZFILE* BZ_API(BZ2_bzReadOpen) (
+      int*  bzerror,
+      FILE* f,
+      int   verbosity,
+      int   small,
+      void* unused,
+      int   nUnused
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzReadClose) (
+      int*    bzerror,
+      BZFILE* b
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzReadGetUnused) (
+      int*    bzerror,
+      BZFILE* b,
+      void**  unused,
+      int*    nUnused
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzRead) (
+      int*    bzerror,
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN BZFILE* BZ_API(BZ2_bzWriteOpen) (
+      int*  bzerror,
+      FILE* f,
+      int   blockSize100k,
+      int   verbosity,
+      int   workFactor
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWrite) (
+      int*    bzerror,
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWriteClose) (
+      int*          bzerror,
+      BZFILE*       b,
+      int           abandon,
+      unsigned int* nbytes_in,
+      unsigned int* nbytes_out
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWriteClose64) (
+      int*          bzerror,
+      BZFILE*       b,
+      int           abandon,
+      unsigned int* nbytes_in_lo32,
+      unsigned int* nbytes_in_hi32,
+      unsigned int* nbytes_out_lo32,
+      unsigned int* nbytes_out_hi32
+   );
+#endif
+
+
+/*-- Utility functions --*/
+
+BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffCompress) (
+      char*         dest,
+      unsigned int* destLen,
+      char*         source,
+      unsigned int  sourceLen,
+      int           blockSize100k,
+      int           verbosity,
+      int           workFactor
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffDecompress) (
+      char*         dest,
+      unsigned int* destLen,
+      char*         source,
+      unsigned int  sourceLen,
+      int           small,
+      int           verbosity
+   );
+
+
+/*--
+   Code contributed by Yoshioka Tsuneo
+   (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp),
+   to support better zlib compatibility.
+   This code is not _officially_ part of libbzip2 (yet);
+   I haven't tested it, documented it, or considered the
+   threading-safeness of it.
+   If this code breaks, please contact both Yoshioka and me.
+--*/
+
+BZ_EXTERN const char * BZ_API(BZ2_bzlibVersion) (
+      void
+   );
+
+#ifndef BZ_NO_STDIO
+BZ_EXTERN BZFILE * BZ_API(BZ2_bzopen) (
+      const char *path,
+      const char *mode
+   );
+
+BZ_EXTERN BZFILE * BZ_API(BZ2_bzdopen) (
+      int        fd,
+      const char *mode
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzread) (
+      BZFILE* b,
+      void* buf,
+      int len
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzwrite) (
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzflush) (
+      BZFILE* b
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzclose) (
+      BZFILE* b
+   );
+
+BZ_EXTERN const char * BZ_API(BZ2_bzerror) (
+      BZFILE *b,
+      int    *errnum
+   );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*-------------------------------------------------------------*/
+/*--- end                                           bzlib.h ---*/
+/*-------------------------------------------------------------*/

u-boot/include/cavium/atf.h

@@ -0,0 +1,22 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+**/
+#ifndef __ATF_H__
+#define __ATF_H__
+#include <cavium/atf_part.h>
+
+ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size);
+ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size);
+ssize_t atf_get_pcount(void);
+ssize_t atf_get_part(struct storage_partition *part, unsigned int index);
+ssize_t atf_erase_nor(uintptr_t offset, size_t size);
+ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size);
+ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size);
+ssize_t atf_dram_size(unsigned int node);
+ssize_t atf_node_count(void);
+ssize_t atf_env_count(void);
+ssize_t atf_env_string(size_t index, char *str);
+
+#endif

u-boot/include/cavium/atf_part.h

@@ -0,0 +1,26 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+**/
+
+#ifndef __ATF_PART_H__
+#define __ATF_PART_H__
+
+struct storage_partition {
+	unsigned int type;
+	unsigned int size;
+	unsigned long offset;
+};
+
+enum {
+	PARTITION_NBL1FW_REST = 0,
+	PARTITION_BL2_BL31 = 1,
+	PARTITION_UBOOT = 2,
+	PARTITION_UEFI = 2,
+	PARTITION_KERNEL = 3,
+	PARTITION_DEVICE_TREE = 4,
+	PARTITION_LAST,
+};
+
+#endif

u-boot/include/cavium/thunderx_svc.h

@@ -0,0 +1,67 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+**/
+
+#ifndef __THUNDERX_SVC_H__
+#define __THUNDERX_SVC_H__
+
+/* SMC function IDs for general purpose queries */
+
+#define THUNDERX_SVC_CALL_COUNT		0x4300ff00
+#define THUNDERX_SVC_UID		0x4300ff01
+
+#define THUNDERX_SVC_VERSION		0x4300ff03
+
+#define ARM_STD_SVC_VERSION		0x8400ff03
+
+/* ThunderX Service Calls version numbers */
+#define THUNDERX_VERSION_MAJOR	0x0
+#define THUNDERX_VERSION_MINOR	0x1
+
+#define THUNDERX_MMC_READ		0x43000101
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_MMC_WRITE		0x43000102
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+
+#define THUNDERX_NOR_READ		0x43000111
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_NOR_WRITE		0x43000112
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_NOR_ERASE		0x43000113
+/* x1 - block address
+ */
+
+#define THUNDERX_PART_COUNT		0x43000201
+#define THUNDERX_GET_PART		0x43000202
+/* x1 - pointer to the buffer
+ * x2 - index
+ */
+
+#define THUNDERX_DRAM_SIZE		0x43000301
+/* x1 - node number
+ */
+
+#define THUNDERX_GTI_SYNC		0x43000401
+
+#define THUNDERX_ENV_COUNT		0x43000501
+#define THUNDERX_ENV_STRING		0x43000502
+/* x1 - index
+ */
+
+#define THUNDERX_NODE_COUNT		0x43000601
+
+#endif /* __THUNDERX_SVC_H__ */

u-boot/include/cbfs.h

@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CBFS_H
+#define __CBFS_H
+
+#include <compiler.h>
+#include <linux/compiler.h>
+
+enum cbfs_result {
+	CBFS_SUCCESS = 0,
+	CBFS_NOT_INITIALIZED,
+	CBFS_BAD_HEADER,
+	CBFS_BAD_FILE,
+	CBFS_FILE_NOT_FOUND
+};
+
+enum cbfs_filetype {
+	CBFS_TYPE_STAGE = 0x10,
+	CBFS_TYPE_PAYLOAD = 0x20,
+	CBFS_TYPE_OPTIONROM = 0x30,
+	CBFS_TYPE_BOOTSPLASH = 0x40,
+	CBFS_TYPE_RAW = 0x50,
+	CBFS_TYPE_VSA = 0x51,
+	CBFS_TYPE_MBI = 0x52,
+	CBFS_TYPE_MICROCODE = 0x53,
+	CBFS_COMPONENT_CMOS_DEFAULT = 0xaa,
+	CBFS_COMPONENT_CMOS_LAYOUT = 0x01aa
+};
+
+struct cbfs_header {
+	u32 magic;
+	u32 version;
+	u32 rom_size;
+	u32 boot_block_size;
+	u32 align;
+	u32 offset;
+	u32 pad[2];
+} __packed;
+
+struct cbfs_fileheader {
+	u8 magic[8];
+	u32 len;
+	u32 type;
+	u32 checksum;
+	u32 offset;
+} __packed;
+
+struct cbfs_cachenode {
+	struct cbfs_cachenode *next;
+	u32 type;
+	void *data;
+	u32 data_length;
+	char *name;
+	u32 name_length;
+	u32 checksum;
+} __packed;
+
+extern enum cbfs_result file_cbfs_result;
+
+/**
+ * file_cbfs_error() - Return a string describing the most recent error
+ * condition.
+ *
+ * @return A pointer to the constant string.
+ */
+const char *file_cbfs_error(void);
+
+/**
+ * file_cbfs_init() - Initialize the CBFS driver and load metadata into RAM.
+ *
+ * @end_of_rom: Points to the end of the ROM the CBFS should be read
+ *                      from.
+ */
+void file_cbfs_init(uintptr_t end_of_rom);
+
+/**
+ * file_cbfs_get_header() - Get the header structure for the current CBFS.
+ *
+ * @return A pointer to the constant structure, or NULL if there is none.
+ */
+const struct cbfs_header *file_cbfs_get_header(void);
+
+/**
+ * file_cbfs_get_first() - Get a handle for the first file in CBFS.
+ *
+ * @return A handle for the first file in CBFS, NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_get_first(void);
+
+/**
+ * file_cbfs_get_next() - Get a handle to the file after this one in CBFS.
+ *
+ * @file:		A pointer to the handle to advance.
+ */
+void file_cbfs_get_next(const struct cbfs_cachenode **file);
+
+/**
+ * file_cbfs_find() - Find a file with a particular name in CBFS.
+ *
+ * @name:		The name to search for.
+ *
+ * @return A handle to the file, or NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_find(const char *name);
+
+
+/***************************************************************************/
+/* All of the functions below can be used without first initializing CBFS. */
+/***************************************************************************/
+
+/**
+ * file_cbfs_find_uncached() - Find a file with a particular name in CBFS
+ * without using the heap.
+ *
+ * @end_of_rom:		Points to the end of the ROM the CBFS should be read
+ *                      from.
+ * @name:		The name to search for.
+ *
+ * @return A handle to the file, or NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom,
+						     const char *name);
+
+/**
+ * file_cbfs_name() - Get the name of a file in CBFS.
+ *
+ * @file:		The handle to the file.
+ *
+ * @return The name of the file, NULL on error.
+ */
+const char *file_cbfs_name(const struct cbfs_cachenode *file);
+
+/**
+ * file_cbfs_size() - Get the size of a file in CBFS.
+ *
+ * @file:		The handle to the file.
+ *
+ * @return The size of the file, zero on error.
+ */
+u32 file_cbfs_size(const struct cbfs_cachenode *file);
+
+/**
+ * file_cbfs_type() - Get the type of a file in CBFS.
+ *
+ * @file:		The handle to the file.
+ *
+ * @return The type of the file, zero on error.
+ */
+u32 file_cbfs_type(const struct cbfs_cachenode *file);
+
+/**
+ * file_cbfs_read() - Read a file from CBFS into RAM
+ *
+ * @file:		A handle to the file to read.
+ * @buffer:		Where to read it into memory.
+ * @maxsize:		Maximum number of bytes to read
+ *
+ * @return If positive or zero, the number of characters read. If negative, an
+ *	   error occurred.
+ */
+long file_cbfs_read(const struct cbfs_cachenode *file, void *buffer,
+		    unsigned long maxsize);
+
+#endif /* __CBFS_H */

u-boot/include/circbuf.h

@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CIRCBUF_H__
+#define __CIRCBUF_H__
+
+typedef struct circbuf {
+	unsigned int size;	/* current number of bytes held */
+	unsigned int totalsize; /* number of bytes allocated */
+
+	char *top;		/* pointer to current buffer start */
+	char *tail;		/* pointer to space for next element */
+
+	char *data;		/* all data */
+	char *end;		/* end of data buffer */
+} circbuf_t;
+
+int buf_init (circbuf_t * buf, unsigned int size);
+int buf_free (circbuf_t * buf);
+int buf_pop (circbuf_t * buf, char *dest, unsigned int len);
+int buf_push (circbuf_t * buf, const char *src, unsigned int len);
+
+#endif

u-boot/include/cli.h

@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2014 Google, Inc
+ * Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CLI_H
+#define __CLI_H
+
+/**
+ * Go into the command loop
+ *
+ * This will return if we get a timeout waiting for a command. See
+ * CONFIG_BOOT_RETRY_TIME.
+ */
+void cli_simple_loop(void);
+
+/**
+ * cli_simple_run_command() - Execute a command with the simple CLI
+ *
+ * @cmd:	String containing the command to execute
+ * @flag	Flag value - see CMD_FLAG_...
+ * @return 1  - command executed, repeatable
+ *	0  - command executed but not repeatable, interrupted commands are
+ *	     always considered not repeatable
+ *	-1 - not executed (unrecognized, bootd recursion or too many args)
+ *           (If cmd is NULL or "" or longer than CONFIG_SYS_CBSIZE-1 it is
+ *           considered unrecognized)
+ */
+int cli_simple_run_command(const char *cmd, int flag);
+
+/**
+ * cli_simple_process_macros() - Expand $() and ${} format env. variables
+ *
+ * @param input		Input string possible containing $() / ${} vars
+ * @param output	Output string with $() / ${} vars expanded
+ */
+void cli_simple_process_macros(const char *input, char *output);
+
+/**
+ * cli_simple_run_command_list() - Execute a list of command
+ *
+ * The commands should be separated by ; or \n and will be executed
+ * by the built-in parser.
+ *
+ * This function cannot take a const char * for the command, since if it
+ * finds newlines in the string, it replaces them with \0.
+ *
+ * @param cmd	String containing list of commands
+ * @param flag	Execution flags (CMD_FLAG_...)
+ * @return 0 on success, or != 0 on error.
+ */
+int cli_simple_run_command_list(char *cmd, int flag);
+
+/**
+ * cli_readline() - read a line into the console_buffer
+ *
+ * This is a convenience function which calls cli_readline_into_buffer().
+ *
+ * @prompt: Prompt to display
+ * @return command line length excluding terminator, or -ve on error
+ */
+int cli_readline(const char *const prompt);
+
+/**
+ * readline_into_buffer() - read a line into a buffer
+ *
+ * Display the prompt, then read a command line into @buffer. The
+ * maximum line length is CONFIG_SYS_CBSIZE including a \0 terminator, which
+ * will always be added.
+ *
+ * The command is echoed as it is typed. Command editing is supported if
+ * CONFIG_CMDLINE_EDITING is defined. Tab auto-complete is supported if
+ * CONFIG_AUTO_COMPLETE is defined. If CONFIG_BOOT_RETRY_TIME is defined,
+ * then a timeout will be applied.
+ *
+ * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0,
+ * time out when time goes past endtime (timebase time in ticks).
+ *
+ * @prompt:	Prompt to display
+ * @buffer:	Place to put the line that is entered
+ * @timeout:	Timeout in milliseconds, 0 if none
+ * @return command line length excluding terminator, or -ve on error: of the
+ * timeout is exceeded (either CONFIG_BOOT_RETRY_TIME or the timeout
+ * parameter), then -2 is returned. If a break is detected (Ctrl-C) then
+ * -1 is returned.
+ */
+int cli_readline_into_buffer(const char *const prompt, char *buffer,
+				int timeout);
+
+/**
+ * parse_line() - split a command line down into separate arguments
+ *
+ * The argv[] array is filled with pointers into @line, and each argument
+ * is terminated by \0 (i.e. @line is changed in the process unless there
+ * is only one argument).
+ *
+ * #argv is terminated by a NULL after the last argument pointer.
+ *
+ * At most CONFIG_SYS_MAXARGS arguments are permited - if there are more
+ * than that then an error is printed, and this function returns
+ * CONFIG_SYS_MAXARGS, with argv[] set up to that point.
+ *
+ * @line:	Command line to parse
+ * @args:	Array to hold arguments
+ * @return number of arguments
+ */
+int cli_simple_parse_line(char *line, char *argv[]);
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+/**
+ * cli_process_fdt() - process the boot command from the FDT
+ *
+ * If bootcmmd is defined in the /config node of the FDT, we use that
+ * as the boot command. Further, if bootsecure is set to 1 (in the same
+ * node) then we return true, indicating that the command should be executed
+ * as securely as possible, avoiding the CLI parser.
+ *
+ * @cmdp:	On entry, the command that will be executed if the FDT does
+ *		not have a command. Returns the command to execute after
+ *		checking the FDT.
+ * @return true to execute securely, else false
+ */
+bool cli_process_fdt(const char **cmdp);
+
+/** cli_secure_boot_cmd() - execute a command as securely as possible
+ *
+ * This avoids using the parser, thus executing the command with the
+ * smallest amount of code. Parameters are not supported.
+ */
+void cli_secure_boot_cmd(const char *cmd);
+#else
+static inline bool cli_process_fdt(const char **cmdp)
+{
+	return false;
+}
+
+static inline void cli_secure_boot_cmd(const char *cmd)
+{
+}
+#endif /* CONFIG_OF_CONTROL */
+
+/**
+ * Go into the command loop
+ *
+ * This will return if we get a timeout waiting for a command, but only for
+ * the simple parser (not hush). See CONFIG_BOOT_RETRY_TIME.
+ */
+void cli_loop(void);
+
+/** Set up the command line interpreter ready for action */
+void cli_init(void);
+
+#define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk())
+
+#endif

u-boot/include/cli_hush.h

@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CLI_HUSH_H_
+#define _CLI_HUSH_H_
+
+#define FLAG_EXIT_FROM_LOOP 1
+#define FLAG_PARSE_SEMICOLON (1 << 1)	  /* symbol ';' is special for parser */
+#define FLAG_REPARSING       (1 << 2)	  /* >=2nd pass */
+#define FLAG_CONT_ON_NEWLINE (1 << 3)	  /* continue when we see \n */
+
+extern int u_boot_hush_start(void);
+extern int parse_string_outer(const char *, int);
+extern int parse_file_outer(void);
+
+int set_local_var(const char *s, int flg_export);
+void unset_local_var(const char *name);
+char *get_local_var(const char *s);
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+extern int hush_init_var (void);
+#endif
+#endif

u-boot/include/clk-uclass.h

@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CLK_UCLASS_H
+#define _CLK_UCLASS_H
+
+/* See clk.h for background documentation. */
+
+#include <clk.h>
+#include <fdtdec.h>
+
+/**
+ * struct clk_ops - The functions that a clock driver must implement.
+ */
+struct clk_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) clock specifier.
+	 *
+	 * The clock core calls this function as the first step in implementing
+	 * a client's clk_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the clock core will use a
+	 * default implementation, which assumes #clock-cells = <1>, and that
+	 * the DT cell contains a simple integer clock ID.
+	 *
+	 * At present, the clock API solely supports device-tree. If this
+	 * changes, other xxx_xlate() functions may be added to support those
+	 * other mechanisms.
+	 *
+	 * @clock:	The clock struct to hold the translation result.
+	 * @args:	The clock specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct clk *clock,
+			struct fdtdec_phandle_args *args);
+	/**
+	 * request - Request a translated clock.
+	 *
+	 * The clock core calls this function as the second step in
+	 * implementing a client's clk_get_by_*() call, following a successful
+	 * xxx_xlate() call, or as the only step in implementing a client's
+	 * clk_request() call.
+	 *
+	 * @clock:	The clock struct to request; this has been fille in by
+	 *		a previoux xxx_xlate() function call, or by the caller
+	 *		of clk_request().
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct clk *clock);
+	/**
+	 * free - Free a previously requested clock.
+	 *
+	 * This is the implementation of the client clk_free() API.
+	 *
+	 * @clock:	The clock to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct clk *clock);
+	/**
+	 * get_rate() - Get current clock rate.
+	 *
+	 * @clk:	The clock to query.
+	 * @return clock rate in Hz, or -ve error code
+	 */
+	ulong (*get_rate)(struct clk *clk);
+	/**
+	 * set_rate() - Set current clock rate.
+	 *
+	 * @clk:	The clock to manipulate.
+	 * @rate:	New clock rate in Hz.
+	 * @return new rate, or -ve error code.
+	 */
+	ulong (*set_rate)(struct clk *clk, ulong rate);
+	/**
+	 * enable() - Enable a clock.
+	 *
+	 * @clk:	The clock to manipulate.
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*enable)(struct clk *clk);
+	/**
+	 * disable() - Disable a clock.
+	 *
+	 * @clk:	The clock to manipulate.
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*disable)(struct clk *clk);
+};
+
+#endif

u-boot/include/clk.h

@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CLK_H_
+#define _CLK_H_
+
+#include <linux/types.h>
+
+/**
+ * A clock is a hardware signal that oscillates autonomously at a specific
+ * frequency and duty cycle. Most hardware modules require one or more clock
+ * signal to drive their operation. Clock signals are typically generated
+ * externally to the HW module consuming them, by an entity this API calls a
+ * clock provider. This API provides a standard means for drivers to enable and
+ * disable clocks, and to set the rate at which they oscillate.
+ *
+ * A driver that implements UCLASS_CLOCK is a clock provider. A provider will
+ * often implement multiple separate clocks, since the hardware it manages
+ * often has this capability. clock_uclass.h describes the interface which
+ * clock providers must implement.
+ *
+ * Clock consumers/clients are the HW modules driven by the clock signals. This
+ * header file describes the API used by drivers for those HW modules.
+ */
+
+struct udevice;
+
+/**
+ * struct clk - A handle to (allowing control of) a single clock.
+ *
+ * Clients provide storage for clock handles. The content of the structure is
+ * managed solely by the clock API and clock drivers. A clock struct is
+ * initialized by "get"ing the clock struct. The clock struct is passed to all
+ * other clock APIs to identify which clock signal to operate upon.
+ *
+ * @dev: The device which implements the clock signal.
+ * @id: The clock signal ID within the provider.
+ *
+ * Currently, the clock API assumes that a single integer ID is enough to
+ * identify and configure any clock signal for any clock provider. If this
+ * assumption becomes invalid in the future, the struct could be expanded to
+ * either (a) add more fields to allow clock providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct clk {
+	struct udevice *dev;
+	/*
+	 * Written by of_xlate. We assume a single id is enough for now. In the
+	 * future, we might add more fields here.
+	 */
+	unsigned long id;
+};
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+/**
+ * clock_get_by_index - Get/request a clock by integer index.
+ *
+ * This looks up and requests a clock. The index is relative to the client
+ * device; each device is assumed to have n clocks associated with it somehow,
+ * and this function finds and requests one of them. The mapping of client
+ * device clock indices to provider clocks may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the clock to request, within the client's list of
+ *		clocks.
+ * @clock	A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
+
+/**
+ * clock_get_by_name - Get/request a clock by name.
+ *
+ * This looks up and requests a clock. The name is relative to the client
+ * device; each device is assumed to have n clocks associated with it somehow,
+ * and this function finds and requests one of them. The mapping of client
+ * device clock names to provider clocks may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the clock to request, within the client's list of
+ *		clocks.
+ * @clock:	A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk);
+#else
+static inline int clk_get_by_index(struct udevice *dev, int index,
+				   struct clk *clk)
+{
+	return -ENOSYS;
+}
+
+static int clk_get_by_name(struct udevice *dev, const char *name,
+			   struct clk *clk)
+{
+	return -ENOSYS;
+}
+#endif
+
+/**
+ * clk_request - Request a clock by provider-specific ID.
+ *
+ * This requests a clock using a provider-specific ID. Generally, this function
+ * should not be used, since clk_get_by_index/name() provide an interface that
+ * better separates clients from intimate knowledge of clock providers.
+ * However, this function may be useful in core SoC-specific code.
+ *
+ * @dev:	The clock provider device.
+ * @clock:	A pointer to a clock struct to initialize. The caller must
+ *		have already initialized any field in this struct which the
+ *		clock provider uses to identify the clock.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_request(struct udevice *dev, struct clk *clk);
+
+/**
+ * clock_free - Free a previously requested clock.
+ *
+ * @clock:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_free(struct clk *clk);
+
+/**
+ * clk_get_rate() - Get current clock rate.
+ *
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return clock rate in Hz, or -ve error code.
+ */
+ulong clk_get_rate(struct clk *clk);
+
+/**
+ * clk_set_rate() - Set current clock rate.
+ *
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @rate:	New clock rate in Hz.
+ * @return new rate, or -ve error code.
+ */
+ulong clk_set_rate(struct clk *clk, ulong rate);
+
+/**
+ * clk_enable() - Enable (turn on) a clock.
+ *
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return zero on success, or -ve error code.
+ */
+int clk_enable(struct clk *clk);
+
+/**
+ * clk_disable() - Disable (turn off) a clock.
+ *
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return zero on success, or -ve error code.
+ */
+int clk_disable(struct clk *clk);
+
+int soc_clk_dump(void);
+
+#endif

u-boot/include/cmd_spl.h

@@ -0,0 +1,15 @@
+/* Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _NAND_SPL_H_
+#define	_NAND_SPL_H_
+
+#define SPL_EXPORT	(0x00000001)
+
+#define SPL_EXPORT_FDT		(0x00000001)
+#define SPL_EXPORT_ATAGS	(0x00000002)
+#define SPL_EXPORT_LAST		SPL_EXPORT_ATAGS
+
+#endif /* _NAND_SPL_H_ */

u-boot/include/command.h

@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *  Definitions for Command Processor
+ */
+#ifndef __COMMAND_H
+#define __COMMAND_H
+
+#include <linker_lists.h>
+
+#ifndef NULL
+#define NULL	0
+#endif
+
+/* Default to a width of 8 characters for help message command width */
+#ifndef CONFIG_SYS_HELP_CMD_WIDTH
+#define CONFIG_SYS_HELP_CMD_WIDTH	8
+#endif
+
+#ifndef	__ASSEMBLY__
+/*
+ * Monitor Command Table
+ */
+
+struct cmd_tbl_s {
+	char		*name;		/* Command Name			*/
+	int		maxargs;	/* maximum number of arguments	*/
+	int		repeatable;	/* autorepeat allowed?		*/
+					/* Implementation function	*/
+	int		(*cmd)(struct cmd_tbl_s *, int, int, char * const []);
+	char		*usage;		/* Usage message	(short)	*/
+#ifdef	CONFIG_SYS_LONGHELP
+	char		*help;		/* Help  message	(long)	*/
+#endif
+#ifdef CONFIG_AUTO_COMPLETE
+	/* do auto completion on the arguments */
+	int		(*complete)(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]);
+#endif
+};
+
+typedef struct cmd_tbl_s	cmd_tbl_t;
+
+
+#if defined(CONFIG_CMD_RUN)
+extern int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif
+
+/* common/command.c */
+int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
+	      flag, int argc, char * const argv[]);
+cmd_tbl_t *find_cmd(const char *cmd);
+cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len);
+
+extern int cmd_usage(const cmd_tbl_t *cmdtp);
+
+#ifdef CONFIG_AUTO_COMPLETE
+extern int var_complete(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]);
+extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp);
+#endif
+
+/**
+ * cmd_process_error() - report and process a possible error
+ *
+ * @cmdtp: Command which caused the error
+ * @err: Error code (0 if none, -ve for error, like -EIO)
+ * @return 0 if there is not error, 1 (CMD_RET_FAILURE) if an error is found
+ */
+int cmd_process_error(cmd_tbl_t *cmdtp, int err);
+
+/*
+ * Monitor Command
+ *
+ * All commands use a common argument format:
+ *
+ * void function (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+ */
+
+#if defined(CONFIG_CMD_MEMORY)		\
+	|| defined(CONFIG_CMD_I2C)	\
+	|| defined(CONFIG_CMD_ITEST)	\
+	|| defined(CONFIG_CMD_PCI)	\
+	|| defined(CONFIG_CMD_PORTIO)
+#define CMD_DATA_SIZE
+extern int cmd_get_data_size(char* arg, int default_size);
+#endif
+
+#ifdef CONFIG_CMD_BOOTD
+extern int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif
+#ifdef CONFIG_CMD_BOOTM
+extern int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd);
+#else
+static inline int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd)
+{
+	return 0;
+}
+#endif
+
+extern int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+extern int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+extern int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
+			   char *const argv[]);
+
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+/*
+ * Error codes that commands return to cmd_process(). We use the standard 0
+ * and 1 for success and failure, but add one more case - failure with a
+ * request to call cmd_usage(). But the cmd_process() function handles
+ * CMD_RET_USAGE itself and after calling cmd_usage() it will return 1.
+ * This is just a convenience for commands to avoid them having to call
+ * cmd_usage() all over the place.
+ */
+enum command_ret_t {
+	CMD_RET_SUCCESS,	/* 0 = Success */
+	CMD_RET_FAILURE,	/* 1 = Failure */
+	CMD_RET_USAGE = -1,	/* Failure, please report 'usage' error */
+};
+
+/**
+ * Process a command with arguments. We look up the command and execute it
+ * if valid. Otherwise we print a usage message.
+ *
+ * @param flag		Some flags normally 0 (see CMD_FLAG_.. above)
+ * @param argc		Number of arguments (arg 0 must be the command text)
+ * @param argv		Arguments
+ * @param repeatable	This function sets this to 0 if the command is not
+ *			repeatable. If the command is repeatable, the value
+ *			is left unchanged.
+ * @param ticks		If ticks is not null, this function set it to the
+ *			number of ticks the command took to complete.
+ * @return 0 if the command succeeded, 1 if it failed
+ */
+int cmd_process(int flag, int argc, char * const argv[],
+			       int *repeatable, unsigned long *ticks);
+
+void fixup_cmdtable(cmd_tbl_t *cmdtp, int size);
+
+/**
+ * board_run_command() - Fallback function to execute a command
+ *
+ * When no command line features are enabled in U-Boot, this function is
+ * called to execute a command. Typically the function can look at the
+ * command and perform a few very specific tasks, such as booting the
+ * system in a particular way.
+ *
+ * This function is only used when CONFIG_CMDLINE is not enabled.
+ *
+ * In normal situations this function should not return, since U-Boot will
+ * simply hang.
+ *
+ * @cmdline:	Command line string to execute
+ * @return 0 if OK, 1 for error
+ */
+int board_run_command(const char *cmdline);
+#endif	/* __ASSEMBLY__ */
+
+/*
+ * Command Flags:
+ */
+#define CMD_FLAG_REPEAT		0x0001	/* repeat last command		*/
+#define CMD_FLAG_BOOTD		0x0002	/* command is from bootd	*/
+#define CMD_FLAG_ENV		0x0004	/* command is from the environment */
+
+#ifdef CONFIG_AUTO_COMPLETE
+# define _CMD_COMPLETE(x) x,
+#else
+# define _CMD_COMPLETE(x)
+#endif
+#ifdef CONFIG_SYS_LONGHELP
+# define _CMD_HELP(x) x,
+#else
+# define _CMD_HELP(x)
+#endif
+
+#ifdef CONFIG_CMDLINE
+#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd,		\
+				_usage, _help, _comp)			\
+		{ #_name, _maxargs, _rep, _cmd, _usage,			\
+			_CMD_HELP(_help) _CMD_COMPLETE(_comp) }
+
+#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \
+	ll_entry_declare(cmd_tbl_t, _name, cmd) =			\
+		U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd,	\
+						_usage, _help, _comp);
+
+#else
+#define U_BOOT_SUBCMD_START(name)	static cmd_tbl_t name[] = {};
+#define U_BOOT_SUBCMD_END
+
+#define _CMD_REMOVE(_name, _cmd)					\
+	int __remove_ ## _name(void)					\
+	{								\
+		if (0)							\
+			_cmd(NULL, 0, 0, NULL);				\
+		return 0;						\
+	}
+#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, _usage,	\
+				  _help, _comp)				\
+		{ #_name, _maxargs, _rep, 0 ? _cmd : NULL, _usage,	\
+			_CMD_HELP(_help) _CMD_COMPLETE(_comp) }
+
+#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help,	\
+			    _comp)				\
+	_CMD_REMOVE(sub_ ## _name, _cmd)
+
+#endif /* CONFIG_CMDLINE */
+
+#define U_BOOT_CMD(_name, _maxargs, _rep, _cmd, _usage, _help)		\
+	U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, NULL)
+
+#define U_BOOT_CMD_MKENT(_name, _maxargs, _rep, _cmd, _usage, _help)	\
+	U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd,		\
+					_usage, _help, NULL)
+
+#endif	/* __COMMAND_H */

u-boot/include/common.h

@@ -0,0 +1,973 @@
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __COMMON_H_
+#define __COMMON_H_	1
+
+#ifndef __ASSEMBLY__		/* put C only stuff in this section */
+
+typedef unsigned char		uchar;
+typedef volatile unsigned long	vu_long;
+typedef volatile unsigned short vu_short;
+typedef volatile unsigned char	vu_char;
+
+#include <config.h>
+#include <errno.h>
+#include <asm-offsets.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/stringify.h>
+#include <asm/ptrace.h>
+#include <stdarg.h>
+#include <linux/kernel.h>
+#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
+#include <pci.h>
+#endif
+#if defined(CONFIG_8xx)
+#include <asm/8xx_immap.h>
+#if defined(CONFIG_MPC859)	|| defined(CONFIG_MPC859T)	|| \
+    defined(CONFIG_MPC866)	|| \
+    defined(CONFIG_MPC866P)
+# define CONFIG_MPC866_FAMILY 1
+#elif defined(CONFIG_MPC885)
+# define CONFIG_MPC885_FAMILY   1
+#endif
+#if   defined(CONFIG_MPC860)	   \
+   || defined(CONFIG_MPC860T)	   \
+   || defined(CONFIG_MPC866_FAMILY) \
+   || defined(CONFIG_MPC885_FAMILY)
+# define CONFIG_MPC86x 1
+#endif
+#elif defined(CONFIG_5xx)
+#include <asm/5xx_immap.h>
+#elif defined(CONFIG_MPC5xxx)
+#include <mpc5xxx.h>
+#elif defined(CONFIG_MPC512X)
+#include <asm/immap_512x.h>
+#elif defined(CONFIG_MPC8260)
+#if   defined(CONFIG_MPC8247) \
+   || defined(CONFIG_MPC8272)
+#define CONFIG_MPC8272_FAMILY	1
+#endif
+#include <asm/immap_8260.h>
+#endif
+#ifdef CONFIG_MPC86xx
+#include <mpc86xx.h>
+#include <asm/immap_86xx.h>
+#endif
+#ifdef CONFIG_MPC85xx
+#include <mpc85xx.h>
+#include <asm/immap_85xx.h>
+#endif
+#ifdef CONFIG_MPC83xx
+#include <mpc83xx.h>
+#include <asm/immap_83xx.h>
+#endif
+#ifdef	CONFIG_4xx
+#include <asm/ppc4xx.h>
+#endif
+#ifdef CONFIG_BLACKFIN
+#include <asm/blackfin.h>
+#endif
+#ifdef CONFIG_SOC_DA8XX
+#include <asm/arch/hardware.h>
+#endif
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/immap_lsch3.h>
+#endif
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#endif
+
+#include <part.h>
+#include <flash.h>
+#include <image.h>
+
+/* Bring in printf format macros if inttypes.h is included */
+#define __STDC_FORMAT_MACROS
+
+#ifdef __LP64__
+#define CONFIG_SYS_SUPPORT_64BIT_DATA
+#endif
+
+#ifdef DEBUG
+#define _DEBUG	1
+#else
+#define _DEBUG	0
+#endif
+
+#ifndef pr_fmt
+#define pr_fmt(fmt) fmt
+#endif
+
+/*
+ * Output a debug text when condition "cond" is met. The "cond" should be
+ * computed by a preprocessor in the best case, allowing for the best
+ * optimization.
+ */
+#define debug_cond(cond, fmt, args...)			\
+	do {						\
+		if (cond)				\
+			printf(pr_fmt(fmt), ##args);	\
+	} while (0)
+
+#define debug(fmt, args...)			\
+	debug_cond(_DEBUG, fmt, ##args)
+
+/*
+ * An assertion is run-time check done in debug mode only. If DEBUG is not
+ * defined then it is skipped. If DEBUG is defined and the assertion fails,
+ * then it calls panic*( which may or may not reset/halt U-Boot (see
+ * CONFIG_PANIC_HANG), It is hoped that all failing assertions are found
+ * before release, and after release it is hoped that they don't matter. But
+ * in any case these failing assertions cannot be fixed with a reset (which
+ * may just do the same assertion again).
+ */
+void __assert_fail(const char *assertion, const char *file, unsigned line,
+		   const char *function);
+#define assert(x) \
+	({ if (!(x) && _DEBUG) \
+		__assert_fail(#x, __FILE__, __LINE__, __func__); })
+
+#define error(fmt, args...) do {					\
+		printf("ERROR: " pr_fmt(fmt) "\nat %s:%d/%s()\n",	\
+			##args, __FILE__, __LINE__, __func__);		\
+} while (0)
+
+#ifndef BUG
+#define BUG() do { \
+	printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
+	panic("BUG!"); \
+} while (0)
+#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
+#endif /* BUG */
+
+typedef void (interrupt_handler_t)(void *);
+
+#include <asm/u-boot.h> /* boot information for Linux kernel */
+#include <asm/global_data.h>	/* global data used for startup functions */
+
+/*
+ * enable common handling for all TQM8xxL/M boards:
+ * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards
+ * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards
+ *                  and for the TQM885D board
+ */
+#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
+    defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
+    defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M)
+# ifndef CONFIG_TQM8xxM
+#  define CONFIG_TQM8xxM
+# endif
+#endif
+#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \
+    defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \
+    defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \
+    defined(CONFIG_TQM885D)
+# ifndef CONFIG_TQM8xxL
+#  define CONFIG_TQM8xxL
+# endif
+#endif
+
+#if defined(CONFIG_ENV_IS_EMBEDDED)
+#define TOTAL_MALLOC_LEN	CONFIG_SYS_MALLOC_LEN
+#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
+	(CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \
+      defined(CONFIG_ENV_IS_IN_NVRAM)
+#define	TOTAL_MALLOC_LEN	(CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
+#else
+#define	TOTAL_MALLOC_LEN	CONFIG_SYS_MALLOC_LEN
+#endif
+
+/*
+ * Function Prototypes
+ */
+int dram_init(void);
+
+void	hang		(void) __attribute__ ((noreturn));
+
+int	timer_init(void);
+int	cpu_init(void);
+
+/* */
+phys_size_t initdram (int);
+
+#include <display_options.h>
+
+/* common/main.c */
+void	main_loop	(void);
+int run_command(const char *cmd, int flag);
+int run_command_repeatable(const char *cmd, int flag);
+
+/**
+ * Run a list of commands separated by ; or even \0
+ *
+ * Note that if 'len' is not -1, then the command does not need to be nul
+ * terminated, Memory will be allocated for the command in that case.
+ *
+ * @param cmd	List of commands to run, each separated bu semicolon
+ * @param len	Length of commands excluding terminator if known (-1 if not)
+ * @param flag	Execution flags (CMD_FLAG_...)
+ * @return 0 on success, or != 0 on error.
+ */
+int run_command_list(const char *cmd, int len, int flag);
+
+/* arch/$(ARCH)/lib/board.c */
+void board_init_f(ulong);
+void board_init_r(gd_t *, ulong) __attribute__ ((noreturn));
+
+/**
+ * ulong board_init_f_alloc_reserve - allocate reserved area
+ *
+ * This function is called by each architecture very early in the start-up
+ * code to allow the C runtime to reserve space on the stack for writable
+ * 'globals' such as GD and the malloc arena.
+ *
+ * @top:	top of the reserve area, growing down.
+ * @return:	bottom of reserved area
+ */
+ulong board_init_f_alloc_reserve(ulong top);
+
+/**
+ * board_init_f_init_reserve - initialize the reserved area(s)
+ *
+ * This function is called once the C runtime has allocated the reserved
+ * area on the stack. It must initialize the GD at the base of that area.
+ *
+ * @base:	top from which reservation was done
+ */
+void board_init_f_init_reserve(ulong base);
+
+/**
+ * arch_setup_gd() - Set up the global_data pointer
+ *
+ * This pointer is special in some architectures and cannot easily be assigned
+ * to. For example on x86 it is implemented by adding a specific record to its
+ * Global Descriptor Table! So we we provide a function to carry out this task.
+ * For most architectures this can simply be:
+ *
+ *    gd = gd_ptr;
+ *
+ * @gd_ptr:	Pointer to global data
+ */
+void arch_setup_gd(gd_t *gd_ptr);
+
+int checkboard(void);
+int show_board_info(void);
+int checkflash(void);
+int checkdram(void);
+int last_stage_init(void);
+extern ulong monitor_flash_len;
+int mac_read_from_eeprom(void);
+extern u8 __dtb_dt_begin[];	/* embedded device tree blob */
+int set_cpu_clk_info(void);
+int mdm_init(void);
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void);
+#else
+static inline int print_cpuinfo(void)
+{
+	return 0;
+}
+#endif
+int update_flash_size(int flash_size);
+int arch_early_init_r(void);
+
+/**
+ * arch_cpu_init_dm() - init CPU after driver model is available
+ *
+ * This is called immediately after driver model is available before
+ * relocation. This is similar to arch_cpu_init() but is able to reference
+ * devices
+ *
+ * @return 0 if OK, -ve on error
+ */
+int arch_cpu_init_dm(void);
+
+/**
+ * Reserve all necessary stacks
+ *
+ * This is used in generic board init sequence in common/board_f.c. Each
+ * architecture could provide this function to tailor the required stacks.
+ *
+ * On entry gd->start_addr_sp is pointing to the suggested top of the stack.
+ * The callee ensures gd->start_add_sp is 16-byte aligned, so architectures
+ * require only this can leave it untouched.
+ *
+ * On exit gd->start_addr_sp and gd->irq_sp should be set to the respective
+ * positions of the stack. The stack pointer(s) will be set to this later.
+ * gd->irq_sp is only required, if the architecture needs it.
+ *
+ * @return 0 if no error
+ */
+__weak int arch_reserve_stacks(void);
+
+/**
+ * Show the DRAM size in a board-specific way
+ *
+ * This is used by boards to display DRAM information in their own way.
+ *
+ * @param size	Size of DRAM (which should be displayed along with other info)
+ */
+void board_show_dram(phys_size_t size);
+
+/**
+ * arch_fixup_fdt() - Write arch-specific information to fdt
+ *
+ * Defined in arch/$(ARCH)/lib/bootm-fdt.c
+ *
+ * @blob:	FDT blob to write to
+ * @return 0 if ok, or -ve FDT_ERR_... on failure
+ */
+int arch_fixup_fdt(void *blob);
+
+/* common/flash.c */
+void flash_perror (int);
+
+/* common/cmd_source.c */
+int	source (ulong addr, const char *fit_uname);
+
+extern ulong load_addr;		/* Default Load Address */
+extern ulong save_addr;		/* Default Save Address */
+extern ulong save_size;		/* Default Save Size */
+
+/* common/cmd_doc.c */
+void	doc_probe(unsigned long physadr);
+
+/* common/cmd_net.c */
+int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+/* common/cmd_fat.c */
+int do_fat_fsload(cmd_tbl_t *, int, int, char * const []);
+
+/* common/cmd_ext2.c */
+int do_ext2load(cmd_tbl_t *, int, int, char * const []);
+
+/* common/cmd_nvedit.c */
+int	env_init     (void);
+void	env_relocate (void);
+int	envmatch     (uchar *, int);
+
+/* Avoid unfortunate conflict with libc's getenv() */
+#ifdef CONFIG_SANDBOX
+#define getenv uboot_getenv
+#endif
+char	*getenv	     (const char *);
+int	getenv_f     (const char *name, char *buf, unsigned len);
+ulong getenv_ulong(const char *name, int base, ulong default_val);
+
+/**
+ * getenv_hex() - Return an environment variable as a hex value
+ *
+ * Decode an environment as a hex number (it may or may not have a 0x
+ * prefix). If the environment variable cannot be found, or does not start
+ * with hex digits, the default value is returned.
+ *
+ * @varname:		Variable to decode
+ * @default_val:	Value to return on error
+ */
+ulong getenv_hex(const char *varname, ulong default_val);
+
+/*
+ * Read an environment variable as a boolean
+ * Return -1 if variable does not exist (default to true)
+ */
+int getenv_yesno(const char *var);
+int	saveenv	     (void);
+int	setenv	     (const char *, const char *);
+int setenv_ulong(const char *varname, ulong value);
+int setenv_hex(const char *varname, ulong value);
+/**
+ * setenv_addr - Set an environment variable to an address in hex
+ *
+ * @varname:	Environment variable to set
+ * @addr:	Value to set it to
+ * @return 0 if ok, 1 on error
+ */
+static inline int setenv_addr(const char *varname, const void *addr)
+{
+	return setenv_hex(varname, (ulong)addr);
+}
+
+#ifdef CONFIG_ARM
+# include <asm/mach-types.h>
+# include <asm/setup.h>
+# include <asm/u-boot-arm.h>	/* ARM version to be fixed! */
+#endif /* CONFIG_ARM */
+#ifdef CONFIG_X86		/* x86 version to be fixed! */
+# include <asm/u-boot-x86.h>
+#endif /* CONFIG_X86 */
+#ifdef CONFIG_SANDBOX
+# include <asm/u-boot-sandbox.h>	/* TODO(sjg) what needs to be fixed? */
+#endif
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/setup.h>
+# include <asm/u-boot-nds32.h>
+#endif /* CONFIG_NDS32 */
+#ifdef CONFIG_MIPS
+# include <asm/u-boot-mips.h>
+#endif /* CONFIG_MIPS */
+#ifdef CONFIG_ARC
+# include <asm/u-boot-arc.h>
+#endif /* CONFIG_ARC */
+
+#ifdef CONFIG_AUTO_COMPLETE
+int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
+#endif
+int get_env_id (void);
+
+void	pci_init      (void);
+void	pci_init_board(void);
+
+#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
+    int	   pci_pre_init	       (struct pci_controller *);
+    int	   is_pci_host	       (struct pci_controller *);
+#endif
+
+#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX))
+#   if defined(CONFIG_SYS_PCI_TARGET_INIT)
+	void	pci_target_init	     (struct pci_controller *);
+#   endif
+#   if defined(CONFIG_SYS_PCI_MASTER_INIT)
+	void	pci_master_init	     (struct pci_controller *);
+#   endif
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+   void pcie_setup_hoses(int busno);
+#endif
+#endif
+
+int	misc_init_f   (void);
+int	misc_init_r   (void);
+
+/* common/exports.c */
+void	jumptable_init(void);
+
+/* common/kallsysm.c */
+const char *symbol_lookup(unsigned long addr, unsigned long *caddr);
+
+/* api/api.c */
+void	api_init (void);
+
+/* common/memsize.c */
+long	get_ram_size  (long *, long);
+phys_size_t get_effective_memsize(void);
+
+/* $(BOARD)/$(BOARD).c */
+void	reset_phy     (void);
+void	fdc_hw_init   (void);
+
+/* $(BOARD)/eeprom.c */
+void eeprom_init  (int bus);
+int  eeprom_read  (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+int  eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+
+/*
+ * Set this up regardless of board
+ * type, to prevent errors.
+ */
+#if defined(CONFIG_SPI) || !defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+# define CONFIG_SYS_DEF_EEPROM_ADDR 0
+#else
+#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
+# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
+#endif
+#endif /* CONFIG_SPI || !defined(CONFIG_SYS_I2C_EEPROM_ADDR) */
+
+#if defined(CONFIG_SPI)
+extern void spi_init_f (void);
+extern void spi_init_r (void);
+extern ssize_t spi_read	 (uchar *, int, uchar *, int);
+extern ssize_t spi_write (uchar *, int, uchar *, int);
+#endif
+
+/* $(BOARD)/$(BOARD).c */
+int board_early_init_f (void);
+int board_late_init (void);
+int board_postclk_init (void); /* after clocks/timebase, before env/serial */
+int board_early_init_r (void);
+void board_poweroff (void);
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram(void);
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+/* $(CPU)/start.S */
+#if defined(CONFIG_5xx) || \
+    defined(CONFIG_8xx)
+uint	get_immr      (uint);
+#endif
+#if defined(CONFIG_MPC5xxx)
+uint	get_svr       (void);
+#endif
+uint	get_pvr	      (void);
+uint	get_svr	      (void);
+uint	rd_ic_cst     (void);
+void	wr_ic_cst     (uint);
+void	wr_ic_adr     (uint);
+uint	rd_dc_cst     (void);
+void	wr_dc_cst     (uint);
+void	wr_dc_adr     (uint);
+int	icache_status (void);
+void	icache_enable (void);
+void	icache_disable(void);
+int	dcache_status (void);
+void	dcache_enable (void);
+void	dcache_disable(void);
+void	mmu_disable(void);
+#if defined(CONFIG_ARM)
+void	relocate_code(ulong);
+#else
+void	relocate_code(ulong, gd_t *, ulong) __attribute__ ((noreturn));
+#endif
+ulong	get_endaddr   (void);
+void	trap_init     (ulong);
+#if defined (CONFIG_4xx)	|| \
+    defined (CONFIG_MPC5xxx)	|| \
+    defined (CONFIG_MPC85xx)	|| \
+    defined (CONFIG_MPC86xx)	|| \
+    defined (CONFIG_MPC83xx)
+unsigned char	in8(unsigned int);
+void		out8(unsigned int, unsigned char);
+unsigned short	in16(unsigned int);
+unsigned short	in16r(unsigned int);
+void		out16(unsigned int, unsigned short value);
+void		out16r(unsigned int, unsigned short value);
+unsigned long	in32(unsigned int);
+unsigned long	in32r(unsigned int);
+void		out32(unsigned int, unsigned long value);
+void		out32r(unsigned int, unsigned long value);
+void		ppcDcbf(unsigned long value);
+void		ppcDcbi(unsigned long value);
+void		ppcSync(void);
+void		ppcDcbz(unsigned long value);
+#endif
+#if defined (CONFIG_MICROBLAZE)
+unsigned short	in16(unsigned int);
+void		out16(unsigned int, unsigned short value);
+#endif
+
+#if defined (CONFIG_MPC83xx)
+void		ppcDWload(unsigned int *addr, unsigned int *ret);
+void		ppcDWstore(unsigned int *addr, unsigned int *value);
+void disable_addr_trans(void);
+void enable_addr_trans(void);
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+#endif
+
+/*
+ * Return the current value of a monotonically increasing microsecond timer.
+ * Granularity may be larger than 1us if hardware does not support this.
+ */
+ulong timer_get_us(void);
+
+/* $(CPU)/cpu.c */
+static inline int cpumask_next(int cpu, unsigned int mask)
+{
+	for (cpu++; !((1 << cpu) & mask); cpu++)
+		;
+
+	return cpu;
+}
+
+#define for_each_cpu(iter, cpu, num_cpus, mask) \
+	for (iter = 0, cpu = cpumask_next(-1, mask); \
+		iter < num_cpus; \
+		iter++, cpu = cpumask_next(cpu, mask)) \
+
+int	cpu_numcores  (void);
+int	cpu_num_dspcores(void);
+u32	cpu_mask      (void);
+u32	cpu_dsp_mask(void);
+int	is_core_valid (unsigned int);
+int	probecpu      (void);
+int	checkcpu      (void);
+int	checkicache   (void);
+int	checkdcache   (void);
+void	upmconfig     (unsigned int, unsigned int *, unsigned int);
+ulong	get_tbclk     (void);
+void	reset_misc    (void);
+void	reset_cpu     (ulong addr);
+void ft_cpu_setup(void *blob, bd_t *bd);
+void ft_pci_setup(void *blob, bd_t *bd);
+
+void smp_set_core_boot_addr(unsigned long addr, int corenr);
+void smp_kick_all_cpus(void);
+
+/* $(CPU)/serial.c */
+int	serial_init   (void);
+void	serial_setbrg (void);
+void	serial_putc   (const char);
+void	serial_putc_raw(const char);
+void	serial_puts   (const char *);
+int	serial_getc   (void);
+int	serial_tstc   (void);
+
+/* These versions take a stdio_dev pointer */
+struct stdio_dev;
+int serial_stub_getc(struct stdio_dev *sdev);
+int serial_stub_tstc(struct stdio_dev *sdev);
+
+/* $(CPU)/speed.c */
+int	get_clocks (void);
+int	get_clocks_866 (void);
+int	sdram_adjust_866 (void);
+int	adjust_sdram_tbs_8xx (void);
+#if defined(CONFIG_MPC8260)
+int	prt_8260_clks (void);
+#elif defined(CONFIG_MPC5xxx)
+int	prt_mpc5xxx_clks (void);
+#endif
+#ifdef CONFIG_4xx
+ulong	get_OPB_freq (void);
+ulong	get_PCI_freq (void);
+#endif
+#if defined(CONFIG_S3C24X0) || \
+    defined(CONFIG_LH7A40X) || \
+    defined(CONFIG_EP93XX)
+ulong	get_FCLK (void);
+ulong	get_HCLK (void);
+ulong	get_PCLK (void);
+ulong	get_UCLK (void);
+#endif
+#if defined(CONFIG_LH7A40X)
+ulong	get_PLLCLK (void);
+#endif
+#if defined(CONFIG_IMX)
+ulong get_systemPLLCLK(void);
+ulong get_FCLK(void);
+ulong get_HCLK(void);
+ulong get_BCLK(void);
+ulong get_PERCLK1(void);
+ulong get_PERCLK2(void);
+ulong get_PERCLK3(void);
+#endif
+ulong	get_bus_freq  (ulong);
+int get_serial_clock(void);
+
+#if defined(CONFIG_MPC85xx)
+typedef MPC85xx_SYS_INFO sys_info_t;
+void	get_sys_info  ( sys_info_t * );
+void ft_fixup_cpu(void *, u64);
+void ft_fixup_num_cores(void *);
+#endif
+#if defined(CONFIG_MPC86xx)
+typedef MPC86xx_SYS_INFO sys_info_t;
+void   get_sys_info  ( sys_info_t * );
+static inline ulong get_ddr_freq(ulong dummy)
+{
+	return get_bus_freq(dummy);
+}
+#else
+ulong get_ddr_freq(ulong);
+#endif
+
+#if defined(CONFIG_4xx)
+#  if defined(CONFIG_440)
+#	if defined(CONFIG_440SPE)
+	 unsigned long determine_sysper(void);
+	 unsigned long determine_pci_clock_per(void);
+#	endif
+#  endif
+typedef PPC4xx_SYS_INFO sys_info_t;
+int	ppc440spe_revB(void);
+void	get_sys_info  ( sys_info_t * );
+#endif
+
+/* $(CPU)/cpu_init.c */
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
+void	cpu_init_f    (volatile immap_t *immr);
+#endif
+#if defined(CONFIG_4xx) || defined(CONFIG_MCF52x2) || defined(CONFIG_MPC86xx)
+void	cpu_init_f    (void);
+#endif
+#ifdef CONFIG_MPC85xx
+ulong cpu_init_f(void);
+#endif
+
+int	cpu_init_r    (void);
+#if defined(CONFIG_MPC8260)
+int	prt_8260_rsr  (void);
+#elif defined(CONFIG_MPC83xx)
+int	prt_83xx_rsr  (void);
+#endif
+
+/* $(CPU)/interrupts.c */
+int	interrupt_init	   (void);
+void	timer_interrupt	   (struct pt_regs *);
+void	external_interrupt (struct pt_regs *);
+void	irq_install_handler(int, interrupt_handler_t *, void *);
+void	irq_free_handler   (int);
+void	reset_timer	   (void);
+ulong	get_timer	   (ulong base);
+
+/* Return value of monotonic microsecond timer */
+unsigned long timer_get_us(void);
+
+void	enable_interrupts  (void);
+int	disable_interrupts (void);
+
+/* $(CPU)/.../commproc.c */
+int	dpram_init (void);
+uint	dpram_base(void);
+uint	dpram_base_align(uint align);
+uint	dpram_alloc(uint size);
+uint	dpram_alloc_align(uint size,uint align);
+void	bootcount_store (ulong);
+ulong	bootcount_load (void);
+#define BOOTCOUNT_MAGIC		0xB001C041
+
+/* $(CPU)/.../<eth> */
+void mii_init (void);
+
+/* $(CPU)/.../lcd.c */
+ulong	lcd_setmem (ulong);
+
+/* $(CPU)/.../video.c */
+ulong	video_setmem (ulong);
+
+/* arch/$(ARCH)/lib/cache.c */
+void	enable_caches(void);
+void	flush_cache   (unsigned long, unsigned long);
+void	flush_dcache_all(void);
+void	flush_dcache_range(unsigned long start, unsigned long stop);
+void	invalidate_dcache_range(unsigned long start, unsigned long stop);
+void	invalidate_dcache_all(void);
+void	invalidate_icache_all(void);
+
+enum {
+	/* Disable caches (else flush caches but leave them active) */
+	CBL_DISABLE_CACHES		= 1 << 0,
+	CBL_SHOW_BOOTSTAGE_REPORT	= 1 << 1,
+
+	CBL_ALL				= 3,
+};
+
+/**
+ * Clean up ready for linux
+ *
+ * @param flags		Flags to control what is done
+ */
+int cleanup_before_linux_select(int flags);
+
+/* arch/$(ARCH)/lib/ticks.S */
+uint64_t get_ticks(void);
+void	wait_ticks    (unsigned long);
+
+/* arch/$(ARCH)/lib/time.c */
+void	__udelay      (unsigned long);
+ulong	usec2ticks    (unsigned long usec);
+ulong	ticks2usec    (unsigned long ticks);
+int	init_timebase (void);
+
+/* lib/gunzip.c */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
+						int stoponerr, int offset);
+
+/**
+ * gzwrite progress indicators: defined weak to allow board-specific
+ * overrides:
+ *
+ *	gzwrite_progress_init called on startup
+ *	gzwrite_progress called during decompress/write loop
+ *	gzwrite_progress_finish called at end of loop to
+ *		indicate success (retcode=0) or failure
+ */
+void gzwrite_progress_init(u64 expected_size);
+
+void gzwrite_progress(int iteration,
+		     u64 bytes_written,
+		     u64 total_bytes);
+
+void gzwrite_progress_finish(int retcode,
+			     u64 totalwritten,
+			     u64 totalsize,
+			     u32 expected_crc,
+			     u32 calculated_crc);
+
+/**
+ * decompress and write gzipped image from memory to block device
+ *
+ * @param	src		compressed image address
+ * @param	len		compressed image length in bytes
+ * @param	dev		block device descriptor
+ * @param	szwritebuf	bytes per write (pad to erase size)
+ * @param	startoffs	offset in bytes of first write
+ * @param	szexpected	expected uncompressed length
+ *				may be zero to use gzip trailer
+ *				for files under 4GiB
+ */
+int gzwrite(unsigned char *src, int len,
+	    struct blk_desc *dev,
+	    unsigned long szwritebuf,
+	    u64 startoffs,
+	    u64 szexpected);
+
+/* lib/lz4_wrapper.c */
+int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn);
+
+/* lib/qsort.c */
+void qsort(void *base, size_t nmemb, size_t size,
+	   int(*compar)(const void *, const void *));
+int strcmp_compar(const void *, const void *);
+
+/* lib/time.c */
+void	udelay        (unsigned long);
+void mdelay(unsigned long);
+
+/* lib/uuid.c */
+#include <uuid.h>
+
+/* lib/vsprintf.c */
+#include <vsprintf.h>
+
+/* lib/strmhz.c */
+char *	strmhz(char *buf, unsigned long hz);
+
+/* lib/crc32.c */
+#include <u-boot/crc.h>
+
+/* lib/rand.c */
+#define RAND_MAX -1U
+void srand(unsigned int seed);
+unsigned int rand(void);
+unsigned int rand_r(unsigned int *seedp);
+
+/*
+ * STDIO based functions (can always be used)
+ */
+/* serial stuff */
+int	serial_printf (const char *fmt, ...)
+		__attribute__ ((format (__printf__, 1, 2)));
+/* stdin */
+int	getc(void);
+int	tstc(void);
+
+/* stdout */
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SERIAL_SUPPORT)
+#define	putc(...) do { } while (0)
+#define puts(...) do { } while (0)
+#define printf(...) do { } while (0)
+#define vprintf(...) do { } while (0)
+#else
+void	putc(const char c);
+void	puts(const char *s);
+int	printf(const char *fmt, ...)
+		__attribute__ ((format (__printf__, 1, 2)));
+int	vprintf(const char *fmt, va_list args);
+#endif
+
+/* stderr */
+#define eputc(c)		fputc(stderr, c)
+#define eputs(s)		fputs(stderr, s)
+#define eprintf(fmt,args...)	fprintf(stderr,fmt ,##args)
+
+/*
+ * FILE based functions (can only be used AFTER relocation!)
+ */
+#define stdin		0
+#define stdout		1
+#define stderr		2
+#define MAX_FILES	3
+
+int	fprintf(int file, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 2, 3)));
+void	fputs(int file, const char *s);
+void	fputc(int file, const char c);
+int	ftstc(int file);
+int	fgetc(int file);
+
+/* lib/gzip.c */
+int gzip(void *dst, unsigned long *lenp,
+		unsigned char *src, unsigned long srclen);
+int zzip(void *dst, unsigned long *lenp, unsigned char *src,
+		unsigned long srclen, int stoponerr,
+		int (*func)(unsigned long, unsigned long));
+
+/* lib/net_utils.c */
+#include <net.h>
+static inline struct in_addr getenv_ip(char *var)
+{
+	return string_to_ip(getenv(var));
+}
+
+int	pcmcia_init (void);
+
+#ifdef CONFIG_STATUS_LED
+# include <status_led.h>
+#endif
+
+#include <bootstage.h>
+
+#ifdef CONFIG_SHOW_ACTIVITY
+void show_activity(int arg);
+#endif
+
+/* Multicore arch functions */
+#ifdef CONFIG_MP
+int cpu_status(int nr);
+int cpu_reset(int nr);
+int cpu_disable(int nr);
+int cpu_release(int nr, int argc, char * const argv[]);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_PPC
+/*
+ * Has to be included outside of the #ifndef __ASSEMBLY__ section.
+ * Otherwise might lead to compilation errors in assembler files.
+ */
+#include <asm/cache.h>
+#endif
+
+/* Put only stuff here that the assembler can digest */
+
+#ifdef CONFIG_POST
+#define CONFIG_HAS_POST
+#ifndef CONFIG_POST_ALT_LIST
+#define CONFIG_POST_STD_LIST
+#endif
+#endif
+
+#ifdef CONFIG_INIT_CRITICAL
+#error CONFIG_INIT_CRITICAL is deprecated!
+#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
+#endif
+
+#define ROUND(a,b)		(((a) + (b) - 1) & ~((b) - 1))
+
+/*
+ * check_member() - Check the offset of a structure member
+ *
+ * @structure:	Name of structure (e.g. global_data)
+ * @member:	Name of member (e.g. baudrate)
+ * @offset:	Expected offset in bytes
+ */
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset)
+
+/* Avoid using CONFIG_EFI_STUB directly as we may boot from other loaders */
+#ifdef CONFIG_EFI_STUB
+#define ll_boot_init()	false
+#else
+#define ll_boot_init()	true
+#endif
+
+/* Pull in stuff for the build system */
+#ifdef DO_DEPS_ONLY
+# include <environment.h>
+#endif
+
+#endif	/* __COMMON_H_ */

u-boot/include/common_timing_params.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef COMMON_TIMING_PARAMS_H
+#define COMMON_TIMING_PARAMS_H
+
+typedef struct {
+	/* parameters to constrict */
+
+	unsigned int tckmin_x_ps;
+	unsigned int tckmax_ps;
+	unsigned int trcd_ps;
+	unsigned int trp_ps;
+	unsigned int tras_ps;
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+	unsigned int taamin_ps;
+#endif
+
+#ifdef CONFIG_SYS_FSL_DDR4
+	unsigned int trfc1_ps;
+	unsigned int trfc2_ps;
+	unsigned int trfc4_ps;
+	unsigned int trrds_ps;
+	unsigned int trrdl_ps;
+	unsigned int tccdl_ps;
+#else
+	unsigned int twtr_ps;	/* maximum = 63750 ps */
+	unsigned int trfc_ps;	/* maximum = 255 ns + 256 ns + .75 ns
+					   = 511750 ps */
+
+	unsigned int trrd_ps;	/* maximum = 63750 ps */
+	unsigned int trtp_ps;	/* byte 38, spd->trtp */
+#endif
+	unsigned int twr_ps;	/* maximum = 63750 ps */
+	unsigned int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+
+	unsigned int refresh_rate_ps;
+	unsigned int extended_op_srt;
+
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
+	unsigned int tis_ps;	/* byte 32, spd->ca_setup */
+	unsigned int tih_ps;	/* byte 33, spd->ca_hold */
+	unsigned int tds_ps;	/* byte 34, spd->data_setup */
+	unsigned int tdh_ps;	/* byte 35, spd->data_hold */
+	unsigned int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
+	unsigned int tqhs_ps;	/* byte 45, spd->tqhs */
+#endif
+
+	unsigned int ndimms_present;
+	unsigned int lowest_common_spd_caslat;
+	unsigned int highest_common_derated_caslat;
+	unsigned int additive_latency;
+	unsigned int all_dimms_burst_lengths_bitmask;
+	unsigned int all_dimms_registered;
+	unsigned int all_dimms_unbuffered;
+	unsigned int all_dimms_ecc_capable;
+
+	unsigned long long total_mem;
+	unsigned long long base_address;
+
+	/* DDR3 RDIMM */
+	unsigned char rcw[16];	/* Register Control Word 0-15 */
+} common_timing_params_t;
+
+#endif

u-boot/include/commproc.h

@@ -0,0 +1,865 @@
+/*
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file contains structures and information for the communication
+ * processor channels.  Some CPM control and status is available
+ * throught the MPC8xx internal memory map.  See immap.h for details.
+ * This file only contains what I need for the moment, not the total
+ * CPM capabilities.  I (or someone else) will add definitions as they
+ * are needed.  -- Dan
+ *
+ */
+#ifndef __CPM_8XX__
+#define __CPM_8XX__
+
+#include <asm/8xx_immap.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST		((ushort)0x8000)
+#define CPM_CR_OPCODE		((ushort)0x0f00)
+#define CPM_CR_CHAN		((ushort)0x00f0)
+#define CPM_CR_FLG		((ushort)0x0001)
+
+/* Some commands (there are more...later)
+*/
+#define CPM_CR_INIT_TRX		((ushort)0x0000)
+#define CPM_CR_INIT_RX		((ushort)0x0001)
+#define CPM_CR_INIT_TX		((ushort)0x0002)
+#define CPM_CR_HUNT_MODE	((ushort)0x0003)
+#define CPM_CR_STOP_TX		((ushort)0x0004)
+#define CPM_CR_RESTART_TX	((ushort)0x0006)
+#define CPM_CR_SET_GADDR	((ushort)0x0008)
+
+/* Channel numbers.
+*/
+#define CPM_CR_CH_SCC1		((ushort)0x0000)
+#define CPM_CR_CH_I2C		((ushort)0x0001)    /* I2C and IDMA1 */
+#define CPM_CR_CH_SCC2		((ushort)0x0004)
+#define CPM_CR_CH_SPI		((ushort)0x0005)    /* SPI/IDMA2/Timers */
+#define CPM_CR_CH_SCC3		((ushort)0x0008)
+#define CPM_CR_CH_SMC1		((ushort)0x0009)    /* SMC1 / DSP1 */
+#define CPM_CR_CH_SCC4		((ushort)0x000c)
+#define CPM_CR_CH_SMC2		((ushort)0x000d)    /* SMC2 / DSP2 */
+
+#define mk_cr_cmd(CH, CMD)	((CMD << 8) | (CH << 4))
+
+/*
+ * DPRAM defines and allocation functions
+ */
+
+/* The dual ported RAM is multi-functional.  Some areas can be (and are
+ * being) used for microcode.  There is an area that can only be used
+ * as data ram for buffer descriptors, which is all we use right now.
+ * Currently the first 512 and last 256 bytes are used for microcode.
+ */
+#ifdef  CONFIG_SYS_ALLOC_DPRAM
+
+#define CPM_DATAONLY_BASE	((uint)0x0800)
+#define CPM_DATAONLY_SIZE	((uint)0x0700)
+#define CPM_DP_NOSPACE		((uint)0x7fffffff)
+
+#else
+
+#define CPM_SERIAL_BASE		0x0800
+#define CPM_I2C_BASE		0x0820
+#define CPM_SPI_BASE		0x0840
+#define CPM_FEC_BASE		0x0860
+#define CPM_SERIAL2_BASE	0x08E0
+#define CPM_SCC_BASE		0x0900
+#define CPM_POST_BASE		0x0980
+#define CPM_WLKBD_BASE		0x0a00
+
+#endif
+
+#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
+#define CPM_POST_WORD_ADDR	0x07FC
+#else
+#define CPM_POST_WORD_ADDR	CONFIG_SYS_CPM_POST_WORD_ADDR
+#endif
+
+#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
+#define CPM_BOOTCOUNT_ADDR	(CPM_POST_WORD_ADDR - 2*sizeof(ulong))
+#else
+#define CPM_BOOTCOUNT_ADDR	CONFIG_SYS_CPM_BOOTCOUNT_ADDR
+#endif
+
+#define BD_IIC_START	((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+extern	cpm8xx_t	*cpmp;		/* Pointer to comm processor */
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+	ushort	cbd_sc;		/* Status and Control */
+	ushort	cbd_datlen;	/* Data length in buffer */
+	uint	cbd_bufaddr;	/* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
+#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
+#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
+#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
+#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
+#define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
+#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
+#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
+#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
+#define BD_SC_BR	((ushort)0x0020)	/* Break received */
+#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
+#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
+#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
+#define BD_SC_CD	((ushort)0x0001)	/* Carrier Detect lost */
+
+/* Parameter RAM offsets.
+*/
+#define PROFF_SCC1	((uint)0x0000)
+#define PROFF_IIC	((uint)0x0080)
+#define PROFF_REVNUM	((uint)0x00b0)
+#define PROFF_SCC2	((uint)0x0100)
+#define PROFF_SPI	((uint)0x0180)
+#define PROFF_SCC3	((uint)0x0200)
+#define PROFF_SMC1	((uint)0x0280)
+#define PROFF_SCC4	((uint)0x0300)
+#define PROFF_SMC2	((uint)0x0380)
+
+/* Define enough so I can at least use the serial port as a UART.
+ */
+typedef struct smc_uart {
+	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	smc_rfcr;	/* Rx function code */
+	u_char	smc_tfcr;	/* Tx function code */
+	ushort	smc_mrblr;	/* Max receive buffer length */
+	uint	smc_rstate;	/* Internal */
+	uint	smc_idp;	/* Internal */
+	ushort	smc_rbptr;	/* Internal */
+	ushort	smc_ibc;	/* Internal */
+	uint	smc_rxtmp;	/* Internal */
+	uint	smc_tstate;	/* Internal */
+	uint	smc_tdp;	/* Internal */
+	ushort	smc_tbptr;	/* Internal */
+	ushort	smc_tbc;	/* Internal */
+	uint	smc_txtmp;	/* Internal */
+	ushort	smc_maxidl;	/* Maximum idle characters */
+	ushort	smc_tmpidl;	/* Temporary idle counter */
+	ushort	smc_brklen;	/* Last received break length */
+	ushort	smc_brkec;	/* rcv'd break condition counter */
+	ushort	smc_brkcr;	/* xmt break count register */
+	ushort	smc_rmask;	/* Temporary bit mask */
+	u_char	res1[8];
+	ushort	smc_rpbase;	/* Relocation pointer */
+} smc_uart_t;
+
+/* Function code bits.
+*/
+#define SMC_EB	((u_char)0x10)	/* Set big endian byte order */
+
+/* SMC uart mode register.
+*/
+#define	SMCMR_REN	((ushort)0x0001)
+#define SMCMR_TEN	((ushort)0x0002)
+#define SMCMR_DM	((ushort)0x000c)
+#define SMCMR_SM_GCI	((ushort)0x0000)
+#define SMCMR_SM_UART	((ushort)0x0020)
+#define SMCMR_SM_TRANS	((ushort)0x0030)
+#define SMCMR_SM_MASK	((ushort)0x0030)
+#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
+#define SMCMR_REVD	SMCMR_PM_EVEN
+#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
+#define SMCMR_BS	SMCMR_PEN
+#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
+#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
+#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC2 as Centronics parallel printer.  It is half duplex, in that
+ * it can only receive or transmit.  The parameter ram values for
+ * each direction are either unique or properly overlap, so we can
+ * include them in one structure.
+ */
+typedef struct smc_centronics {
+	ushort	scent_rbase;
+	ushort	scent_tbase;
+	u_char	scent_cfcr;
+	u_char	scent_smask;
+	ushort	scent_mrblr;
+	uint	scent_rstate;
+	uint	scent_r_ptr;
+	ushort	scent_rbptr;
+	ushort	scent_r_cnt;
+	uint	scent_rtemp;
+	uint	scent_tstate;
+	uint	scent_t_ptr;
+	ushort	scent_tbptr;
+	ushort	scent_t_cnt;
+	uint	scent_ttemp;
+	ushort	scent_max_sl;
+	ushort	scent_sl_cnt;
+	ushort	scent_character1;
+	ushort	scent_character2;
+	ushort	scent_character3;
+	ushort	scent_character4;
+	ushort	scent_character5;
+	ushort	scent_character6;
+	ushort	scent_character7;
+	ushort	scent_character8;
+	ushort	scent_rccm;
+	ushort	scent_rccr;
+} smc_cent_t;
+
+/* Centronics Status Mask Register.
+*/
+#define SMC_CENT_F	((u_char)0x08)
+#define SMC_CENT_PE	((u_char)0x04)
+#define SMC_CENT_S	((u_char)0x02)
+
+/* SMC Event and Mask register.
+*/
+#define	SMCM_BRKE	((unsigned char)0x40)	/* When in UART Mode */
+#define	SMCM_BRK	((unsigned char)0x10)	/* When in UART Mode */
+#define	SMCM_TXE	((unsigned char)0x10)	/* When in Transparent Mode */
+#define	SMCM_BSY	((unsigned char)0x04)
+#define	SMCM_TX		((unsigned char)0x02)
+#define	SMCM_RX		((unsigned char)0x01)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST		((uint)0x00020000)
+#define CPM_BRG_EN		((uint)0x00010000)
+#define CPM_BRG_EXTC_INT	((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK2	((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK6	((uint)0x00008000)
+#define CPM_BRG_ATB		((uint)0x00002000)
+#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
+#define CPM_BRG_DIV16		((uint)0x00000001)
+
+/* SI Clock Route Register
+*/
+#define SICR_RCLK_SCC1_BRG1	((uint)0x00000000)
+#define SICR_TCLK_SCC1_BRG1	((uint)0x00000000)
+#define SICR_RCLK_SCC2_BRG2	((uint)0x00000800)
+#define SICR_TCLK_SCC2_BRG2	((uint)0x00000100)
+#define SICR_RCLK_SCC3_BRG3	((uint)0x00100000)
+#define SICR_TCLK_SCC3_BRG3	((uint)0x00020000)
+#define SICR_RCLK_SCC4_BRG4	((uint)0x18000000)
+#define SICR_TCLK_SCC4_BRG4	((uint)0x03000000)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP		((uint)0x00040000)
+#define SCC_GSMRH_GDE		((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
+#define SCC_GSMRH_REVD		((uint)0x00002000)
+#define SCC_GSMRH_TRX		((uint)0x00001000)
+#define SCC_GSMRH_TTX		((uint)0x00000800)
+#define SCC_GSMRH_CDP		((uint)0x00000400)
+#define SCC_GSMRH_CTSP		((uint)0x00000200)
+#define SCC_GSMRH_CDS		((uint)0x00000100)
+#define SCC_GSMRH_CTSS		((uint)0x00000080)
+#define SCC_GSMRH_TFL		((uint)0x00000040)
+#define SCC_GSMRH_RFW		((uint)0x00000020)
+#define SCC_GSMRH_TXSY		((uint)0x00000010)
+#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8		((uint)0x00000008)
+#define SCC_GSMRH_SYNL4		((uint)0x00000004)
+#define SCC_GSMRH_RTSM		((uint)0x00000002)
+#define SCC_GSMRH_RSYN		((uint)0x00000001)
+
+#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
+#define SCC_GSMRL_TCI		((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
+#define SCC_GSMRL_RINV		((uint)0x02000000)
+#define SCC_GSMRL_TINV		((uint)0x01000000)
+#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48	((uint)0x00800000)
+#define SCC_GSMRL_TPL_32	((uint)0x00600000)
+#define SCC_GSMRL_TPL_16	((uint)0x00400000)
+#define SCC_GSMRL_TPL_8		((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
+#define SCC_GSMRL_TPP_01	((uint)0x00100000)
+#define SCC_GSMRL_TPP_10	((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
+#define SCC_GSMRL_TEND		((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
+#define SCC_GSMRL_ENR		((uint)0x00000020)
+#define SCC_GSMRL_ENT		((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
+
+#define SCC_TODR_TOD		((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define	SCCM_TXE	((unsigned char)0x10)
+#define	SCCM_BSY	((unsigned char)0x04)
+#define	SCCM_TX		((unsigned char)0x02)
+#define	SCCM_RX		((unsigned char)0x01)
+
+typedef struct scc_param {
+	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	scc_rfcr;	/* Rx function code */
+	u_char	scc_tfcr;	/* Tx function code */
+	ushort	scc_mrblr;	/* Max receive buffer length */
+	uint	scc_rstate;	/* Internal */
+	uint	scc_idp;	/* Internal */
+	ushort	scc_rbptr;	/* Internal */
+	ushort	scc_ibc;	/* Internal */
+	uint	scc_rxtmp;	/* Internal */
+	uint	scc_tstate;	/* Internal */
+	uint	scc_tdp;	/* Internal */
+	ushort	scc_tbptr;	/* Internal */
+	ushort	scc_tbc;	/* Internal */
+	uint	scc_txtmp;	/* Internal */
+	uint	scc_rcrc;	/* Internal */
+	uint	scc_tcrc;	/* Internal */
+} sccp_t;
+
+/* Function code bits.
+*/
+#define SCC_EB	((u_char)0x10)	/* Set big endian byte order */
+
+/* CPM Ethernet through SCCx.
+ */
+typedef struct scc_enet {
+	sccp_t	sen_genscc;
+	uint	sen_cpres;	/* Preset CRC */
+	uint	sen_cmask;	/* Constant mask for CRC */
+	uint	sen_crcec;	/* CRC Error counter */
+	uint	sen_alec;	/* alignment error counter */
+	uint	sen_disfc;	/* discard frame counter */
+	ushort	sen_pads;	/* Tx short frame pad character */
+	ushort	sen_retlim;	/* Retry limit threshold */
+	ushort	sen_retcnt;	/* Retry limit counter */
+	ushort	sen_maxflr;	/* maximum frame length register */
+	ushort	sen_minflr;	/* minimum frame length register */
+	ushort	sen_maxd1;	/* maximum DMA1 length */
+	ushort	sen_maxd2;	/* maximum DMA2 length */
+	ushort	sen_maxd;	/* Rx max DMA */
+	ushort	sen_dmacnt;	/* Rx DMA counter */
+	ushort	sen_maxb;	/* Max BD byte count */
+	ushort	sen_gaddr1;	/* Group address filter */
+	ushort	sen_gaddr2;
+	ushort	sen_gaddr3;
+	ushort	sen_gaddr4;
+	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf0rba;	/* Internal */
+	uint	sen_tbuf0crc;	/* Internal */
+	ushort	sen_tbuf0bcnt;	/* Internal */
+	ushort	sen_paddrh;	/* physical address (MSB) */
+	ushort	sen_paddrm;
+	ushort	sen_paddrl;	/* physical address (LSB) */
+	ushort	sen_pper;	/* persistence */
+	ushort	sen_rfbdptr;	/* Rx first BD pointer */
+	ushort	sen_tfbdptr;	/* Tx first BD pointer */
+	ushort	sen_tlbdptr;	/* Tx last BD pointer */
+	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf1rba;	/* Internal */
+	uint	sen_tbuf1crc;	/* Internal */
+	ushort	sen_tbuf1bcnt;	/* Internal */
+	ushort	sen_txlen;	/* Tx Frame length counter */
+	ushort	sen_iaddr1;	/* Individual address filter */
+	ushort	sen_iaddr2;
+	ushort	sen_iaddr3;
+	ushort	sen_iaddr4;
+	ushort	sen_boffcnt;	/* Backoff counter */
+
+	/* NOTE: Some versions of the manual have the following items
+	 * incorrectly documented.  Below is the proper order.
+	 */
+	ushort	sen_taddrh;	/* temp address (MSB) */
+	ushort	sen_taddrm;
+	ushort	sen_taddrl;	/* temp address (LSB) */
+} scc_enet_t;
+
+/**********************************************************************
+ *
+ * Board specific configuration settings.
+ *
+ * Please note that we use the presence of a #define SCC_ENET and/or
+ * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
+ **********************************************************************/
+
+/***  BSEIP  **********************************************************/
+
+#ifdef CONFIG_BSEIP
+/* This ENET stuff is for the MPC823 with ethernet on SCC2.
+ * This is unique to the BSE ip-Engine board.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0100)
+#define PA_ENET_RCLK	((ushort)0x0200)
+#define PB_ENET_TENA	((uint)0x00002000)
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+/* BSE uses port B and C bits for PHY control also.
+*/
+#define PB_BSE_POWERUP	((uint)0x00000004)
+#define PB_BSE_FDXDIS	((uint)0x00008000)
+#define PC_BSE_LOOPBACK	((ushort)0x0800)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002c00)
+#endif	/* CONFIG_BSEIP */
+
+/***  KM8XX  *********************************************************/
+
+/* The KM8XX Service Module uses SCC3 for Ethernet */
+
+#ifdef CONFIG_KM8XX
+#define PROFF_ENET	PROFF_SCC3		/* Ethernet on SCC3 */
+#define CPM_CR_ENET	CPM_CR_CH_SCC3
+#define SCC_ENET	2
+#define PA_ENET_RXD	((ushort)0x0010)	/* PA 11 */
+#define PA_ENET_TXD	((ushort)0x0020)	/* PA 10 */
+#define PA_ENET_RCLK	((ushort)0x1000)	/* PA  3 CLK 5 */
+#define PA_ENET_TCLK	((ushort)0x2000)	/* PA  2 CLK 6 */
+
+#define PC_ENET_TENA	((ushort)0x0004)	/* PC 13 */
+
+#define PC_ENET_RENA	((ushort)0x0200)	/* PC  6 */
+#define PC_ENET_CLSN	((ushort)0x0100)	/* PC  7 */
+
+/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
+ * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x00FF0000)
+#define SICR_ENET_CLKRT	((uint)0x00250000)
+#endif	/* CONFIG_KM8XX */
+
+/***  MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI  **********/
+
+#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
+    defined(CONFIG_TQM823L) || \
+    defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
+    defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D)
+
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002600)
+
+# ifdef CONFIG_FEC_ENET		/* Use FEC for Fast Ethernet */
+#define FEC_ENET
+# endif	/* CONFIG_FEC_ENET */
+
+#endif	/* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
+
+/***  TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M  *********************/
+
+#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
+    defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
+    defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
+    defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
+
+# ifdef CONFIG_SCC1_ENET	/* use SCC for 10Mbps Ethernet	*/
+
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+#define	SCC_ENET	0
+#define PA_ENET_RXD	((ushort)0x0001)	/* PA 15 */
+#define PA_ENET_TXD	((ushort)0x0002)	/* PA 14 */
+#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PC_ENET_TENA	((ushort)0x0001)	/* PC 15 */
+#define PC_ENET_CLSN	((ushort)0x0010)	/* PC 11 */
+#define PC_ENET_RENA	((ushort)0x0020)	/* PC 10 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x00000026)
+
+# endif	/* CONFIG_SCC1_ENET */
+
+# ifdef CONFIG_FEC_ENET		/* Use FEC for Fast Ethernet */
+
+#define FEC_ENET
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
+
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
+
+# endif	/* CONFIG_FEC_ENET */
+#endif	/* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
+
+/*********************************************************************/
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
+#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
+#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
+#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
+#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
+#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
+#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
+#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
+#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
+#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
+#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
+#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
+#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
+#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
+#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
+#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
+#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
+#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_WRAP		((ushort)0x2000)
+#define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_LAST		((ushort)0x0800)
+#define BD_ENET_RX_FIRST	((ushort)0x0400)
+#define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_LG		((ushort)0x0020)
+#define BD_ENET_RX_NO		((ushort)0x0010)
+#define BD_ENET_RX_SH		((ushort)0x0008)
+#define BD_ENET_RX_CR		((ushort)0x0004)
+#define BD_ENET_RX_OV		((ushort)0x0002)
+#define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY	((ushort)0x8000)
+#define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_WRAP		((ushort)0x2000)
+#define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_LAST		((ushort)0x0800)
+#define BD_ENET_TX_TC		((ushort)0x0400)
+#define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_HB		((ushort)0x0100)
+#define BD_ENET_TX_LC		((ushort)0x0080)
+#define BD_ENET_TX_RL		((ushort)0x0040)
+#define BD_ENET_TX_RCMASK	((ushort)0x003c)
+#define BD_ENET_TX_UN		((ushort)0x0002)
+#define BD_ENET_TX_CSL		((ushort)0x0001)
+#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+	sccp_t	scc_genscc;
+	uint	scc_res1;	/* Reserved */
+	uint	scc_res2;	/* Reserved */
+	ushort	scc_maxidl;	/* Maximum idle chars */
+	ushort	scc_idlc;	/* temp idle counter */
+	ushort	scc_brkcr;	/* Break count register */
+	ushort	scc_parec;	/* receive parity error counter */
+	ushort	scc_frmec;	/* receive framing error counter */
+	ushort	scc_nosec;	/* receive noise counter */
+	ushort	scc_brkec;	/* receive break condition counter */
+	ushort	scc_brkln;	/* last received break length */
+	ushort	scc_uaddr1;	/* UART address character 1 */
+	ushort	scc_uaddr2;	/* UART address character 2 */
+	ushort	scc_rtemp;	/* Temp storage */
+	ushort	scc_toseq;	/* Transmit out of sequence char */
+	ushort	scc_char1;	/* control character 1 */
+	ushort	scc_char2;	/* control character 2 */
+	ushort	scc_char3;	/* control character 3 */
+	ushort	scc_char4;	/* control character 4 */
+	ushort	scc_char5;	/* control character 5 */
+	ushort	scc_char6;	/* control character 6 */
+	ushort	scc_char7;	/* control character 7 */
+	ushort	scc_char8;	/* control character 8 */
+	ushort	scc_rccm;	/* receive control character mask */
+	ushort	scc_rccr;	/* receive control character register */
+	ushort	scc_rlbc;	/* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR		((ushort)0x1000)
+#define UART_SCCM_GLT		((ushort)0x0800)
+#define UART_SCCM_AB		((ushort)0x0200)
+#define UART_SCCM_IDL		((ushort)0x0100)
+#define UART_SCCM_GRA		((ushort)0x0080)
+#define UART_SCCM_BRKE		((ushort)0x0040)
+#define UART_SCCM_BRKS		((ushort)0x0020)
+#define UART_SCCM_CCR		((ushort)0x0008)
+#define UART_SCCM_BSY		((ushort)0x0004)
+#define UART_SCCM_TX		((ushort)0x0002)
+#define UART_SCCM_RX		((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC		((ushort)0x8000)
+#define SCU_PSMR_SL		((ushort)0x4000)
+#define SCU_PSMR_CL		((ushort)0x3000)
+#define SCU_PSMR_UM		((ushort)0x0c00)
+#define SCU_PSMR_FRZ		((ushort)0x0200)
+#define SCU_PSMR_RZS		((ushort)0x0100)
+#define SCU_PSMR_SYN		((ushort)0x0080)
+#define SCU_PSMR_DRT		((ushort)0x0040)
+#define SCU_PSMR_PEN		((ushort)0x0010)
+#define SCU_PSMR_RPM		((ushort)0x000c)
+#define SCU_PSMR_REVP		((ushort)0x0008)
+#define SCU_PSMR_TPM		((ushort)0x0003)
+#define SCU_PSMR_TEVP		((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+	sccp_t	st_genscc;
+	uint	st_cpres;	/* Preset CRC */
+	uint	st_cmask;	/* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST		((ushort)0x0800)
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
+	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
+	u_char	iic_rfcr;	/* Rx function code */
+	u_char	iic_tfcr;	/* Tx function code */
+	ushort	iic_mrblr;	/* Max receive buffer length */
+	uint	iic_rstate;	/* Internal */
+	uint	iic_rdp;	/* Internal */
+	ushort	iic_rbptr;	/* Internal */
+	ushort	iic_rbc;	/* Internal */
+	uint	iic_rxtmp;	/* Internal */
+	uint	iic_tstate;	/* Internal */
+	uint	iic_tdp;	/* Internal */
+	ushort	iic_tbptr;	/* Internal */
+	ushort	iic_tbc;	/* Internal */
+	uint	iic_txtmp;	/* Internal */
+	uint	iic_res;	/* reserved */
+	ushort	iic_rpbase;	/* Relocation pointer */
+	ushort	iic_res2;	/* reserved */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
+	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
+	u_char	spi_rfcr;	/* Rx function code */
+	u_char	spi_tfcr;	/* Tx function code */
+	ushort	spi_mrblr;	/* Max receive buffer length */
+	uint	spi_rstate;	/* Internal */
+	uint	spi_rdp;	/* Internal */
+	ushort	spi_rbptr;	/* Internal */
+	ushort	spi_rbc;	/* Internal */
+	uint	spi_rxtmp;	/* Internal */
+	uint	spi_tstate;	/* Internal */
+	uint	spi_tdp;	/* Internal */
+	ushort	spi_tbptr;	/* Internal */
+	ushort	spi_tbc;	/* Internal */
+	uint	spi_txtmp;	/* Internal */
+	uint	spi_res;
+	ushort	spi_rpbase;	/* Relocation pointer */
+	ushort	spi_res2;
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
+#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
+#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
+#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
+#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
+#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
+#define SPMODE_EN	((ushort)0x0100)	/* Enable */
+#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
+#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
+
+#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
+#define SPMODE_PM(x)	((x) &0xF)
+
+/* HDLC parameter RAM.
+*/
+
+typedef struct hdlc_pram_s {
+	/*
+	 * SCC parameter RAM
+	 */
+	ushort	rbase;		/* Rx Buffer descriptor base address */
+	ushort	tbase;		/* Tx Buffer descriptor base address */
+	uchar	rfcr;		/* Rx function code */
+	uchar	tfcr;		/* Tx function code */
+	ushort	mrblr;		/* Rx buffer length */
+	ulong	rstate;		/* Rx internal state */
+	ulong	rptr;		/* Rx internal data pointer */
+	ushort	rbptr;		/* rb BD Pointer */
+	ushort	rcount;		/* Rx internal byte count */
+	ulong	rtemp;		/* Rx temp */
+	ulong	tstate;		/* Tx internal state */
+	ulong	tptr;		/* Tx internal data pointer */
+	ushort	tbptr;		/* Tx BD pointer */
+	ushort	tcount;		/* Tx byte count */
+	ulong	ttemp;		/* Tx temp */
+	ulong	rcrc;		/* temp receive CRC */
+	ulong	tcrc;		/* temp transmit CRC */
+	/*
+	 * HDLC specific parameter RAM
+	 */
+	uchar	res[4];		/* reserved */
+	ulong	c_mask;		/* CRC constant */
+	ulong	c_pres;		/* CRC preset */
+	ushort	disfc;		/* discarded frame counter */
+	ushort	crcec;		/* CRC error counter */
+	ushort	abtsc;		/* abort sequence counter */
+	ushort	nmarc;		/* nonmatching address rx cnt */
+	ushort	retrc;		/* frame retransmission cnt */
+	ushort	mflr;		/* maximum frame length reg */
+	ushort	max_cnt;	/* maximum length counter */
+	ushort	rfthr;		/* received frames threshold */
+	ushort	rfcnt;		/* received frames count */
+	ushort	hmask;		/* user defined frm addr mask */
+	ushort	haddr1;		/* user defined frm address 1 */
+	ushort	haddr2;		/* user defined frm address 2 */
+	ushort	haddr3;		/* user defined frm address 3 */
+	ushort	haddr4;		/* user defined frm address 4 */
+	ushort	tmp;		/* temp */
+	ushort	tmp_mb;		/* temp */
+} hdlc_pram_t;
+
+/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
+ * channels or devices.  All of these are presented to the PPC core
+ * as a single interrupt.  The CPM interrupt handler dispatches its
+ * own handlers, in a similar fashion to the PPC core handler.  We
+ * use the table as defined in the manuals (i.e. no special high
+ * priority and SCC1 == SCCa, etc...).
+ */
+#define CPMVEC_NR		32
+#define CPMVEC_OFFSET           0x00010000
+#define CPMVEC_PIO_PC15		((ushort)0x1f | CPMVEC_OFFSET)
+#define CPMVEC_SCC1		((ushort)0x1e | CPMVEC_OFFSET)
+#define CPMVEC_SCC2		((ushort)0x1d | CPMVEC_OFFSET)
+#define CPMVEC_SCC3		((ushort)0x1c | CPMVEC_OFFSET)
+#define CPMVEC_SCC4		((ushort)0x1b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC14		((ushort)0x1a | CPMVEC_OFFSET)
+#define CPMVEC_TIMER1		((ushort)0x19 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC13		((ushort)0x18 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC12		((ushort)0x17 | CPMVEC_OFFSET)
+#define CPMVEC_SDMA_CB_ERR	((ushort)0x16 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA1		((ushort)0x15 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA2		((ushort)0x14 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER2		((ushort)0x12 | CPMVEC_OFFSET)
+#define CPMVEC_RISCTIMER	((ushort)0x11 | CPMVEC_OFFSET)
+#define CPMVEC_I2C		((ushort)0x10 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC11		((ushort)0x0f | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC10		((ushort)0x0e | CPMVEC_OFFSET)
+#define CPMVEC_TIMER3		((ushort)0x0c | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC9		((ushort)0x0b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC8		((ushort)0x0a | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC7		((ushort)0x09 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER4		((ushort)0x07 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC6		((ushort)0x06 | CPMVEC_OFFSET)
+#define CPMVEC_SPI		((ushort)0x05 | CPMVEC_OFFSET)
+#define CPMVEC_SMC1		((ushort)0x04 | CPMVEC_OFFSET)
+#define CPMVEC_SMC2		((ushort)0x03 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC5		((ushort)0x02 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC4		((ushort)0x01 | CPMVEC_OFFSET)
+#define CPMVEC_ERROR		((ushort)0x00 | CPMVEC_OFFSET)
+
+extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
+
+/* CPM interrupt configuration vector.
+*/
+#define	CICR_SCD_SCC4		((uint)0x00c00000)	/* SCC4 @ SCCd */
+#define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
+#define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
+#define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
+#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrrupt */
+#define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
+#define CICR_IEN		((uint)0x00000080)	/* Int. enable */
+#define CICR_SPS		((uint)0x00000001)	/* SCC Spread */
+#endif /* __CPM_8XX__ */

u-boot/include/compiler.h

@@ -0,0 +1,144 @@
+/*
+ * Keep all the ugly #ifdef for system stuff here
+ */
+
+#ifndef __COMPILER_H__
+#define __COMPILER_H__
+
+#include <stddef.h>
+
+#ifdef USE_HOSTCC
+
+#if defined(__BEOS__)	 || \
+    defined(__NetBSD__)  || \
+    defined(__FreeBSD__) || \
+    defined(__sun__)	 || \
+    defined(__APPLE__)
+# include <inttypes.h>
+#elif defined(__linux__) || defined(__WIN32__) || defined(__MINGW32__)
+# include <stdint.h>
+#endif
+
+#include <errno.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#if !defined(__WIN32__) && !defined(__MINGW32__)
+# include <sys/mman.h>
+#endif
+
+/* Not all systems (like Windows) has this define, and yes
+ * we do replace/emulate mmap() on those systems ...
+ */
+#ifndef MAP_FAILED
+# define MAP_FAILED ((void *)-1)
+#endif
+
+#include <fcntl.h>
+#ifndef O_BINARY		/* should be define'd on __WIN32__ */
+#define O_BINARY	0
+#endif
+
+#ifdef __linux__
+# include <endian.h>
+# include <byteswap.h>
+#elif defined(__MACH__) || defined(__FreeBSD__)
+# include <machine/endian.h>
+typedef unsigned long ulong;
+#endif
+#ifdef __FreeBSD__
+# include <sys/endian.h> /* htole32 and friends */
+#endif
+
+#include <time.h>
+
+typedef uint8_t __u8;
+typedef uint16_t __u16;
+typedef uint32_t __u32;
+typedef unsigned int uint;
+
+#define uswap_16(x) \
+	((((x) & 0xff00) >> 8) | \
+	 (((x) & 0x00ff) << 8))
+#define uswap_32(x) \
+	((((x) & 0xff000000) >> 24) | \
+	 (((x) & 0x00ff0000) >>  8) | \
+	 (((x) & 0x0000ff00) <<  8) | \
+	 (((x) & 0x000000ff) << 24))
+#define _uswap_64(x, sfx) \
+	((((x) & 0xff00000000000000##sfx) >> 56) | \
+	 (((x) & 0x00ff000000000000##sfx) >> 40) | \
+	 (((x) & 0x0000ff0000000000##sfx) >> 24) | \
+	 (((x) & 0x000000ff00000000##sfx) >>  8) | \
+	 (((x) & 0x00000000ff000000##sfx) <<  8) | \
+	 (((x) & 0x0000000000ff0000##sfx) << 24) | \
+	 (((x) & 0x000000000000ff00##sfx) << 40) | \
+	 (((x) & 0x00000000000000ff##sfx) << 56))
+#if defined(__GNUC__)
+# define uswap_64(x) _uswap_64(x, ull)
+#else
+# define uswap_64(x) _uswap_64(x, )
+#endif
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+# define cpu_to_le16(x)		(x)
+# define cpu_to_le32(x)		(x)
+# define cpu_to_le64(x)		(x)
+# define le16_to_cpu(x)		(x)
+# define le32_to_cpu(x)		(x)
+# define le64_to_cpu(x)		(x)
+# define cpu_to_be16(x)		uswap_16(x)
+# define cpu_to_be32(x)		uswap_32(x)
+# define cpu_to_be64(x)		uswap_64(x)
+# define be16_to_cpu(x)		uswap_16(x)
+# define be32_to_cpu(x)		uswap_32(x)
+# define be64_to_cpu(x)		uswap_64(x)
+#else
+# define cpu_to_le16(x)		uswap_16(x)
+# define cpu_to_le32(x)		uswap_32(x)
+# define cpu_to_le64(x)		uswap_64(x)
+# define le16_to_cpu(x)		uswap_16(x)
+# define le32_to_cpu(x)		uswap_32(x)
+# define le64_to_cpu(x)		uswap_64(x)
+# define cpu_to_be16(x)		(x)
+# define cpu_to_be32(x)		(x)
+# define cpu_to_be64(x)		(x)
+# define be16_to_cpu(x)		(x)
+# define be32_to_cpu(x)		(x)
+# define be64_to_cpu(x)		(x)
+#endif
+
+#else /* !USE_HOSTCC */
+
+#ifdef CONFIG_USE_STDINT
+/* Provided by gcc. */
+#include <stdint.h>
+#else
+/* Type for `void *' pointers. */
+typedef unsigned long int uintptr_t;
+#endif
+
+#include <linux/string.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+#if __SIZEOF_LONG__ == 8
+# define __WORDSIZE	64
+#elif __SIZEOF_LONG__ == 4
+# define __WORDSIZE	32
+#else
+/*
+ * Assume 32-bit for now - only newer toolchains support this feature and
+ * this is only required for sandbox support at present.
+ */
+#define __WORDSIZE	32
+#endif
+
+#endif /* USE_HOSTCC */
+
+#define likely(x)	__builtin_expect(!!(x), 1)
+#define unlikely(x)	__builtin_expect(!!(x), 0)
+
+#endif

u-boot/include/config_cmd_all.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License Version 2. This file is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _CONFIG_CMD_ALL_H
+#define _CONFIG_CMD_ALL_H
+
+/*
+ * Alphabetical list of all possible commands.
+ */
+
+#define CONFIG_CMD_BEDBUG	/* Include BedBug Debugger	*/
+#define CONFIG_CMD_BMP		/* BMP support			*/
+#define CONFIG_CMD_BSP		/* Board Specific functions	*/
+#define CONFIG_CMD_CLK		/* Clock support		*/
+#define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
+#define CONFIG_CMD_DIAG		/* Diagnostics			*/
+#define CONFIG_CMD_DISPLAY	/* Display support		*/
+#define CONFIG_CMD_DOC		/* Disk-On-Chip Support		*/
+#define CONFIG_CMD_DTT		/* Digital Therm and Thermostat */
+#define CONFIG_CMD_EEPROM	/* EEPROM read/write support	*/
+#define CONFIG_CMD_FDC		/* Floppy Disk Support		*/
+#define CONFIG_CMD_FUSE		/* Device fuse support		*/
+#define CONFIG_CMD_GETTIME	/* Get time since boot         */
+#define CONFIG_CMD_HASH		/* calculate hash / digest	*/
+#define CONFIG_CMD_IDE		/* IDE harddisk support		*/
+#define CONFIG_CMD_IMMAP	/* IMMR dump support		*/
+#define CONFIG_CMD_IO		/* Access to X86 IO space	*/
+#define CONFIG_CMD_IRQ		/* irqinfo			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+#define CONFIG_CMD_KGDB		/* kgdb				*/
+#define CONFIG_CMD_MFSL		/* FSL support for Microblaze	*/
+#define CONFIG_CMD_MTDPARTS	/* mtd parts support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_ONENAND	/* OneNAND support		*/
+#define CONFIG_CMD_PCI		/* pciinfo			*/
+#define CONFIG_CMD_PCMCIA	/* PCMCIA support		*/
+#define CONFIG_CMD_PORTIO	/* Port I/O			*/
+#define CONFIG_CMD_REGINFO	/* Register dump		*/
+#define CONFIG_CMD_REISER	/* Reiserfs support		*/
+#define CONFIG_CMD_READ		/* Read data from partition	*/
+#define CONFIG_CMD_SANDBOX	/* sb command to access sandbox features */
+#define CONFIG_CMD_SAVES	/* save S record dump		*/
+#define CONFIG_SCSI		/* SCSI Support			*/
+#define CONFIG_CMD_SDRAM	/* SDRAM DIMM SPD info printout */
+#define CONFIG_CMD_TERMINAL	/* built-in Serial Terminal	*/
+#define CONFIG_CMD_UBI		/* UBI Support			*/
+#define CONFIG_CMD_UBIFS	/* UBIFS Support		*/
+#define CONFIG_CMD_UNIVERSE	/* Tundra Universe Support	*/
+#define CONFIG_CMD_UNZIP	/* unzip from memory to memory	*/
+#define CONFIG_CMD_ZFS		/* ZFS Support			*/
+
+#endif	/* _CONFIG_CMD_ALL_H */

u-boot/include/config_defaults.h

@@ -0,0 +1,23 @@
+/*
+ * config_defaults.h - sane defaults for everyone
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _CONFIG_DEFAULTS_H_
+#define _CONFIG_DEFAULTS_H_
+
+/* Support bootm-ing different OSes */
+#define CONFIG_BOOTM_LINUX 1
+#define CONFIG_BOOTM_NETBSD 1
+#define CONFIG_BOOTM_PLAN9 1
+#define CONFIG_BOOTM_RTEMS 1
+#define CONFIG_BOOTM_VXWORKS 1
+
+#define CONFIG_GZIP 1
+#define CONFIG_ZLIB 1
+#define CONFIG_PARTITIONS 1
+
+#endif

u-boot/include/config_distro_bootcmd.h

@@ -0,0 +1,410 @@
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * Copyright 2014 Red Hat, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _CONFIG_CMD_DISTRO_BOOTCMD_H
+#define _CONFIG_CMD_DISTRO_BOOTCMD_H
+
+/*
+ * A note on error handling: It is possible for BOOT_TARGET_DEVICES to
+ * reference a device that is not enabled in the U-Boot configuration, e.g.
+ * it may include MMC in the list without CONFIG_CMD_MMC being enabled. Given
+ * that BOOT_TARGET_DEVICES is a macro that's expanded by the C pre-processor
+ * at compile time, it's not  possible to detect and report such problems via
+ * a simple #ifdef/#error combination. Still, the code needs to report errors.
+ * The best way I've found to do this is to make BOOT_TARGET_DEVICES expand to
+ * reference a non-existent symbol, and have the name of that symbol encode
+ * the error message. Consequently, this file contains references to e.g.
+ * BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC. Given the
+ * prevalence of capitals here, this looks like a pre-processor macro and
+ * hence seems like it should be all capitals, but it's really an error
+ * message that includes some other pre-processor symbols in the text.
+ */
+
+/* We need the part command */
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+#define BOOTENV_SHARED_BLKDEV_BODY(devtypel) \
+		"if " #devtypel " dev ${devnum}; then " \
+			"setenv devtype " #devtypel "; " \
+			"run scan_dev_for_boot_part; " \
+		"fi\0"
+
+#define BOOTENV_SHARED_BLKDEV(devtypel) \
+	#devtypel "_boot=" \
+	BOOTENV_SHARED_BLKDEV_BODY(devtypel)
+
+#define BOOTENV_DEV_BLKDEV(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+		"setenv devnum " #instance "; " \
+		"run " #devtypel "_boot\0"
+
+#define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#ifdef CONFIG_SANDBOX
+#define BOOTENV_SHARED_HOST	BOOTENV_SHARED_BLKDEV(host)
+#define BOOTENV_DEV_HOST	BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_HOST	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_SHARED_HOST
+#define BOOTENV_DEV_HOST \
+	BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX
+#define BOOTENV_DEV_NAME_HOST \
+	BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOTENV_SHARED_MMC	BOOTENV_SHARED_BLKDEV(mmc)
+#define BOOTENV_DEV_MMC		BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_MMC	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_SHARED_MMC
+#define BOOTENV_DEV_MMC \
+	BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC
+#define BOOTENV_DEV_NAME_MMC \
+	BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC
+#endif
+
+#ifdef CONFIG_CMD_UBIFS
+#define BOOTENV_SHARED_UBIFS \
+	"ubifs_boot=" \
+		"if ubi part UBI && ubifsmount ubi${devnum}:boot; then "  \
+			"setenv devtype ubi; "                            \
+			"setenv bootpart 0; "                             \
+			"run scan_dev_for_boot; "                         \
+		"fi\0"
+#define BOOTENV_DEV_UBIFS	BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_UBIFS	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_SHARED_UBIFS
+#define BOOTENV_DEV_UBIFS \
+	BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS
+#define BOOTENV_DEV_NAME_UBIFS \
+	BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS
+#endif
+
+#ifdef CONFIG_EFI_LOADER
+#if defined(CONFIG_ARM64)
+#define BOOTEFI_NAME "bootaa64.efi"
+#elif defined(CONFIG_ARM)
+#define BOOTEFI_NAME "bootarm.efi"
+#endif
+#endif
+
+#ifdef BOOTEFI_NAME
+#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
+/*
+ * On 32bit ARM systems there is a reasonable number of systems that follow
+ * the $soc-$board$boardver.dtb name scheme for their device trees. Use that
+ * scheme if we don't have an explicit fdtfile variable.
+ */
+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK                                  \
+	"if test -z \"${fdtfile}\" -a -n \"${soc}\"; then "               \
+	  "setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; "           \
+	"fi; "
+#else
+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK
+#endif
+
+
+#define BOOTENV_SHARED_EFI                                                \
+	"boot_efi_binary="                                                \
+		"load ${devtype} ${devnum}:${distro_bootpart} "           \
+			"${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; "      \
+		"if fdt addr ${fdt_addr_r}; then "                        \
+			"bootefi ${kernel_addr_r} ${fdt_addr_r};"         \
+		"else "                                                    \
+			"bootefi ${kernel_addr_r} ${fdtcontroladdr};"     \
+		"fi\0"                                                    \
+	\
+	"load_efi_dtb="                                                   \
+		"load ${devtype} ${devnum}:${distro_bootpart} "           \
+			"${fdt_addr_r} ${prefix}${efi_fdtfile}\0"         \
+	\
+	"efi_dtb_prefixes=/ /dtb/ /dtb/current/\0"                        \
+	"scan_dev_for_efi="                                               \
+		"setenv efi_fdtfile ${fdtfile}; "                         \
+		BOOTENV_EFI_SET_FDTFILE_FALLBACK                          \
+		"for prefix in ${efi_dtb_prefixes}; do "                  \
+			"if test -e ${devtype} "                          \
+					"${devnum}:${distro_bootpart} "   \
+					"${prefix}${efi_fdtfile}; then "  \
+				"run load_efi_dtb; "                      \
+			"fi;"                                             \
+		"done;"                                                   \
+		"if test -e ${devtype} ${devnum}:${distro_bootpart} "     \
+					"efi/boot/"BOOTEFI_NAME"; then "  \
+				"echo Found EFI removable media binary "  \
+					"efi/boot/"BOOTEFI_NAME"; "       \
+				"run boot_efi_binary; "                   \
+				"echo EFI LOAD FAILED: continuing...; "   \
+		"fi; "                                                    \
+		"setenv efi_fdtfile\0"
+#define SCAN_DEV_FOR_EFI "run scan_dev_for_efi;"
+#else
+#define BOOTENV_SHARED_EFI
+#define SCAN_DEV_FOR_EFI
+#endif
+
+#ifdef CONFIG_CMD_SATA
+#define BOOTENV_SHARED_SATA	BOOTENV_SHARED_BLKDEV(sata)
+#define BOOTENV_DEV_SATA	BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_SATA	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_SHARED_SATA
+#define BOOTENV_DEV_SATA \
+	BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_CMD_SATA
+#define BOOTENV_DEV_NAME_SATA \
+	BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_CMD_SATA
+#endif
+
+#ifdef CONFIG_SCSI
+#define BOOTENV_RUN_SCSI_INIT "run scsi_init; "
+#define BOOTENV_SET_SCSI_NEED_INIT "setenv scsi_need_init; "
+#define BOOTENV_SHARED_SCSI \
+	"scsi_init=" \
+		"if ${scsi_need_init}; then " \
+			"setenv scsi_need_init false; " \
+			"scsi scan; " \
+		"fi\0" \
+	\
+	"scsi_boot=" \
+		BOOTENV_RUN_SCSI_INIT \
+		BOOTENV_SHARED_BLKDEV_BODY(scsi)
+#define BOOTENV_DEV_SCSI	BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_SCSI	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_RUN_SCSI_INIT
+#define BOOTENV_SET_SCSI_NEED_INIT
+#define BOOTENV_SHARED_SCSI
+#define BOOTENV_DEV_SCSI \
+	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
+#define BOOTENV_DEV_NAME_SCSI \
+	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
+#endif
+
+#ifdef CONFIG_CMD_IDE
+#define BOOTENV_SHARED_IDE	BOOTENV_SHARED_BLKDEV(ide)
+#define BOOTENV_DEV_IDE		BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_IDE	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_SHARED_IDE
+#define BOOTENV_DEV_IDE \
+	BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_CMD_IDE
+#define BOOTENV_DEV_NAME_IDE \
+	BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_CMD_IDE
+#endif
+
+#if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI)
+#define BOOTENV_RUN_NET_PCI_ENUM "run boot_net_pci_enum; "
+#define BOOTENV_SHARED_PCI \
+	"boot_net_pci_enum=pci enum\0"
+#else
+#define BOOTENV_RUN_NET_PCI_ENUM
+#define BOOTENV_SHARED_PCI
+#endif
+
+#ifdef CONFIG_CMD_USB
+#define BOOTENV_RUN_NET_USB_START "run boot_net_usb_start; "
+#define BOOTENV_SHARED_USB \
+	"boot_net_usb_start=usb start\0" \
+	"usb_boot=" \
+		"usb start; " \
+		BOOTENV_SHARED_BLKDEV_BODY(usb)
+#define BOOTENV_DEV_USB		BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_USB	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_RUN_NET_USB_START
+#define BOOTENV_SHARED_USB
+#define BOOTENV_DEV_USB \
+	BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
+#define BOOTENV_DEV_NAME_USB \
+	BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
+#endif
+
+#if defined(CONFIG_CMD_DHCP)
+#if defined(CONFIG_EFI_LOADER)
+#if defined(CONFIG_ARM64)
+#define BOOTENV_EFI_PXE_ARCH "0xb"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000"
+#elif defined(CONFIG_ARM)
+#define BOOTENV_EFI_PXE_ARCH "0xa"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00010:UNDI:003000"
+#elif defined(CONFIG_X86)
+/* Always assume we're running 64bit */
+#define BOOTENV_EFI_PXE_ARCH "0x7"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000"
+#else
+#error Please specify an EFI client identifier
+#endif
+
+/*
+ * Ask the dhcp server for an EFI binary. If we get one, check for a
+ * device tree in the same folder. Then boot everything. If the file was
+ * not an EFI binary, we just return from the bootefi command and continue.
+ */
+#define BOOTENV_EFI_RUN_DHCP \
+	"setenv efi_fdtfile ${fdtfile}; "                                 \
+	BOOTENV_EFI_SET_FDTFILE_FALLBACK                                  \
+	"setenv efi_old_vci ${bootp_vci};"                                \
+	"setenv efi_old_arch ${bootp_arch};"                              \
+	"setenv bootp_vci " BOOTENV_EFI_PXE_VCI ";"                       \
+	"setenv bootp_arch " BOOTENV_EFI_PXE_ARCH ";"                     \
+	"if dhcp ${kernel_addr_r}; then "                                 \
+		"tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};"              \
+		"if fdt addr ${fdt_addr_r}; then "                        \
+			"bootefi ${kernel_addr_r} ${fdt_addr_r}; "        \
+		"else "                                                   \
+			"bootefi ${kernel_addr_r} ${fdtcontroladdr};"     \
+		"fi;"                                                     \
+	"fi;"                                                             \
+	"setenv bootp_vci ${efi_old_vci};"                                \
+	"setenv bootp_arch ${efi_old_arch};"                              \
+	"setenv efi_fdtfile;"                                             \
+	"setenv efi_old_arch;"                                            \
+	"setenv efi_old_vci;"
+#else
+#define BOOTENV_EFI_RUN_DHCP
+#endif
+#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \
+	"bootcmd_dhcp=" \
+		BOOTENV_RUN_NET_USB_START \
+		BOOTENV_RUN_NET_PCI_ENUM \
+		"if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \
+			"source ${scriptaddr}; " \
+		"fi;" \
+		BOOTENV_EFI_RUN_DHCP \
+		"\0"
+#define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \
+	"dhcp "
+#else
+#define BOOTENV_DEV_DHCP \
+	BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP
+#define BOOTENV_DEV_NAME_DHCP \
+	BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP
+#endif
+
+#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE)
+#define BOOTENV_DEV_PXE(devtypeu, devtypel, instance) \
+	"bootcmd_pxe=" \
+		BOOTENV_RUN_NET_USB_START \
+		BOOTENV_RUN_NET_PCI_ENUM \
+		"dhcp; " \
+		"if pxe get; then " \
+			"pxe boot; " \
+		"fi\0"
+#define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \
+	"pxe "
+#else
+#define BOOTENV_DEV_PXE \
+	BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE
+#define BOOTENV_DEV_NAME_PXE \
+	BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE
+#endif
+
+#if defined(CONFIG_CMD_USB_MASS_STORAGE)
+#define BOOTENV_DEV_UMS(devtypeu, devtypel, instance) \
+	"bootcmd_ums" #instance "=" \
+		"echo Entering USB mass storage...; " \
+		"ums ums " #instance "\0"
+#define BOOTENV_DEV_NAME_UMS(devtypeu, devtypel, instance) \
+	"ums" #instance " "
+#else
+#define BOOTENV_DEV_UMS \
+	BOOT_TARGET_DEVICES_references_UMS_without_CONFIG_CMD_UMS
+#define BOOTENV_DEV_NAME_UMS \
+	BOOT_TARGET_DEVICES_references_UMS_without_CONFIG_CMD_UMS
+#endif
+
+#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance) \
+	BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance)
+#define BOOTENV_BOOT_TARGETS \
+	"boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0"
+
+#define BOOTENV_DEV(devtypeu, devtypel, instance) \
+	BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance)
+#define BOOTENV \
+	BOOTENV_SHARED_HOST \
+	BOOTENV_SHARED_MMC \
+	BOOTENV_SHARED_PCI \
+	BOOTENV_SHARED_USB \
+	BOOTENV_SHARED_SATA \
+	BOOTENV_SHARED_SCSI \
+	BOOTENV_SHARED_IDE \
+	BOOTENV_SHARED_UBIFS \
+	BOOTENV_SHARED_EFI \
+	"boot_prefixes=/ /boot/\0" \
+	"boot_scripts=boot.scr.uimg boot.scr\0" \
+	"boot_script_dhcp=boot.scr.uimg\0" \
+	BOOTENV_BOOT_TARGETS \
+	\
+	"boot_extlinux="                                                  \
+		"sysboot ${devtype} ${devnum}:${distro_bootpart} any "    \
+			"${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \
+	\
+	"scan_dev_for_extlinux="                                          \
+		"if test -e ${devtype} "                                  \
+				"${devnum}:${distro_bootpart} "           \
+				"${prefix}extlinux/extlinux.conf; then "  \
+			"echo Found ${prefix}extlinux/extlinux.conf; "    \
+			"run boot_extlinux; "                             \
+			"echo SCRIPT FAILED: continuing...; "             \
+		"fi\0"                                                    \
+	\
+	"boot_a_script="                                                  \
+		"load ${devtype} ${devnum}:${distro_bootpart} "           \
+			"${scriptaddr} ${prefix}${script}; "              \
+		"source ${scriptaddr}\0"                                  \
+	\
+	"scan_dev_for_scripts="                                           \
+		"for script in ${boot_scripts}; do "                      \
+			"if test -e ${devtype} "                          \
+					"${devnum}:${distro_bootpart} "   \
+					"${prefix}${script}; then "       \
+				"echo Found U-Boot script "               \
+					"${prefix}${script}; "            \
+				"run boot_a_script; "                     \
+				"echo SCRIPT FAILED: continuing...; "     \
+			"fi; "                                            \
+		"done\0"                                                  \
+	\
+	"scan_dev_for_boot="                                              \
+		"echo Scanning ${devtype} "                               \
+				"${devnum}:${distro_bootpart}...; "       \
+		"for prefix in ${boot_prefixes}; do "                     \
+			"run scan_dev_for_extlinux; "                     \
+			"run scan_dev_for_scripts; "                      \
+		"done;"                                                   \
+		SCAN_DEV_FOR_EFI                                          \
+		"\0"                                                      \
+	\
+	"scan_dev_for_boot_part="                                         \
+		"part list ${devtype} ${devnum} -bootable devplist; "     \
+		"env exists devplist || setenv devplist 1; "              \
+		"for distro_bootpart in ${devplist}; do "                 \
+			"if fstype ${devtype} "                           \
+					"${devnum}:${distro_bootpart} "   \
+					"bootfstype; then "               \
+				"run scan_dev_for_boot; "                 \
+			"fi; "                                            \
+		"done\0"                                                  \
+	\
+	BOOT_TARGET_DEVICES(BOOTENV_DEV)                                  \
+	\
+	"distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT                      \
+		"for target in ${boot_targets}; do "                      \
+			"run bootcmd_${target}; "                         \
+		"done\0"
+
+#ifndef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
+#endif
+
+#endif  /* _CONFIG_CMD_DISTRO_BOOTCMD_H */

u-boot/include/config_distro_defaults.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright 2013-2014 Red Hat, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _CONFIG_CMD_DISTRO_DEFAULTS_H
+#define _CONFIG_CMD_DISTRO_DEFAULTS_H
+
+/*
+ * List of all commands and options that when defined enables support for
+ * features required by distros to support boards in a standardised and
+ * consistent manner.
+ */
+
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_SUBNETMASK
+
+#ifdef CONFIG_ARM64
+#define CONFIG_CMD_BOOTI
+#endif
+#define CONFIG_CMD_PXE
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_MENU
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+
+#endif	/* _CONFIG_CMD_DISTRO_DEFAULTS_H */

u-boot/include/config_fallbacks.h

@@ -0,0 +1,102 @@
+/*
+ * Copyright 2012 Texas Instruments
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License Version 2. This file is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __CONFIG_FALLBACKS_H
+#define __CONFIG_FALLBACKS_H
+
+#ifdef CONFIG_SPL
+#ifdef CONFIG_SPL_PAD_TO
+#ifdef CONFIG_SPL_MAX_SIZE
+#if CONFIG_SPL_PAD_TO && CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
+#error CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
+#endif
+#endif
+#else
+#ifdef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_PAD_TO	CONFIG_SPL_MAX_SIZE
+#else
+#define CONFIG_SPL_PAD_TO	0
+#endif
+#endif
+#endif
+
+#ifndef CONFIG_SYS_BAUDRATE_TABLE
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#endif
+
+#if defined(CONFIG_CMD_FAT) && !defined(CONFIG_FS_FAT)
+#define CONFIG_FS_FAT
+#endif
+
+#if (defined(CONFIG_CMD_EXT4) || defined(CONFIG_CMD_EXT2)) && \
+						!defined(CONFIG_FS_EXT4)
+#define CONFIG_FS_EXT4
+#endif
+
+#if defined(CONFIG_CMD_EXT4_WRITE) && !defined(CONFIG_EXT4_WRITE)
+#define CONFIG_EXT4_WRITE
+#endif
+
+/* Rather than repeat this expression each time, add a define for it */
+#if defined(CONFIG_CMD_IDE) || \
+	defined(CONFIG_CMD_SATA) || \
+	defined(CONFIG_SCSI) || \
+	defined(CONFIG_CMD_USB) || \
+	defined(CONFIG_CMD_PART) || \
+	defined(CONFIG_CMD_GPT) || \
+	defined(CONFIG_MMC) || \
+	defined(CONFIG_SYSTEMACE) || \
+	defined(CONFIG_SANDBOX)
+#define HAVE_BLOCK_DEVICE
+#endif
+
+#if (defined(CONFIG_PARTITION_UUIDS) || \
+	defined(CONFIG_EFI_PARTITION) || \
+	defined(CONFIG_RANDOM_UUID) || \
+	defined(CONFIG_CMD_UUID) || \
+	defined(CONFIG_BOOTP_PXE)) && \
+	!defined(CONFIG_LIB_UUID)
+#define CONFIG_LIB_UUID
+#endif
+
+#if (defined(CONFIG_RANDOM_UUID) || \
+	defined(CONFIG_CMD_UUID)) && \
+	(!defined(CONFIG_LIB_RAND) && \
+	!defined(CONFIG_LIB_HW_RAND))
+#define CONFIG_LIB_RAND
+#endif
+
+#if defined(CONFIG_API) && defined(CONFIG_LCD)
+#define CONFIG_CMD_BMP
+#endif
+
+#ifndef CONFIG_SYS_PBSIZE
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + 128)
+#endif
+
+#ifndef CONFIG_FIT_SIGNATURE
+#define CONFIG_IMAGE_FORMAT_LEGACY
+#endif
+
+#ifdef CONFIG_DISABLE_IMAGE_LEGACY
+#undef CONFIG_IMAGE_FORMAT_LEGACY
+#endif
+
+#ifdef CONFIG_DM_I2C
+# ifdef CONFIG_SYS_I2C
+#  error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
+# endif
+#endif
+
+#ifndef CONFIG_CMDLINE
+#undef CONFIG_CMDLINE_EDITING
+#undef CONFIG_SYS_LONGHELP
+#undef CONFIG_MENU
+#endif
+
+#endif	/* __CONFIG_FALLBACKS_H */

u-boot/include/config_fsl_chain_trust.h

@@ -0,0 +1,110 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_FSL_CHAIN_TRUST_H
+#define __CONFIG_FSL_CHAIN_TRUST_H
+
+/* For secure boot, since ENVIRONMENT in flash/external memories is
+ * not verified, undef CONFIG_ENV_xxx and set default env
+ * (CONFIG_ENV_IS_NOWHERE)
+ */
+#ifdef CONFIG_SECURE_BOOT
+
+#undef CONFIG_ENV_IS_IN_EEPROM
+#undef CONFIG_ENV_IS_IN_NAND
+#undef CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_SPI_FLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#endif
+
+#ifdef CONFIG_CHAIN_OF_TRUST
+
+#ifndef CONFIG_EXTRA_ENV
+#define CONFIG_EXTRA_ENV	""
+#endif
+
+/*
+ * Control should not reach back to uboot after validation of images
+ * for secure boot flow and therefore bootscript should have
+ * the bootm command. If control reaches back to uboot anyhow
+ * after validating images, core should just spin.
+ */
+
+/*
+ * Define the key hash for boot script here if public/private key pair used to
+ * sign bootscript are different from the SRK hash put in the fuse
+ * Example of defining KEY_HASH is
+ * #define CONFIG_BOOTSCRIPT_KEY_HASH \
+ *	 "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ */
+
+#ifdef CONFIG_BOOTARGS
+#define CONFIG_SET_BOOTARGS	"setenv bootargs \'" CONFIG_BOOTARGS" \';"
+#else
+#define CONFIG_SET_BOOTARGS	"setenv bootargs \'root=/dev/ram "	\
+				"rw console=ttyS0,115200 ramdisk_size=600000\';"
+#endif
+
+
+#ifdef CONFIG_BOOTSCRIPT_KEY_HASH
+#define CONFIG_SECBOOT \
+	"setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
+	CONFIG_SET_BOOTARGS	\
+	CONFIG_EXTRA_ENV	\
+	"esbc_validate $bs_hdraddr " \
+	  __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \
+	"source $img_addr;"	\
+	"esbc_halt\0"
+#else
+#define CONFIG_SECBOOT \
+	"setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
+	CONFIG_SET_BOOTARGS	\
+	CONFIG_EXTRA_ENV	\
+	"esbc_validate $bs_hdraddr;" \
+	"source $img_addr;"	\
+	"esbc_halt\0"
+#endif
+
+#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
+#define CONFIG_BS_COPY_ENV \
+	"setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \
+	"setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \
+	"setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \
+	"setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \
+	"setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \
+	"setenv bs_size " __stringify(CONFIG_BS_SIZE)";"
+
+/* For secure boot flow, default environment used will be used */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_BS_COPY_CMD \
+	"nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \
+	"nand read $bs_ram $bs_flash $bs_size ;"
+#endif /* CONFIG_RAMBOOT_NAND */
+#else
+#define CONFIG_BS_COPY_CMD \
+	"cp.b $bs_hdr_flash $bs_hdr_ram  $bs_hdr_size ;" \
+	"cp.b $bs_flash $bs_ram  $bs_size ;"
+#endif
+#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */
+
+#ifndef CONFIG_BS_COPY_ENV
+#define CONFIG_BS_COPY_ENV
+#endif
+
+#ifndef CONFIG_BS_COPY_CMD
+#define CONFIG_BS_COPY_CMD
+#endif
+
+#define CONFIG_CHAIN_BOOT_CMD	CONFIG_BS_COPY_ENV \
+				CONFIG_BS_COPY_CMD \
+				CONFIG_SECBOOT
+
+#endif
+#endif

u-boot/include/config_phylib_all_drivers.h

@@ -0,0 +1,34 @@
+/*
+ * Enable all PHYs
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * author Andy Fleming
+ *
+ */
+#ifndef _CONFIG_PHYLIB_ALL_H
+#define _CONFIG_PHYLIB_ALL_H
+
+#ifdef CONFIG_PHYLIB
+
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_MARVELL
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_BROADCOM
+#define CONFIG_PHY_DAVICOM
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_NATSEMI
+#define CONFIG_PHY_LXT
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_PHY_SMSC
+
+#ifdef CONFIG_PHYLIB_10G
+#define CONFIG_PHY_TERANETICS
+#endif /* CONFIG_PHYLIB_10G */
+
+#endif /* CONFIG_PHYLIB */
+
+#endif /*_CONFIG_PHYLIB_ALL_H */

u-boot/include/config_uncmd_spl.h

@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2012
+ * Ilya Yanok, ilya.yanok@gmail.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_UNCMD_SPL_H__
+#define __CONFIG_UNCMD_SPL_H__
+
+#ifdef CONFIG_SPL_BUILD
+/* SPL needs only BOOTP + TFTP so undefine other stuff to save space */
+
+#ifndef CONFIG_SPL_DM
+#undef CONFIG_DM_SERIAL
+#undef CONFIG_DM_GPIO
+#undef CONFIG_DM_I2C
+#undef CONFIG_DM_SPI
+#endif
+
+#undef CONFIG_DM_WARN
+#undef CONFIG_DM_STDIO
+
+#endif /* CONFIG_SPL_BUILD */
+#endif /* __CONFIG_UNCMD_SPL_H__ */

u-boot/include/configs/10m50_devboard.h

@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * SERIAL
+ */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress console info */
+#define CONFIG_SYS_NS16550_MEM32
+
+/*
+ * Flash
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_MTD_DEVICE
+
+/*
+ * NET options
+ */
+#define CONFIG_SYS_RX_ETH_BUFFER	0
+#define CONFIG_PHY_GIGE
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_PHY_MARVELL
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * FDT options
+ */
+#define CONFIG_LMB
+
+/*
+ * MEMORY ORGANIZATION
+ * -Monitor at top of sdram.
+ * -The heap is placed below the monitor
+ * -The stack is placed below the heap (&grows down).
+ */
+#define CONFIG_SYS_SDRAM_BASE		0xc8000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_LEN		0x80000	/* Reserve 512k */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_MALLOC_LEN		0x20000
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE			0x10000	/* 64k, 1 sector */
+#define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+#define CONFIG_ENV_ADDR			(0xf4000000 + CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		0xcc000000	/* Half of RAM */
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_ENV_SIZE - \
+					 CONFIG_SYS_MALLOC_LEN -	\
+					 0x10000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#endif /* __CONFIG_H */

u-boot/include/configs/3c120_devboard.h

@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * SERIAL
+ */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress console info */
+
+/*
+ * CFI Flash
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/*
+ * NET options
+ */
+#define CONFIG_SYS_RX_ETH_BUFFER	0
+#define CONFIG_PHY_GIGE
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_PHY_MARVELL
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * FDT options
+ */
+#define CONFIG_LMB
+
+/*
+ * MEMORY ORGANIZATION
+ * -Monitor at top of sdram.
+ * -The heap is placed below the monitor
+ * -The stack is placed below the heap (&grows down).
+ */
+#define CONFIG_SYS_SDRAM_BASE		0xD0000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_LEN		0x80000	/* Reserve 512k */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_MALLOC_LEN		0x20000
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE			0x20000	/* 128k, 1 sector */
+#define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+#define CONFIG_ENV_ADDR			(0xe2800000 + CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		0xd4000000	/* Half of RAM */
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_ENV_SIZE - \
+					 CONFIG_SYS_MALLOC_LEN -	\
+					 0x10000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#endif /* __CONFIG_H */

u-boot/include/configs/B4860QDS.h

@@ -0,0 +1,903 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * B4860 QDS board configuration file
+ */
+#define CONFIG_B4860QDS
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI	$(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW	$(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
+#ifndef CONFIG_NAND
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#else
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFD8000
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+#endif
+#endif
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#ifndef CONFIG_PPC_B4420
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#endif
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR                0x77
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
+#define I2C_CH_DEFAULT                  0x8
+#define I2C_CH_VSC3316                  0xc
+#define I2C_CH_VSC3308                  0xd
+
+#define VSC3316_TX_ADDRESS              0x70
+#define VSC3316_RX_ADDRESS              0x71
+#define VSC3308_TX_ADDRESS              0x02
+#define VSC3308_RX_ADDRESS              0x03
+
+/* IDT clock synthesizers */
+#define CONFIG_IDT8T49N222A
+#define I2C_CH_IDT                     0x9
+
+#define IDT_SERDES1_ADDRESS            0x6E
+#define IDT_SERDES2_ADDRESS            0x6C
+
+/* Voltage monitor on channel 2*/
+#define I2C_MUX_CH_VOL_MONITOR		0xa
+#define I2C_VOL_MONITOR_ADDR		0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+
+#define CONFIG_ZM7300
+#define I2C_MUX_CH_DPM			0xa
+#define I2C_DPM_ADDR			0x28
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+#endif
+
+#if 0
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#endif
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		256 << 10
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_NAND
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_FSL_DDR3
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FSL_DDR_INTERACTIVE
+#endif
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x53
+
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128 * 1024 * 1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) | \
+				FTIM0_NOR_TEADC(0x04) | \
+				FTIM0_NOR_TEAHC(0x20))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x01) | \
+				FTIM2_NOR_TCH(0x0E) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define CONFIG_FSL_QIXIS_V2
+#define QIXIS_BASE		0xffdf0000
+#ifdef CONFIG_PHYS_64BIT
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+#else
+#define QIXIS_BASE_PHYS		QIXIS_BASE
+#endif
+#define QIXIS_LBMAP_SWITCH		0x01
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x02
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(4 * 1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/*
+ * RapidIO
+ */
+#ifdef CONFIG_SYS_SRIO
+#ifdef CONFIG_SRIO1
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
+#endif
+
+#ifdef CONFIG_SRIO2
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
+#endif
+#endif
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+/*
+ * MAPLE
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
+#else
+#define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	25
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE	0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE	0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE	CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE	(CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE	(CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE	(CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	25
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+
+#define CONFIG_SYS_DPAA_RMAN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR	(13 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x10
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x11
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
+#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
+
+/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7	 /*SLOT 1*/
+#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6	 /*SLOT 2*/
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_REGINFO
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#endif
+
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+
+#define CONFIG_BAUDRATE	115200
+
+#define __USB_PHY_TYPE	ulpi
+
+#ifdef CONFIG_PPC_B4860
+#define HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,"	\
+			"bank_intlv=cs0_cs1;"	\
+			"en_cpc:cpc2;"
+#else
+#define	HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	HWCONFIG						\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"			\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=b4860qds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=b4860qds/b4860qds.dtb\0"				\
+	"bdev=sda3\0"
+
+/* For emulation this causes u-boot to jump to the start of the proof point
+   app code automatically */
+#define CONFIG_PROOF_POINTS			\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "cpu 1 release 0x29000000 - - -;"		\
+ "cpu 2 release 0x29000000 - - -;"		\
+ "cpu 3 release 0x29000000 - - -;"		\
+ "cpu 4 release 0x29000000 - - -;"		\
+ "cpu 5 release 0x29000000 - - -;"		\
+ "cpu 6 release 0x29000000 - - -;"		\
+ "cpu 7 release 0x29000000 - - -;"		\
+ "go 0x29000000"
+
+#define CONFIG_HVBOOT	\
+ "setenv bootargs config-addr=0x60000000; "	\
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "cpu 1 release 0x01000000 - - -;"		\
+ "cpu 2 release 0x01000000 - - -;"		\
+ "cpu 3 release 0x01000000 - - -;"		\
+ "cpu 4 release 0x01000000 - - -;"		\
+ "cpu 5 release 0x01000000 - - -;"		\
+ "cpu 6 release 0x01000000 - - -;"		\
+ "cpu 7 release 0x01000000 - - -;"		\
+ "go 0x01000000"
+
+#define CONFIG_LINUX				\
+ "setenv bootargs root=/dev/ram rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "setenv ramdiskaddr 0x02000000;"		\
+ "setenv fdtaddr 0x00c00000;"			\
+ "setenv loadaddr 0x1000000;"			\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */

u-boot/include/configs/BSC9131RDB.h

@@ -0,0 +1,431 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * BSC9131 RDB board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#ifdef CONFIG_BSC9131RDB
+#define CONFIG_BSC9131
+#define CONFIG_NAND_FSL_IFC
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE			/* BOOKE */
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_TSEC_ENET
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on 9131 RDB */
+#if defined(CONFIG_SYS_CLK_100)
+#define CONFIG_SYS_CLK_FREQ    100000000 /* SYSCLK for 9131 RDB */
+#else
+#define CONFIG_SYS_CLK_FREQ	66666666 /* SYSCLK for 9131 RDB */
+#endif
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* enable branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01ffffff
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR3
+#undef CONFIG_SYS_DDR_RAW_TIMING
+#undef CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#define SPD_EEPROM_ADDRESS		0x52 /* I2C access */
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_sdram_size(void);
+#endif
+#define CONFIG_SYS_SDRAM_SIZE		get_sdram_size() /* DDR size */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
+#define CONFIG_SYS_DDR_TIMING_4		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5		0x02401400
+
+#define CONFIG_SYS_DDR_TIMING_3_800		0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_800		0x00110104
+#define CONFIG_SYS_DDR_TIMING_1_800		0x6f6b8644
+#define CONFIG_SYS_DDR_TIMING_2_800		0x0fa888cf
+#define CONFIG_SYS_DDR_CLK_CTRL_800		0x03000000
+#define CONFIG_SYS_DDR_MODE_1_800		0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL_800		0x0c300100
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8675f608
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR	CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
+
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses */
+							/* CONFIG_SYS_IMMR */
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x3FFF_FFFF	DDR			1G cacheable
+ * 0x8800_0000	0x8810_0000	IFC internal SRAM		1M
+ * 0xB000_0000	0xB0FF_FFFF	DSP core M2 memory	16M
+ * 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
+ * 0xC1F0_0000	0xC1F3_FFFF	PA L2 SRAM Region 0	256K
+ * 0xC1F8_0000	0xC1F9_FFFF	PA L2 SRAM Region 1	128K
+ * 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
+ * 0xFF60_0000	0xFF6F_FFFF	DSP CCSR		1M
+ * 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
+ * 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND flash buffer	8M
+ *
+ */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND Flash on IFC */
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	/* Port Size = 8 bit*/ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_2	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+/* NAND Flash Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03)  \
+					| FTIM0_NAND_TWP(0x05)   \
+					| FTIM0_NAND_TWCHT(0x02) \
+					| FTIM0_NAND_TWH(0x04))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1C) \
+					| FTIM1_NAND_TWBE(0x1E) \
+					| FTIM1_NAND_TRR(0x07)  \
+					| FTIM1_NAND_TRP(0x05))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08)  \
+					| FTIM2_NAND_TREH(0x04) \
+					| FTIM2_NAND_TWHRE(0x11))
+#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+/* Set up IFC registers for boot location NAND */
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+
+/* I2C EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* eSPI - Enhanced SPI */
+#ifdef CONFIG_FSL_ESPI
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII			/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		3
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+
+#define TSEC2_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_IRQ
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_REGINFO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT "nand0=ff800000.flash,"
+#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
+			"8m(kernel),512k(dtb),-(fs)"
+/*
+ * Override partitions in device tree using info
+ * in "mtdparts" environment variable
+ */
+#ifdef CONFIG_CMD_MTDPARTS
+#define CONFIG_FDT_FIXUP_PARTITIONS
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_HOSTNAME		BSC9131rdb
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */
+
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" CONFIG_UBOOTPATH "\0"				\
+	"loadaddr=1000000\0"			\
+	"bootfile=uImage\0"	\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=c00000\0"				\
+	"fdtfile=bsc9131rdb.dtb\0"		\
+	"bdev=sda1\0"	\
+	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"	\
+	"bootm_size=0x37000000\0"	\
+	"othbootargs=ramdisk_size=600000 " \
+	"default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
+	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"usb start;"			\
+	"ext2load usb 0:4 $loadaddr $bootfile;"		\
+	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
+	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
+
+#define CONFIG_RAMBOOTCOMMAND		\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif	/* __CONFIG_H */

u-boot/include/configs/BSC9132QDS.h

@@ -0,0 +1,695 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * BSC9132 QDS board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#ifdef CONFIG_BSC9132QDS
+#define CONFIG_BSC9132
+#endif
+
+#define CONFIG_MISC_INIT_R
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769	1
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+#ifdef CONFIG_NAND_SECBOOT
+#define CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0x8ff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0x8ffffffc
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE			/* BOOKE */
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
+#define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
+
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_CMD_PCI
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"PCIe Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xC0010000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xC0010000
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_TSEC_ENET /* ethernet */
+
+#if defined(CONFIG_SYS_CLK_100_DDR_100)
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	100000000
+#elif defined(CONFIG_SYS_CLK_100_DDR_133)
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133000000
+#endif
+
+#define CONFIG_MP
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* enable branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01ffffff
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#define SPD_EEPROM_ADDRESS1		0x54 /* I2C access */
+#define SPD_EEPROM_ADDRESS2		0x56 /* I2C access */
+#define CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_SDRAM_SIZE		(1024)
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+/* DDR3 Controller Settings */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG_1333	0x80004302
+#define CONFIG_SYS_DDR_CS0_CONFIG_800	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CONFIG_SYS_DDR1_CS0_BNDS       0x0040007F
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL_800		0x470C0000
+#define CONFIG_SYS_DDR_CONTROL_2_800	0x04401050
+#define CONFIG_SYS_DDR_TIMING_4_800		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5_800		0x03402400
+
+#define CONFIG_SYS_DDR_CONTROL_1333		0x470C0008
+#define CONFIG_SYS_DDR_CONTROL_2_1333	0x24401010
+#define CONFIG_SYS_DDR_TIMING_4_1333		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5_1333		0x03401400
+
+#define CONFIG_SYS_DDR_TIMING_3_800		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800		0x00330004
+#define CONFIG_SYS_DDR_TIMING_1_800		0x6f6B4846
+#define CONFIG_SYS_DDR_TIMING_2_800		0x0FA8C8CF
+#define CONFIG_SYS_DDR_CLK_CTRL_800		0x03000000
+#define CONFIG_SYS_DDR_MODE_1_800		0x40461520
+#define CONFIG_SYS_DDR_MODE_2_800		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL_800		0x0C300000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8655A608
+
+#define CONFIG_SYS_DDR_TIMING_3_1333		0x01061000
+#define CONFIG_SYS_DDR_TIMING_0_1333		0x00440104
+#define CONFIG_SYS_DDR_TIMING_1_1333		0x98913A45
+#define CONFIG_SYS_DDR_TIMING_2_1333		0x0FB8B114
+#define CONFIG_SYS_DDR_CLK_CTRL_1333		0x02800000
+#define CONFIG_SYS_DDR_MODE_1_1333		0x00061A50
+#define CONFIG_SYS_DDR_MODE_2_1333		0x00100000
+#define CONFIG_SYS_DDR_INTERVAL_1333		0x144E0513
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333	0x8655F607
+
+/*FIXME: the following params are constant w.r.t diff freq
+combinations. this should be removed later
+*/
+#if CONFIG_DDR_CLK_FREQ == 100000000
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
+#define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_800
+#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
+#define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_800
+#define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_800
+#elif CONFIG_DDR_CLK_FREQ == 133000000
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
+#define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_1333
+#define CONFIG_SYS_DDR_CONTROL_2	CONFIG_SYS_DDR_CONTROL_2_1333
+#define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_1333
+#define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_1333
+#else
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
+#define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_800
+#define CONFIG_SYS_DDR_CONTROL_2	CONFIG_SYS_DDR_CONTROL_2_800
+#define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_800
+#define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_800
+#endif
+
+/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR	CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
+
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR
+
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+#define CONFIG_SYS_FLASH_BASE		0x88000000
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* Max number of sector: 32M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_NOR_CSPR	0x88000101
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(5)
+/* NOR Flash Timing Params */
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) \
+				| FTIM0_NOR_TEADC(0x03) \
+				| FTIM0_NOR_TAVDS(0x00) \
+				| FTIM0_NOR_TEAHC(0x0f))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1d) \
+				| FTIM1_NOR_TRAD_NOR(0x09) \
+				| FTIM1_NOR_TSEQRAD_NOR(0x09))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x1) \
+				| FTIM2_NOR_TCH(0x4) \
+				| FTIM2_NOR_TWPH(0x7) \
+				| FTIM2_NOR_TWP(0x1e))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+/* CFI for NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* NAND Flash on IFC */
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_2	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+/* NAND Flash Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03) \
+					| FTIM0_NAND_TWP(0x05) \
+					| FTIM0_NAND_TWCHT(0x02) \
+					| FTIM0_NAND_TWH(0x04))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1c) \
+					| FTIM1_NAND_TWBE(0x1e) \
+					| FTIM1_NAND_TRR(0x07) \
+					| FTIM1_NAND_TRP(0x05))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08) \
+					| FTIM2_NAND_TREH(0x04) \
+					| FTIM2_NAND_TWHRE(0x11))
+#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+/* NAND */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FSL_QIXIS
+#endif
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_SYS_FPGA_BASE	0xffb00000
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_BASE	CONFIG_SYS_FPGA_BASE
+#define QIXIS_LBMAP_SWITCH	9
+#define QIXIS_LBMAP_MASK	0x07
+#define QIXIS_LBMAP_SHIFT	0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x83
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+
+#define CONFIG_SYS_FPGA_BASE_PHYS	CONFIG_SYS_FPGA_BASE
+
+#define CONFIG_SYS_CSPR2		(CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
+					| CSPR_PORT_SIZE_8 \
+					| CSPR_MSEL_GPCM \
+					| CSPR_V)
+#define CONFIG_SYS_AMASK2		IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2		0x0
+/* CPLD Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+#endif
+
+/* Set up IFC registers for boot location NOR/NAND */
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR + 0x4700)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR + 0x4800)
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400800 /* I2C speed and slave address*/
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400800 /* I2C speed and slave address*/
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C EEPROM */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* I2C FPGA */
+#define CONFIG_I2C_FPGA
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+
+#define CONFIG_RTC_DS3231
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * SPI interface will not be available in case of NAND boot SPI CS0 will be
+ * used for SLIC
+ */
+/* eSPI - Enhanced SPI */
+#ifdef CONFIG_FSL_ESPI
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII			/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+/* TBI PHY configuration for SGMII mode */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+		TBICR_PHY_RESET \
+		| TBICR_ANEG_ENABLE \
+		| TBICR_FULL_DUPLEX \
+		| TBICR_SPEED1_SET \
+		)
+
+#endif	/* CONFIG_TSEC_ENET */
+
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#define CONFIG_USB_EHCI  /* USB */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE			0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash,"
+#define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \
+			"55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \
+			"8m(kernel),512k(dtb),-(fs)"
+#endif
+/*
+ * Override partitions in device tree using info
+ * in "mtdparts" environment variable
+ */
+#ifdef CONFIG_CMD_MTDPARTS
+#define CONFIG_FDT_FIXUP_PARTITIONS
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME		BSC9132qds
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+
+#define CONFIG_BAUDRATE		115200
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_DEF_HWCONFIG	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+#else
+#define CONFIG_DEF_HWCONFIG	"hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" CONFIG_UBOOTPATH "\0"				\
+	"loadaddr=1000000\0"			\
+	"bootfile=uImage\0"	\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=c00000\0"				\
+	"fdtfile=bsc9132qds.dtb\0"		\
+	"bdev=sda1\0"	\
+	CONFIG_DEF_HWCONFIG\
+	"othbootargs=mem=880M ramdisk_size=600000 " \
+		"default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
+		"isolcpus=0\0" \
+	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
+		"console=$consoledev,$baudrate $othbootargs; "	\
+		"usb start;"			\
+		"ext2load usb 0:4 $loadaddr $bootfile;"		\
+		"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
+		"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
+	"debug_halt_off=mw ff7e0e30 0xf0000000;"
+
+#define CONFIG_NFSBOOTCOMMAND	\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "	\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;" \
+	"tftp $loadaddr $bootfile;"	\
+	"tftp $fdtaddr $fdtfile;"	\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT	\
+	"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
+	"console=$consoledev,$baudrate $othbootargs;" \
+	"usb start;"	\
+	"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
+	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */

u-boot/include/configs/C29XPCIE.h

@@ -0,0 +1,549 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * C29XPCIE board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PHYS_64BIT
+#define CONFIG_DISPLAY_BOARDINFO
+
+#ifdef CONFIG_C29XPCIE
+#define CONFIG_PPC_C29X
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifdef CONFIG_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE		0xff800000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE			/* BOOKE */
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
+#define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
+
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#ifdef CONFIG_PCI
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_CMD_PCI
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_TSEC_ENET
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ	100000000
+#define CONFIG_SYS_CLK_FREQ	66666666
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_PANIC_HANG
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#define SPD_EEPROM_ADDRESS		0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/* DDR ECC Setup*/
+#define CONFIG_DDR_ECC
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+
+#define CONFIG_SYS_SDRAM_SIZE		512
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* Platform SRAM setting  */
+#define CONFIG_SYS_PLATFORM_SRAM_BASE	0xffb00000
+#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
+			(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
+#define CONFIG_SYS_PLATFORM_SRAM_SIZE	(512 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+#define CONFIG_SYS_FLASH_BASE		0xec000000
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* in ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* in ms */
+
+/* 16Bit NOR Flash - S29GL512S10TFI01 */
+#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(64*1024*1024)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+/* CFI for NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(1024 * 1024)
+
+/* 8Bit NAND Flash - K9F1G08U0B */
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_NAND \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_OOBSIZE	0x00000280	/* 640b */
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
+				| CSOR_NAND_PGS_8K	/* Page Size = 8K */ \
+				| CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
+				| CSOR_NAND_PB(128))	/*128 Pages Per Block*/
+#define CONFIG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x01) | \
+				FTIM0_NAND_TWP(0x0c)   | \
+				FTIM0_NAND_TWCHT(0x08) | \
+				FTIM0_NAND_TWH(0x06))
+#define CONFIG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x28) | \
+				FTIM1_NAND_TWBE(0x1d)  | \
+				FTIM1_NAND_TRR(0x08)   | \
+				FTIM1_NAND_TRP(0x0c))
+#define CONFIG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x0c) | \
+				FTIM2_NAND_TREH(0x0a) | \
+				FTIM2_NAND_TWHRE(0x18))
+#define CONFIG_SYS_NAND_FTIM3	(FTIM3_NAND_TWW(0x04))
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT		CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR1_EXT		CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+/* CPLD on IFC, selected by CS2 */
+#define CONFIG_SYS_CPLD_BASE		0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull \
+					| CONFIG_SYS_CPLD_BASE)
+
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2	0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
+				FTIM0_GPCM_TEADC(0x0e) | \
+				FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1	(FTIM1_GPCM_TACO(0x0e) | \
+				FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2	(FTIM2_GPCM_TCS(0x0e) | \
+				FTIM2_GPCM_TCH(0x8) | \
+				FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3	0x0
+
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C EEPROM */
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* eSPI - Enhanced SPI */
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_MII			/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+/* Default mode is RGMII mode */
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		2
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE	CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET	CONFIG_SYS_NAND_BLOCK_SIZE
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_REGINFO
+
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_DEF_HWCONFIG	fsl_ddr:ecc=on
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"	\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"loadaddr=1000000\0"				\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"				\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=c00000\0"				\
+	"fdtfile=name/of/device-tree.dtb\0"			\
+	"othbootargs=ramdisk_size=600000\0"		\
+
+#define CONFIG_RAMBOOTCOMMAND			\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */

u-boot/include/configs/CPCI2DP.h

@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0280	/* PCI Class Code: Network/Other*/
+
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA	0xef000000	/* point to internal regs + PB0/1 */
+#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+#define CONFIG_SYS_EEPROM_WREN         1
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0               /* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (PB0) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (PB1) initialization				*/
+#define CONFIG_SYS_EBC_PB3AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * GPIO definitions
+ */
+#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 13)   /* GPIO13 */
+#define CONFIG_SYS_SELF_RST		(0x80000000 >> 14)   /* GPIO14 */
+#define CONFIG_SYS_PB_LED		(0x80000000 >> 16)   /* GPIO16 */
+#define CONFIG_SYS_INTA_FAKE		(0x80000000 >> 23)   /* GPIO23 */
+
+#endif	/* __CONFIG_H */

u-boot/include/configs/CPCI4052.h

@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
+#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
+#undef  CONFIG_CPCI405_6U               /* enable this for 6U boards    */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	 1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
+
+#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
+#define CONFIG_ENV_ADDR		\
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+#endif
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_LED_ADDR		0xF0000380
+
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+/*#define CONFIG_SYS_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CONFIG_SYS_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 5 (optional Quart) initialization				*/
+#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 6 (FPGA internal) initialization					*/
+#define CONFIG_SYS_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	    0x0001
+#define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
+#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	    0x2000
+
+/* FPGA Status Reg */
+#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
+#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#endif	/* __CONFIG_H */

u-boot/include/configs/M5208EVBE.h

@@ -0,0 +1,201 @@
+/*
+ * Configuation settings for the Freescale MCF5208EVBe.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _M5208EVBE_H
+#define _M5208EVBE_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE			115200
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT		5000
+
+/* Command line configuration */
+#define CONFIG_CMD_REGINFO
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#endif				/* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME		M5208EVBe
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off 0 3ffff;"		\
+	"era 0 3ffff;"				\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Arg Buf Sz */
+#define CONFIG_SYS_LOAD_ADDR	0x40010000
+
+#define CONFIG_SYS_CLK		166666666	/* CPU Core Clock */
+#define CONFIG_SYS_PLL_ODR	0x36
+#define CONFIG_SYS_PLL_FDR	0x7D
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x43711630
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1002000
+#define CONFIG_SYS_SDRAM_EMOD		0x80010000
+#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER		1
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	254	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+/*
+ * Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET		0x2000
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x2000
+#define CONFIG_ENV_IS_IN_FLASH		1
+
+#define LDS_BOARD_TEXT \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o (.text*);
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/* Chipselect bank definitions */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x007F0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+
+#endif				/* _M5208EVBE_H */

u-boot/include/configs/M52277EVB.h

@@ -0,0 +1,305 @@
+/*
+ * Configuation settings for the Freescale MCF52277 EVB board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M52277EVB_H
+#define _M52277EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_M52277EVB	/* M52277EVB board */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE			115200
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_REGINFO
+#undef CONFIG_CMD_BMP
+
+#define CONFIG_HOSTNAME			M52277EVB
+#define CONFIG_SYS_UBOOT_END		0x3FFFF
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
+#ifdef CONFIG_SYS_STMICRO_BOOT
+/* ST Micro serial flash */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=loadb ${loadaddr} ${baudrate};"	\
+	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
+	"upd=run load; run prog\0"		\
+	"prog=sf probe 0:2 10000 1;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
+	"save\0"				\
+	""
+#endif
+#ifdef CONFIG_SYS_SPANSION_BOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=loadb ${loadaddr} ${baudrate}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
+	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
+	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
+	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" ${filesize}; save\0"			\
+	"updsbf=run loadsbf; run progsbf\0"	\
+	"loadsbf=loadb ${loadaddr} ${baudrate};"	\
+	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
+	"progsbf=sf probe 0:2 10000 1;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
+	""
+#endif
+
+/* LCD */
+#ifdef CONFIG_CMD_BMP
+#define CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_LCD_LOGO
+#define CONFIG_SHARP_LQ035Q7DH06
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SYS_USB_EHCI_REGS_BASE	0xFC0B0000
+#define CONFIG_SYS_USB_EHCI_CPU_INIT
+#endif
+
+/* Realtime clock */
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
+#define CONFIG_CF_DSPI
+#define CONFIG_HARD_SPI
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+#ifdef CONFIG_CMD_SPI
+#	define CONFIG_SYS_DSPI_CS2
+
+#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
+					 DSPI_CTAR_PCSSCK_1CLK | \
+					 DSPI_CTAR_PASC(0) | \
+					 DSPI_CTAR_PDT(0) | \
+					 DSPI_CTAR_CSSCK(0) | \
+					 DSPI_CTAR_ASC(0) | \
+					 DSPI_CTAR_DT(1))
+#endif
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_SYS_INPUT_CLKSRC	16000000
+
+#define CONFIG_PRAM		2048	/* 2048 KB */
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x43711630
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x81810000
+#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x00
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*
+ * Configuration for environment
+ * Environment is not embedded in u-boot. First time runing may have env
+ * crc error warning if there is no correct environment on the flash.
+ */
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_ENV_IS_IN_SPI_FLASH
+#	define CONFIG_ENV_SPI_CS	2
+#else
+#	define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+#define CONFIG_ENV_OVERWRITE		1
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_STMICRO_BOOT
+#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_ENV_OFFSET	0x30000
+#	define CONFIG_ENV_SIZE		0x1000
+#	define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#ifdef CONFIG_SYS_SPANSION_BOOT
+#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#	define CONFIG_ENV_SIZE		0x1000
+#	define CONFIG_ENV_SECT_SIZE	0x8000
+#endif
+
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#	define CONFIG_FLASH_SPANSION_S29WS_N	1
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
+#endif
+
+#define LDS_BOARD_TEXT \
+        arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
+	arch/m68k/lib/built-in.o            (.text*)
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#	define CONFIG_JFFS2_DEV		"nor0"
+#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x40000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x40000)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+#ifdef CONFIG_CF_SBF
+#define CONFIG_SYS_CS0_BASE		0x04000000
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#else
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#endif
+
+#endif				/* _M52277EVB_H */

u-boot/include/configs/M5235EVB.h

@@ -0,0 +1,237 @@
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5235EVB_H
+#define _M5235EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_REGINFO
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_i2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_I2C_PINMUX_REG	(gpio->par_qspi)
+#define CONFIG_SYS_I2C_PINMUX_CLR	~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
+#define CONFIG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#define CONFIG_BOOTFILE		"u-boot.bin"
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		M5235EVB
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b ${loadaddr} ffe00000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_KGDB)
+#	define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#	define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE+0x20000)
+
+#define CONFIG_SYS_CLK			75000000
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
+
+#define CONFIG_SYS_MBAR		0x40000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#ifdef NORFLASH_PS32BIT
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
+#else
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#endif
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text);
+
+#ifdef NORFLASH_PS32BIT
+#	define CONFIG_ENV_OFFSET		(0x8000)
+#	define CONFIG_ENV_SIZE		0x4000
+#	define CONFIG_ENV_SECT_SIZE	0x4000
+#else
+#	define CONFIG_ENV_OFFSET		(0x4000)
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x2000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ * CS6 - Available
+ * CS7 - Available
+ */
+#ifdef NORFLASH_PS32BIT
+#	define CONFIG_SYS_CS0_BASE	0xFFC00000
+#	define CONFIG_SYS_CS0_MASK	0x003f0001
+#	define CONFIG_SYS_CS0_CTRL	0x00001D00
+#else
+#	define CONFIG_SYS_CS0_BASE	0xFFE00000
+#	define CONFIG_SYS_CS0_MASK	0x001f0001
+#	define CONFIG_SYS_CS0_CTRL	0x00001D80
+#endif
+
+#endif				/* _M5329EVB_H */

u-boot/include/configs/M5249EVB.h

@@ -0,0 +1,186 @@
+/*
+ * Configuation settings for the esd TASREG board.
+ *
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5249EVB_H
+#define _M5249EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef  CONFIG_WATCHDOG
+
+#undef CONFIG_MONITOR_IS_IN_RAM		/* no pre-loader required!!! ;-) */
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup	*/
+#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support	*/
+#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
+
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+/*
+ * Clock configuration: enable only one of the following options
+ */
+
+#undef  CONFIG_SYS_PLL_BYPASS				/* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
+#define	CONFIG_SYS_CLK			132025600	/* MCF5249 can run at 140MHz   */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define	CONFIG_SYS_MBAR2		0x80000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+
+#define LDS_BOARD_TEXT \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o (.text);
+
+#define CONFIG_ENV_OFFSET		0x4000	/* Address of Environment Sector*/
+#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	0x2000 /* see README - env sector total size	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+
+#if 0 /* test-only */
+#define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define	CONFIG_SYS_CS0_BASE		0xffe00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
+/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
+
+/* CS1 - FPGA, address 0xe0000000 */
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define	CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
+#define	CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
+#define	CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define	CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led                     */
+
+#endif	/* M5249 */