avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/drivers/watchdog/Makefile

@@ -0,0 +1,18 @@
+#
+# (C) Copyright 2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
+obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
+ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610))
+obj-y += imx_watchdog.o
+endif
+obj-$(CONFIG_S5P)               += s5p_wdt.o
+obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
+obj-$(CONFIG_BFIN_WATCHDOG)  += bfin_wdt.o
+obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
+obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
+obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o

u-boot/drivers/watchdog/at91sam9_wdt.c

@@ -0,0 +1,81 @@
+/*
+ * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
+ *
+ * Watchdog driver for Atmel AT91SAM9x processors.
+ *
+ * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * The Watchdog Timer Mode Register can be only written to once. If the
+ * timeout need to be set from U-Boot, be sure that the bootstrap doesn't
+ * write to this register. Inform Linux to it too
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/at91_wdt.h>
+
+/*
+ * AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
+ * use this to convert a watchdog
+ * value from/to milliseconds.
+ */
+#define ms_to_ticks(t)	(((t << 8) / 1000) - 1)
+#define ticks_to_ms(t)	(((t + 1) * 1000) >> 8)
+
+/* Hardware timeout in seconds */
+#if !defined(CONFIG_AT91_HW_WDT_TIMEOUT)
+#define WDT_HW_TIMEOUT 2
+#else
+#define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT
+#endif
+
+/*
+ * Set the watchdog time interval in 1/256Hz (write-once)
+ * Counter is 12 bit.
+ */
+static int at91_wdt_settimeout(unsigned int timeout)
+{
+	unsigned int reg;
+	at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
+
+	/* Check if disabled */
+	if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) {
+		printf("sorry, watchdog is disabled\n");
+		return -1;
+	}
+
+	/*
+	 * All counting occurs at SLOW_CLOCK / 128 = 256 Hz
+	 *
+	 * Since WDV is a 12-bit counter, the maximum period is
+	 * 4096 / 256 = 16 seconds.
+	 */
+
+	reg = AT91_WDT_MR_WDRSTEN		/* causes watchdog reset */
+		| AT91_WDT_MR_WDDBGHLT		/* disabled in debug mode */
+		| AT91_WDT_MR_WDD(0xfff)	/* restart at any time */
+		| AT91_WDT_MR_WDV(timeout);	/* timer value */
+
+	writel(reg, &wd->mr);
+
+	return 0;
+}
+
+void hw_watchdog_reset(void)
+{
+	at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
+	writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr);
+}
+
+void hw_watchdog_init(void)
+{
+	/* 16 seconds timer, resets enabled */
+	at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
+}

u-boot/drivers/watchdog/bfin_wdt.c

@@ -0,0 +1,27 @@
+/*
+ * watchdog.c - driver for Blackfin on-chip watchdog
+ *
+ * Copyright (c) 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/blackfin.h>
+#include <asm/clock.h>
+#include <asm/mach-common/bits/watchdog.h>
+
+void hw_watchdog_reset(void)
+{
+	bfin_write_WDOG_STAT(0);
+}
+
+void hw_watchdog_init(void)
+{
+	bfin_write_WDOG_CTL(WDDIS);
+	SSYNC();
+	bfin_write_WDOG_CNT(CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000 * get_sclk());
+	hw_watchdog_reset();
+	bfin_write_WDOG_CTL(WDEN);
+}

u-boot/drivers/watchdog/designware_wdt.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/utils.h>
+
+#define DW_WDT_CR	0x00
+#define DW_WDT_TORR	0x04
+#define DW_WDT_CRR	0x0C
+
+#define DW_WDT_CR_EN_OFFSET	0x00
+#define DW_WDT_CR_RMOD_OFFSET	0x01
+#define DW_WDT_CR_RMOD_VAL	0x00
+#define DW_WDT_CRR_RESTART_VAL	0x76
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+static int designware_wdt_settimeout(unsigned int timeout)
+{
+	signed int i;
+
+	/* calculate the timeout range value */
+	i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
+	if (i > 15)
+		i = 15;
+	if (i < 0)
+		i = 0;
+
+	writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
+	return 0;
+}
+
+static void designware_wdt_enable(void)
+{
+	writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
+	      (0x1 << DW_WDT_CR_EN_OFFSET)),
+	      (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+}
+
+static unsigned int designware_wdt_is_enabled(void)
+{
+	unsigned long val;
+	val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
+	return val & 0x1;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+	if (designware_wdt_is_enabled())
+		/* restart the watchdog counter */
+		writel(DW_WDT_CRR_RESTART_VAL,
+		       (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+}
+
+void hw_watchdog_init(void)
+{
+	/* reset to disable the watchdog */
+	hw_watchdog_reset();
+	/* set timer in miliseconds */
+	designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);
+	/* enable the watchdog */
+	designware_wdt_enable();
+	/* reset the watchdog */
+	hw_watchdog_reset();
+}
+#endif

u-boot/drivers/watchdog/ftwdt010_wdt.c

@@ -0,0 +1,92 @@
+/*
+ * Watchdog driver for the FTWDT010 Watch Dog Driver
+ *
+ * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com)
+ * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu>
+ * Based on SoftDog driver by Alan Cox <alan@redhat.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * 27/11/2004 Initial release, Faraday.
+ * 12/01/2011 Port to u-boot, Macpaul Lin.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+int ftwdt010_wdt_settimeout(unsigned int timeout)
+{
+	unsigned int reg;
+
+	struct ftwdt010_wdt *wd = (struct ftwdt010_wdt *)CONFIG_FTWDT010_BASE;
+
+	debug("Activating WDT..\n");
+
+	/* Check if disabled */
+	if (readl(&wd->wdcr) & ~FTWDT010_WDCR_ENABLE) {
+		printf("sorry, watchdog is disabled\n");
+		return -1;
+	}
+
+	/*
+	 * In a 66MHz system,
+	 * if you set WDLOAD as 0x03EF1480 (66000000)
+	 * the reset timer is 1 second.
+	 */
+	reg = FTWDT010_WDLOAD(timeout * FTWDT010_TIMEOUT_FACTOR);
+
+	writel(reg, &wd->wdload);
+
+	return 0;
+}
+
+void ftwdt010_wdt_reset(void)
+{
+	struct ftwdt010_wdt *wd = (struct ftwdt010_wdt *)CONFIG_FTWDT010_BASE;
+
+	/* clear control register */
+	writel(0, &wd->wdcr);
+
+	/* Write Magic number */
+	writel(FTWDT010_WDRESTART_MAGIC, &wd->wdrestart);
+
+	/* Enable WDT */
+	writel((FTWDT010_WDCR_RST | FTWDT010_WDCR_ENABLE), &wd->wdcr);
+}
+
+void ftwdt010_wdt_disable(void)
+{
+	struct ftwdt010_wdt *wd = (struct ftwdt010_wdt *)CONFIG_FTWDT010_BASE;
+
+	debug("Deactivating WDT..\n");
+
+	/*
+	 * It was defined with CONFIG_WATCHDOG_NOWAYOUT in Linux
+	 *
+	 * Shut off the timer.
+	 * Lock it in if it's a module and we defined ...NOWAYOUT
+	 */
+	writel(0, &wd->wdcr);
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+	ftwdt010_wdt_reset();
+}
+
+void hw_watchdog_init(void)
+{
+	/* set timer in ms */
+	ftwdt010_wdt_settimeout(CONFIG_FTWDT010_HW_TIMEOUT * 1000);
+}
+#endif

u-boot/drivers/watchdog/imx_watchdog.c

@@ -0,0 +1,55 @@
+/*
+ * watchdog.c - driver for i.mx on-chip watchdog
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <watchdog.h>
+#include <asm/arch/imx-regs.h>
+#include <fsl_wdog.h>
+
+#ifdef CONFIG_IMX_WATCHDOG
+void hw_watchdog_reset(void)
+{
+	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+	writew(0x5555, &wdog->wsr);
+	writew(0xaaaa, &wdog->wsr);
+}
+
+void hw_watchdog_init(void)
+{
+	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+	u16 timeout;
+
+	/*
+	 * The timer watchdog can be set between
+	 * 0.5 and 128 Seconds. If not defined
+	 * in configuration file, sets 128 Seconds
+	 */
+#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
+#endif
+	timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
+	writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
+		SET_WCR_WT(timeout), &wdog->wcr);
+	hw_watchdog_reset();
+}
+#endif
+
+void reset_cpu(ulong addr)
+{
+	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+	clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
+
+	writew(0x5555, &wdog->wsr);
+	writew(0xaaaa, &wdog->wsr);	/* load minimum 1/2 second timeout */
+	while (1) {
+		/*
+		 * spin for .5 seconds before reset
+		 */
+	}
+}

u-boot/drivers/watchdog/omap_wdt.c

@@ -0,0 +1,121 @@
+/*
+ * omap_wdt.c
+ *
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * Based on:
+ *
+ * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
+ *
+ * commit 2d991a164a61858012651e13c59521975504e260
+ * Author: Bill Pemberton <wfp5p@virginia.edu>
+ * Date:   Mon Nov 19 13:21:41 2012 -0500
+ *
+ * watchdog: remove use of __devinit
+ *
+ * CONFIG_HOTPLUG is going away as an option so __devinit is no longer
+ * needed.
+ *
+ * Author: MontaVista Software, Inc.
+ *	 <gdavis@mvista.com> or <source@mvista.com>
+ *
+ * History:
+ *
+ * 20030527: George G. Davis <gdavis@mvista.com>
+ *	Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
+ *	(c) Copyright 2000 Oleg Drokin <green@crimea.edu>
+ *	Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
+ *
+ * Copyright (c) 2004 Texas Instruments.
+ *	1. Modified to support OMAP1610 32-KHz watchdog timer
+ *	2. Ported to 2.6 kernel
+ *
+ * Copyright (c) 2005 David Brownell
+ *	Use the driver model and standard identifiers; handle bigger timeouts.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/cpu.h>
+
+/* Hardware timeout in seconds */
+#define WDT_HW_TIMEOUT 60
+
+static unsigned int wdt_trgr_pattern = 0x1234;
+
+void hw_watchdog_reset(void)
+{
+	struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+
+	/* wait for posted write to complete */
+	while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
+		;
+
+	wdt_trgr_pattern = ~wdt_trgr_pattern;
+	writel(wdt_trgr_pattern, &wdt->wdtwtgr);
+
+	/* wait for posted write to complete */
+	while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR))
+		;
+}
+
+static int omap_wdt_set_timeout(unsigned int timeout)
+{
+	struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+	u32 pre_margin = GET_WLDR_VAL(timeout);
+
+	/* just count up at 32 KHz */
+	while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
+		;
+
+	writel(pre_margin, &wdt->wdtwldr);
+	while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
+		;
+
+	return 0;
+}
+
+void hw_watchdog_init(void)
+{
+	struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+
+	/* initialize prescaler */
+	while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
+		;
+
+	writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr);
+	while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
+		;
+
+	omap_wdt_set_timeout(WDT_HW_TIMEOUT);
+
+	/* Sequence to enable the watchdog */
+	writel(0xBBBB, &wdt->wdtwspr);
+	while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
+		;
+
+	writel(0x4444, &wdt->wdtwspr);
+	while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
+		;
+}
+
+void hw_watchdog_disable(void)
+{
+	struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+
+	/*
+	 * Disable watchdog
+	 */
+	writel(0xAAAA, &wdt->wdtwspr);
+	while (readl(&wdt->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdt->wdtwspr);
+	while (readl(&wdt->wdtwwps) != 0x0)
+		;
+}

u-boot/drivers/watchdog/s5p_wdt.c

@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/watchdog.h>
+
+#define PRESCALER_VAL 255
+
+void wdt_stop(void)
+{
+	struct s5p_watchdog *wdt =
+		(struct s5p_watchdog *)samsung_get_base_watchdog();
+	unsigned int wtcon;
+
+	wtcon = readl(&wdt->wtcon);
+	wtcon &= ~(WTCON_EN | WTCON_INT | WTCON_RESET);
+
+	writel(wtcon, &wdt->wtcon);
+}
+
+void wdt_start(unsigned int timeout)
+{
+	struct s5p_watchdog *wdt =
+		(struct s5p_watchdog *)samsung_get_base_watchdog();
+	unsigned int wtcon;
+
+	wdt_stop();
+
+	wtcon = readl(&wdt->wtcon);
+	wtcon |= (WTCON_EN | WTCON_CLK(WTCON_CLK_128));
+	wtcon &= ~WTCON_INT;
+	wtcon |= WTCON_RESET;
+	wtcon |= WTCON_PRESCALER(PRESCALER_VAL);
+
+	writel(timeout, &wdt->wtdat);
+	writel(timeout, &wdt->wtcnt);
+	writel(wtcon, &wdt->wtcon);
+}

u-boot/drivers/watchdog/tegra_wdt.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright 2016 Avionic Design GmbH
+ * Copyright 2016 Julian Scheel <julian@jusst.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/wdt.h>
+#include <asm/arch-tegra/tegra.h>
+
+/* Timeout in seconds */
+#define WDT_TIMEOUT 60
+
+/* Timer to use - 5 is used in linux kernel */
+#define WDT_TIMER_ID 5
+void hw_watchdog_init(void)
+{
+	struct timer_ctrl *timer = (struct timer_ctrl *)NV_PA_TMR5_BASE;
+	struct wdt_ctrl *wdt = (struct wdt_ctrl *)NV_PA_TMRWDT0_BASE;
+	u32 val;
+
+	/* Timer runs fixed at 1 MHz, reset is triggered at 4th timeout of
+	 * timer */
+	val = 1000000ul / 4;
+	val |= (TIMER_PTV_EN | TIMER_PTV_PERIODIC);
+	writel(val, &timer->ptv);
+
+	/* Setup actual wdt */
+	val = WDT_TIMER_ID |
+		((WDT_TIMEOUT << WDT_CFG_PERIOD_SHIFT) & WDT_CFG_PERIOD_MASK) |
+		WDT_CFG_PMC2CAR_RST_EN;
+	writel(val, &wdt->config);
+
+	/* Activate the wdt */
+	writel(WDT_CMD_START_COUNTER, &wdt->command);
+}
+
+void hw_watchdog_reset(void)
+{
+	struct wdt_ctrl *wdt = (struct wdt_ctrl *)NV_PA_TMRWDT0_BASE;
+
+	/* Activate the wdt */
+	writel(WDT_CMD_START_COUNTER, &wdt->command);
+}
+
+void hw_watchdog_disable(void)
+{
+	struct timer_ctrl *timer = (struct timer_ctrl *)NV_PA_TMR5_BASE;
+	struct wdt_ctrl *wdt = (struct wdt_ctrl *)NV_PA_TMRWDT0_BASE;
+
+	/* Write unlock pattern */
+	writel(WDT_UNLOCK_PATTERN, &wdt->unlock);
+	/* Disable wdt */
+	writel(WDT_CMD_DISABLE_COUNTER, &wdt->command);
+	/* Stop timer */
+	writel(0, &timer->ptv);
+}

u-boot/drivers/watchdog/xilinx_tb_wdt.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2011-2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/microblaze_intc.h>
+#include <asm/processor.h>
+#include <watchdog.h>
+
+#define XWT_CSR0_WRS_MASK	0x00000008 /* Reset status Mask */
+#define XWT_CSR0_WDS_MASK	0x00000004 /* Timer state Mask */
+#define XWT_CSR0_EWDT1_MASK	0x00000002 /* Enable bit 1 Mask*/
+#define XWT_CSRX_EWDT2_MASK	0x00000001 /* Enable bit 2 Mask */
+
+struct watchdog_regs {
+	u32 twcsr0; /* 0x0 */
+	u32 twcsr1; /* 0x4 */
+	u32 tbr; /* 0x8 */
+};
+
+static struct watchdog_regs *watchdog_base =
+			(struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR;
+
+void hw_watchdog_reset(void)
+{
+	u32 reg;
+
+	/* Read the current contents of TCSR0 */
+	reg = readl(&watchdog_base->twcsr0);
+
+	/* Clear the watchdog WDS bit */
+	if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
+		writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0);
+}
+
+void hw_watchdog_disable(void)
+{
+	u32 reg;
+
+	/* Read the current contents of TCSR0 */
+	reg = readl(&watchdog_base->twcsr0);
+
+	writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0);
+	writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
+
+	puts("Watchdog disabled!\n");
+}
+
+static void hw_watchdog_isr(void *arg)
+{
+	hw_watchdog_reset();
+}
+
+void hw_watchdog_init(void)
+{
+	int ret;
+
+	writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
+	       &watchdog_base->twcsr0);
+	writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
+
+	ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ,
+						hw_watchdog_isr, NULL);
+	if (ret)
+		puts("Watchdog IRQ registration failed.");
+}