avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/drivers/pwm/Kconfig

@@ -0,0 +1,37 @@
+config DM_PWM
+	bool "Enable support for pulse-width modulation devices (PWM)"
+	depends on DM
+	help
+	  A pulse-width modulator emits a pulse of varying width and provides
+	  control over the duty cycle (high and low time) of the signal. This
+	  is often used to control a voltage level. The more time the PWM
+	  spends in the 'high' state, the higher the voltage. The PWM's
+	  frequency/period can be controlled along with the proportion of that
+	  time that the signal is high.
+
+config PWM_EXYNOS
+	bool "Enable support for the Exynos PWM"
+	depends on DM_PWM
+	help
+	  This PWM is found on Samsung Exynos 5250 and other Samsung SoCs. It
+	  supports a programmable period and duty cycle. A 32-bit counter is
+	  used. It provides 5 channels which can be independently
+	  programmed. Channel 4 (the last) is normally used as a timer.
+
+config PWM_ROCKCHIP
+	bool "Enable support for the Rockchip PWM"
+	depends on DM_PWM
+	help
+	  This PWM is found on RK3288 and other Rockchip SoCs. It supports a
+	  programmable period and duty cycle. A 32-bit counter is used.
+	  Various options provided in the hardware (such as capture mode and
+	  continuous/single-shot) are not supported by the driver.
+
+config PWM_TEGRA
+	bool "Enable support for the Tegra PWM"
+	depends on DM_PWM
+	help
+	  This PWM is found on Tegra 20 and other Nvidia SoCs. It supports
+	  four channels with a programmable period and duty cycle. Only a
+	  32KHz clock is supported by the driver but the duty cycle is
+	  configurable.

u-boot/drivers/pwm/Makefile

@@ -0,0 +1,19 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2001
+# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+#ccflags-y += -DDEBUG
+
+obj-$(CONFIG_DM_PWM) += pwm-uclass.o
+obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
+obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
+ifdef CONFIG_DM_PWM
+obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o
+obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
+endif

u-boot/drivers/pwm/exynos_pwm.c

@@ -0,0 +1,120 @@
+/*
+ * Copyright 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pwm.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pwm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct exynos_pwm_priv {
+	struct s5p_timer *regs;
+};
+
+static int exynos_pwm_set_config(struct udevice *dev, uint channel,
+				uint period_ns, uint duty_ns)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+	struct s5p_timer *regs = priv->regs;
+	unsigned int offset, prescaler;
+	uint div = 4, rate, rate_ns;
+	u32 val;
+	u32 tcnt, tcmp, tcon;
+
+	if (channel >= 5)
+		return -EINVAL;
+	debug("%s: Configure '%s' channel %u, period_ns %u, duty_ns %u\n",
+	      __func__, dev->name, channel, period_ns, duty_ns);
+
+	val = readl(&regs->tcfg0);
+	prescaler = (channel < 2 ? val : (val >> 8)) & 0xff;
+	div = (readl(&regs->tcfg1) >> MUX_DIV_SHIFT(channel)) & 0xf;
+
+	rate = get_pwm_clk() / ((prescaler + 1) * (1 << div));
+	debug("%s: pwm_clk %lu, rate %u\n", __func__, get_pwm_clk(), rate);
+
+	if (channel < 4) {
+		rate_ns = 1000000000 / rate;
+		tcnt = period_ns / rate_ns;
+		tcmp = duty_ns / rate_ns;
+		debug("%s: tcnt %u, tcmp %u\n", __func__, tcnt, tcmp);
+		offset = channel * 3;
+		writel(tcnt, &regs->tcntb0 + offset);
+		writel(tcmp, &regs->tcmpb0 + offset);
+	}
+
+	tcon = readl(&regs->tcon);
+	tcon |= TCON_UPDATE(channel);
+	if (channel < 4)
+		tcon |= TCON_AUTO_RELOAD(channel);
+	else
+		tcon |= TCON4_AUTO_RELOAD;
+	writel(tcon, &regs->tcon);
+
+	tcon &= ~TCON_UPDATE(channel);
+	writel(tcon, &regs->tcon);
+
+	return 0;
+}
+
+static int exynos_pwm_set_enable(struct udevice *dev, uint channel,
+				 bool enable)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+	struct s5p_timer *regs = priv->regs;
+	u32 mask;
+
+	if (channel >= 4)
+		return -EINVAL;
+	debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
+	mask = TCON_START(channel);
+	clrsetbits_le32(&regs->tcon, mask, enable ? mask : 0);
+
+	return 0;
+}
+
+static int exynos_pwm_probe(struct udevice *dev)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+	struct s5p_timer *regs = priv->regs;
+
+	writel(PRESCALER_0 | PRESCALER_1 << 8, &regs->tcfg0);
+
+	return 0;
+}
+
+static int exynos_pwm_ofdata_to_platdata(struct udevice *dev)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+
+	priv->regs = (struct s5p_timer *)dev_get_addr(dev);
+
+	return 0;
+}
+
+static const struct pwm_ops exynos_pwm_ops = {
+	.set_config	= exynos_pwm_set_config,
+	.set_enable	= exynos_pwm_set_enable,
+};
+
+static const struct udevice_id exynos_channels[] = {
+	{ .compatible = "samsung,exynos4210-pwm" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos_pwm) = {
+	.name	= "exynos_pwm",
+	.id	= UCLASS_PWM,
+	.of_match = exynos_channels,
+	.ops	= &exynos_pwm_ops,
+	.probe	= exynos_pwm_probe,
+	.ofdata_to_platdata	= exynos_pwm_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct exynos_pwm_priv),
+};

u-boot/drivers/pwm/pwm-imx-util.c

@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Basic support for the pwm modul on imx6.
+ *
+ * Based on linux:drivers/pwm/pwm-imx.c
+ * from
+ * Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+
+/* pwm_id from 0..3 */
+struct pwm_regs *pwm_id_to_reg(int pwm_id)
+{
+	switch (pwm_id) {
+	case 0:
+		return (struct pwm_regs *)PWM1_BASE_ADDR;
+	case 1:
+		return (struct pwm_regs *)PWM2_BASE_ADDR;
+	case 2:
+		return (struct pwm_regs *)PWM3_BASE_ADDR;
+	case 3:
+		return (struct pwm_regs *)PWM4_BASE_ADDR;
+	default:
+		printf("unknown pwm_id: %d\n", pwm_id);
+		break;
+	}
+	return NULL;
+}
+
+int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
+		      unsigned long *duty_c, unsigned long *prescale)
+{
+	unsigned long long c;
+
+	/*
+	 * we have not yet a clock framework for imx6, so add the clock
+	 * value here as a define. Replace it when we have the clock
+	 * framework.
+	 */
+	c = CONFIG_IMX6_PWM_PER_CLK;
+	c = c * period_ns;
+	do_div(c, 1000000000);
+	*period_c = c;
+
+	*prescale = *period_c / 0x10000 + 1;
+
+	*period_c /= *prescale;
+	c = *period_c * (unsigned long long)duty_ns;
+	do_div(c, period_ns);
+	*duty_c = c;
+
+	/*
+	 * according to imx pwm RM, the real period value should be
+	 * PERIOD value in PWMPR plus 2.
+	 */
+	if (*period_c > 2)
+		*period_c -= 2;
+	else
+		*period_c = 0;
+
+	return 0;
+}

u-boot/drivers/pwm/pwm-imx-util.h

@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Basic support for the pwm modul on imx6.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _pwm_imx_util_h_
+#define _pwm_imx_util_h_
+
+struct pwm_regs *pwm_id_to_reg(int pwm_id);
+int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
+		      unsigned long *duty_c, unsigned long *prescale);
+#endif

u-boot/drivers/pwm/pwm-imx.c

@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Basic support for the pwm modul on imx6.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <pwm.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include "pwm-imx-util.h"
+
+int pwm_init(int pwm_id, int div, int invert)
+{
+	struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+
+	if (!pwm)
+		return -1;
+
+	writel(0, &pwm->ir);
+	return 0;
+}
+
+int pwm_config(int pwm_id, int duty_ns, int period_ns)
+{
+	struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+	unsigned long period_cycles, duty_cycles, prescale;
+	u32 cr;
+
+	if (!pwm)
+		return -1;
+
+	pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
+			  &prescale);
+
+	cr = PWMCR_PRESCALER(prescale) |
+		PWMCR_DOZEEN | PWMCR_WAITEN |
+		PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH;
+
+	writel(cr, &pwm->cr);
+	/* set duty cycles */
+	writel(duty_cycles, &pwm->sar);
+	/* set period cycles */
+	writel(period_cycles, &pwm->pr);
+	return 0;
+}
+
+int pwm_enable(int pwm_id)
+{
+	struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+
+	if (!pwm)
+		return -1;
+
+	setbits_le32(&pwm->cr, PWMCR_EN);
+	return 0;
+}
+
+void pwm_disable(int pwm_id)
+{
+	struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+
+	if (!pwm)
+		return;
+
+	clrbits_le32(&pwm->cr, PWMCR_EN);
+}

u-boot/drivers/pwm/pwm-uclass.c

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pwm.h>
+
+int pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
+		   uint duty_ns)
+{
+	struct pwm_ops *ops = pwm_get_ops(dev);
+
+	if (!ops->set_config)
+		return -ENOSYS;
+
+	return ops->set_config(dev, channel, period_ns, duty_ns);
+}
+
+int pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+	struct pwm_ops *ops = pwm_get_ops(dev);
+
+	if (!ops->set_enable)
+		return -ENOSYS;
+
+	return ops->set_enable(dev, channel, enable);
+}
+
+UCLASS_DRIVER(pwm) = {
+	.id		= UCLASS_PWM,
+	.name		= "pwm",
+};

u-boot/drivers/pwm/rk_pwm.c

@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <pwm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3288.h>
+#include <asm/arch/grf_rk3288.h>
+#include <asm/arch/pwm.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk_pwm_priv {
+	struct rk3288_pwm *regs;
+	struct rk3288_grf *grf;
+};
+
+static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
+			     uint duty_ns)
+{
+	struct rk_pwm_priv *priv = dev_get_priv(dev);
+	struct rk3288_pwm *regs = priv->regs;
+	unsigned long period, duty;
+
+	debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
+	writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
+		PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
+		RK_PWM_DISABLE,
+		&regs->ctrl);
+
+	period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000);
+	duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000);
+
+	writel(period, &regs->period_hpr);
+	writel(duty, &regs->duty_lpr);
+	debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
+
+	return 0;
+}
+
+static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+	struct rk_pwm_priv *priv = dev_get_priv(dev);
+	struct rk3288_pwm *regs = priv->regs;
+
+	debug("%s: Enable '%s'\n", __func__, dev->name);
+	clrsetbits_le32(&regs->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
+
+	return 0;
+}
+
+static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rk_pwm_priv *priv = dev_get_priv(dev);
+	struct regmap *map;
+
+	priv->regs = (struct rk3288_pwm *)dev_get_addr(dev);
+	map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(map))
+		return PTR_ERR(map);
+	priv->grf = regmap_get_range(map, 0);
+
+	return 0;
+}
+
+static int rk_pwm_probe(struct udevice *dev)
+{
+	struct rk_pwm_priv *priv = dev_get_priv(dev);
+
+	rk_setreg(&priv->grf->soc_con2, 1 << 0);
+
+	return 0;
+}
+
+static const struct pwm_ops rk_pwm_ops = {
+	.set_config	= rk_pwm_set_config,
+	.set_enable	= rk_pwm_set_enable,
+};
+
+static const struct udevice_id rk_pwm_ids[] = {
+	{ .compatible = "rockchip,rk3288-pwm" },
+	{ }
+};
+
+U_BOOT_DRIVER(rk_pwm) = {
+	.name	= "rk_pwm",
+	.id	= UCLASS_PWM,
+	.of_match = rk_pwm_ids,
+	.ops	= &rk_pwm_ops,
+	.ofdata_to_platdata	= rk_pwm_ofdata_to_platdata,
+	.probe		= rk_pwm_probe,
+	.priv_auto_alloc_size	= sizeof(struct rk_pwm_priv),
+};

u-boot/drivers/pwm/tegra_pwm.c

@@ -0,0 +1,85 @@
+/*
+ * Copyright 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pwm.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pwm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra_pwm_priv {
+	struct pwm_ctlr *regs;
+};
+
+static int tegra_pwm_set_config(struct udevice *dev, uint channel,
+				uint period_ns, uint duty_ns)
+{
+	struct tegra_pwm_priv *priv = dev_get_priv(dev);
+	struct pwm_ctlr *regs = priv->regs;
+	uint pulse_width;
+	u32 reg;
+
+	if (channel >= 4)
+		return -EINVAL;
+	debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
+	/* We ignore the period here and just use 32KHz */
+	clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768);
+
+	pulse_width = duty_ns * 255 / period_ns;
+
+	reg = pulse_width << PWM_WIDTH_SHIFT;
+	reg |= 1 << PWM_DIVIDER_SHIFT;
+	writel(reg, &regs[channel].control);
+	debug("%s: pulse_width=%u\n", __func__, pulse_width);
+
+	return 0;
+}
+
+static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+	struct tegra_pwm_priv *priv = dev_get_priv(dev);
+	struct pwm_ctlr *regs = priv->regs;
+
+	if (channel >= 4)
+		return -EINVAL;
+	debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
+	clrsetbits_le32(&regs[channel].control, PWM_ENABLE_MASK,
+			enable ? PWM_ENABLE_MASK : 0);
+
+	return 0;
+}
+
+static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
+{
+	struct tegra_pwm_priv *priv = dev_get_priv(dev);
+
+	priv->regs = (struct pwm_ctlr *)dev_get_addr(dev);
+
+	return 0;
+}
+
+static const struct pwm_ops tegra_pwm_ops = {
+	.set_config	= tegra_pwm_set_config,
+	.set_enable	= tegra_pwm_set_enable,
+};
+
+static const struct udevice_id tegra_pwm_ids[] = {
+	{ .compatible = "nvidia,tegra124-pwm" },
+	{ .compatible = "nvidia,tegra20-pwm" },
+	{ }
+};
+
+U_BOOT_DRIVER(tegra_pwm) = {
+	.name	= "tegra_pwm",
+	.id	= UCLASS_PWM,
+	.of_match = tegra_pwm_ids,
+	.ops	= &tegra_pwm_ops,
+	.ofdata_to_platdata	= tegra_pwm_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct tegra_pwm_priv),
+};