avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/drivers/pcmcia/Makefile

@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_8xx) += mpc8xx_pcmcia.o
+obj-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o
+obj-y += tqm8xx_pcmcia.o
+obj-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o

u-boot/drivers/pcmcia/marubun_pcmcia.c

@@ -0,0 +1,100 @@
+/*
+ * Marubun MR-SHPC-01 PCMCIA controller device driver
+ *
+ * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <pcmcia.h>
+#include <asm/io.h>
+
+#undef CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_PCMCIA)
+
+/* MR-SHPC-01 register */
+#define MRSHPC_MODE	(CONFIG_SYS_MARUBUN_MRSHPC + 4)
+#define MRSHPC_OPTION   (CONFIG_SYS_MARUBUN_MRSHPC + 6)
+#define MRSHPC_CSR      (CONFIG_SYS_MARUBUN_MRSHPC + 8)
+#define MRSHPC_ISR      (CONFIG_SYS_MARUBUN_MRSHPC + 10)
+#define MRSHPC_ICR      (CONFIG_SYS_MARUBUN_MRSHPC + 12)
+#define MRSHPC_CPWCR    (CONFIG_SYS_MARUBUN_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (CONFIG_SYS_MARUBUN_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (CONFIG_SYS_MARUBUN_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (CONFIG_SYS_MARUBUN_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (CONFIG_SYS_MARUBUN_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (CONFIG_SYS_MARUBUN_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (CONFIG_SYS_MARUBUN_MRSHPC + 26)
+#define MRSHPC_CDCR     (CONFIG_SYS_MARUBUN_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (CONFIG_SYS_MARUBUN_MRSHPC + 30)
+
+int pcmcia_on (void)
+{
+	printf("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	/* Init */
+	outw( 0x0000 , MRSHPC_MODE );
+
+	if ((inw(MRSHPC_CSR) & 0x000c) == 0){	/* if card detect is true */
+		if ((inw(MRSHPC_CSR) & 0x0080) == 0){
+			outw(0x0674 ,MRSHPC_CPWCR);  /* Card Vcc is 3.3v? */
+		}else{
+			outw(0x0678 ,MRSHPC_CPWCR);  /* Card Vcc is 5V */
+		}
+		udelay( 100000 );   /* wait for power on */
+	}else{
+		return 1;
+	}
+	/*
+	 *	PC-Card window open
+	 *	flag == COMMON/ATTRIBUTE/IO
+	 */
+	/* common window open */
+	outw(0x8a84,MRSHPC_MW0CR1); /* window 0xb8400000 */
+	if ((inw(MRSHPC_CSR) & 0x4000) != 0)
+		outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */
+	else
+		outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */
+
+	/* attribute window open */
+	outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */
+	if ((inw(MRSHPC_CSR) & 0x4000) != 0)
+		outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */
+	else
+		outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */
+
+	/* I/O window open */
+	outw(0x8a86,MRSHPC_IOWCR1); /* I/O window 0xb8600000 */
+	outw(0x0008,MRSHPC_CDCR);   /* I/O card mode */
+	if ((inw(MRSHPC_CSR) & 0x4000) != 0)
+		outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */
+	else
+		outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */
+
+	outw(0x0000,MRSHPC_ISR);
+	outw(0x2000,MRSHPC_ICR);
+	outb(0x00,(CONFIG_SYS_MARUBUN_MW2 + 0x206));
+	outb(0x42,(CONFIG_SYS_MARUBUN_MW2 + 0x200));
+
+	return 0;
+}
+
+int pcmcia_off (void)
+{
+	printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	return 0;
+}
+
+#endif /* CONFIG_PCMCIA */

u-boot/drivers/pcmcia/mpc8xx_pcmcia.c

@@ -0,0 +1,258 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+#include <linux/compiler.h>
+
+#undef	CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_PCMCIA)
+
+#if	defined(CONFIG_IDE_8xx_PCCARD)
+extern int check_ide_device (int slot);
+#endif
+
+extern int pcmcia_hardware_enable (int slot);
+extern int pcmcia_voltage_set(int slot, int vcc, int vpp);
+
+#if defined(CONFIG_CMD_PCMCIA)
+extern int pcmcia_hardware_disable(int slot);
+#endif
+
+static u_int m8xx_get_graycode(u_int size);
+#if 0 /* Disabled */
+static u_int m8xx_get_speed(u_int ns, u_int is_io);
+#endif
+
+/* look up table for pgcrx registers */
+u_int *pcmcia_pgcrx[2] = {
+	&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcra,
+	&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb,
+};
+
+/*
+ * Search this table to see if the windowsize is
+ * supported...
+ */
+
+#define M8XX_SIZES_NO 32
+
+static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
+{ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
+  0x00000080, 0x00000040, 0x00000010, 0x00000020,
+  0x00008000, 0x00004000, 0x00001000, 0x00002000,
+  0x00000100, 0x00000200, 0x00000800, 0x00000400,
+
+  0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x01000000, 0x02000000, 0xffffffff, 0x04000000,
+  0x00010000, 0x00020000, 0x00080000, 0x00040000,
+  0x00800000, 0x00400000, 0x00100000, 0x00200000 };
+
+
+/* -------------------------------------------------------------------- */
+
+#define	CONFIG_SYS_PCMCIA_TIMING	(	PCMCIA_SHT(2)	\
+				|	PCMCIA_SST(4)	\
+				|	PCMCIA_SL(9))
+
+/* -------------------------------------------------------------------- */
+
+int pcmcia_on (void)
+{
+	u_long reg, base;
+	pcmcia_win_t *win;
+	u_int rc, slot;
+	__maybe_unused u_int slotbit;
+	int i;
+
+	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	/* intialize the fixed memory windows */
+	win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);
+	base = CONFIG_SYS_PCMCIA_MEM_ADDR;
+
+	if((reg = m8xx_get_graycode(CONFIG_SYS_PCMCIA_MEM_SIZE)) == -1) {
+		printf ("Cannot set window size to 0x%08x\n",
+			CONFIG_SYS_PCMCIA_MEM_SIZE);
+		return (1);
+	}
+
+	slotbit = PCMCIA_SLOT_x;
+	for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
+		win->br = base;
+
+#if	(PCMCIA_SOCKETS_NO == 2)
+		if (i == 4) /* Another slot starting from win 4 */
+			slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
+#endif
+		switch (i) {
+#ifdef	CONFIG_IDE_8xx_PCCARD
+		case 4:
+		case 0:	{	/* map attribute memory */
+			win->or = (	PCMCIA_BSIZE_64M
+				|	PCMCIA_PPS_8
+				|	PCMCIA_PRS_ATTR
+				|	slotbit
+				|	PCMCIA_PV
+				|	CONFIG_SYS_PCMCIA_TIMING );
+			break;
+		}
+		case 5:
+		case 1: {	/* map I/O window for data reg */
+			win->or = (	PCMCIA_BSIZE_1K
+				|	PCMCIA_PPS_16
+				|	PCMCIA_PRS_IO
+				|	slotbit
+				|	PCMCIA_PV
+				|	CONFIG_SYS_PCMCIA_TIMING );
+			break;
+		}
+		case 6:
+		case 2: {	/* map I/O window for cmd/ctrl reg block */
+			win->or = (	PCMCIA_BSIZE_1K
+				|	PCMCIA_PPS_8
+				|	PCMCIA_PRS_IO
+				|	slotbit
+				|	PCMCIA_PV
+				|	CONFIG_SYS_PCMCIA_TIMING );
+			break;
+		}
+#endif	/* CONFIG_IDE_8xx_PCCARD */
+		default:	/* set to not valid */
+			win->or = 0;
+			break;
+		}
+
+		debug ("MemWin %d: PBR 0x%08lX  POR %08lX\n",
+		       i, win->br, win->or);
+		base += CONFIG_SYS_PCMCIA_MEM_SIZE;
+		++win;
+	}
+
+	for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) {
+		/* turn off voltage */
+		if ((rc = pcmcia_voltage_set(slot, 0, 0)))
+			continue;
+
+		/* Enable external hardware */
+		if ((rc = pcmcia_hardware_enable(slot)))
+			continue;
+
+#ifdef	CONFIG_IDE_8xx_PCCARD
+		if ((rc = check_ide_device(i)))
+			continue;
+#endif
+	}
+	return rc;
+}
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_off (void)
+{
+	int i;
+	pcmcia_win_t *win;
+
+	printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	/* clear interrupt state, and disable interrupts */
+	((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pscr =  PCMCIA_MASK(_slot_);
+	((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+	/* turn off interrupt and disable CxOE */
+	PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE;
+
+	/* turn off memory windows */
+	win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);
+
+	for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
+		/* disable memory window */
+		win->or = 0;
+		++win;
+	}
+
+	/* turn off voltage */
+	pcmcia_voltage_set(_slot_, 0, 0);
+
+	/* disable external hardware */
+	printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n");
+	pcmcia_hardware_disable(_slot_);
+	return 0;
+}
+#endif
+
+
+static u_int m8xx_get_graycode(u_int size)
+{
+	u_int k;
+
+	for (k = 0; k < M8XX_SIZES_NO; k++) {
+		if(m8xx_size_to_gray[k] == size)
+			break;
+	}
+
+	if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
+		k = -1;
+
+	return k;
+}
+
+#if	0
+
+static u_int m8xx_get_speed(u_int ns, u_int is_io)
+{
+	u_int reg, clocks, psst, psl, psht;
+
+	if(!ns) {
+
+		/*
+		* We get called with IO maps setup to 0ns
+		* if not specified by the user.
+		* They should be 255ns.
+		*/
+
+		if(is_io)
+			ns = 255;
+		else
+			ns = 100;  /* fast memory if 0 */
+	}
+
+	/*
+	* In PSST, PSL, PSHT fields we tell the controller
+	* timing parameters in CLKOUT clock cycles.
+	* CLKOUT is the same as GCLK2_50.
+	*/
+
+	/* how we want to adjust the timing - in percent */
+
+#define ADJ 180 /* 80 % longer accesstime - to be sure */
+
+	clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
+	clocks = (clocks * ADJ) / (100*1000);
+
+	if(clocks >= PCMCIA_BMT_LIMIT) {
+		DEBUG(0, "Max access time limit reached\n");
+		clocks = PCMCIA_BMT_LIMIT-1;
+	}
+
+	psst = clocks / 7;          /* setup time */
+	psht = clocks / 7;          /* hold time */
+	psl  = (clocks * 5) / 7;    /* strobe length */
+
+	psst += clocks - (psst + psht + psl);
+
+	reg =  psst << 12;
+	reg |= psl  << 7;
+	reg |= psht << 16;
+
+	return reg;
+}
+#endif	/* 0 */
+
+#endif	/* CONFIG_PCMCIA */

u-boot/drivers/pcmcia/ti_pci1410a.c

@@ -0,0 +1,623 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ ********************************************************************
+ *
+ * Lots of code copied from:
+ *
+ * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
+ * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
+ *
+ * "The ExCA standard specifies that socket controllers should provide
+ * two IO and five memory windows per socket, which can be independently
+ * configured and positioned in the host address space and mapped to
+ * arbitrary segments of card address space. " - David A Hinds. 1999
+ *
+ * This controller does _not_ meet the ExCA standard.
+ *
+ * m8xx pcmcia controller brief info:
+ * + 8 windows (attrib, mem, i/o)
+ * + up to two slots (SLOT_A and SLOT_B)
+ * + inputpins, outputpins, event and mask registers.
+ * - no offset register. sigh.
+ *
+ * Because of the lacking offset register we must map the whole card.
+ * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
+ * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
+ * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
+ * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
+ * They are maximum 64KByte each...
+ */
+
+
+#undef DEBUG		/**/
+
+/*
+ * PCMCIA support
+ */
+#include <common.h>
+#include <command.h>
+#include <config.h>
+#include <pci.h>
+#include <asm/io.h>
+
+#include <pcmcia.h>
+
+#if defined(CONFIG_CMD_PCMCIA)
+
+int pcmcia_on(int ide_base_bus);
+
+static int  hardware_disable(int slot);
+static int  hardware_enable(int slot);
+static int  voltage_set(int slot, int vcc, int vpp);
+static void print_funcid(int func);
+static void print_fixed(volatile char *p);
+static int  identify(volatile char *p);
+static int  check_ide_device(int slot, int ide_base_bus);
+
+
+/* ------------------------------------------------------------------------- */
+
+
+const char *indent = "\t   ";
+
+/* ------------------------------------------------------------------------- */
+
+
+static struct pci_device_id supported[] = {
+	{ PCI_VENDOR_ID_TI, 0xac50 }, /* Ti PCI1410A */
+	{ PCI_VENDOR_ID_TI, 0xac56 }, /* Ti PCI1510 */
+	{ }
+};
+
+static pci_dev_t devbusfn;
+static u32 socket_base;
+static u32 pcmcia_cis_ptr;
+
+int pcmcia_on(int ide_base_bus)
+{
+	u16 dev_id;
+	u32 socket_status;
+	int slot = 0;
+	int cis_len;
+	u16 io_base;
+	u16 io_len;
+
+	/*
+	 * Find the CardBus PCI device(s).
+	 */
+	if ((devbusfn = pci_find_devices(supported, 0)) < 0) {
+		printf("Ti CardBus: not found\n");
+		return 1;
+	}
+
+	pci_read_config_word(devbusfn, PCI_DEVICE_ID, &dev_id);
+
+	if (dev_id == 0xac56) {
+		debug("Enable PCMCIA Ti PCI1510\n");
+	} else {
+		debug("Enable PCMCIA Ti PCI1410A\n");
+	}
+
+	pcmcia_cis_ptr = CONFIG_SYS_PCMCIA_CIS_WIN;
+	cis_len = CONFIG_SYS_PCMCIA_CIS_WIN_SIZE;
+
+	io_base = CONFIG_SYS_PCMCIA_IO_WIN;
+	io_len = CONFIG_SYS_PCMCIA_IO_WIN_SIZE;
+
+	/*
+	 * Setup the PCI device.
+	 */
+	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &socket_base);
+	socket_base &= ~0xf;
+
+	socket_status = readl(socket_base+8);
+	if ((socket_status & 6) == 0) {
+		printf("Card Present: ");
+
+		switch (socket_status & 0x3c00) {
+
+		case 0x400:
+			printf("5V ");
+			break;
+		case 0x800:
+			printf("3.3V ");
+			break;
+		case 0xc00:
+			printf("3.3/5V ");
+			break;
+		default:
+			printf("unsupported Vcc ");
+			break;
+		}
+		switch (socket_status & 0x30) {
+		case 0x10:
+			printf("16bit PC-Card\n");
+			break;
+		case 0x20:
+			printf("32bit CardBus Card\n");
+			break;
+		default:
+			printf("8bit PC-Card\n");
+			break;
+		}
+	}
+
+
+	writeb(0x41, socket_base + 0x806); /* Enable I/O window 0 and memory window 0 */
+	writeb(0x0e, socket_base + 0x807); /* Reset I/O window options */
+
+	/* Careful: the linux yenta driver do not seem to reset the offset
+	 * in the i/o windows, so leaving them non-zero is a problem */
+
+	writeb(io_base & 0xff, socket_base + 0x808); /* I/O window 0 base address */
+	writeb(io_base>>8, socket_base + 0x809);
+	writeb((io_base + io_len - 1) & 0xff, socket_base + 0x80a); /* I/O window 0 end address */
+	writeb((io_base + io_len - 1)>>8, socket_base + 0x80b);
+	writeb(0x00, socket_base + 0x836);      /* I/O window 0 offset address 0x000 */
+	writeb(0x00, socket_base + 0x837);
+
+
+	writeb((pcmcia_cis_ptr&0x000ff000) >> 12,
+	       socket_base + 0x810); /* Memory window 0 start address bits 19-12 */
+	writeb((pcmcia_cis_ptr&0x00f00000) >> 20,
+	       socket_base + 0x811);  /* Memory window 0 start address bits 23-20 */
+	writeb(((pcmcia_cis_ptr+cis_len-1) & 0x000ff000) >> 12,
+		socket_base + 0x812); /* Memory window 0 end address bits 19-12*/
+	writeb(((pcmcia_cis_ptr+cis_len-1) & 0x00f00000) >> 20,
+		socket_base + 0x813); /* Memory window 0 end address bits 23-20*/
+	writeb(0x00, socket_base + 0x814); /* Memory window 0 offset bits 19-12 */
+	writeb(0x40, socket_base + 0x815); /* Memory window 0 offset bits 23-20 and
+					    * options (read/write, attribute access) */
+	writeb(0x00, socket_base + 0x816); /* ExCA card-detect and general control  */
+	writeb(0x00, socket_base + 0x81e); /* ExCA global control (interrupt modes) */
+
+	writeb((pcmcia_cis_ptr & 0xff000000) >> 24,
+	       socket_base + 0x840); /* Memory window address bits 31-24 */
+
+
+	/* turn off voltage */
+	if (voltage_set(slot, 0, 0)) {
+		return 1;
+	}
+
+	/* Enable external hardware */
+	if (hardware_enable(slot)) {
+		return 1;
+	}
+
+	if (check_ide_device(slot, ide_base_bus)) {
+		return 1;
+	}
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_off (void)
+{
+	int slot = 0;
+
+	writeb(0x00, socket_base + 0x806); /* disable all I/O and memory windows */
+
+	writeb(0x00, socket_base + 0x808); /* I/O window 0 base address */
+	writeb(0x00, socket_base + 0x809);
+	writeb(0x00, socket_base + 0x80a); /* I/O window 0 end address */
+	writeb(0x00, socket_base + 0x80b);
+	writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address  */
+	writeb(0x00, socket_base + 0x837);
+
+	writeb(0x00, socket_base + 0x80c); /* I/O window 1 base address  */
+	writeb(0x00, socket_base + 0x80d);
+	writeb(0x00, socket_base + 0x80e); /* I/O window 1 end address  */
+	writeb(0x00, socket_base + 0x80f);
+	writeb(0x00, socket_base + 0x838); /* I/O window 1 offset address  */
+	writeb(0x00, socket_base + 0x839);
+
+	writeb(0x00, socket_base + 0x810); /* Memory window 0 start address */
+	writeb(0x00, socket_base + 0x811);
+	writeb(0x00, socket_base + 0x812); /* Memory window 0 end address  */
+	writeb(0x00, socket_base + 0x813);
+	writeb(0x00, socket_base + 0x814); /* Memory window 0 offset */
+	writeb(0x00, socket_base + 0x815);
+
+	writeb(0xc0, socket_base + 0x840); /* Memory window 0 page address */
+
+
+	/* turn off voltage */
+	voltage_set(slot, 0, 0);
+
+	/* disable external hardware */
+	printf ("Shutdown and Poweroff Ti PCI1410A\n");
+	hardware_disable(slot);
+
+	return 0;
+}
+
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+
+#define	MAX_TUPEL_SZ	512
+#define MAX_FEATURES	4
+int ide_devices_found;
+static int check_ide_device(int slot, int ide_base_bus)
+{
+	volatile char *ident = NULL;
+	volatile char *feature_p[MAX_FEATURES];
+	volatile char *p, *start;
+	int n_features = 0;
+	uchar func_id = ~0;
+	uchar code, len;
+	ushort config_base = 0;
+	int found = 0;
+	int i;
+	u32 socket_status;
+
+	debug ("PCMCIA MEM: %08X\n", pcmcia_cis_ptr);
+
+	socket_status = readl(socket_base+8);
+
+	if ((socket_status & 6) != 0 || (socket_status & 0x20) != 0) {
+		printf("no card or CardBus card\n");
+		return 1;
+	}
+
+	start = p = (volatile char *) pcmcia_cis_ptr;
+
+	while ((p - start) < MAX_TUPEL_SZ) {
+
+		code = *p; p += 2;
+
+		if (code == 0xFF) { /* End of chain */
+			break;
+		}
+
+		len = *p; p += 2;
+#if defined(DEBUG) && (DEBUG > 1)
+		{
+			volatile uchar *q = p;
+			printf ("\nTuple code %02x  length %d\n\tData:",
+				code, len);
+
+			for (i = 0; i < len; ++i) {
+				printf (" %02x", *q);
+				q+= 2;
+			}
+		}
+#endif	/* DEBUG */
+		switch (code) {
+		case CISTPL_VERS_1:
+			ident = p + 4;
+			break;
+		case CISTPL_FUNCID:
+			/* Fix for broken SanDisk which may have 0x80 bit set */
+			func_id = *p & 0x7F;
+			break;
+		case CISTPL_FUNCE:
+			if (n_features < MAX_FEATURES)
+				feature_p[n_features++] = p;
+			break;
+		case CISTPL_CONFIG:
+			config_base = (*(p+6) << 8) + (*(p+4));
+			debug ("\n## Config_base = %04x ###\n", config_base);
+		default:
+			break;
+		}
+		p += 2 * len;
+	}
+
+	found = identify(ident);
+
+	if (func_id != ((uchar)~0)) {
+		print_funcid (func_id);
+
+		if (func_id == CISTPL_FUNCID_FIXED)
+			found = 1;
+		else
+			return 1;	/* no disk drive */
+	}
+
+	for (i=0; i<n_features; ++i) {
+		print_fixed(feature_p[i]);
+	}
+
+	if (!found) {
+		printf("unknown card type\n");
+		return 1;
+	}
+
+	/* select config index 1 */
+	writeb(1, pcmcia_cis_ptr + config_base);
+
+#if 0
+	printf("Confiuration Option Register: %02x\n", readb(pcmcia_cis_ptr + config_base));
+	printf("Card Confiuration and Status Register: %02x\n", readb(pcmcia_cis_ptr + config_base + 2));
+	printf("Pin Replacement Register Register: %02x\n", readb(pcmcia_cis_ptr + config_base + 4));
+	printf("Socket and Copy Register: %02x\n", readb(pcmcia_cis_ptr + config_base + 6));
+#endif
+	ide_devices_found |= (1 << (slot+ide_base_bus));
+
+	return 0;
+}
+
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+	u32 socket_control;
+	int reg=0;
+
+	switch (slot) {
+	case 0:
+		reg = socket_base + 0x10;
+		break;
+	default:
+		return 1;
+	}
+
+	socket_control = 0;
+
+
+	switch (vcc) {
+	case 50:
+		socket_control |= 0x20;
+		break;
+	case 33:
+		socket_control |= 0x30;
+		break;
+	case 0:
+	default: ;
+	}
+
+	switch (vpp) {
+	case 120:
+		socket_control |= 0x1;
+		break;
+	case 50:
+		socket_control |= 0x2;
+		break;
+	case 33:
+		socket_control |= 0x3;
+		break;
+	case 0:
+	default: ;
+	}
+
+	writel(socket_control, reg);
+
+	debug ("voltage_set: Ti PCI1410A Slot %d, Vcc=%d.%d, Vpp=%d.%d\n",
+		slot, vcc/10, vcc%10, vpp/10, vpp%10);
+
+	udelay(500);
+	return 0;
+}
+
+
+static int hardware_enable(int slot)
+{
+	u32 socket_status;
+	u16 brg_ctrl;
+	int is_82365sl;
+
+	socket_status = readl(socket_base+8);
+
+	if ((socket_status & 6) == 0) {
+
+		switch (socket_status & 0x3c00) {
+
+		case 0x400:
+			printf("5V ");
+			voltage_set(slot, 50, 0);
+			break;
+		case 0x800:
+			voltage_set(slot, 33, 0);
+			break;
+		case 0xc00:
+			voltage_set(slot, 33, 0);
+			break;
+		default:
+			voltage_set(slot, 0, 0);
+			break;
+		}
+	} else {
+		voltage_set(slot, 0, 0);
+	}
+
+	pci_read_config_word(devbusfn, PCI_BRIDGE_CONTROL, &brg_ctrl);
+	brg_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
+	pci_write_config_word(devbusfn, PCI_BRIDGE_CONTROL, brg_ctrl);
+	is_82365sl = ((readb(socket_base+0x800) & 0x0f) == 2);
+	writeb(is_82365sl?0x90:0x98, socket_base+0x802);
+	writeb(0x67, socket_base+0x803);
+	udelay(100000);
+#if 0
+	printf("ExCA Id %02x, Card Status %02x, Power config %02x, Interrupt Config %02x, bridge control %04x %d\n",
+	       readb(socket_base+0x800), readb(socket_base+0x801),
+	       readb(socket_base+0x802), readb(socket_base+0x803), brg_ctrl, is_82365sl);
+#endif
+
+	return ((readb(socket_base+0x801)&0x6c)==0x6c)?0:1;
+}
+
+
+static int hardware_disable(int slot)
+{
+	voltage_set(slot, 0, 0);
+	return 0;
+}
+
+static void print_funcid(int func)
+{
+	puts(indent);
+	switch (func) {
+	case CISTPL_FUNCID_MULTI:
+		puts(" Multi-Function");
+		break;
+	case CISTPL_FUNCID_MEMORY:
+		puts(" Memory");
+		break;
+	case CISTPL_FUNCID_SERIAL:
+		puts(" Serial Port");
+		break;
+	case CISTPL_FUNCID_PARALLEL:
+		puts(" Parallel Port");
+		break;
+	case CISTPL_FUNCID_FIXED:
+		puts(" Fixed Disk");
+		break;
+	case CISTPL_FUNCID_VIDEO:
+		puts(" Video Adapter");
+		break;
+	case CISTPL_FUNCID_NETWORK:
+		puts(" Network Adapter");
+		break;
+	case CISTPL_FUNCID_AIMS:
+		puts(" AIMS Card");
+		break;
+	case CISTPL_FUNCID_SCSI:
+		puts(" SCSI Adapter");
+		break;
+	default:
+		puts(" Unknown");
+		break;
+	}
+	puts(" Card\n");
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void print_fixed(volatile char *p)
+{
+	if (p == NULL)
+		return;
+
+	puts(indent);
+
+	switch (*p) {
+	case CISTPL_FUNCE_IDE_IFACE:
+		{   uchar iface = *(p+2);
+
+			puts ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
+			puts (" interface ");
+			break;
+		}
+	case CISTPL_FUNCE_IDE_MASTER:
+	case CISTPL_FUNCE_IDE_SLAVE:
+		{
+			uchar f1 = *(p+2);
+			uchar f2 = *(p+4);
+
+			puts((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
+
+			if (f1 & CISTPL_IDE_UNIQUE) {
+				puts(" [unique]");
+			}
+
+			puts((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
+
+			if (f2 & CISTPL_IDE_HAS_SLEEP) {
+				puts(" [sleep]");
+			}
+
+			if (f2 & CISTPL_IDE_HAS_STANDBY) {
+				puts(" [standby]");
+			}
+
+			if (f2 & CISTPL_IDE_HAS_IDLE) {
+				puts(" [idle]");
+			}
+
+			if (f2 & CISTPL_IDE_LOW_POWER) {
+				puts(" [low power]");
+			}
+
+			if (f2 & CISTPL_IDE_REG_INHIBIT) {
+				puts(" [reg inhibit]");
+			}
+
+			if (f2 & CISTPL_IDE_HAS_INDEX) {
+				puts(" [index]");
+			}
+
+			if (f2 & CISTPL_IDE_IOIS16) {
+				puts(" [IOis16]");
+			}
+
+			break;
+		}
+	}
+	putc('\n');
+}
+
+/* ------------------------------------------------------------------------- */
+
+#define MAX_IDENT_CHARS		64
+#define	MAX_IDENT_FIELDS	4
+
+static char *known_cards[] = {
+	"ARGOSY PnPIDE D5",
+	NULL
+};
+
+static int identify(volatile char *p)
+{
+	char id_str[MAX_IDENT_CHARS];
+	char data;
+	char *t;
+	char **card;
+	int i, done;
+
+	if (p == NULL)
+		return (0);	/* Don't know */
+
+	t = id_str;
+	done =0;
+
+	for (i=0; i<=4 && !done; ++i, p+=2) {
+		while ((data = *p) != '\0') {
+			if (data == 0xFF) {
+				done = 1;
+				break;
+			}
+			*t++ = data;
+			if (t == &id_str[MAX_IDENT_CHARS-1]) {
+				done = 1;
+				break;
+			}
+			p += 2;
+		}
+		if (!done)
+			*t++ = ' ';
+	}
+	*t = '\0';
+	while (--t > id_str) {
+		if (*t == ' ') {
+			*t = '\0';
+		} else {
+			break;
+		}
+	}
+	puts(id_str);
+	putc('\n');
+
+	for (card=known_cards; *card; ++card) {
+		debug ("## Compare against \"%s\"\n", *card);
+		if (strcmp(*card, id_str) == 0) {	/* found! */
+			debug ("## CARD FOUND ##\n");
+			return 1;
+		}
+	}
+
+	return 0;	/* don't know */
+}
+
+#endif /* CONFIG_CMD_PCMCIA */

u-boot/drivers/pcmcia/tqm8xx_pcmcia.c

@@ -0,0 +1,254 @@
+/* -------------------------------------------------------------------- */
+/* TQM8xxL Boards by TQ Components					*/
+/* SC8xx   Boards by SinoVee Microsystems				*/
+/* -------------------------------------------------------------------- */
+#include <common.h>
+#include <asm/io.h>
+#ifdef CONFIG_8xx
+#include <mpc8xx.h>
+#endif
+#include <pcmcia.h>
+
+#undef	CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#if	defined(CONFIG_PCMCIA)	\
+	&& defined(CONFIG_TQM8xxL)
+
+#if	defined(CONFIG_TQM8xxL)
+#define	PCMCIA_BOARD_MSG	"TQM8xxL"
+#endif
+
+static inline void power_config(int slot)
+{
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	/*
+	 * Configure Port C pins for
+	 * 5 Volts Enable and 3 Volts enable
+	 */
+	clrbits_be16(&immap->im_ioport.iop_pcpar, 0x0002 | 0x0004);
+	clrbits_be16(&immap->im_ioport.iop_pcso, 0x0002 | 0x0004);
+}
+
+static inline void power_off(int slot)
+{
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	clrbits_be16(&immap->im_ioport.iop_pcdat, 0x0002 | 0x0004);
+}
+
+static inline void power_on_5_0(int slot)
+{
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	setbits_be16(&immap->im_ioport.iop_pcdat, 0x0004);
+	setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004);
+}
+
+static inline void power_on_3_3(int slot)
+{
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	setbits_be16(&immap->im_ioport.iop_pcdat, 0x0002);
+	setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004);
+}
+
+/*
+ * Function to retrieve the PIPR register, used for debuging purposes.
+ */
+static inline uint32_t debug_get_pipr(void)
+{
+	uint32_t pipr = 0;
+#ifdef	DEBUG
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	pipr = in_be32(&immap->im_pcmcia.pcmc_pipr);
+#endif
+	return pipr;
+}
+
+
+static inline int check_card_is_absent(int slot)
+{
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	uint32_t pipr = in_be32(&immap->im_pcmcia.pcmc_pipr);
+	return pipr & (0x18000000 >> (slot << 4));
+}
+
+#define	NSCU_GCRX_CXOE	__MY_PCMCIA_GCRX_CXOE
+
+int pcmcia_hardware_enable(int slot)
+{
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	uint reg, mask;
+
+	debug("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	udelay(10000);
+
+	/*
+	 * Configure SIUMCR to enable PCMCIA port B
+	 * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+	 */
+
+	/* Set DBGC to 00 */
+	clrbits_be32(&immap->im_siu_conf.sc_siumcr, SIUMCR_DBGC11);
+
+	/* Clear interrupt state, and disable interrupts */
+	out_be32(&immap->im_pcmcia.pcmc_pscr, PCMCIA_MASK(slot));
+	clrbits_be32(&immap->im_pcmcia.pcmc_per, PCMCIA_MASK(slot));
+
+	/*
+	 * Disable interrupts, DMA, and PCMCIA buffers
+	 * (isolate the interface) and assert RESET signal
+	 */
+	debug("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= NSCU_GCRX_CXOE;
+
+	PCMCIA_PGCRX(slot) = reg;
+	udelay(500);
+
+	power_config(slot);
+	power_off(slot);
+
+	/*
+	 * Make sure there is a card in the slot, then configure the interface.
+	*/
+	udelay(10000);
+	reg = debug_get_pipr();
+	debug("[%d] %s: PIPR(%p)=0x%x\n", __LINE__, __FUNCTION__,
+		&immap->im_pcmcia.pcmc_pipr, reg);
+
+	if (check_card_is_absent(slot)) {
+		printf ("   No Card found\n");
+		return (1);
+	}
+
+	/*
+	 * Power On.
+	 */
+	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+	reg = in_be32(&immap->im_pcmcia.pcmc_pipr);
+	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+	       reg,
+	       (reg & PCMCIA_VS1(slot)) ? "n" : "ff",
+	       (reg & PCMCIA_VS2(slot)) ? "n" : "ff");
+
+	if ((reg & mask) == mask) {
+		power_on_5_0(slot);
+		puts (" 5.0V card found: ");
+	} else {
+		power_on_3_3(slot);
+		puts (" 3.3V card found: ");
+	}
+
+#if 0
+	/*  VCC switch error flag, PCMCIA slot INPACK_ pin */
+	cp->cp_pbdir &= ~(0x0020 | 0x0010);
+	cp->cp_pbpar &= ~(0x0020 | 0x0010);
+	udelay(500000);
+#endif
+
+	udelay(1000);
+	debug("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(slot);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	reg &= ~NSCU_GCRX_CXOE;
+
+	PCMCIA_PGCRX(slot) = reg;
+
+	udelay(250000);	/* some cards need >150 ms to come up :-( */
+
+	debug("# hardware_enable done\n");
+
+	return (0);
+}
+
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+	u_long reg;
+
+	debug("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	/* remove all power */
+	power_off(slot);
+
+	debug("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= NSCU_GCRX_CXOE;			/* active low  */
+
+	PCMCIA_PGCRX(slot) = reg;
+
+	udelay(10000);
+
+	return (0);
+}
+#endif
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+	u_long reg;
+	uint32_t pipr = 0;
+
+	debug("voltage_set: " PCMCIA_BOARD_MSG
+		" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+		'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+	/*
+	 * Disable PCMCIA buffers (isolate the interface)
+	 * and assert RESET signal
+	 */
+	debug("Disable PCMCIA buffers and assert RESET\n");
+	reg  = PCMCIA_PGCRX(slot);
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	reg |= NSCU_GCRX_CXOE;			/* active low  */
+
+	PCMCIA_PGCRX(slot) = reg;
+	udelay(500);
+
+	debug("PCMCIA power OFF\n");
+	power_config(slot);
+	power_off(slot);
+
+	switch(vcc) {
+		case  0:			break;
+		case 33: power_on_3_3(slot);	break;
+		case 50: power_on_5_0(slot);	break;
+		default:			goto done;
+	}
+
+	/* Checking supported voltages */
+	pipr = debug_get_pipr();
+	debug("PIPR: 0x%x --> %s\n", pipr,
+	       (pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+	if (vcc)
+		debug("PCMCIA powered at %sV\n", (vcc == 50) ? "5.0" : "3.3");
+	else
+		debug("PCMCIA powered down\n");
+
+done:
+	debug("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(slot);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	reg &= ~NSCU_GCRX_CXOE;			/* active low  */
+
+	PCMCIA_PGCRX(slot) = reg;
+	udelay(500);
+
+	debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A');
+	return 0;
+}
+
+#endif	/* CONFIG_PCMCIA && CONFIG_TQM8xxL */