avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/drivers/pch/Makefile

@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += pch-uclass.o
+obj-y += pch7.o
+obj-y += pch9.o

u-boot/drivers/pch/pch-uclass.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+#include <dm/root.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int pch_get_spi_base(struct udevice *dev, ulong *sbasep)
+{
+	struct pch_ops *ops = pch_get_ops(dev);
+
+	*sbasep = 0;
+	if (!ops->get_spi_base)
+		return -ENOSYS;
+
+	return ops->get_spi_base(dev, sbasep);
+}
+
+int pch_set_spi_protect(struct udevice *dev, bool protect)
+{
+	struct pch_ops *ops = pch_get_ops(dev);
+
+	if (!ops->set_spi_protect)
+		return -ENOSYS;
+
+	return ops->set_spi_protect(dev, protect);
+}
+
+int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+	struct pch_ops *ops = pch_get_ops(dev);
+
+	*gbasep = 0;
+	if (!ops->get_gpio_base)
+		return -ENOSYS;
+
+	return ops->get_gpio_base(dev, gbasep);
+}
+
+int pch_get_io_base(struct udevice *dev, u32 *iobasep)
+{
+	struct pch_ops *ops = pch_get_ops(dev);
+
+	*iobasep = 0;
+	if (!ops->get_io_base)
+		return -ENOSYS;
+
+	return ops->get_io_base(dev, iobasep);
+}
+
+static int pch_uclass_post_bind(struct udevice *bus)
+{
+	/*
+	 * Scan the device tree for devices
+	 *
+	 * Before relocation, only bind devices marked for pre-relocation
+	 * use.
+	 */
+	return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
+				gd->flags & GD_FLG_RELOC ? false : true);
+}
+
+UCLASS_DRIVER(pch) = {
+	.id		= UCLASS_PCH,
+	.name		= "pch",
+	.post_bind	= pch_uclass_post_bind,
+};

u-boot/drivers/pch/pch7.c

@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+
+#define GPIO_BASE	0x44
+#define BIOS_CTRL	0xd8
+
+static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep)
+{
+	u32 rcba;
+
+	dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
+	rcba = rcba & 0xffffc000;
+	*sbasep = rcba + 0x3020;
+
+	return 0;
+}
+
+static int pch7_set_spi_protect(struct udevice *dev, bool protect)
+{
+	uint8_t bios_cntl;
+
+	/* Adjust the BIOS write protect to dis/allow write commands */
+	dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
+	if (protect)
+		bios_cntl &= ~BIOS_CTRL_BIOSWE;
+	else
+		bios_cntl |= BIOS_CTRL_BIOSWE;
+	dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
+
+	return 0;
+}
+
+static int pch7_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+	u32 base;
+
+	/*
+	 * GPIO_BASE moved to its current offset with ICH6, but prior to
+	 * that it was unused (or undocumented). Check that it looks
+	 * okay: not all ones or zeros.
+	 *
+	 * Note we don't need check bit0 here, because the Tunnel Creek
+	 * GPIO base address register bit0 is reserved (read returns 0),
+	 * while on the Ivybridge the bit0 is used to indicate it is an
+	 * I/O space.
+	 */
+	dm_pci_read_config32(dev, GPIO_BASE, &base);
+	if (base == 0x00000000 || base == 0xffffffff) {
+		debug("%s: unexpected BASE value\n", __func__);
+		return -ENODEV;
+	}
+
+	/*
+	 * Okay, I guess we're looking at the right device. The actual
+	 * GPIO registers are in the PCI device's I/O space, starting
+	 * at the offset that we just read. Bit 0 indicates that it's
+	 * an I/O address, not a memory address, so mask that off.
+	 */
+	*gbasep = base & 1 ? base & ~3 : base & ~15;
+
+	return 0;
+}
+
+static const struct pch_ops pch7_ops = {
+	.get_spi_base	= pch7_get_spi_base,
+	.set_spi_protect = pch7_set_spi_protect,
+	.get_gpio_base	= pch7_get_gpio_base,
+};
+
+static const struct udevice_id pch7_ids[] = {
+	{ .compatible = "intel,pch7" },
+	{ }
+};
+
+U_BOOT_DRIVER(pch7_drv) = {
+	.name		= "intel-pch7",
+	.id		= UCLASS_PCH,
+	.of_match	= pch7_ids,
+	.ops		= &pch7_ops,
+};

u-boot/drivers/pch/pch9.c

@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+
+#define GPIO_BASE	0x48
+#define IO_BASE		0x4c
+#define SBASE_ADDR	0x54
+
+static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
+{
+	uint32_t sbase_addr;
+
+	dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
+	*sbasep = sbase_addr & 0xfffffe00;
+
+	return 0;
+}
+
+static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+	u32 base;
+
+	/*
+	 * GPIO_BASE moved to its current offset with ICH6, but prior to
+	 * that it was unused (or undocumented). Check that it looks
+	 * okay: not all ones or zeros.
+	 *
+	 * Note we don't need check bit0 here, because the Tunnel Creek
+	 * GPIO base address register bit0 is reserved (read returns 0),
+	 * while on the Ivybridge the bit0 is used to indicate it is an
+	 * I/O space.
+	 */
+	dm_pci_read_config32(dev, GPIO_BASE, &base);
+	if (base == 0x00000000 || base == 0xffffffff) {
+		debug("%s: unexpected BASE value\n", __func__);
+		return -ENODEV;
+	}
+
+	/*
+	 * Okay, I guess we're looking at the right device. The actual
+	 * GPIO registers are in the PCI device's I/O space, starting
+	 * at the offset that we just read. Bit 0 indicates that it's
+	 * an I/O address, not a memory address, so mask that off.
+	 */
+	*gbasep = base & 1 ? base & ~3 : base & ~15;
+
+	return 0;
+}
+
+static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
+{
+	u32 base;
+
+	dm_pci_read_config32(dev, IO_BASE, &base);
+	if (base == 0x00000000 || base == 0xffffffff) {
+		debug("%s: unexpected BASE value\n", __func__);
+		return -ENODEV;
+	}
+
+	*iobasep = base & 1 ? base & ~3 : base & ~15;
+
+	return 0;
+}
+
+static const struct pch_ops pch9_ops = {
+	.get_spi_base	= pch9_get_spi_base,
+	.get_gpio_base	= pch9_get_gpio_base,
+	.get_io_base	= pch9_get_io_base,
+};
+
+static const struct udevice_id pch9_ids[] = {
+	{ .compatible = "intel,pch9" },
+	{ }
+};
+
+U_BOOT_DRIVER(pch9_drv) = {
+	.name		= "intel-pch9",
+	.id		= UCLASS_PCH,
+	.of_match	= pch9_ids,
+	.ops		= &pch9_ops,
+};