avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/drivers/mailbox/Kconfig

@@ -0,0 +1,27 @@
+menu "Mailbox Controller Support"
+
+config DM_MAILBOX
+	bool "Enable mailbox controllers using Driver Model"
+	depends on DM && OF_CONTROL
+	help
+	  Enable support for the mailbox driver class. Mailboxes provide the
+	  ability to transfer small messages and/or notifications from one
+	  CPU to another CPU, or sometimes to dedicated HW modules. They form
+	  the basis of a variety of inter-process/inter-CPU communication
+	  protocols.
+
+config SANDBOX_MBOX
+	bool "Enable the sandbox mailbox test driver"
+	depends on DM_MAILBOX && SANDBOX
+	help
+	  Enable support for a test mailbox implementation, which simply echos
+	  back a modified version of any message that is sent.
+
+config TEGRA_HSP
+	bool "Enable Tegra HSP controller support"
+	depends on DM_MAILBOX && TEGRA
+	help
+	  This enables support for the NVIDIA Tegra HSP Hw module, which
+	  implements doorbells, mailboxes, semaphores, and shared interrupts.
+
+endmenu

u-boot/drivers/mailbox/Makefile

@@ -0,0 +1,8 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_DM_MAILBOX) += mailbox-uclass.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
+obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o

u-boot/drivers/mailbox/mailbox-uclass.c

@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <mailbox.h>
+#include <mailbox-uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline struct mbox_ops *mbox_dev_ops(struct udevice *dev)
+{
+	return (struct mbox_ops *)dev->driver->ops;
+}
+
+static int mbox_of_xlate_default(struct mbox_chan *chan,
+				 struct fdtdec_phandle_args *args)
+{
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	if (args->args_count != 1) {
+		debug("Invaild args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	chan->id = args->args[0];
+
+	return 0;
+}
+
+int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan)
+{
+	struct fdtdec_phandle_args args;
+	int ret;
+	struct udevice *dev_mbox;
+	struct mbox_ops *ops;
+
+	debug("%s(dev=%p, index=%d, chan=%p)\n", __func__, dev, index, chan);
+
+	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+					     "mboxes", "#mbox-cells", 0,
+					     index, &args);
+	if (ret) {
+		debug("%s: fdtdec_parse_phandle_with_args failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_MAILBOX, args.node,
+					     &dev_mbox);
+	if (ret) {
+		debug("%s: uclass_get_device_by_of_offset failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+	ops = mbox_dev_ops(dev_mbox);
+
+	chan->dev = dev_mbox;
+	if (ops->of_xlate)
+		ret = ops->of_xlate(chan, &args);
+	else
+		ret = mbox_of_xlate_default(chan, &args);
+	if (ret) {
+		debug("of_xlate() failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = ops->request(chan);
+	if (ret) {
+		debug("ops->request() failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int mbox_get_by_name(struct udevice *dev, const char *name,
+		     struct mbox_chan *chan)
+{
+	int index;
+
+	debug("%s(dev=%p, name=%s, chan=%p)\n", __func__, dev, name, chan);
+
+	index = fdt_find_string(gd->fdt_blob, dev->of_offset, "mbox-names",
+				name);
+	if (index < 0) {
+		debug("fdt_find_string() failed: %d\n", index);
+		return index;
+	}
+
+	return mbox_get_by_index(dev, index, chan);
+}
+
+int mbox_free(struct mbox_chan *chan)
+{
+	struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	return ops->free(chan);
+}
+
+int mbox_send(struct mbox_chan *chan, const void *data)
+{
+	struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	return ops->send(chan, data);
+}
+
+int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us)
+{
+	struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+	ulong start_time;
+	int ret;
+
+	debug("%s(chan=%p, data=%p, timeout_us=%ld)\n", __func__, chan, data,
+	      timeout_us);
+
+	start_time = timer_get_us();
+	/*
+	 * Account for partial us ticks, but if timeout_us is 0, ensure we
+	 * still don't wait at all.
+	 */
+	if (timeout_us)
+		timeout_us++;
+
+	for (;;) {
+		ret = ops->recv(chan, data);
+		if (ret != -ENODATA)
+			return ret;
+		if ((timer_get_us() - start_time) >= timeout_us)
+			return -ETIMEDOUT;
+	}
+}
+
+UCLASS_DRIVER(mailbox) = {
+	.id		= UCLASS_MAILBOX,
+	.name		= "mailbox",
+};

u-boot/drivers/mailbox/sandbox-mbox-test.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox.h>
+#include <asm/io.h>
+
+struct sandbox_mbox_test {
+	struct mbox_chan chan;
+};
+
+int sandbox_mbox_test_get(struct udevice *dev)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_get_by_name(dev, "test", &sbmt->chan);
+}
+
+int sandbox_mbox_test_send(struct udevice *dev, uint32_t msg)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_send(&sbmt->chan, &msg);
+}
+
+int sandbox_mbox_test_recv(struct udevice *dev, uint32_t *msg)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_recv(&sbmt->chan, msg, 100);
+}
+
+int sandbox_mbox_test_free(struct udevice *dev)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_free(&sbmt->chan);
+}
+
+static const struct udevice_id sandbox_mbox_test_ids[] = {
+	{ .compatible = "sandbox,mbox-test" },
+	{ }
+};
+
+U_BOOT_DRIVER(sandbox_mbox_test) = {
+	.name = "sandbox_mbox_test",
+	.id = UCLASS_MISC,
+	.of_match = sandbox_mbox_test_ids,
+	.priv_auto_alloc_size = sizeof(struct sandbox_mbox_test),
+};

u-boot/drivers/mailbox/sandbox-mbox.c

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox-uclass.h>
+#include <asm/io.h>
+#include <asm/mbox.h>
+
+#define SANDBOX_MBOX_CHANNELS 2
+
+struct sandbox_mbox_chan {
+	bool rx_msg_valid;
+	uint32_t rx_msg;
+};
+
+struct sandbox_mbox {
+	struct sandbox_mbox_chan chans[SANDBOX_MBOX_CHANNELS];
+};
+
+static int sandbox_mbox_request(struct mbox_chan *chan)
+{
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	if (chan->id >= SANDBOX_MBOX_CHANNELS)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int sandbox_mbox_free(struct mbox_chan *chan)
+{
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	return 0;
+}
+
+static int sandbox_mbox_send(struct mbox_chan *chan, const void *data)
+{
+	struct sandbox_mbox *sbm = dev_get_priv(chan->dev);
+	const uint32_t *pmsg = data;
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	sbm->chans[chan->id].rx_msg = *pmsg ^ SANDBOX_MBOX_PING_XOR;
+	sbm->chans[chan->id].rx_msg_valid = true;
+
+	return 0;
+}
+
+static int sandbox_mbox_recv(struct mbox_chan *chan, void *data)
+{
+	struct sandbox_mbox *sbm = dev_get_priv(chan->dev);
+	uint32_t *pmsg = data;
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	if (!sbm->chans[chan->id].rx_msg_valid)
+		return -ENODATA;
+
+	*pmsg = sbm->chans[chan->id].rx_msg;
+	sbm->chans[chan->id].rx_msg_valid = false;
+
+	return 0;
+}
+
+static int sandbox_mbox_bind(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static int sandbox_mbox_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static const struct udevice_id sandbox_mbox_ids[] = {
+	{ .compatible = "sandbox,mbox" },
+	{ }
+};
+
+struct mbox_ops sandbox_mbox_mbox_ops = {
+	.request = sandbox_mbox_request,
+	.free = sandbox_mbox_free,
+	.send = sandbox_mbox_send,
+	.recv = sandbox_mbox_recv,
+};
+
+U_BOOT_DRIVER(sandbox_mbox) = {
+	.name = "sandbox_mbox",
+	.id = UCLASS_MAILBOX,
+	.of_match = sandbox_mbox_ids,
+	.bind = sandbox_mbox_bind,
+	.probe = sandbox_mbox_probe,
+	.priv_auto_alloc_size = sizeof(struct sandbox_mbox),
+	.ops = &sandbox_mbox_mbox_ops,
+};

u-boot/drivers/mailbox/tegra-hsp.c

@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <mailbox-uclass.h>
+#include <dt-bindings/mailbox/tegra-hsp.h>
+
+#define TEGRA_HSP_DB_REG_TRIGGER	0x0
+#define TEGRA_HSP_DB_REG_ENABLE		0x4
+#define TEGRA_HSP_DB_REG_RAW		0x8
+#define TEGRA_HSP_DB_REG_PENDING	0xc
+
+#define TEGRA_HSP_DB_ID_CCPLEX		1
+#define TEGRA_HSP_DB_ID_BPMP		3
+#define TEGRA_HSP_DB_ID_NUM		7
+
+struct tegra_hsp {
+	fdt_addr_t regs;
+	uint32_t db_base;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uint32_t *tegra_hsp_reg(struct tegra_hsp *thsp, uint32_t db_id,
+			       uint32_t reg)
+{
+	return (uint32_t *)(thsp->regs + thsp->db_base + (db_id * 0x100) + reg);
+}
+
+static uint32_t tegra_hsp_readl(struct tegra_hsp *thsp, uint32_t db_id,
+				uint32_t reg)
+{
+	uint32_t *r = tegra_hsp_reg(thsp, db_id, reg);
+	return readl(r);
+}
+
+static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val,
+			     uint32_t db_id, uint32_t reg)
+{
+	uint32_t *r = tegra_hsp_reg(thsp, db_id, reg);
+
+	writel(val, r);
+	readl(r);
+}
+
+static int tegra_hsp_db_id(ulong chan_id)
+{
+	switch (chan_id) {
+	case TEGRA_HSP_MASTER_BPMP:
+		return TEGRA_HSP_DB_ID_BPMP;
+	default:
+		debug("Invalid channel ID\n");
+		return -EINVAL;
+	}
+}
+
+static int tegra_hsp_request(struct mbox_chan *chan)
+{
+	int db_id;
+
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	db_id = tegra_hsp_db_id(chan->id);
+	if (db_id < 0) {
+		debug("tegra_hsp_db_id() failed: %d\n", db_id);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int tegra_hsp_free(struct mbox_chan *chan)
+{
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	return 0;
+}
+
+static int tegra_hsp_send(struct mbox_chan *chan, const void *data)
+{
+	struct tegra_hsp *thsp = dev_get_priv(chan->dev);
+	int db_id;
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	db_id = tegra_hsp_db_id(chan->id);
+	tegra_hsp_writel(thsp, 1, db_id, TEGRA_HSP_DB_REG_TRIGGER);
+
+	return 0;
+}
+
+static int tegra_hsp_recv(struct mbox_chan *chan, void *data)
+{
+	struct tegra_hsp *thsp = dev_get_priv(chan->dev);
+	uint32_t db_id = TEGRA_HSP_DB_ID_CCPLEX;
+	uint32_t val;
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	val = tegra_hsp_readl(thsp, db_id, TEGRA_HSP_DB_REG_RAW);
+	if (!(val & BIT(chan->id)))
+		return -ENODATA;
+
+	tegra_hsp_writel(thsp, BIT(chan->id), db_id, TEGRA_HSP_DB_REG_RAW);
+
+	return 0;
+}
+
+static int tegra_hsp_bind(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static int tegra_hsp_probe(struct udevice *dev)
+{
+	struct tegra_hsp *thsp = dev_get_priv(dev);
+	int nr_sm, nr_ss, nr_as;
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	thsp->regs = dev_get_addr(dev);
+	if (thsp->regs == FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	nr_sm = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SM",
+			       0);
+	nr_ss = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SS",
+			       0);
+	nr_as = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-AS",
+			       0);
+	thsp->db_base = (1 + (nr_sm >> 1) + nr_ss + nr_as) << 16;
+
+	return 0;
+}
+
+static const struct udevice_id tegra_hsp_ids[] = {
+	{ .compatible = "nvidia,tegra186-hsp" },
+	{ }
+};
+
+struct mbox_ops tegra_hsp_mbox_ops = {
+	.request = tegra_hsp_request,
+	.free = tegra_hsp_free,
+	.send = tegra_hsp_send,
+	.recv = tegra_hsp_recv,
+};
+
+U_BOOT_DRIVER(tegra_hsp) = {
+	.name = "tegra-hsp",
+	.id = UCLASS_MAILBOX,
+	.of_match = tegra_hsp_ids,
+	.bind = tegra_hsp_bind,
+	.probe = tegra_hsp_probe,
+	.priv_auto_alloc_size = sizeof(struct tegra_hsp),
+	.ops = &tegra_hsp_mbox_ops,
+};