avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/drivers/ddr/altera/Makefile

@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+# Copyright (C) 2014 Altera Corporation <www.altera.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o

u-boot/drivers/ddr/altera/sdram.c

@@ -0,0 +1,536 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2015
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <div64.h>
+#include <watchdog.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sdram_prot_rule {
+	u32	sdram_start;	/* SDRAM start address */
+	u32	sdram_end;	/* SDRAM end address */
+	u32	rule;		/* SDRAM protection rule number: 0-19 */
+	int	valid;		/* Rule valid or not? 1 - valid, 0 not*/
+
+	u32	security;
+	u32	portmask;
+	u32	result;
+	u32	lo_prot_id;
+	u32	hi_prot_id;
+};
+
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+static struct socfpga_sdr_ctrl *sdr_ctrl =
+	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+
+/**
+ * get_errata_rows() - Up the number of DRAM rows to cover entire address space
+ * @cfg:	SDRAM controller configuration data
+ *
+ * SDRAM Failure happens when accessing non-existent memory. Artificially
+ * increase the number of rows so that the memory controller thinks it has
+ * 4GB of RAM. This function returns such amount of rows.
+ */
+static int get_errata_rows(const struct socfpga_sdram_config *cfg)
+{
+	/* Define constant for 4G memory - used for SDRAM errata workaround */
+#define MEMSIZE_4G	(4ULL * 1024ULL * 1024ULL * 1024ULL)
+	const unsigned long long memsize = MEMSIZE_4G;
+	const unsigned int cs =
+		((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
+			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
+	const unsigned int rows =
+		(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
+			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
+	const unsigned int banks =
+		(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
+			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
+	const unsigned int cols =
+		(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
+			SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
+	const unsigned int width = 8;
+
+	unsigned long long newrows;
+	int bits, inewrowslog2;
+
+	debug("workaround rows - memsize %lld\n", memsize);
+	debug("workaround rows - cs        %d\n", cs);
+	debug("workaround rows - width     %d\n", width);
+	debug("workaround rows - rows      %d\n", rows);
+	debug("workaround rows - banks     %d\n", banks);
+	debug("workaround rows - cols      %d\n", cols);
+
+	newrows = lldiv(memsize, cs * (width / 8));
+	debug("rows workaround - term1 %lld\n", newrows);
+
+	newrows = lldiv(newrows, (1 << banks) * (1 << cols));
+	debug("rows workaround - term2 %lld\n", newrows);
+
+	/*
+	 * Compute the hamming weight - same as number of bits set.
+	 * Need to see if result is ordinal power of 2 before
+	 * attempting log2 of result.
+	 */
+	bits = generic_hweight32(newrows);
+
+	debug("rows workaround - bits %d\n", bits);
+
+	if (bits != 1) {
+		printf("SDRAM workaround failed, bits set %d\n", bits);
+		return rows;
+	}
+
+	if (newrows > UINT_MAX) {
+		printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
+		return rows;
+	}
+
+	inewrowslog2 = __ilog2(newrows);
+
+	debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
+
+	if (inewrowslog2 == -1) {
+		printf("SDRAM workaround failed, newrows %lld\n", newrows);
+		return rows;
+	}
+
+	return inewrowslog2;
+}
+
+/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
+static void sdram_set_rule(struct sdram_prot_rule *prule)
+{
+	u32 lo_addr_bits;
+	u32 hi_addr_bits;
+	int ruleno = prule->rule;
+
+	/* Select the rule */
+	writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
+
+	/* Obtain the address bits */
+	lo_addr_bits = prule->sdram_start >> 20ULL;
+	hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
+
+	debug("sdram set rule start %x, %d\n", lo_addr_bits,
+	      prule->sdram_start);
+	debug("sdram set rule end   %x, %d\n", hi_addr_bits,
+	      prule->sdram_end);
+
+	/* Set rule addresses */
+	writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
+
+	/* Set rule protection ids */
+	writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
+	       &sdr_ctrl->prot_rule_id);
+
+	/* Set the rule data */
+	writel(prule->security | (prule->valid << 2) |
+	       (prule->portmask << 3) | (prule->result << 13),
+	       &sdr_ctrl->prot_rule_data);
+
+	/* write the rule */
+	writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
+
+	/* Set rule number to 0 by default */
+	writel(0, &sdr_ctrl->prot_rule_rdwr);
+}
+
+static void sdram_get_rule(struct sdram_prot_rule *prule)
+{
+	u32 addr;
+	u32 id;
+	u32 data;
+	int ruleno = prule->rule;
+
+	/* Read the rule */
+	writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
+	writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
+
+	/* Get the addresses */
+	addr = readl(&sdr_ctrl->prot_rule_addr);
+	prule->sdram_start = (addr & 0xFFF) << 20;
+	prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
+
+	/* Get the configured protection IDs */
+	id = readl(&sdr_ctrl->prot_rule_id);
+	prule->lo_prot_id = id & 0xFFF;
+	prule->hi_prot_id = (id >> 12) & 0xFFF;
+
+	/* Get protection data */
+	data = readl(&sdr_ctrl->prot_rule_data);
+
+	prule->security = data & 0x3;
+	prule->valid = (data >> 2) & 0x1;
+	prule->portmask = (data >> 3) & 0x3FF;
+	prule->result = (data >> 13) & 0x1;
+}
+
+static void
+sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
+{
+	struct sdram_prot_rule rule;
+	int rules;
+
+	/* Start with accepting all SDRAM transaction */
+	writel(0x0, &sdr_ctrl->protport_default);
+
+	/* Clear all protection rules for warm boot case */
+	memset(&rule, 0, sizeof(rule));
+
+	for (rules = 0; rules < 20; rules++) {
+		rule.rule = rules;
+		sdram_set_rule(&rule);
+	}
+
+	/* new rule: accept SDRAM */
+	rule.sdram_start = sdram_start;
+	rule.sdram_end = sdram_end;
+	rule.lo_prot_id = 0x0;
+	rule.hi_prot_id = 0xFFF;
+	rule.portmask = 0x3FF;
+	rule.security = 0x3;
+	rule.result = 0;
+	rule.valid = 1;
+	rule.rule = 0;
+
+	/* set new rule */
+	sdram_set_rule(&rule);
+
+	/* default rule: reject everything */
+	writel(0x3ff, &sdr_ctrl->protport_default);
+}
+
+static void sdram_dump_protection_config(void)
+{
+	struct sdram_prot_rule rule;
+	int rules;
+
+	debug("SDRAM Prot rule, default %x\n",
+	      readl(&sdr_ctrl->protport_default));
+
+	for (rules = 0; rules < 20; rules++) {
+		rule.rule = rules;
+		sdram_get_rule(&rule);
+		debug("Rule %d, rules ...\n", rules);
+		debug("    sdram start %x\n", rule.sdram_start);
+		debug("    sdram end   %x\n", rule.sdram_end);
+		debug("    low prot id %d, hi prot id %d\n",
+		      rule.lo_prot_id,
+		      rule.hi_prot_id);
+		debug("    portmask %x\n", rule.portmask);
+		debug("    security %d\n", rule.security);
+		debug("    result %d\n", rule.result);
+		debug("    valid %d\n", rule.valid);
+	}
+}
+
+/**
+ * sdram_write_verify() - write to register and verify the write.
+ * @addr:	Register address
+ * @val:	Value to be written and verified
+ *
+ * This function writes to a register, reads back the value and compares
+ * the result with the written value to check if the data match.
+ */
+static unsigned sdram_write_verify(const u32 *addr, const u32 val)
+{
+	u32 rval;
+
+	debug("   Write - Address 0x%p Data 0x%08x\n", addr, val);
+	writel(val, addr);
+
+	debug("   Read and verify...");
+	rval = readl(addr);
+	if (rval != val) {
+		debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
+		      addr, val, rval);
+		return -EINVAL;
+	}
+
+	debug("correct!\n");
+	return 0;
+}
+
+/**
+ * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
+ * @cfg:	SDRAM controller configuration data
+ *
+ * Return the value of DRAM CTRLCFG register.
+ */
+static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
+{
+	const u32 csbits =
+		((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
+			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
+	u32 addrorder =
+		(cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
+			SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
+
+	u32 ctrl_cfg = cfg->ctrl_cfg;
+
+	/*
+	 * SDRAM Failure When Accessing Non-Existent Memory
+	 * Set the addrorder field of the SDRAM control register
+	 * based on the CSBITs setting.
+	 */
+	if (csbits == 1) {
+		if (addrorder != 0)
+			debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
+		addrorder = 0;
+	} else if (csbits == 2) {
+		if (addrorder != 2)
+			debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
+		addrorder = 2;
+	}
+
+	ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
+	ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
+
+	return ctrl_cfg;
+}
+
+/**
+ * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
+ * @cfg:	SDRAM controller configuration data
+ *
+ * Return the value of DRAM ADDRW register.
+ */
+static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
+{
+	/*
+	 * SDRAM Failure When Accessing Non-Existent Memory
+	 * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
+	 * log2(number of chip select bits). Since there's only
+	 * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
+	 * which is the same as "chip selects" - 1.
+	 */
+	const int rows = get_errata_rows(cfg);
+	u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
+
+	return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
+}
+
+/**
+ * sdr_load_regs() - Load SDRAM controller registers
+ * @cfg:	SDRAM controller configuration data
+ *
+ * This function loads the register values into the SDRAM controller block.
+ */
+static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
+{
+	const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
+	const u32 dram_addrw = sdr_get_addr_rw(cfg);
+
+	debug("\nConfiguring CTRLCFG\n");
+	writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
+
+	debug("Configuring DRAMTIMING1\n");
+	writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
+
+	debug("Configuring DRAMTIMING2\n");
+	writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
+
+	debug("Configuring DRAMTIMING3\n");
+	writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
+
+	debug("Configuring DRAMTIMING4\n");
+	writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
+
+	debug("Configuring LOWPWRTIMING\n");
+	writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
+
+	debug("Configuring DRAMADDRW\n");
+	writel(dram_addrw, &sdr_ctrl->dram_addrw);
+
+	debug("Configuring DRAMIFWIDTH\n");
+	writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
+
+	debug("Configuring DRAMDEVWIDTH\n");
+	writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
+
+	debug("Configuring LOWPWREQ\n");
+	writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
+
+	debug("Configuring DRAMINTR\n");
+	writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
+
+	debug("Configuring STATICCFG\n");
+	writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
+
+	debug("Configuring CTRLWIDTH\n");
+	writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
+
+	debug("Configuring PORTCFG\n");
+	writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
+
+	debug("Configuring FIFOCFG\n");
+	writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
+
+	debug("Configuring MPPRIORITY\n");
+	writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
+
+	debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
+	writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
+	writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
+	writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
+	writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
+
+	debug("Configuring MPPACING_MPPACING_0\n");
+	writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
+	writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
+	writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
+	writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
+
+	debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
+	writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
+	writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
+	writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
+
+	debug("Configuring PHYCTRL_PHYCTRL_0\n");
+	writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
+
+	debug("Configuring CPORTWIDTH\n");
+	writel(cfg->cport_width, &sdr_ctrl->cport_width);
+
+	debug("Configuring CPORTWMAP\n");
+	writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
+
+	debug("Configuring CPORTRMAP\n");
+	writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
+
+	debug("Configuring RFIFOCMAP\n");
+	writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
+
+	debug("Configuring WFIFOCMAP\n");
+	writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
+
+	debug("Configuring CPORTRDWR\n");
+	writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
+
+	debug("Configuring DRAMODT\n");
+	writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
+}
+
+/**
+ * sdram_mmr_init_full() - Function to initialize SDRAM MMR
+ * @sdr_phy_reg:	Value of the PHY control register 0
+ *
+ * Initialize the SDRAM MMR.
+ */
+int sdram_mmr_init_full(unsigned int sdr_phy_reg)
+{
+	const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
+	const unsigned int rows =
+		(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
+			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
+	int ret;
+
+	writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
+
+	sdr_load_regs(cfg);
+
+	/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
+	writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
+
+	/* only enable if the FPGA is programmed */
+	if (fpgamgr_test_fpga_ready()) {
+		ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
+					 cfg->fpgaport_rst);
+		if (ret)
+			return ret;
+	}
+
+	/* Restore the SDR PHY Register if valid */
+	if (sdr_phy_reg != 0xffffffff)
+		writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
+
+	/* Final step - apply configuration changes */
+	debug("Configuring STATICCFG\n");
+	clrsetbits_le32(&sdr_ctrl->static_cfg,
+			SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
+			1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
+
+	sdram_set_protection_config(0, sdram_calculate_size() - 1);
+
+	sdram_dump_protection_config();
+
+	return 0;
+}
+
+/**
+ * sdram_calculate_size() - Calculate SDRAM size
+ *
+ * Calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ */
+unsigned long sdram_calculate_size(void)
+{
+	unsigned long temp;
+	unsigned long row, bank, col, cs, width;
+	const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
+	const unsigned int csbits =
+		((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
+			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
+	const unsigned int rowbits =
+		(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
+			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
+
+	temp = readl(&sdr_ctrl->dram_addrw);
+	col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
+		SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
+
+	/*
+	 * SDRAM Failure When Accessing Non-Existent Memory
+	 * Use ROWBITS from Quartus/QSys to calculate SDRAM size
+	 * since the FB specifies we modify ROWBITs to work around SDRAM
+	 * controller issue.
+	 */
+	row = readl(&sysmgr_regs->iswgrp_handoff[4]);
+	if (row == 0)
+		row = rowbits;
+	/*
+	 * If the stored handoff value for rows is greater than
+	 * the field width in the sdr.dramaddrw register then
+	 * something is very wrong. Revert to using the the #define
+	 * value handed off by the SOCEDS tool chain instead of
+	 * using a broken value.
+	 */
+	if (row > 31)
+		row = rowbits;
+
+	bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
+		SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
+
+	/*
+	 * SDRAM Failure When Accessing Non-Existent Memory
+	 * Use CSBITs from Quartus/QSys to calculate SDRAM size
+	 * since the FB specifies we modify CSBITs to work around SDRAM
+	 * controller issue.
+	 */
+	cs = csbits;
+
+	width = readl(&sdr_ctrl->dram_if_width);
+
+	/* ECC would not be calculated as its not addressible */
+	if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
+		width = 32;
+	if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
+		width = 16;
+
+	/* calculate the SDRAM size base on this info */
+	temp = 1 << (row + bank + col);
+	temp = temp * cs * (width  / 8);
+
+	debug("%s returns %ld\n", __func__, temp);
+
+	return temp;
+}

u-boot/drivers/ddr/altera/sequencer.h

@@ -0,0 +1,227 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2015
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ */
+
+#ifndef _SEQUENCER_H_
+#define _SEQUENCER_H_
+
+#define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \
+	/ rwcfg->mem_if_write_dqs_width)
+#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \
+	/ rwcfg->mem_if_write_dqs_width)
+
+#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \
+	/ rwcfg->mem_if_write_dqs_width)
+#define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS)
+
+#define RW_MGR_RUN_SINGLE_GROUP_OFFSET		0x0
+#define RW_MGR_RUN_ALL_GROUPS_OFFSET		0x0400
+#define RW_MGR_RESET_READ_DATAPATH_OFFSET	0x1000
+#define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET	0x1400
+#define RW_MGR_INST_ROM_WRITE_OFFSET		0x1800
+#define RW_MGR_AC_ROM_WRITE_OFFSET		0x1C00
+
+#define NUM_SHADOW_REGS			1
+
+#define RW_MGR_RANK_NONE		0xFF
+#define RW_MGR_RANK_ALL			0x00
+
+#define RW_MGR_ODT_MODE_OFF		0
+#define RW_MGR_ODT_MODE_READ_WRITE	1
+
+#define NUM_CALIB_REPEAT		1
+
+#define NUM_READ_TESTS			7
+#define NUM_READ_PB_TESTS		7
+#define NUM_WRITE_TESTS			15
+#define NUM_WRITE_PB_TESTS		31
+
+#define PASS_ALL_BITS			1
+#define PASS_ONE_BIT			0
+
+/* calibration stages */
+#define CAL_STAGE_NIL			0
+#define CAL_STAGE_VFIFO			1
+#define CAL_STAGE_WLEVEL		2
+#define CAL_STAGE_LFIFO			3
+#define CAL_STAGE_WRITES		4
+#define CAL_STAGE_FULLTEST		5
+#define CAL_STAGE_REFRESH		6
+#define CAL_STAGE_CAL_SKIPPED		7
+#define CAL_STAGE_CAL_ABORTED		8
+#define CAL_STAGE_VFIFO_AFTER_WRITES	9
+
+/* calibration substages */
+#define CAL_SUBSTAGE_NIL		0
+#define CAL_SUBSTAGE_GUARANTEED_READ	1
+#define CAL_SUBSTAGE_DQS_EN_PHASE	2
+#define CAL_SUBSTAGE_VFIFO_CENTER	3
+#define CAL_SUBSTAGE_WORKING_DELAY	1
+#define CAL_SUBSTAGE_LAST_WORKING_DELAY	2
+#define CAL_SUBSTAGE_WLEVEL_COPY	3
+#define CAL_SUBSTAGE_WRITES_CENTER	1
+#define CAL_SUBSTAGE_READ_LATENCY	1
+#define CAL_SUBSTAGE_REFRESH		1
+
+#define SCC_MGR_GROUP_COUNTER_OFFSET		0x0000
+#define SCC_MGR_DQS_IN_DELAY_OFFSET		0x0100
+#define SCC_MGR_DQS_EN_PHASE_OFFSET		0x0200
+#define SCC_MGR_DQS_EN_DELAY_OFFSET		0x0300
+#define SCC_MGR_DQDQS_OUT_PHASE_OFFSET		0x0400
+#define SCC_MGR_OCT_OUT1_DELAY_OFFSET		0x0500
+#define SCC_MGR_IO_OUT1_DELAY_OFFSET		0x0700
+#define SCC_MGR_IO_IN_DELAY_OFFSET		0x0900
+
+/* HHP-HPS-specific versions of some commands */
+#define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET	0x0600
+#define SCC_MGR_IO_OE_DELAY_OFFSET		0x0800
+#define SCC_MGR_HHP_GLOBALS_OFFSET		0x0A00
+#define SCC_MGR_HHP_RFILE_OFFSET		0x0B00
+#define SCC_MGR_AFI_CAL_INIT_OFFSET		0x0D00
+
+#define SDR_PHYGRP_SCCGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x0)
+#define SDR_PHYGRP_PHYMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x1000)
+#define SDR_PHYGRP_RWMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x2000)
+#define SDR_PHYGRP_DATAMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x4000)
+#define SDR_PHYGRP_REGFILEGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x4800)
+
+#define PHY_MGR_CAL_RESET		(0)
+#define PHY_MGR_CAL_SUCCESS		(1)
+#define PHY_MGR_CAL_FAIL		(2)
+
+#define CALIB_SKIP_DELAY_LOOPS		(1 << 0)
+#define CALIB_SKIP_ALL_BITS_CHK		(1 << 1)
+#define CALIB_SKIP_DELAY_SWEEPS		(1 << 2)
+#define CALIB_SKIP_VFIFO		(1 << 3)
+#define CALIB_SKIP_LFIFO		(1 << 4)
+#define CALIB_SKIP_WLEVEL		(1 << 5)
+#define CALIB_SKIP_WRITES		(1 << 6)
+#define CALIB_SKIP_FULL_TEST		(1 << 7)
+#define CALIB_SKIP_ALL			(CALIB_SKIP_VFIFO | \
+				CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
+				CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
+#define CALIB_IN_RTL_SIM			(1 << 8)
+
+/* Scan chain manager command addresses */
+#define READ_SCC_OCT_OUT2_DELAY			0
+#define READ_SCC_DQ_OUT2_DELAY			0
+#define READ_SCC_DQS_IO_OUT2_DELAY		0
+#define READ_SCC_DM_IO_OUT2_DELAY		0
+
+/* HHP-HPS-specific values */
+#define SCC_MGR_HHP_EXTRAS_OFFSET			0
+#define SCC_MGR_HHP_DQSE_MAP_OFFSET			1
+
+/* PHY Debug mode flag constants */
+#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
+#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
+#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
+#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
+#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
+#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
+
+struct socfpga_sdr_rw_load_manager {
+	u32	load_cntr0;
+	u32	load_cntr1;
+	u32	load_cntr2;
+	u32	load_cntr3;
+};
+
+struct socfpga_sdr_rw_load_jump_manager {
+	u32	load_jump_add0;
+	u32	load_jump_add1;
+	u32	load_jump_add2;
+	u32	load_jump_add3;
+};
+
+struct socfpga_sdr_reg_file {
+	u32 signature;
+	u32 debug_data_addr;
+	u32 cur_stage;
+	u32 fom;
+	u32 failing_stage;
+	u32 debug1;
+	u32 debug2;
+	u32 dtaps_per_ptap;
+	u32 trk_sample_count;
+	u32 trk_longidle;
+	u32 delays;
+	u32 trk_rw_mgr_addr;
+	u32 trk_read_dqs_width;
+	u32 trk_rfsh;
+};
+
+/* parameter variable holder */
+struct param_type {
+	u32	read_correct_mask;
+	u32	read_correct_mask_vg;
+	u32	write_correct_mask;
+	u32	write_correct_mask_vg;
+};
+
+
+/* global variable holder */
+struct gbl_type {
+	uint32_t phy_debug_mode_flags;
+
+	/* current read latency */
+
+	uint32_t curr_read_lat;
+
+	/* error code */
+
+	uint32_t error_substage;
+	uint32_t error_stage;
+	uint32_t error_group;
+
+	/* figure-of-merit in, figure-of-merit out */
+
+	uint32_t fom_in;
+	uint32_t fom_out;
+
+	/*USER Number of RW Mgr NOP cycles between
+	write command and write data */
+	uint32_t rw_wl_nop_cycles;
+};
+
+struct socfpga_sdr_scc_mgr {
+	u32	dqs_ena;
+	u32	dqs_io_ena;
+	u32	dq_ena;
+	u32	dm_ena;
+	u32	__padding1[4];
+	u32	update;
+	u32	__padding2[7];
+	u32	active_rank;
+};
+
+/* PHY manager configuration registers. */
+struct socfpga_phy_mgr_cfg {
+	u32	phy_rlat;
+	u32	reset_mem_stbl;
+	u32	mux_sel;
+	u32	cal_status;
+	u32	cal_debug_info;
+	u32	vfifo_rd_en_ovrd;
+	u32	afi_wlat;
+	u32	afi_rlat;
+};
+
+/* PHY manager command addresses. */
+struct socfpga_phy_mgr_cmd {
+	u32	inc_vfifo_fr;
+	u32	inc_vfifo_hard_phy;
+	u32	fifo_reset;
+	u32	inc_vfifo_fr_hr;
+	u32	inc_vfifo_qr;
+};
+
+struct socfpga_data_mgr {
+	u32	__padding1;
+	u32	t_wl_add;
+	u32	mem_t_add;
+	u32	t_rl_add;
+};
+#endif /* _SEQUENCER_H_ */