avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/board/xilinx/microblaze-generic/Kconfig

@@ -0,0 +1,36 @@
+if TARGET_MICROBLAZE_GENERIC
+
+config SYS_BOARD
+	default "microblaze-generic"
+
+config SYS_VENDOR
+	default "xilinx"
+
+config SYS_CONFIG_NAME
+	default "microblaze-generic"
+
+config XILINX_MICROBLAZE0_USE_MSR_INSTR
+	int "USE_MSR_INSTR range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_PCMP_INSTR
+	int "USE_PCMP_INSTR range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_BARREL
+	int "USE_BARREL range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_DIV
+	int "USE_DIV range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_HW_MUL
+	int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
+	default 0
+
+config XILINX_MICROBLAZE0_HW_VER
+	string "Core version number"
+	default 7.10.d
+
+endif

u-boot/board/xilinx/microblaze-generic/MAINTAINERS

@@ -0,0 +1,6 @@
+MICROBLAZE-GENERIC BOARD
+M:	Michal Simek <monstr@monstr.eu>
+S:	Maintained
+F:	board/xilinx/microblaze-generic/
+F:	include/configs/microblaze-generic.h
+F:	configs/microblaze-generic_defconfig

u-boot/board/xilinx/microblaze-generic/Makefile

@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= microblaze-generic.o

u-boot/board/xilinx/microblaze-generic/config.mk

@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2007 - 2016 Michal Simek
+#
+# Michal SIMEK <monstr@monstr.eu>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
+
+# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
+CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
+
+CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
+
+PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)

u-boot/board/xilinx/microblaze-generic/microblaze-generic.c

@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* This is a board specific file.  It's OK to include board specific
+ * header files */
+
+#include <common.h>
+#include <config.h>
+#include <fdtdec.h>
+#include <asm/processor.h>
+#include <asm/microblaze_intc.h>
+#include <asm/asm.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_XILINX_GPIO
+static int reset_pin = -1;
+#endif
+
+ulong ram_base;
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = ram_base;
+	gd->bd->bi_dram[0].size = get_effective_memsize();
+}
+
+int dram_init(void)
+{
+	int node;
+	fdt_addr_t addr;
+	fdt_size_t size;
+	const void *blob = gd->fdt_blob;
+
+	node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
+					     "memory", 7);
+	if (node == -FDT_ERR_NOTFOUND) {
+		debug("DRAM: Can't get memory node\n");
+		return 1;
+	}
+	addr = fdtdec_get_addr_size(blob, node, "reg", &size);
+	if (addr == FDT_ADDR_T_NONE || size == 0) {
+		debug("DRAM: Can't get base address or size\n");
+		return 1;
+	}
+	ram_base = addr;
+
+	gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */
+	gd->ram_size = size;
+
+	return 0;
+};
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_XILINX_GPIO
+	if (reset_pin != -1)
+		gpio_direction_output(reset_pin, 1);
+#endif
+
+#ifdef CONFIG_XILINX_TB_WATCHDOG
+	hw_watchdog_disable();
+#endif
+#endif
+	puts ("Reseting board\n");
+	__asm__ __volatile__ ("	mts rmsr, r0;" \
+				"bra r0");
+
+	return 0;
+}
+
+static int gpio_init(void)
+{
+#ifdef CONFIG_XILINX_GPIO
+	reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
+	if (reset_pin != -1)
+		gpio_request(reset_pin, "reset_pin");
+#endif
+	return 0;
+}
+
+int board_late_init(void)
+{
+	gpio_init();
+
+	return 0;
+}

u-boot/board/xilinx/microblaze-generic/xparameters.h

@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * CAUTION: This file is a faked configuration !!!
+ *          There is no real target for the microblaze-generic
+ *          configuration. You have to replace this file with
+ *          the generated file from your Xilinx design flow.
+ */
+
+#define XILINX_BOARD_NAME	microblaze-generic
+
+/* Microblaze is microblaze_0 */
+#define XILINX_FSL_NUMBER	3
+
+/* GPIO is LEDs_4Bit*/
+#define XILINX_GPIO_BASEADDR	0x40000000
+
+/* Flash Memory is FLASH_2Mx32 */
+#define XILINX_FLASH_START	0x2c000000
+#define XILINX_FLASH_SIZE	0x00800000
+
+/* Watchdog IP is wxi_timebase_wdt_0 */
+#define XILINX_WATCHDOG_BASEADDR	0x50000000
+#define XILINX_WATCHDOG_IRQ		1

u-boot/board/xilinx/ppc405-generic/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_XILINX_PPC405_GENERIC
+
+config SYS_BOARD
+	default "ppc405-generic"
+
+config SYS_VENDOR
+	default "xilinx"
+
+config SYS_CONFIG_NAME
+	default "xilinx-ppc405-generic"
+
+endif

u-boot/board/xilinx/ppc405-generic/MAINTAINERS

@@ -0,0 +1,7 @@
+PPC405-GENERIC BOARD
+M:	Ricardo Ribalda <ricardo.ribalda@gmail.com>
+S:	Maintained
+F:	board/xilinx/ppc405-generic/
+F:	include/configs/xilinx-ppc405-generic.h
+F:	configs/xilinx-ppc405-generic_defconfig
+F:	configs/xilinx-ppc405-generic_flash_defconfig

u-boot/board/xilinx/ppc405-generic/Makefile

@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
+# Work supported by Qtechnology http://www.qtec.com
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= xilinx_ppc405_generic.o

u-boot/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c

@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
+ * This work has been supported by: QTechnology  http://qtec.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+ulong get_PCI_freq(void)
+{
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Xilinx PPC405 Generic Board\n");
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+			    CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
+}
+
+void get_sys_info(sys_info_t *sys_info)
+{
+	sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+	sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+	sys_info->freqPCI = 0;
+
+	return;
+}
+
+int get_serial_clock(void){
+	return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
+}

u-boot/board/xilinx/ppc405-generic/xparameters.h

@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
+#define XPAR_IIC_EEPROM_BASEADDR	0x81600000
+#define XPAR_INTC_0_BASEADDR		0x81800000
+#define XPAR_SPI_0_BASEADDR             0x83400000
+#define XPAR_FLASH_MEM0_BASEADDR	0xFE000000
+#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS	32
+#define XPAR_SPI_0_NUM_TRANSFER_BITS	8
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ	100000000
+
+#endif

u-boot/board/xilinx/ppc440-generic/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_XILINX_PPC440_GENERIC
+
+config SYS_BOARD
+	default "ppc440-generic"
+
+config SYS_VENDOR
+	default "xilinx"
+
+config SYS_CONFIG_NAME
+	default "xilinx-ppc440-generic"
+
+endif

u-boot/board/xilinx/ppc440-generic/MAINTAINERS

@@ -0,0 +1,7 @@
+PPC440-GENERIC BOARD
+M:	Ricardo Ribalda <ricardo.ribalda@gmail.com>
+S:	Maintained
+F:	board/xilinx/ppc440-generic/
+F:	include/configs/xilinx-ppc440-generic.h
+F:	configs/xilinx-ppc440-generic_defconfig
+F:	configs/xilinx-ppc440-generic_flash_defconfig

u-boot/board/xilinx/ppc440-generic/Makefile

@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
+# Work supported by Qtechnology http://www.qtec.com
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= xilinx_ppc440_generic.o
+extra-y += init.o

u-boot/board/xilinx/ppc440-generic/init.S

@@ -0,0 +1,34 @@
+/*
+ *  (C) Copyright 2008
+ *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
+ *  This work has been supported by: QTechnology  http://qtec.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+.section .bootpg,"ax"
+.globl tlbtab
+
+tlbtab:
+tlbtab_start
+tlbentry(0x00000000, SZ_256M, 0x00000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x10000000, SZ_256M, 0x10000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x20000000, SZ_256M, 0x20000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x30000000, SZ_256M, 0x30000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x40000000, SZ_256M, 0x40000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x50000000, SZ_256M, 0x50000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x60000000, SZ_256M, 0x60000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x70000000, SZ_256M, 0x70000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x80000000, SZ_256M, 0x80000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x90000000, SZ_256M, 0x90000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xa0000000, SZ_256M, 0xa0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xb0000000, SZ_256M, 0xb0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xc0000000, SZ_256M, 0xc0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xd0000000, SZ_256M, 0xd0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xe0000000, SZ_256M, 0xe0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xf0000000, SZ_256M, 0xf0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbtab_end

u-boot/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c

@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
+ * This work has been supported by: QTechnology  http://qtec.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#include <config.h>
+#include <common.h>
+#include <netdev.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+	puts("Xilinx PPC440 Generic Board\n");
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+			    CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
+}
+
+void get_sys_info(sys_info_t *sys_info)
+{
+	sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+	sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+	sys_info->freqPCI = 0;
+
+	return;
+}
+
+int get_serial_clock(void){
+	return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret = 0;
+
+	puts("Init xilinx temac\n");
+#ifdef XPAR_LLTEMAC_0_BASEADDR
+	ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR,
+			XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
+			XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR);
+
+#endif
+
+#ifdef XPAR_LLTEMAC_1_BASEADDR
+	ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR,
+			XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
+			XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR);
+#endif
+
+	return ret;
+}

u-boot/board/xilinx/ppc440-generic/xparameters.h

@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
+#define XPAR_IIC_EEPROM_BASEADDR	0x81600000
+#define XPAR_INTC_0_BASEADDR		0x87000000
+#define XPAR_FLASH_MEM0_BASEADDR	0xF0000000
+#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS	32
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ	100000000
+#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80
+#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98
+#define XPAR_LLTEMAC_0_BASEADDR		0x83000000
+#define XPAR_LLTEMAC_1_BASEADDR		0x83000040
+
+#endif

u-boot/board/xilinx/zynq/.gitignore

@@ -0,0 +1 @@
+/ps7_init_gpl.[ch]

u-boot/board/xilinx/zynq/MAINTAINERS

@@ -0,0 +1,6 @@
+ZYNQ BOARD
+M:	Michal Simek <monstr@monstr.eu>
+S:	Maintained
+F:	board/xilinx/zynq/
+F:	include/configs/zynq*.h
+F:	configs/zynq_*_defconfig

u-boot/board/xilinx/zynq/Makefile

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+
+init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
+	$(hw-platform-y)/ps7_init_gpl.o)
+
+ifeq ($(init-objs),)
+ifneq ($(wildcard $(srctree)/$(src)/ps7_init_gpl.c),)
+init-objs := ps7_init_gpl.o
+$(if $(CONFIG_SPL_BUILD),\
+$(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custom_hw_platform/))
+endif
+endif
+
+obj-$(CONFIG_SPL_BUILD) += $(init-objs)
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
+
+# To include xil_io.h
+CFLAGS_ps7_init_gpl.o := -I$(srctree)/$(src)

u-boot/board/xilinx/zynq/board.c

@@ -0,0 +1,244 @@
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <fpga.h>
+#include <mmc.h>
+#include <zynqpl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static xilinx_desc fpga;
+
+/* It can be done differently */
+static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
+static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
+static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
+#endif
+
+int board_init(void)
+{
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	u32 idcode;
+
+	idcode = zynq_slcr_get_idcode();
+
+	switch (idcode) {
+	case XILINX_ZYNQ_7010:
+		fpga = fpga010;
+		break;
+	case XILINX_ZYNQ_7015:
+		fpga = fpga015;
+		break;
+	case XILINX_ZYNQ_7020:
+		fpga = fpga020;
+		break;
+	case XILINX_ZYNQ_7030:
+		fpga = fpga030;
+		break;
+	case XILINX_ZYNQ_7035:
+		fpga = fpga035;
+		break;
+	case XILINX_ZYNQ_7045:
+		fpga = fpga045;
+		break;
+	case XILINX_ZYNQ_7100:
+		fpga = fpga100;
+		break;
+	}
+#endif
+
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	fpga_init();
+	fpga_add(fpga_xilinx, &fpga);
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+	case ZYNQ_BM_NOR:
+		setenv("modeboot", "norboot");
+		break;
+	case ZYNQ_BM_SD:
+		setenv("modeboot", "sdboot");
+		break;
+	case ZYNQ_BM_JTAG:
+		setenv("modeboot", "jtagboot");
+		break;
+	default:
+		setenv("modeboot", "");
+		break;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board: Xilinx Zynq\n");
+	return 0;
+}
+#endif
+
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
+    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
+	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
+			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
+			ethaddr, 6))
+		printf("I2C EEPROM MAC address read failed\n");
+#endif
+
+	return 0;
+}
+
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+/*
+ * fdt_get_reg - Fill buffer by information from DT
+ */
+static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
+			       const u32 *cell, int n)
+{
+	int i = 0, b, banks;
+	int parent_offset = fdt_parent_offset(fdt, nodeoffset);
+	int address_cells = fdt_address_cells(fdt, parent_offset);
+	int size_cells = fdt_size_cells(fdt, parent_offset);
+	char *p = buf;
+	u64 val;
+	u64 vals;
+
+	debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
+	      __func__, address_cells, size_cells, buf, cell);
+
+	/* Check memory bank setup */
+	banks = n % (address_cells + size_cells);
+	if (banks)
+		panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
+		      n, address_cells, size_cells);
+
+	banks = n / (address_cells + size_cells);
+
+	for (b = 0; b < banks; b++) {
+		debug("%s: Bank #%d:\n", __func__, b);
+		if (address_cells == 2) {
+			val = cell[i + 1];
+			val <<= 32;
+			val |= cell[i];
+			val = fdt64_to_cpu(val);
+			debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
+			      __func__, val, p, &cell[i]);
+			*(phys_addr_t *)p = val;
+		} else {
+			debug("%s: addr32=%x, ptr=%p\n",
+			      __func__, fdt32_to_cpu(cell[i]), p);
+			*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
+		}
+		p += sizeof(phys_addr_t);
+		i += address_cells;
+
+		debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
+		      sizeof(phys_addr_t));
+
+		if (size_cells == 2) {
+			vals = cell[i + 1];
+			vals <<= 32;
+			vals |= cell[i];
+			vals = fdt64_to_cpu(vals);
+
+			debug("%s: size64=%llx, ptr=%p, cell=%p\n",
+			      __func__, vals, p, &cell[i]);
+			*(phys_size_t *)p = vals;
+		} else {
+			debug("%s: size32=%x, ptr=%p\n",
+			      __func__, fdt32_to_cpu(cell[i]), p);
+			*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
+		}
+		p += sizeof(phys_size_t);
+		i += size_cells;
+
+		debug("%s: ps=%p, i=%x, size=%zu\n",
+		      __func__, p, i, sizeof(phys_size_t));
+	}
+
+	/* Return the first address size */
+	return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
+}
+
+#define FDT_REG_SIZE  sizeof(u32)
+/* Temp location for sharing data for storing */
+/* Up to 64-bit address + 64-bit size */
+static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+
+void dram_init_banksize(void)
+{
+	int bank;
+
+	memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		debug("Bank #%d: start %llx\n", bank,
+		      (unsigned long long)gd->bd->bi_dram[bank].start);
+		debug("Bank #%d: size %llx\n", bank,
+		      (unsigned long long)gd->bd->bi_dram[bank].size);
+	}
+}
+
+int dram_init(void)
+{
+	int node, len;
+	const void *blob = gd->fdt_blob;
+	const u32 *cell;
+
+	memset(&tmp, 0, sizeof(tmp));
+
+	/* find or create "/memory" node. */
+	node = fdt_subnode_offset(blob, 0, "memory");
+	if (node < 0) {
+		printf("%s: Can't get memory node\n", __func__);
+		return node;
+	}
+
+	/* Get pointer to cells and lenght of it */
+	cell = fdt_getprop(blob, node, "reg", &len);
+	if (!cell) {
+		printf("%s: Can't get reg property\n", __func__);
+		return -1;
+	}
+
+	gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
+
+	debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+
+	zynq_ddrc_init();
+
+	return 0;
+}
+#else
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	zynq_ddrc_init();
+
+	return 0;
+}
+#endif

u-boot/board/xilinx/zynq/xil_io.h

@@ -0,0 +1,13 @@
+/*
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H
+
+/*
+ * This empty file is here because ps7_init_gpl.c exported by hw project
+ * has #include "xil_io.h" line.
+ */
+
+#endif /* XIL_IO_H */

u-boot/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h

@@ -0,0 +1,117 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158731
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  100000000
+#define FPGA2_FREQ  33333336
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif

u-boot/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h

@@ -0,0 +1,117 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158731
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  25000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  23809523
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  50000000
+#define FPGA1_FREQ  50000000
+#define FPGA2_FREQ  50000000
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif

u-boot/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h

@@ -0,0 +1,117 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158731
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  25000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  50000000
+#define FPGA1_FREQ  50000000
+#define FPGA2_FREQ  50000000
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif

u-boot/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h

@@ -0,0 +1,117 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158731
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  142857132
+#define FPGA2_FREQ  50000000
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif

u-boot/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h

@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*typedef unsigned int  u32; */
+
+/** do we need to make this name more unique ? **/
+/*extern u32 ps7_init_data[]; */
+extern unsigned long *ps7_ddr_init_data;
+extern unsigned long *ps7_mio_init_data;
+extern unsigned long *ps7_pll_init_data;
+extern unsigned long *ps7_clock_init_data;
+extern unsigned long *ps7_peripherals_init_data;
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ((OPCODE_EXIT      << 4) | 0)
+#define EMIT_CLEAR(addr)              ((OPCODE_CLEAR     << 4) | 1) , addr
+#define EMIT_WRITE(addr, val)          ((OPCODE_WRITE     << 4) | 2) , addr, val
+#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
+#define EMIT_MASKPOLL(addr, mask)      ((OPCODE_MASKPOLL  << 4) | 2) , addr, mask
+#define EMIT_MASKDELAY(addr, mask)      ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)	/* 0 is success in good old C */
+#define PS7_INIT_CORRUPT   (1)	/* 1 the data is corrupted, and slcr reg are in corrupted state now */
+#define PS7_INIT_TIMEOUT   (2)	/* 2 when a poll operation timed out */
+#define PS7_POLL_FAILED_DDR_INIT (3)	/* 3 when a poll operation timed out for ddr init */
+#define PS7_POLL_FAILED_DMA      (4)	/* 4 when a poll operation timed out for dma done bit */
+#define PS7_POLL_FAILED_PLL      (5)	/* 5 when a poll operation timed out for pll sequence init */
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  650000000
+#define DDR_FREQ  525000000
+#define DCI_FREQ  10096154
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  108333336
+#define WDT_FREQ  108333336
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  142857132
+#define FPGA2_FREQ  200000000
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config(unsigned long *);
+int ps7_init(void);
+int ps7_post_config(void);
+int ps7_debug(void);
+char *getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(void);
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif

u-boot/board/xilinx/zynqmp/MAINTAINERS

@@ -0,0 +1,6 @@
+XILINX_ZYNQMP BOARDS
+M:	Michal Simek <michal.simek@xilinx.com>
+S:	Maintained
+F:	board/xilinx/zynqmp/
+F:	include/configs/xilinx_zynqmp*
+F:	configs/xilinx_zynqmp*

u-boot/board/xilinx/zynqmp/Makefile

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2014 - 2016 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= zynqmp.o
+
+hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME))
+
+init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
+	$(hw-platform-y)/psu_init_gpl.o)
+
+ifeq ($(init-objs),)
+ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),)
+init-objs := psu_init_gpl.o
+$(if $(CONFIG_SPL_BUILD),\
+$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/))
+endif
+endif
+
+obj-$(CONFIG_SPL_BUILD) += $(init-objs)
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
+
+# To include xil_io.h
+CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src)

u-boot/board/xilinx/zynqmp/xil_io.h

@@ -0,0 +1,35 @@
+/*
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H
+
+/* FIXME remove this when vivado is fixed */
+#include <asm/io.h>
+
+#define xil_printf(...)
+
+void Xil_ICacheEnable(void)
+{}
+
+void Xil_DCacheEnable(void)
+{}
+
+void Xil_ICacheDisable(void)
+{}
+
+void Xil_DCacheDisable(void)
+{}
+
+void Xil_Out32(unsigned long addr, unsigned long val)
+{
+	writel(val, addr);
+}
+
+int Xil_In32(unsigned long addr)
+{
+	return readl(addr);
+}
+
+#endif /* XIL_IO_H */

u-boot/board/xilinx/zynqmp/zynqmp.c

@@ -0,0 +1,309 @@
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <sata.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <malloc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	printf("EL Level:\tEL%d\n", current_el());
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	u32 val;
+
+	if (current_el() == 3) {
+		val = readl(&crlapb_base->timestamp_ref_ctrl);
+		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+		writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+		/* Program freq register in System counter */
+		writel(zynqmp_get_system_timer_freq(),
+		       &iou_scntr_secure->base_frequency_id_register);
+		/* And enable system counter */
+		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+		       &iou_scntr_secure->counter_control_register);
+	}
+	/* Program freq register in System counter and enable system counter */
+	writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
+	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
+	       ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+	       &iou_scntr->counter_control_register);
+
+	return 0;
+}
+
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
+    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
+    defined(CONFIG_ZYNQ_EEPROM_BUS)
+	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
+
+	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
+			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
+			ethaddr, 6))
+		printf("I2C EEPROM MAC address read failed\n");
+#endif
+
+	return 0;
+}
+
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+/*
+ * fdt_get_reg - Fill buffer by information from DT
+ */
+static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
+			       const u32 *cell, int n)
+{
+	int i = 0, b, banks;
+	int parent_offset = fdt_parent_offset(fdt, nodeoffset);
+	int address_cells = fdt_address_cells(fdt, parent_offset);
+	int size_cells = fdt_size_cells(fdt, parent_offset);
+	char *p = buf;
+	u64 val;
+	u64 vals;
+
+	debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
+	      __func__, address_cells, size_cells, buf, cell);
+
+	/* Check memory bank setup */
+	banks = n % (address_cells + size_cells);
+	if (banks)
+		panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
+		      n, address_cells, size_cells);
+
+	banks = n / (address_cells + size_cells);
+
+	for (b = 0; b < banks; b++) {
+		debug("%s: Bank #%d:\n", __func__, b);
+		if (address_cells == 2) {
+			val = cell[i + 1];
+			val <<= 32;
+			val |= cell[i];
+			val = fdt64_to_cpu(val);
+			debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
+			      __func__, val, p, &cell[i]);
+			*(phys_addr_t *)p = val;
+		} else {
+			debug("%s: addr32=%x, ptr=%p\n",
+			      __func__, fdt32_to_cpu(cell[i]), p);
+			*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
+		}
+		p += sizeof(phys_addr_t);
+		i += address_cells;
+
+		debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
+		      sizeof(phys_addr_t));
+
+		if (size_cells == 2) {
+			vals = cell[i + 1];
+			vals <<= 32;
+			vals |= cell[i];
+			vals = fdt64_to_cpu(vals);
+
+			debug("%s: size64=%llx, ptr=%p, cell=%p\n",
+			      __func__, vals, p, &cell[i]);
+			*(phys_size_t *)p = vals;
+		} else {
+			debug("%s: size32=%x, ptr=%p\n",
+			      __func__, fdt32_to_cpu(cell[i]), p);
+			*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
+		}
+		p += sizeof(phys_size_t);
+		i += size_cells;
+
+		debug("%s: ps=%p, i=%x, size=%zu\n",
+		      __func__, p, i, sizeof(phys_size_t));
+	}
+
+	/* Return the first address size */
+	return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
+}
+
+#define FDT_REG_SIZE  sizeof(u32)
+/* Temp location for sharing data for storing */
+/* Up to 64-bit address + 64-bit size */
+static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+
+void dram_init_banksize(void)
+{
+	int bank;
+
+	memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		debug("Bank #%d: start %llx\n", bank,
+		      (unsigned long long)gd->bd->bi_dram[bank].start);
+		debug("Bank #%d: size %llx\n", bank,
+		      (unsigned long long)gd->bd->bi_dram[bank].size);
+	}
+}
+
+int dram_init(void)
+{
+	int node, len;
+	const void *blob = gd->fdt_blob;
+	const u32 *cell;
+
+	memset(&tmp, 0, sizeof(tmp));
+
+	/* find or create "/memory" node. */
+	node = fdt_subnode_offset(blob, 0, "memory");
+	if (node < 0) {
+		printf("%s: Can't get memory node\n", __func__);
+		return node;
+	}
+
+	/* Get pointer to cells and lenght of it */
+	cell = fdt_getprop(blob, node, "reg", &len);
+	if (!cell) {
+		printf("%s: Can't get reg property\n", __func__);
+		return -1;
+	}
+
+	gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
+
+	debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+
+	return 0;
+}
+#else
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+#endif
+
+void reset_cpu(ulong addr)
+{
+}
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+void scsi_init(void)
+{
+#if defined(CONFIG_SATA_CEVA)
+	init_sata(0);
+#endif
+	ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
+	scsi_scan(1);
+}
+#endif
+
+int board_late_init(void)
+{
+	u32 reg = 0;
+	u8 bootmode;
+	const char *mode;
+	char *new_targets;
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	reg = readl(&crlapb_base->boot_mode);
+	bootmode = reg & BOOT_MODES_MASK;
+
+	puts("Bootmode: ");
+	switch (bootmode) {
+	case JTAG_MODE:
+		puts("JTAG_MODE\n");
+		mode = "pxe dhcp";
+		break;
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		mode = "qspi0";
+		puts("QSPI_MODE\n");
+		break;
+	case EMMC_MODE:
+		puts("EMMC_MODE\n");
+		mode = "mmc0";
+		break;
+	case SD_MODE:
+		puts("SD_MODE\n");
+		mode = "mmc0";
+		break;
+	case SD_MODE1:
+		puts("SD_MODE1\n");
+#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
+		mode = "mmc1";
+#else
+		mode = "mmc0";
+#endif
+		break;
+	case NAND_MODE:
+		puts("NAND_MODE\n");
+		mode = "nand0";
+		break;
+	default:
+		mode = "";
+		printf("Invalid Boot Mode:0x%x\n", bootmode);
+		break;
+	}
+
+	/*
+	 * One terminating char + one byte for space between mode
+	 * and default boot_targets
+	 */
+	new_targets = calloc(1, strlen(mode) +
+				strlen(getenv("boot_targets")) + 2);
+
+	sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
+	setenv("boot_targets", new_targets);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Xilinx ZynqMP\n");
+	return 0;
+}
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = ZYNQMP_USB0_XHCI_BASEADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+	dwc3_uboot_handle_interrupt(0);
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	return dwc3_uboot_init(&dwc3_device_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	dwc3_uboot_exit(index);
+	return 0;
+}
+#endif