avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/board/xes/common/Makefile

@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_FSL_PCI_INIT)	+= fsl_8xxx_pci.o
+obj-$(CONFIG_MPC8572)		+= fsl_8xxx_clk.o
+obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
+obj-$(CONFIG_P2020)		+= fsl_8xxx_clk.o
+obj-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
+obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_misc.o board.o
+obj-$(CONFIG_NAND_ACTL)	+= actl_nand.o

u-boot/board/xes/common/actl_nand.c

@@ -0,0 +1,49 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This driver support NAND devices which have address lines
+ * connected as ALE and CLE inputs.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
+{
+	struct nand_chip *this = mtd_to_nand(mtd);
+	ulong IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		IO_ADDR_W = (ulong)this->IO_ADDR_W;
+
+		IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
+				CONFIG_SYS_NAND_ACTL_ALE |
+				CONFIG_SYS_NAND_ACTL_NCE);
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
+		if (ctrl & NAND_NCE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
+
+		this->IO_ADDR_W = (void *)IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nand_addr_hwcontrol;
+	nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
+
+	return 0;
+}

u-boot/board/xes/common/board.c

@@ -0,0 +1,66 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include "fsl_8xxx_misc.h"
+
+int checkboard(void)
+{
+	char name[] = CONFIG_SYS_BOARD_NAME;
+	char buf[64];
+	char *s;
+	int i;
+
+#ifdef CONFIG_SYS_FORM_CUSTOM
+	s = "Custom";
+#elif CONFIG_SYS_FORM_6U_CPCI
+	s = "6U CompactPCI";
+#elif CONFIG_SYS_FORM_ATCA_PMC
+	s = "ATCA w/PMC";
+#elif CONFIG_SYS_FORM_ATCA_AMC
+	s = "ATCA w/AMC";
+#elif CONFIG_SYS_FORM_VME
+	s = "VME";
+#elif CONFIG_SYS_FORM_6U_VPX
+	s = "6U VPX";
+#elif CONFIG_SYS_FORM_PMC
+	s = "PMC";
+#elif CONFIG_SYS_FORM_PCI
+	s = "PCI";
+#elif CONFIG_SYS_FORM_3U_CPCI
+	s = "3U CompactPCI";
+#elif CONFIG_SYS_FORM_AMC
+	s = "AdvancedMC";
+#elif CONFIG_SYS_FORM_XMC
+	s = "XMC";
+#elif CONFIG_SYS_FORM_PMC_XMC
+	s = "PMC/XMC";
+#elif CONFIG_SYS_FORM_PCI_EXPRESS
+	s = "PCI Express";
+#elif CONFIG_SYS_FORM_3U_VPX
+	s = "3U VPX";
+#else
+#error "Form factor not defined"
+#endif
+
+	name[strlen(name) - 1] += get_board_derivative();
+	printf("Board: X-ES %s %s SBC\n", name, s);
+
+	/* Display board specific information */
+	puts("       ");
+	i = getenv_f("board_rev", buf, sizeof(buf));
+	if (i > 0)
+		printf("Rev %s, ", buf);
+	i = getenv_f("serial#", buf, sizeof(buf));
+	if (i > 0)
+		printf("Serial# %s, ", buf);
+	i = getenv_f("board_cfg", buf, sizeof(buf));
+	if (i > 0)
+		printf("Cfg %s", buf);
+	puts("\n");
+
+	return 0;
+}

u-boot/board/xes/common/fsl_8xxx_clk.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+/*
+ * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
+ */
+unsigned long get_board_sys_clk(ulong dummy)
+{
+#if defined(CONFIG_MPC85xx)
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#elif defined(CONFIG_MPC86xx)
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+	if (in_be32(&gur->gpporcr) & 0x10000)
+		return 66666666;
+	else
+#ifdef CONFIG_P2020
+		return 100000000;
+#else
+		return 50000000;
+#endif
+}
+
+#ifdef CONFIG_MPC85xx
+/*
+ * Return DDR input clock - synchronous with SYSCLK or 66 MHz
+ * Note: 86xx doesn't support asynchronous DDR clk
+ */
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
+
+	if (ddr_ratio == 0x7)
+		return get_board_sys_clk(dummy);
+
+#ifdef CONFIG_P2020
+	if (in_be32(&gur->gpporcr) & 0x20000)
+		return 66666666;
+	else
+		return 100000000;
+#else
+	return 66666666;
+#endif
+}
+#endif

u-boot/board/xes/common/fsl_8xxx_misc.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#ifdef CONFIG_PCA953X
+#include <pca953x.h>
+
+/*
+ * Determine if a board's flashes are write protected
+ */
+int board_flash_wp_on(void)
+{
+	if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_NVM_WP)
+		return 1;
+
+	return 0;
+}
+#endif
+
+/*
+ * Return a board's derivative model number.  For example:
+ * return 2 for the XPedite5372 and return 1 for the XPedite5201.
+ */
+uint get_board_derivative(void)
+{
+#if defined(CONFIG_MPC85xx)
+       volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#elif defined(CONFIG_MPC86xx)
+       volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
+       volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+       /*
+	* The top 4 lines of the local bus address are pulled low/high and
+	* can be read to determine the least significant digit of a board's
+	* model number.
+	*/
+       return gur->gpporcr >> 28;
+}

u-boot/board/xes/common/fsl_8xxx_misc.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_8XXX_MISC_H___
+#define __FSL_8XXX_MISC_H___
+
+uint get_board_derivative(void);
+
+#endif /* __FSL_8XXX_MISC_H__ */

u-boot/board/xes/common/fsl_8xxx_pci.c

@@ -0,0 +1,72 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+
+void pci_init_board(void)
+{
+	int first_free_busno = 0;
+
+#ifdef CONFIG_PCI1
+	int pcie_ep;
+	struct fsl_pci_info pci_info;
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 devdisr = in_be32(&gur->devdisr);
+	uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
+	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
+	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
+	uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
+	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
+		printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
+			pci_32 ? 32 : 64,
+			pcix ? "PCIX" : "PCI",
+			pci_spd_norm ? ">=" : "<=",
+			pcix ? freq * 2 : freq,
+			pcie_ep ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter");
+
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+	} else {
+		printf("PCI1: disabled\n");
+	}
+#elif defined CONFIG_MPC8548
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	/* PCI1 not present on MPC8572 */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
+#endif
+
+	fsl_pcie_init_board(first_free_busno);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_pci_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */

u-boot/board/xes/xpedite1000/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_XPEDITE1000
+
+config SYS_BOARD
+	default "xpedite1000"
+
+config SYS_VENDOR
+	default "xes"
+
+config SYS_CONFIG_NAME
+	default "xpedite1000"
+
+endif

u-boot/board/xes/xpedite1000/MAINTAINERS

@@ -0,0 +1,6 @@
+XPEDITE1000 BOARD
+M:	Peter Tyser <ptyser@xes-inc.com>
+S:	Maintained
+F:	board/xes/xpedite1000/
+F:	include/configs/xpedite1000.h
+F:	configs/xpedite1000_defconfig

u-boot/board/xes/xpedite1000/Makefile

@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= xpedite1000.o
+extra-y	+= init.o

u-boot/board/xes/xpedite1000/README

@@ -0,0 +1,82 @@
+			   XES XPedite1000 Board
+
+		    Last Update: December 29, 2003
+=======================================================================
+
+This file contains some handy info regarding U-Boot and the XES
+XPedite1000 PPC440GX PrPMC board. See the README.ppc440 for additional
+information.
+
+
+SWITCH SETTINGS & JUMPERS
+==========================
+
+Jumpers selected for AMD29LV040B flash part as the boot flash.
+
+
+I2C Strap EEPROM & Environment Settings
+=======================================
+
+The XPedite1000 uses a single I2C eeprom for the 440 strappings and for
+the environment variables.  The first page (256 bytes) contains the
+strappings and the 2 EMAC HW Ethernet addresses.  Be careful not to
+change the 1st page of the EEPROM!  Unpopulated jumper J560 can get you
+out of trouble as it disables the strapping read from EEPROM.
+
+I2C probe
+=====================
+
+The i2c utilities work and have been tested on Rev B. of the 440GX. See
+README.ebony for more information about i2c probing with the 440.
+
+
+GETTING OUT OF I2C TROUBLE
+===========================
+
+(Direct quote from README.ebony)
+If you're like me ... you may have screwed up your bootstrap serial
+eeprom ... or worse, your SPD eeprom when experimenting with the
+i2c commands. If so, here are some ideas on how to get out of
+trouble:
+
+Serial bootstrap eeprom corruption:
+-----------------------------------
+Power down the board and set the following straps:
+
+J560 - closed
+
+This will select the default sys0 and sys1 settings (the serial
+eeproms are not used). Then power up the board and fix the serial
+eeprom using the 'i2c mm' command. Here are the values I currently
+use:
+
+=> i2c md 50 0 10
+
+0000: 85 7d 42 06 07 80 11 00 00 00 00 00 00 00 00 00    .}B.............
+
+Once you have the eeproms set correctly change the
+J560 straps as you desire.
+
+
+PPC440GX Ethernet EMACs
+=======================
+
+The XES XPedite1000 uses emac 2 & 3 and ignores emac 0 & 1.  PHYs are connected
+only to emac 2 & 3.  The HW Ethernet addresses are read from the i2c eeprom and
+placed in the bd info structure for enet2addr and enet3addr.  The ethernet driver
+senses that enetaddr and enet1addr are 0's and does not use them.
+
+As of this writing gigabit ethernet and the TCPIP acceleration hardware is not
+supported.
+
+
+Flash Support
+=============
+
+As of this writing, there is support for the 1/2mb boot flash only.  User flash
+is not yet supported.
+
+
+Regards,
+--Travis
+<travis.sawyer@sandburst.com>

u-boot/board/xes/xpedite1000/config.mk

@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2002-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+#
+# XES XPedite1000 PPC440GX
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif

u-boot/board/xes/xpedite1000/init.S

@@ -0,0 +1,33 @@
+/*
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ */
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
+	tlbtab_end

u-boot/board/xes/xpedite1000/u-boot.lds.debug

@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/ppc4xx/start.o	(.text)
+    board/xes/xpedite1000/init.o (.text)
+    arch/powerpc/cpu/ppc4xx/kgdb.o	(.text)
+    arch/powerpc/cpu/ppc4xx/traps.o	(.text)
+    arch/powerpc/cpu/ppc4xx/interrupts.o	(.text)
+    arch/powerpc/cpu/ppc4xx/4xx_uart.o	(.text)
+    arch/powerpc/cpu/ppc4xx/cpu_init.o	(.text)
+    arch/powerpc/cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib/crc32.o		(.text)
+    arch/powerpc/lib/extable.o	(.text)
+    lib/zlib.o		(.text)
+
+/*    common/env_embedded.o(.text) */
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	KEEP(*(SORT(.u_boot_list*)));
+  }
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  __bss_end = . ;
+  PROVIDE (end = .);
+}

u-boot/board/xes/xpedite1000/xpedite1000.c

@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <console.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	unsigned long sdrreg;
+
+	/*
+	 * Enable GPIO for pins 18 - 24
+	 * 18 = SEEPROM_WP
+	 * 19 = #M_RST
+	 * 20 = #MONARCH
+	 * 21 = #LED_ALARM
+	 * 22 = #LED_ACT
+	 * 23 = #LED_STATUS1
+	 * 24 = #LED_STATUS2
+	 */
+	mfsdr(SDR0_PFC0, sdrreg);
+	mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00);
+	out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
+	LED0_OFF();
+	LED1_OFF();
+	LED2_OFF();
+	LED3_OFF();
+
+	/* Setup the external bus controller/chip selects */
+	mtebc(PB0AP, 0x04055200);	/* 16MB Strata FLASH */
+	mtebc(PB0CR, 0xff098000);	/* BAS=0xff0 16MB R/W 8-bit */
+	mtebc(PB1AP, 0x04055200);	/* 512KB Socketed AMD FLASH */
+	mtebc(PB1CR, 0xfe018000);	/* BAS=0xfe0 1MB R/W 8-bit */
+	mtebc(PB6AP, 0x05006400);	/* 32-64MB AMD MirrorBit FLASH */
+	mtebc(PB6CR, 0xf00da000);	/* BAS=0xf00 64MB R/W i6-bit */
+	mtebc(PB7AP, 0x05006400);	/* 32-64MB AMD MirrorBit FLASH */
+	mtebc(PB7CR, 0xf40da000);	/* BAS=0xf40 64MB R/W 16-bit */
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000003);	/* SMI & UIC1 crit are critical */
+	mtdcr(UIC1PR, 0xfffffe00);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x01c00000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffc0ff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00ff8000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all */
+	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr(UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC0SR, 0xfc000000);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC0PR, 0xfc000000);	/* */
+	mtdcr(UIC0TR, 0x00000000);	/* */
+	mtdcr(UIC0VR, 0x00000001);	/* */
+
+	LED0_ON();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char buf[64];
+	int i;
+
+	printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME);
+	printf("       ");
+	i = getenv_f("board_rev", buf, sizeof(buf));
+	if (i > 0)
+		printf("Rev %s, ", buf);
+	i = getenv_f("serial#", buf, sizeof(buf));
+	if (i > 0)
+		printf("Serial# %s, ", buf);
+	i = getenv_f("board_cfg", buf, sizeof(buf));
+	if (i > 0)
+		printf("Cfg %s", buf);
+	printf("\n");
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return spd_sdram();
+}
+
+/*
+ * Override weak pci_pre_init()
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller * hose)
+{
+	unsigned long strap;
+
+	/* See if we're supposed to setup the pci */
+	mfsdr(SDR0_SDSTP1, strap);
+	if ((strap & 0x00010000) == 0)
+		return 0;
+
+#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
+	/* Setup System Device Register PCIL0_XCR */
+	mfsdr(SDR0_XCR, strap);
+	strap &= 0x0f000000;
+	mtsdr(SDR0_XCR, strap);
+#endif
+
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#if defined(CONFIG_PCI)
+/*
+ * Override weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+	return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return ctrlc();
+}
+#endif

u-boot/board/xes/xpedite517x/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_XPEDITE517X
+
+config SYS_BOARD
+	default "xpedite517x"
+
+config SYS_VENDOR
+	default "xes"
+
+config SYS_CONFIG_NAME
+	default "xpedite517x"
+
+endif

u-boot/board/xes/xpedite517x/MAINTAINERS

@@ -0,0 +1,6 @@
+XPEDITE517X BOARD
+M:	Peter Tyser <ptyser@xes-inc.com>
+S:	Maintained
+F:	board/xes/xpedite517x/
+F:	include/configs/xpedite517x.h
+F:	configs/xpedite517x_defconfig

u-boot/board/xes/xpedite517x/Makefile

@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= xpedite517x.o
+obj-y	+= ddr.o
+obj-y	+= law.o

u-boot/board/xes/xpedite517x/ddr.c

@@ -0,0 +1,124 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
+{
+	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+		sizeof(ddr2_spd_eeprom_t));
+}
+
+/*
+ * There are four board-specific SDRAM timing parameters which must be
+ * calculated based on the particular PCB artwork.  These are:
+ *   1.) CPO (Read Capture Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths and
+ *                   chip-specific internal delays.
+ *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths.
+ *                   Unless clock and DQ lanes are very different
+ *                   lengths (>2"), this should be set to the nominal value
+ *                   of 1/2 clock delay.
+ *   3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ *           - DDR_SDRAM_CLK_CNTL register
+ *           Source: Signal Integrity Simulations
+ *   4.) 2T Timing on Addr/Ctl
+ *           - TIMING_CFG_2 register
+ *           Source: Signal Integrity Simulations
+ *           Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ *     PCB routing on the XPedite5170 is nearly identical to the XPedite5370
+ *     so we use the XPedite5370 settings as a basis for the XPedite5170.
+ */
+
+typedef struct board_memctl_options {
+	uint16_t datarate_mhz_low;
+	uint16_t datarate_mhz_high;
+	uint8_t clk_adjust;
+	uint8_t cpo_override;
+	uint8_t write_data_delay;
+} board_memctl_options_t;
+
+static struct board_memctl_options bopts_ctrl[][2] = {
+	{
+		/* Controller 0 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 9,
+			.write_data_delay	= 2,
+		},
+	},
+	{
+		/* Controller 1 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 7,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			dimm_params_t *pdimm,
+			unsigned int ctrl_num)
+{
+	struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
+	sys_info_t sysinfo;
+	int i;
+	unsigned int datarate;
+
+	get_sys_info(&sysinfo);
+	datarate = get_ddr_freq(0) / 1000000;
+
+	for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
+		if ((bopts[i].datarate_mhz_low <= datarate) &&
+		    (bopts[i].datarate_mhz_high >= datarate)) {
+			debug("controller %d:\n", ctrl_num);
+			debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
+			debug(" cpo = %d\n", bopts[i].cpo_override);
+			debug(" write_data_delay = %d\n",
+				bopts[i].write_data_delay);
+			popts->clk_adjust = bopts[i].clk_adjust;
+			popts->cpo_override = bopts[i].cpo_override;
+			popts->write_data_delay = bopts[i].write_data_delay;
+		}
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}

u-boot/board/xes/xpedite517x/law.c

@@ -0,0 +1,28 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE
+	/* NAND LAW covers 2 NAND flashes */
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

u-boot/board/xes/xpedite517x/xpedite517x.c

@@ -0,0 +1,81 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+#include "../common/fsl_8xxx_misc.h"
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+#endif
+
+/*
+ * Print out which flash was booted from and if booting from the 2nd flash,
+ * swap flash chip selects to maintain consistent flash numbering/addresses.
+ */
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size = fsl_ddr_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/* Initialize and enable DDR ECC */
+	ddr_enable_ecc(dram_size);
+#endif
+
+	return dram_size;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif

u-boot/board/xes/xpedite520x/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_XPEDITE520X
+
+config SYS_BOARD
+	default "xpedite520x"
+
+config SYS_VENDOR
+	default "xes"
+
+config SYS_CONFIG_NAME
+	default "xpedite520x"
+
+endif

u-boot/board/xes/xpedite520x/MAINTAINERS

@@ -0,0 +1,6 @@
+XPEDITE520X BOARD
+M:	Peter Tyser <ptyser@xes-inc.com>
+S:	Maintained
+F:	board/xes/xpedite520x/
+F:	include/configs/xpedite520x.h
+F:	configs/xpedite520x_defconfig

u-boot/board/xes/xpedite520x/Makefile

@@ -0,0 +1,13 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= xpedite520x.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o

u-boot/board/xes/xpedite520x/ddr.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+
+	/* We use soldered memory, but use an SPD EEPROM to describe it.
+	 * The SPD has an unspecified dimm type, but the DDR2 initialization
+	 * code requires a specific type to be specified. This sets the type
+	 * as a standard unregistered SO-DIMM. */
+	if (spd->dimm_type == 0) {
+		spd->dimm_type = 0x4;
+		((uchar *)spd)[63] += 0x4;
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 9;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}

u-boot/board/xes/xpedite520x/law.c

@@ -0,0 +1,27 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

u-boot/board/xes/xpedite520x/tlb.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if CONFIG_PCI1
+	/* *I*G* - PCI MEM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#if CONFIG_PCI2
+	/* *I*G* - PCI MEM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+	/* *I*G* - PCI IO */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_16M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);

u-boot/board/xes/xpedite520x/xpedite520x.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif

u-boot/board/xes/xpedite537x/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_XPEDITE537X
+
+config SYS_BOARD
+	default "xpedite537x"
+
+config SYS_VENDOR
+	default "xes"
+
+config SYS_CONFIG_NAME
+	default "xpedite537x"
+
+endif

u-boot/board/xes/xpedite537x/MAINTAINERS

@@ -0,0 +1,6 @@
+XPEDITE537X BOARD
+M:	Peter Tyser <ptyser@xes-inc.com>
+S:	Maintained
+F:	board/xes/xpedite537x/
+F:	include/configs/xpedite537x.h
+F:	configs/xpedite537x_defconfig

u-boot/board/xes/xpedite537x/Makefile

@@ -0,0 +1,13 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= xpedite537x.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o

u-boot/board/xes/xpedite537x/ddr.c

@@ -0,0 +1,234 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
+{
+	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+		 sizeof(ddr2_spd_eeprom_t));
+}
+
+/*
+ * There are four board-specific SDRAM timing parameters which must be
+ * calculated based on the particular PCB artwork.  These are:
+ *   1.) CPO (Read Capture Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths and
+ *                   chip-specific internal delays.
+ *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths.
+ *                   Unless clock and DQ lanes are very different
+ *                   lengths (>2"), this should be set to the nominal value
+ *                   of 1/2 clock delay.
+ *   3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ *           - DDR_SDRAM_CLK_CNTL register
+ *           Source: Signal Integrity Simulations
+ *   4.) 2T Timing on Addr/Ctl
+ *           - TIMING_CFG_2 register
+ *           Source: Signal Integrity Simulations
+ *           Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ *     ====== XPedite5370 DDR2-600 read delay calculations ======
+ *
+ *     See Freescale's App Note AN2583 as refrence.  This document also
+ *     contains the chip-specific delays for 8548E, 8572, etc.
+ *
+ *     For MPC8572E
+ *     Minimum chip delay (Ch 0): 1.372ns
+ *     Maximum chip delay (Ch 0): 2.914ns
+ *     Minimum chip delay (Ch 1): 1.220ns
+ *     Maximum chip delay (Ch 1): 2.595ns
+ *
+ *     CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
+ *
+ *     Minimum delay calc (Ch 0):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     2.3" * 180 - 400ps     + 1.9" * 180         + 2080ps     + 1372ps
+ *                                                 = 3808ps
+ *                                                 = 3.808ns
+ *
+ *     Maximum delay calc (Ch 0):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
+ *     2.3" * 180 + 400ps     + 2.4" * 180         + 2080ps     + 2914ps
+ *                                                 = 6240ps
+ *                                                 = 6.240ns
+ *
+ *     Minimum delay calc (Ch 1):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180- 400ps     + 0.7" * 180         + 2080ps     + 1220ps
+ *                                                 = 3288ps
+ *                                                 = 3.288ns
+ *
+ *     Maximum delay calc (Ch 1):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180+ 400ps     + 1.1" * 180         + 2080ps     + 2595ps
+ *                                                 = 5536ps
+ *                                                 = 5.536ns
+ *
+ *     Ch.0: 3.808ns to 6.240ns additional delay needed  (pick 5ns as target)
+ *              This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
+ *     Ch.1: 3.288ns to 5.536ns additional delay needed  (pick 4.4ns as target)
+ *              This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
+ *
+ *
+ *     ====== XPedite5370 DDR2-800 read delay calculations ======
+ *
+ *     See Freescale's App Note AN2583 as refrence.  This document also
+ *     contains the chip-specific delays for 8548E, 8572, etc.
+ *
+ *     For MPC8572E
+ *     Minimum chip delay (Ch 0): 1.372ns
+ *     Maximum chip delay (Ch 0): 2.914ns
+ *     Minimum chip delay (Ch 1): 1.220ns
+ *     Maximum chip delay (Ch 1): 2.595ns
+ *
+ *     CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
+ *
+ *     Minimum delay calc (Ch 0):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     2.3" * 180 - 350ps     + 1.9" * 180         + 1563ps     + 1372ps
+ *                                                 = 3341ps
+ *                                                 = 3.341ns
+ *
+ *     Maximum delay calc (Ch 0):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
+ *     2.3" * 180 + 350ps     + 2.4" * 180         + 1563ps     + 2914ps
+ *                                                 = 5673ps
+ *                                                 = 5.673ns
+ *
+ *     Minimum delay calc (Ch 1):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180- 350ps     + 0.7" * 180         + 1563ps     + 1220ps
+ *                                                 = 2822ps
+ *                                                 = 2.822ns
+ *
+ *     Maximum delay calc (Ch 1):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180+ 350ps     + 1.1" * 180         + 1563ps     + 2595ps
+ *                                                 = 4968ps
+ *                                                 = 4.968ns
+ *
+ *     Ch.0: 3.341ns to 5.673ns additional delay needed  (pick 4.5ns as target)
+ *              This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
+ *     Ch.1: 2.822ns to 4.968ns additional delay needed  (pick 3.9ns as target)
+ *              This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
+ *
+ * Write latency (WR_DATA_DELAY) is calculated by doing the following:
+ *
+ *      The DDR SDRAM specification requires DQS be received no sooner than
+ *      75% of an SDRAM clock period—and no later than 125% of a clock
+ *      period—from the capturing clock edge of the command/address at the
+ *      SDRAM.
+ *
+ * Based on the above tracelengths, the following are calculated:
+ *      Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 =  0.342ns
+ *      Ch. 0 8572 to DRAM propagation (CLKs) :     2.3" * 180 =  0.414ns
+ *      Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 =  0.126ns
+ *      Ch. 1 8572 to DRAM propagation (CLKs   ) : 1.47" * 180 =  0.264ns
+ *
+ * Difference in arrival time CLK vs. DQS:
+ *      Ch. 0 0.072ns
+ *      Ch. 1 0.138ns
+ *
+ *      Both of these values are much less than 25% of the clock
+ *      period at DDR2-600 or DDR2-800, so no additional delay is needed over
+ *      the 1/2 cycle which normally aligns the first DQS transition
+ *      exactly WL (CAS latency minus one cycle) after the CAS strobe.
+ *      See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
+ *      terminology corresponds to exactly one clock period delay after
+ *      the CAS strobe. (due to the fact that the "delay" is referenced
+ *      from the *falling* edge of the CLK, just after the rising edge
+ *      which the CAS strobe is latched on.
+ */
+
+typedef struct board_memctl_options {
+	uint16_t datarate_mhz_low;
+	uint16_t datarate_mhz_high;
+	uint8_t clk_adjust;
+	uint8_t cpo_override;
+	uint8_t write_data_delay;
+} board_memctl_options_t;
+
+static struct board_memctl_options bopts_ctrl[][2] = {
+	{
+		/* Controller 0 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 9,
+			.write_data_delay	= 2,
+		},
+	},
+	{
+		/* Controller 1 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 7,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
+	sys_info_t sysinfo;
+	int i;
+	unsigned int datarate;
+
+	get_sys_info(&sysinfo);
+	datarate = sysinfo.freq_ddrbus / 1000 / 1000;
+
+	for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
+		if ((bopts[i].datarate_mhz_low <= datarate) &&
+		    (bopts[i].datarate_mhz_high >= datarate)) {
+			debug("controller %d:\n", ctrl_num);
+			debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
+			debug(" cpo = %d\n", bopts[i].cpo_override);
+			debug(" write_data_delay = %d\n",
+			      bopts[i].write_data_delay);
+			popts->clk_adjust = bopts[i].clk_adjust;
+			popts->cpo_override = bopts[i].cpo_override;
+			popts->write_data_delay = bopts[i].write_data_delay;
+		}
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}

u-boot/board/xes/xpedite537x/law.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

u-boot/board/xes/xpedite537x/tlb.c

@@ -0,0 +1,83 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+	/* **M** - Boot page for secondary processors */
+	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);

u-boot/board/xes/xpedite537x/xpedite537x.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif

u-boot/board/xes/xpedite550x/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_XPEDITE550X
+
+config SYS_BOARD
+	default "xpedite550x"
+
+config SYS_VENDOR
+	default "xes"
+
+config SYS_CONFIG_NAME
+	default "xpedite550x"
+
+endif

u-boot/board/xes/xpedite550x/MAINTAINERS

@@ -0,0 +1,6 @@
+XPEDITE550X BOARD
+M:	Peter Tyser <ptyser@xes-inc.com>
+S:	Maintained
+F:	board/xes/xpedite550x/
+F:	include/configs/xpedite550x.h
+F:	configs/xpedite550x_defconfig

u-boot/board/xes/xpedite550x/Makefile

@@ -0,0 +1,10 @@
+#
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= xpedite550x.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o

u-boot/board/xes/xpedite550x/ddr.c

@@ -0,0 +1,136 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
+{
+	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+		 sizeof(ddr3_spd_eeprom_t));
+}
+
+/*
+ *     There are traditionally three board-specific SDRAM timing parameters
+ *     which must be calculated based on the particular PCB artwork.  These are:
+ *     1.) CPO (Read Capture Delay)
+ *	       - TIMING_CFG_2 register
+ *	       Source: Calculation based on board trace lengths and
+ *		       chip-specific internal delays.
+ *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ *	       - DDR_SDRAM_CLK_CNTL register
+ *	       Source: Signal Integrity Simulations
+ *     3.) 2T Timing on Addr/Ctl
+ *	       - TIMING_CFG_2 register
+ *	       Source: Signal Integrity Simulations
+ *	       Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ *     ====== XPedite550x DDR3-800 read delay calculations ======
+ *
+ *     The P2020 processor provides an autoleveling option. Setting CPO to
+ *     0x1f enables this auto configuration.
+ */
+
+typedef struct {
+	unsigned short datarate_mhz_low;
+	unsigned short datarate_mhz_high;
+	unsigned char clk_adjust;
+	unsigned char cpo;
+} board_specific_parameters_t;
+
+const board_specific_parameters_t board_specific_parameters[][20] = {
+	{
+		/* Controller 0 */
+		{
+			/* DDR3-600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo			= 31,
+		},
+		{
+			/* DDR3-800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo			= 31,
+		},
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const board_specific_parameters_t *pbsp =
+				&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+				sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	ulong ddr_freq;
+
+	/*
+	 * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+	 */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i&1) {	/* odd CS */
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 0;
+		} else {	/* even CS */
+			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+				popts->cs_local_opts[i].odt_rd_cfg = 0;
+				popts->cs_local_opts[i].odt_wr_cfg = 4;
+			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+				popts->cs_local_opts[i].odt_rd_cfg = 3;
+				popts->cs_local_opts[i].odt_wr_cfg = 3;
+			}
+		}
+	}
+
+	/*
+	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+
+	for (i = 0; i < num_params; i++) {
+		if (ddr_freq >= pbsp->datarate_mhz_low &&
+		    ddr_freq <= pbsp->datarate_mhz_high) {
+			popts->clk_adjust = pbsp->clk_adjust;
+			popts->cpo_override = pbsp->cpo;
+			popts->twot_en = 0;
+			break;
+		}
+		pbsp++;
+	}
+
+	if (i == num_params) {
+		printf("Warning: board specific timing not found "
+		"for data rate %lu MT/s!\n", ddr_freq);
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+
+	/*
+	 * Enable on-die termination.
+	 * From the Micron Technical Node TN-41-04, RTT_Nom should typically
+	 * be 30 to 40 ohms, while RTT_WR should be 120 ohms.  Setting RTT_WR
+	 * is handled in the Freescale DDR3 driver.  Set RTT_Nom here.
+	 */
+	popts->rtt_override = 1;
+	popts->rtt_override_value = 3;
+}

u-boot/board/xes/xpedite550x/law.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

u-boot/board/xes/xpedite550x/tlb.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+	/* **M** - Boot page for secondary processors */
+	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);

u-boot/board/xes/xpedite550x/xpedite550x.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif