avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
24
u-boot/board/vscom/baltos/Kconfig
Normal file
24
u-boot/board/vscom/baltos/Kconfig
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@@ -0,0 +1,24 @@
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if TARGET_AM335X_BALTOS
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config SYS_BOARD
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default "baltos"
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config SYS_VENDOR
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default "vscom"
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config SYS_SOC
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default "am33xx"
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config SYS_CONFIG_NAME
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default "baltos"
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config CONS_INDEX
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int "UART used for console"
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range 1 6
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default 1
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help
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The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
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in documentation, etc) available to it. Depending on your specific
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board you may want something other than UART0.
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endif
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6
u-boot/board/vscom/baltos/MAINTAINERS
Normal file
6
u-boot/board/vscom/baltos/MAINTAINERS
Normal file
@@ -0,0 +1,6 @@
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BALTOS BOARD
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M: Yegor Yefremov <yegorslists@googlemail.com>
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S: Maintained
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F: board/vscom/baltos/
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F: include/configs/baltos.h
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F: configs/am335x_baltos_defconfig
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13
u-boot/board/vscom/baltos/Makefile
Normal file
13
u-boot/board/vscom/baltos/Makefile
Normal file
@@ -0,0 +1,13 @@
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#
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# Makefile
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#
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# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
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obj-y := mux.o
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endif
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obj-y += board.o
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1
u-boot/board/vscom/baltos/README
Normal file
1
u-boot/board/vscom/baltos/README
Normal file
@@ -0,0 +1 @@
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BSP for VScom OnRISC Balios family devices, like Balios iR 5221.
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477
u-boot/board/vscom/baltos/board.c
Normal file
477
u-boot/board/vscom/baltos/board.c
Normal file
@@ -0,0 +1,477 @@
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/*
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* board.c
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*
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* Board functions for TI AM335X based boards
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <libfdt.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <power/tps65217.h>
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#include <power/tps65910.h>
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#include <environment.h>
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#include <watchdog.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* GPIO that controls power to DDR on EVM-SK */
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#define GPIO_DDR_VTT_EN 7
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#define DIP_S1 44
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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static int baltos_set_console(void)
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{
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int val, i, dips = 0;
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char buf[7];
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for (i = 0; i < 4; i++) {
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sprintf(buf, "dip_s%d", i + 1);
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if (gpio_request(DIP_S1 + i, buf)) {
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printf("failed to export GPIO %d\n", DIP_S1 + i);
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return 0;
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}
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if (gpio_direction_input(DIP_S1 + i)) {
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printf("failed to set GPIO %d direction\n", DIP_S1 + i);
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return 0;
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}
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val = gpio_get_value(DIP_S1 + i);
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dips |= val << i;
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}
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printf("DIPs: 0x%1x\n", (~dips) & 0xf);
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if ((dips & 0xf) == 0xe)
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setenv("console", "ttyUSB0,115200n8");
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return 0;
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}
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static int read_eeprom(BSP_VS_HWPARAM *header)
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{
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i2c_set_bus_num(1);
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/* Check if baseboard eeprom is available */
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
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puts("Could not probe the EEPROM; something fundamentally "
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"wrong on the I2C bus.\n");
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return -ENODEV;
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}
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/* read the eeprom using i2c */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
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sizeof(BSP_VS_HWPARAM))) {
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puts("Could not read the EEPROM; something fundamentally"
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" wrong on the I2C bus.\n");
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return -EIO;
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}
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if (header->Magic != 0xDEADBEEF) {
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printf("Incorrect magic number (0x%x) in EEPROM\n",
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header->Magic);
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/* fill default values */
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header->SystemId = 211;
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header->MAC1[0] = 0x00;
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header->MAC1[1] = 0x00;
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header->MAC1[2] = 0x00;
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header->MAC1[3] = 0x00;
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header->MAC1[4] = 0x00;
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header->MAC1[5] = 0x01;
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header->MAC2[0] = 0x00;
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header->MAC2[1] = 0x00;
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header->MAC2[2] = 0x00;
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header->MAC2[3] = 0x00;
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header->MAC2[4] = 0x00;
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header->MAC2[5] = 0x02;
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header->MAC3[0] = 0x00;
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header->MAC3[1] = 0x00;
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header->MAC3[2] = 0x00;
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header->MAC3[3] = 0x00;
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header->MAC3[4] = 0x00;
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header->MAC3[5] = 0x03;
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}
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return 0;
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}
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#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
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static const struct ddr_data ddr3_baltos_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_baltos_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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return (serial_tstc() && serial_getc() == 'c');
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}
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#endif
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#define OSC (V_OSCK/1000000)
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const struct dpll_params dpll_ddr = {
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266, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_ddr_evm_sk = {
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303, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_ddr_baltos = {
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400, OSC-1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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int mpu_vdd;
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int sil_rev;
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/* Get the frequency */
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dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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/*
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* The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
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* MPU frequencies we support we use a CORE voltage of
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* 1.1375V. For MPU voltage we need to switch based on
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* the frequency we are running at.
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*/
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i2c_set_bus_num(1);
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printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
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if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
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puts("i2c: cannot access TPS65910\n");
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return;
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}
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/*
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* Depending on MPU clock and PG we will need a different
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* VDD to drive at that speed.
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*/
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sil_rev = readl(&cdev->deviceid) >> 28;
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mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
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dpll_mpu_opp100.m);
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/* Tell the TPS65910 to use i2c */
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tps65910_set_i2c_control();
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/* First update MPU voltage. */
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if (tps65910_voltage_update(MPU, mpu_vdd))
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return;
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/* Second, update the CORE voltage. */
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if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
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return;
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/* Set CORE Frequencies to OPP100 */
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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/* Set MPU Frequency to what we detected now that voltages are set */
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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writel(0x000010ff, PRM_DEVICE_INST + 4);
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}
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||||
|
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const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
enable_i2c1_pin_mux();
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||||
i2c_set_bus_num(1);
|
||||
|
||||
return &dpll_ddr_baltos;
|
||||
}
|
||||
|
||||
void set_uart_mux_conf(void)
|
||||
{
|
||||
enable_uart0_pin_mux();
|
||||
}
|
||||
|
||||
void set_mux_conf_regs(void)
|
||||
{
|
||||
enable_board_pin_mux();
|
||||
}
|
||||
|
||||
const struct ctrl_ioregs ioregs_baltos = {
|
||||
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
|
||||
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
|
||||
|
||||
config_ddr(400, &ioregs_baltos,
|
||||
&ddr3_baltos_data,
|
||||
&ddr3_baltos_cmd_ctrl_data,
|
||||
&ddr3_baltos_emif_reg_data, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Basic board specific setup. Pinmux has been handled already.
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
hw_watchdog_init();
|
||||
#endif
|
||||
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
|
||||
gpmc_init();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int node, ret;
|
||||
unsigned char mac_addr[6];
|
||||
BSP_VS_HWPARAM header;
|
||||
|
||||
/* get production data */
|
||||
if (read_eeprom(&header))
|
||||
return 0;
|
||||
|
||||
/* setup MAC1 */
|
||||
mac_addr[0] = header.MAC1[0];
|
||||
mac_addr[1] = header.MAC1[1];
|
||||
mac_addr[2] = header.MAC1[2];
|
||||
mac_addr[3] = header.MAC1[3];
|
||||
mac_addr[4] = header.MAC1[4];
|
||||
mac_addr[5] = header.MAC1[5];
|
||||
|
||||
|
||||
node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
|
||||
if (node < 0) {
|
||||
printf("no /soc/fman/ethernet path offset\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
|
||||
if (ret) {
|
||||
printf("error setting local-mac-address property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* setup MAC2 */
|
||||
mac_addr[0] = header.MAC2[0];
|
||||
mac_addr[1] = header.MAC2[1];
|
||||
mac_addr[2] = header.MAC2[2];
|
||||
mac_addr[3] = header.MAC2[3];
|
||||
mac_addr[4] = header.MAC2[4];
|
||||
mac_addr[5] = header.MAC2[5];
|
||||
|
||||
node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
|
||||
if (node < 0) {
|
||||
printf("no /soc/fman/ethernet path offset\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
|
||||
if (ret) {
|
||||
printf("error setting local-mac-address property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
printf("\nFDT was successfully setup\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct module_pin_mux dip_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
|
||||
{OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
|
||||
{OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
|
||||
{OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INIT
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
BSP_VS_HWPARAM header;
|
||||
char model[4];
|
||||
|
||||
/* get production data */
|
||||
if (read_eeprom(&header)) {
|
||||
strcpy(model, "211");
|
||||
} else {
|
||||
sprintf(model, "%d", header.SystemId);
|
||||
if (header.SystemId == 215) {
|
||||
configure_module_pin_mux(dip_pin_mux);
|
||||
baltos_set_console();
|
||||
}
|
||||
}
|
||||
setenv("board_name", model);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
||||
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
||||
static void cpsw_control(int enabled)
|
||||
{
|
||||
/* VTP can be added here */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static struct cpsw_slave_data cpsw_slaves[] = {
|
||||
{
|
||||
.slave_reg_ofs = 0x208,
|
||||
.sliver_reg_ofs = 0xd80,
|
||||
.phy_addr = 0,
|
||||
},
|
||||
{
|
||||
.slave_reg_ofs = 0x308,
|
||||
.sliver_reg_ofs = 0xdc0,
|
||||
.phy_addr = 7,
|
||||
},
|
||||
};
|
||||
|
||||
static struct cpsw_platform_data cpsw_data = {
|
||||
.mdio_base = CPSW_MDIO_BASE,
|
||||
.cpsw_base = CPSW_BASE,
|
||||
.mdio_div = 0xff,
|
||||
.channels = 8,
|
||||
.cpdma_reg_ofs = 0x800,
|
||||
.slaves = 2,
|
||||
.slave_data = cpsw_slaves,
|
||||
.active_slave = 1,
|
||||
.ale_reg_ofs = 0xd00,
|
||||
.ale_entries = 1024,
|
||||
.host_port_reg_ofs = 0x108,
|
||||
.hw_stats_reg_ofs = 0x900,
|
||||
.bd_ram_ofs = 0x2000,
|
||||
.mac_control = (1 << 5),
|
||||
.control = cpsw_control,
|
||||
.host_port_num = 0,
|
||||
.version = CPSW_CTRL_VERSION_2,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
|
||||
&& defined(CONFIG_SPL_BUILD)) || \
|
||||
((defined(CONFIG_DRIVER_TI_CPSW) || \
|
||||
defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
|
||||
!defined(CONFIG_SPL_BUILD))
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rv, n = 0;
|
||||
uint8_t mac_addr[6];
|
||||
uint32_t mac_hi, mac_lo;
|
||||
__maybe_unused struct am335x_baseboard_id header;
|
||||
|
||||
/*
|
||||
* Note here that we're using CPSW1 since that has a 1Gbit PHY while
|
||||
* CSPW0 has a 100Mbit PHY.
|
||||
*
|
||||
* On product, CPSW1 maps to port labeled WAN.
|
||||
*/
|
||||
|
||||
/* try reading mac address from efuse */
|
||||
mac_lo = readl(&cdev->macid1l);
|
||||
mac_hi = readl(&cdev->macid1h);
|
||||
mac_addr[0] = mac_hi & 0xFF;
|
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||
mac_addr[4] = mac_lo & 0xFF;
|
||||
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||
|
||||
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
||||
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
||||
if (!getenv("ethaddr")) {
|
||||
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
|
||||
|
||||
if (is_valid_ethaddr(mac_addr))
|
||||
eth_setenv_enetaddr("ethaddr", mac_addr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRIVER_TI_CPSW
|
||||
writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
|
||||
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
|
||||
rv = cpsw_register(&cpsw_data);
|
||||
if (rv < 0)
|
||||
printf("Error %d registering CPSW switch\n", rv);
|
||||
else
|
||||
n += rv;
|
||||
#endif
|
||||
|
||||
/*
|
||||
*
|
||||
* CPSW RGMII Internal Delay Mode is not supported in all PVT
|
||||
* operating points. So we must set the TX clock delay feature
|
||||
* in the AR8051 PHY. Since we only support a single ethernet
|
||||
* device in U-Boot, we only do this for the first instance.
|
||||
*/
|
||||
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
|
||||
#define AR8051_PHY_DEBUG_DATA_REG 0x1e
|
||||
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
|
||||
#define AR8051_RGMII_TX_CLK_DLY 0x100
|
||||
const char *devname;
|
||||
devname = miiphy_get_current_dev();
|
||||
|
||||
miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
|
||||
AR8051_DEBUG_RGMII_CLK_DLY_REG);
|
||||
miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
|
||||
AR8051_RGMII_TX_CLK_DLY);
|
||||
#endif
|
||||
return n;
|
||||
}
|
||||
#endif
|
||||
90
u-boot/board/vscom/baltos/board.h
Normal file
90
u-boot/board/vscom/baltos/board.h
Normal file
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* board.h
|
||||
*
|
||||
* TI AM335x boards information header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
/*
|
||||
* TI AM335x parts define a system EEPROM that defines certain sub-fields.
|
||||
* We use these fields to in turn see what board we are on, and what
|
||||
* that might require us to set or not set.
|
||||
*/
|
||||
#define HDR_NO_OF_MAC_ADDR 3
|
||||
#define HDR_ETH_ALEN 6
|
||||
#define HDR_NAME_LEN 8
|
||||
|
||||
struct am335x_baseboard_id {
|
||||
unsigned int magic;
|
||||
char name[HDR_NAME_LEN];
|
||||
char version[4];
|
||||
char serial[12];
|
||||
char config[32];
|
||||
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
|
||||
};
|
||||
|
||||
typedef struct _BSP_VS_HWPARAM // v1.0
|
||||
{
|
||||
uint32_t Magic;
|
||||
uint32_t HwRev;
|
||||
uint32_t SerialNumber;
|
||||
char PrdDate[11]; // as a string ie. "01.01.2006"
|
||||
uint16_t SystemId;
|
||||
uint8_t MAC1[6]; // internal EMAC
|
||||
uint8_t MAC2[6]; // SMSC9514
|
||||
uint8_t MAC3[6]; // WL1271 WLAN
|
||||
} __attribute__ ((packed)) BSP_VS_HWPARAM;
|
||||
|
||||
static inline int board_is_bone(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_idk(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return !strncmp(header->config, "SKU#02", 6);
|
||||
}
|
||||
|
||||
static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return (board_is_gp_evm(header) &&
|
||||
strncmp("1.5", header->version, 3) <= 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* We have three pin mux functions that must exist. We must be able to enable
|
||||
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
|
||||
* main pinmux function that can be overridden to enable all other pinmux that
|
||||
* is required on the board.
|
||||
*/
|
||||
void enable_uart0_pin_mux(void);
|
||||
void enable_uart1_pin_mux(void);
|
||||
void enable_uart2_pin_mux(void);
|
||||
void enable_uart3_pin_mux(void);
|
||||
void enable_uart4_pin_mux(void);
|
||||
void enable_uart5_pin_mux(void);
|
||||
void enable_i2c0_pin_mux(void);
|
||||
void enable_i2c1_pin_mux(void);
|
||||
void enable_board_pin_mux(void);
|
||||
#endif
|
||||
194
u-boot/board/vscom/baltos/mux.c
Normal file
194
u-boot/board/vscom/baltos/mux.c
Normal file
@@ -0,0 +1,194 @@
|
||||
/*
|
||||
* mux.c
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/io.h>
|
||||
#include <i2c.h>
|
||||
#include "board.h"
|
||||
|
||||
static struct module_pin_mux uart0_pin_mux[] = {
|
||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart1_pin_mux[] = {
|
||||
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
|
||||
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart2_pin_mux[] = {
|
||||
{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
|
||||
{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart3_pin_mux[] = {
|
||||
{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart4_pin_mux[] = {
|
||||
{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
|
||||
{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart5_pin_mux[] = {
|
||||
{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
|
||||
{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc0_pin_mux[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||
//{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux i2c1_pin_mux[] = {
|
||||
{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
||||
{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux gpio0_7_pin_mux[] = {
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux rmii1_pin_mux[] = {
|
||||
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
|
||||
{OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */
|
||||
{OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */
|
||||
{OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */
|
||||
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
|
||||
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
|
||||
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux rgmii2_pin_mux[] = {
|
||||
{OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */
|
||||
{OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
|
||||
{OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */
|
||||
{OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */
|
||||
{OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */
|
||||
{OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */
|
||||
{OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */
|
||||
{OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
|
||||
{OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
|
||||
{OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
|
||||
{OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
|
||||
{OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux nand_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
|
||||
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
|
||||
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
|
||||
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
|
||||
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
|
||||
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
|
||||
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
|
||||
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
|
||||
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
|
||||
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
|
||||
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
|
||||
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
|
||||
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
|
||||
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
|
||||
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart1_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart1_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart2_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart2_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart3_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart3_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart4_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart4_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart5_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart5_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c1_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c1_pin_mux);
|
||||
}
|
||||
|
||||
void enable_board_pin_mux()
|
||||
{
|
||||
/* Baltos */
|
||||
configure_module_pin_mux(i2c1_pin_mux);
|
||||
configure_module_pin_mux(gpio0_7_pin_mux);
|
||||
configure_module_pin_mux(rgmii2_pin_mux);
|
||||
configure_module_pin_mux(rmii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
|
||||
#if defined(CONFIG_NAND)
|
||||
configure_module_pin_mux(nand_pin_mux);
|
||||
#endif
|
||||
}
|
||||
128
u-boot/board/vscom/baltos/u-boot.lds
Normal file
128
u-boot/board/vscom/baltos/u-boot.lds
Normal file
@@ -0,0 +1,128 @@
|
||||
/*
|
||||
* Copyright (c) 2004-2008 Texas Instruments
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.__image_copy_start)
|
||||
*(.vectors)
|
||||
CPUDIR/start.o (.text*)
|
||||
board/vscom/baltos/built-in.o (.text*)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : {
|
||||
*(.data*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
. = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.image_copy_end :
|
||||
{
|
||||
*(.__image_copy_end)
|
||||
}
|
||||
|
||||
.rel_dyn_start :
|
||||
{
|
||||
*(.__rel_dyn_start)
|
||||
}
|
||||
|
||||
.rel.dyn : {
|
||||
*(.rel*)
|
||||
}
|
||||
|
||||
.rel_dyn_end :
|
||||
{
|
||||
*(.__rel_dyn_end)
|
||||
}
|
||||
|
||||
.hash : { *(.hash*) }
|
||||
|
||||
.end :
|
||||
{
|
||||
*(.__end)
|
||||
}
|
||||
|
||||
_image_binary_end = .;
|
||||
|
||||
/*
|
||||
* Deprecated: this MMU section is used by pxa at present but
|
||||
* should not be used by new boards/CPUs.
|
||||
*/
|
||||
. = ALIGN(4096);
|
||||
.mmutable : {
|
||||
*(.mmutable)
|
||||
}
|
||||
|
||||
/*
|
||||
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
|
||||
* __bss_base and __bss_limit are for linker only (overlay ordering)
|
||||
*/
|
||||
|
||||
.bss_start __rel_dyn_start (OVERLAY) : {
|
||||
KEEP(*(.__bss_start));
|
||||
__bss_base = .;
|
||||
}
|
||||
|
||||
.bss __bss_base (OVERLAY) : {
|
||||
*(.bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_limit = .;
|
||||
}
|
||||
|
||||
.bss_end __bss_limit (OVERLAY) : {
|
||||
KEEP(*(.__bss_end));
|
||||
}
|
||||
|
||||
.dynsym _image_binary_end : { *(.dynsym) }
|
||||
.dynbss : { *(.dynbss) }
|
||||
.dynstr : { *(.dynstr*) }
|
||||
.dynamic : { *(.dynamic*) }
|
||||
.gnu.hash : { *(.gnu.hash) }
|
||||
.plt : { *(.plt*) }
|
||||
.interp : { *(.interp*) }
|
||||
.gnu : { *(.gnu*) }
|
||||
.ARM.exidx : { *(.ARM.exidx*) }
|
||||
}
|
||||
Reference in New Issue
Block a user