avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
75
u-boot/board/tqc/tqma6/Kconfig
Normal file
75
u-boot/board/tqc/tqma6/Kconfig
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@@ -0,0 +1,75 @@
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if TARGET_TQMA6
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config SYS_BOARD
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default "tqma6"
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config SYS_VENDOR
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default "tqc"
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config SYS_CONFIG_NAME
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default "tqma6"
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choice
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prompt "TQMa6 SoC variant"
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default TQMA6Q
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help
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select the TQMa6 module variant. The variants differing in the used
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i.MX6 CPU type and DRAM
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config TQMA6Q
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bool "TQMa6Q / TQMa6D"
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select MX6Q
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help
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select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM
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config TQMA6S
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bool "TQMa6S"
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select MX6S
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help
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select TQMa6S with i.MX6S and 512 MiB DRAM
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endchoice
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choice
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prompt "TQMa6 boot configuration"
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default TQMA6X_MMC_BOOT
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help
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Configure boot device. This is also used to implement environment
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location.
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config TQMA6X_MMC_BOOT
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bool "MMC / SD Boot"
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help
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Boot from eMMC / SD Card
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config TQMA6X_SPI_BOOT
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bool "SPI NOR Boot"
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help
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Boot from on board SPI NOR flash
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endchoice
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choice
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prompt "TQMa6 base board variant"
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default MBA6
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help
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Select base board for TQMa6
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config MBA6
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bool "TQMa6 on MBa6 Starterkit"
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help
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Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card
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etc.
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config WRU4
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bool "OHB WRU-IV"
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help
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Select the OHB Systems AG WRU-IV baseboard.
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endchoice
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config IMX_CONFIG
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default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q
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default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S
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endif
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6
u-boot/board/tqc/tqma6/MAINTAINERS
Normal file
6
u-boot/board/tqc/tqma6/MAINTAINERS
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@@ -0,0 +1,6 @@
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TQ SYSTEMS TQMA6 BOARD
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M: Markus Niebel <Markus.Niebel@tq-group.com>
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S: Maintained
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F: board/tqc/tqma6/
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F: include/configs/tqma6.h
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F: configs/tqma6*_defconfig
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10
u-boot/board/tqc/tqma6/Makefile
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10
u-boot/board/tqc/tqma6/Makefile
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@@ -0,0 +1,10 @@
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#
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# Copyright (C) 2014, Markus Niebel <Markus.Niebel@tq-group.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := tqma6.o
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obj-$(CONFIG_MBA6) += tqma6_mba6.o
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obj-$(CONFIG_WRU4) += tqma6_wru4.o
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35
u-boot/board/tqc/tqma6/README
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35
u-boot/board/tqc/tqma6/README
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@@ -0,0 +1,35 @@
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U-Boot for the TQ Systems TQMa6 modules
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This file contains information for the port of
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U-Boot to the TQ Systems TQMa6 modules.
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1. Boot source
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--------------
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The following boot source is supported:
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- SD/eMMC
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- SPI NOR
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2. Building
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------------
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To build U-Boot for the TQ Systems TQMa6 modules:
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make tqma6<x>_<baseboard>_<boot>_config
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make
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x is a placeholder for the CPU variant
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q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D)
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s - means i.MX6S: TQMa6S (i.MX6S)
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baseboard is a placeholder for the boot device
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mmc - means eMMC
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spi - mean SPI NOR
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This gives the following configurations:
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tqma6q_mba6_mmc_config
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tqma6q_mba6_spi_config
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tqma6s_mba6_mmc_config
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tqma6s_mba6_spi_config
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24
u-boot/board/tqc/tqma6/clocks.cfg
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24
u-boot/board/tqc/tqma6/clocks.cfg
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@@ -0,0 +1,24 @@
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/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*/
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/* set the default clock gate to save power */
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DATA 4, CCM_CCGR0, 0x00C03F3F
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DATA 4, CCM_CCGR1, 0x0030FC03
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DATA 4, CCM_CCGR2, 0x0FFFC000
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DATA 4, CCM_CCGR3, 0x3FF00000
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DATA 4, CCM_CCGR4, 0x00FFF300
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DATA 4, CCM_CCGR5, 0x0F0000C3
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DATA 4, CCM_CCGR6, 0x000003FF
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
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DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
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280
u-boot/board/tqc/tqma6/tqma6.c
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280
u-boot/board/tqc/tqma6/tqma6.c
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@@ -0,0 +1,280 @@
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/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
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* Author: Markus Niebel <markus.niebel@tq-group.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/spi.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <libfdt.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <power/pfuze100_pmic.h>
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#include <power/pmic.h>
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#include <spi_flash.h>
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#include "tqma6_bb.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static const uint16_t tqma6_emmc_dsr = 0x0100;
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/* eMMC on USDHCI3 always present */
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static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
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NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
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/* eMMC reset */
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NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
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};
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/*
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* According to board_mmc_init() the following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 eMMC (SD3) on TQMa6
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* mmc1 .. n optional slots used on baseboard
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*/
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struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
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.esdhc_base = USDHC3_BASE_ADDR,
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.max_bus_width = 8,
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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if (cfg->esdhc_base == USDHC3_BASE_ADDR)
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/* eMMC/uSDHC3 is always present */
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ret = 1;
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else
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ret = tqma6_bb_board_mmc_getcd(mmc);
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return ret;
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}
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int board_mmc_getwp(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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if (cfg->esdhc_base == USDHC3_BASE_ADDR)
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/* eMMC/uSDHC3 is always present */
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ret = 0;
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else
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ret = tqma6_bb_board_mmc_getwp(mmc);
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||||
|
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return ret;
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||||
}
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int board_mmc_init(bd_t *bis)
|
||||
{
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imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
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ARRAY_SIZE(tqma6_usdhc3_pads));
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tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
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puts("Warning: failed to initialize eMMC dev\n");
|
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} else {
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struct mmc *mmc = find_mmc_device(0);
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||||
if (mmc)
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||||
mmc_set_dsr(mmc, tqma6_emmc_dsr);
|
||||
}
|
||||
|
||||
tqma6_bb_board_mmc_init(bis);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
|
||||
/* SS1 */
|
||||
NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
|
||||
|
||||
static unsigned const tqma6_ecspi1_cs[] = {
|
||||
TQMA6_SF_CS_GPIO,
|
||||
};
|
||||
|
||||
__weak void tqma6_iomuxc_spi(void)
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
|
||||
gpio_direction_output(tqma6_ecspi1_cs[i], 1);
|
||||
imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
|
||||
ARRAY_SIZE(tqma6_ecspi1_pads));
|
||||
}
|
||||
|
||||
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
||||
{
|
||||
return ((bus == CONFIG_SF_DEFAULT_BUS) &&
|
||||
(cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
|
||||
}
|
||||
|
||||
static struct i2c_pads_info tqma6_i2c3_pads = {
|
||||
/* I2C3: on board LM75, M24C64, */
|
||||
.scl = {
|
||||
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
|
||||
I2C_PAD_CTRL),
|
||||
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
|
||||
I2C_PAD_CTRL),
|
||||
.gp = IMX_GPIO_NR(1, 5)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
|
||||
I2C_PAD_CTRL),
|
||||
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
|
||||
I2C_PAD_CTRL),
|
||||
.gp = IMX_GPIO_NR(1, 6)
|
||||
}
|
||||
};
|
||||
|
||||
static void tqma6_setup_i2c(void)
|
||||
{
|
||||
int ret;
|
||||
/*
|
||||
* use logical index for bus, e.g. I2C1 -> 0
|
||||
* warn on error
|
||||
*/
|
||||
ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
|
||||
if (ret)
|
||||
printf("setup I2C3 failed: %d\n", ret);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return tqma6_bb_board_early_init_f();
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
tqma6_iomuxc_spi();
|
||||
tqma6_setup_i2c();
|
||||
|
||||
tqma6_bb_board_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char *tqma6_get_boardname(void)
|
||||
{
|
||||
u32 cpurev = get_cpu_rev();
|
||||
|
||||
switch ((cpurev & 0xFF000) >> 12) {
|
||||
case MXC_CPU_MX6SOLO:
|
||||
return "TQMa6S";
|
||||
break;
|
||||
case MXC_CPU_MX6DL:
|
||||
return "TQMa6DL";
|
||||
break;
|
||||
case MXC_CPU_MX6D:
|
||||
return "TQMa6D";
|
||||
break;
|
||||
case MXC_CPU_MX6Q:
|
||||
return "TQMa6Q";
|
||||
break;
|
||||
default:
|
||||
return "??";
|
||||
};
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
struct pmic *p;
|
||||
u32 reg;
|
||||
|
||||
setenv("board_name", tqma6_get_boardname());
|
||||
|
||||
/*
|
||||
* configure PFUZE100 PMIC:
|
||||
* TODO: should go to power_init_board if bus switching is
|
||||
* fixed in generic power code
|
||||
*/
|
||||
power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
|
||||
p = pmic_get("PFUZE100");
|
||||
if (p && !pmic_probe(p)) {
|
||||
pmic_reg_read(p, PFUZE100_DEVICEID, ®);
|
||||
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
|
||||
}
|
||||
|
||||
tqma6_bb_board_late_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("Board: %s on a %s\n", tqma6_get_boardname(),
|
||||
tqma6_bb_get_boardname());
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Device Tree Support
|
||||
*/
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
/* bring in eMMC dsr settings */
|
||||
do_fixup_by_path_u32(blob,
|
||||
"/soc/aips-bus@02100000/usdhc@02198000",
|
||||
"dsr", tqma6_emmc_dsr, 2);
|
||||
tqma6_bb_ft_board_setup(blob, bd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
|
||||
30
u-boot/board/tqc/tqma6/tqma6_bb.h
Normal file
30
u-boot/board/tqc/tqma6/tqma6_bb.h
Normal file
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (C) 2013, 2014 TQ Systems
|
||||
* Author: Markus Niebel <markus.niebel@tq-group.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __TQMA6_BB__
|
||||
#define __TQMA6_BB__
|
||||
|
||||
#include <common.h>
|
||||
|
||||
int tqma6_bb_board_mmc_getwp(struct mmc *mmc);
|
||||
int tqma6_bb_board_mmc_getcd(struct mmc *mmc);
|
||||
int tqma6_bb_board_mmc_init(bd_t *bis);
|
||||
|
||||
int tqma6_bb_board_early_init_f(void);
|
||||
int tqma6_bb_board_init(void);
|
||||
int tqma6_bb_board_late_init(void);
|
||||
int tqma6_bb_checkboard(void);
|
||||
|
||||
const char *tqma6_bb_get_boardname(void);
|
||||
/*
|
||||
* Device Tree Support
|
||||
*/
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
|
||||
void tqma6_bb_ft_board_setup(void *blob, bd_t *bd);
|
||||
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
|
||||
|
||||
#endif
|
||||
369
u-boot/board/tqc/tqma6/tqma6_mba6.c
Normal file
369
u-boot/board/tqc/tqma6/tqma6_mba6.c
Normal file
@@ -0,0 +1,369 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Freescale Semiconductor, Inc.
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
|
||||
* Author: Markus Niebel <markus.niebel@tq-group.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/mxc_i2c.h>
|
||||
|
||||
#include <common.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <libfdt.h>
|
||||
#include <malloc.h>
|
||||
#include <i2c.h>
|
||||
#include <micrel.h>
|
||||
#include <miiphy.h>
|
||||
#include <mmc.h>
|
||||
#include <netdev.h>
|
||||
|
||||
#include "tqma6_bb.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
||||
|
||||
#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
||||
|
||||
#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
|
||||
|
||||
#if defined(CONFIG_MX6Q)
|
||||
|
||||
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
|
||||
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
|
||||
|
||||
#elif defined(CONFIG_MX6S)
|
||||
|
||||
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
|
||||
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
|
||||
|
||||
#else
|
||||
|
||||
#error "need to define target CPU"
|
||||
|
||||
#endif
|
||||
|
||||
#define ENET_RX_PAD_CTRL (PAD_CTL_DSE_34ohm)
|
||||
#define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm)
|
||||
#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
|
||||
PAD_CTL_DSE_34ohm)
|
||||
#define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_60ohm)
|
||||
|
||||
/* disable on die termination for RGMII */
|
||||
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000
|
||||
/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
|
||||
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000
|
||||
/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
|
||||
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000
|
||||
|
||||
#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25)
|
||||
|
||||
static iomux_v3_cfg_t const mba6_enet_pads[] = {
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_MDIO_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_MDIO_PAD_CTRL),
|
||||
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_TX_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_TX_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_TX_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_TX_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_TX_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL,
|
||||
ENET_TX_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL),
|
||||
/*
|
||||
* these pins are also used for config strapping by phy
|
||||
*/
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_RX_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_RX_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_RX_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_RX_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_RX_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL,
|
||||
ENET_RX_PAD_CTRL),
|
||||
/* KSZ9031 PHY Reset */
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25, GPIO_OUT_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void mba6_setup_iomuxc_enet(void)
|
||||
{
|
||||
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
|
||||
(void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
|
||||
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
|
||||
(void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(mba6_enet_pads,
|
||||
ARRAY_SIZE(mba6_enet_pads));
|
||||
|
||||
/* Reset PHY */
|
||||
gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
|
||||
/* Need delay 10ms after power on according to KSZ9031 spec */
|
||||
udelay(1000 * 10);
|
||||
gpio_set_value(ENET_PHY_RESET_GPIO, 1);
|
||||
/*
|
||||
* KSZ9031 manual: 100 usec wait time after reset before communication
|
||||
* over MDIO
|
||||
* BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
|
||||
* reset before the phy sees a high level
|
||||
*/
|
||||
udelay(200);
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const mba6_uart2_pads[] = {
|
||||
NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void mba6_setup_iomuxc_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
|
||||
ARRAY_SIZE(mba6_uart2_pads));
|
||||
}
|
||||
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
|
||||
#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
|
||||
|
||||
int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
|
||||
ret = gpio_get_value(USDHC2_WP_GPIO);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct fsl_esdhc_cfg mba6_usdhc_cfg = {
|
||||
.esdhc_base = USDHC2_BASE_ADDR,
|
||||
.max_bus_width = 4,
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const mba6_usdhc2_pads[] = {
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC_CLK_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
|
||||
/* CD */
|
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, GPIO_IN_PAD_CTRL),
|
||||
/* WP */
|
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02, GPIO_IN_PAD_CTRL),
|
||||
};
|
||||
|
||||
int tqma6_bb_board_mmc_init(bd_t *bis)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads,
|
||||
ARRAY_SIZE(mba6_usdhc2_pads));
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
gpio_direction_input(USDHC2_WP_GPIO);
|
||||
|
||||
mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg))
|
||||
puts("Warning: failed to initialize SD\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct i2c_pads_info mba6_i2c1_pads = {
|
||||
/* I2C1: MBa6x */
|
||||
.scl = {
|
||||
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL,
|
||||
I2C_PAD_CTRL),
|
||||
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27,
|
||||
I2C_PAD_CTRL),
|
||||
.gp = IMX_GPIO_NR(5, 27)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA,
|
||||
I2C_PAD_CTRL),
|
||||
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26,
|
||||
I2C_PAD_CTRL),
|
||||
.gp = IMX_GPIO_NR(5, 26)
|
||||
}
|
||||
};
|
||||
|
||||
static void mba6_setup_i2c(void)
|
||||
{
|
||||
int ret;
|
||||
/*
|
||||
* use logical index for bus, e.g. I2C1 -> 0
|
||||
* warn on error
|
||||
*/
|
||||
ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
|
||||
if (ret)
|
||||
printf("setup I2C1 failed: %d\n", ret);
|
||||
}
|
||||
|
||||
|
||||
static iomux_v3_cfg_t const mba6_ecspi1_pads[] = {
|
||||
NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL),
|
||||
};
|
||||
|
||||
static unsigned const mba6_ecspi1_cs[] = {
|
||||
IMX_GPIO_NR(3, 24),
|
||||
IMX_GPIO_NR(3, 25),
|
||||
};
|
||||
|
||||
static void mba6_setup_iomuxc_spi(void)
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i)
|
||||
gpio_direction_output(mba6_ecspi1_cs[i], 1);
|
||||
imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads,
|
||||
ARRAY_SIZE(mba6_ecspi1_pads));
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
/*
|
||||
* optimized pad skew values depends on CPU variant on the TQMa6x module:
|
||||
* i.MX6Q/D or i.MX6DL/S
|
||||
*/
|
||||
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
|
||||
#define MBA6X_KSZ9031_CTRL_SKEW 0x0032
|
||||
#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
|
||||
#define MBA6X_KSZ9031_RX_SKEW 0x3333
|
||||
#define MBA6X_KSZ9031_TX_SKEW 0x2036
|
||||
#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
|
||||
#define MBA6X_KSZ9031_CTRL_SKEW 0x0030
|
||||
#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
|
||||
#define MBA6X_KSZ9031_RX_SKEW 0x3333
|
||||
#define MBA6X_KSZ9031_TX_SKEW 0x2052
|
||||
#else
|
||||
#error
|
||||
#endif
|
||||
/* min rx/tx ctrl delay */
|
||||
ksz9031_phy_extended_write(phydev, 2,
|
||||
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
MBA6X_KSZ9031_CTRL_SKEW);
|
||||
/* min rx delay */
|
||||
ksz9031_phy_extended_write(phydev, 2,
|
||||
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
MBA6X_KSZ9031_RX_SKEW);
|
||||
/* max tx delay */
|
||||
ksz9031_phy_extended_write(phydev, 2,
|
||||
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
MBA6X_KSZ9031_TX_SKEW);
|
||||
/* rx/tx clk skew */
|
||||
ksz9031_phy_extended_write(phydev, 2,
|
||||
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
MBA6X_KSZ9031_CLK_SKEW);
|
||||
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
uint32_t base = IMX_FEC_BASE;
|
||||
struct mii_dev *bus = NULL;
|
||||
struct phy_device *phydev = NULL;
|
||||
int ret;
|
||||
|
||||
bus = fec_get_miibus(base, -1);
|
||||
if (!bus)
|
||||
return -EINVAL;
|
||||
/* scan phy */
|
||||
phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
|
||||
PHY_INTERFACE_MODE_RGMII);
|
||||
|
||||
if (!phydev) {
|
||||
ret = -EINVAL;
|
||||
goto free_bus;
|
||||
}
|
||||
ret = fec_probe(bis, -1, base, bus, phydev);
|
||||
if (ret)
|
||||
goto free_phydev;
|
||||
|
||||
return 0;
|
||||
|
||||
free_phydev:
|
||||
free(phydev);
|
||||
free_bus:
|
||||
free(bus);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int tqma6_bb_board_early_init_f(void)
|
||||
{
|
||||
mba6_setup_iomuxc_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tqma6_bb_board_init(void)
|
||||
{
|
||||
mba6_setup_i2c();
|
||||
mba6_setup_iomuxc_spi();
|
||||
/* do it here - to have reset completed */
|
||||
mba6_setup_iomuxc_enet();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tqma6_bb_board_late_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
const char *tqma6_bb_get_boardname(void)
|
||||
{
|
||||
return "MBa6x";
|
||||
}
|
||||
|
||||
/*
|
||||
* Device Tree Support
|
||||
*/
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
|
||||
void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
/* TBD */
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
|
||||
346
u-boot/board/tqc/tqma6/tqma6_wru4.c
Normal file
346
u-boot/board/tqc/tqma6/tqma6_wru4.c
Normal file
@@ -0,0 +1,346 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Freescale Semiconductor, Inc.
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
|
||||
* Author: Markus Niebel <markus.niebel@tq-group.com>
|
||||
*
|
||||
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/boot_mode.h>
|
||||
#include <asm/imx-common/mxc_i2c.h>
|
||||
|
||||
#include <common.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <libfdt.h>
|
||||
#include <malloc.h>
|
||||
#include <i2c.h>
|
||||
#include <micrel.h>
|
||||
#include <miiphy.h>
|
||||
#include <mmc.h>
|
||||
#include <netdev.h>
|
||||
|
||||
#include "tqma6_bb.h"
|
||||
|
||||
/* UART */
|
||||
#define UART4_PAD_CTRL ( \
|
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_PUE | \
|
||||
PAD_CTL_PKE | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_SLOW \
|
||||
)
|
||||
|
||||
static iomux_v3_cfg_t const uart4_pads[] = {
|
||||
NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomuxc_uart4(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
|
||||
}
|
||||
|
||||
/* MMC */
|
||||
#define USDHC2_PAD_CTRL ( \
|
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_47K_UP | \
|
||||
PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | \
|
||||
PAD_CTL_SRE_FAST \
|
||||
)
|
||||
|
||||
#define USDHC2_CLK_PAD_CTRL ( \
|
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_47K_UP | \
|
||||
PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_FAST \
|
||||
)
|
||||
|
||||
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL),
|
||||
|
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */
|
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */
|
||||
};
|
||||
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
|
||||
#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc2_cfg = {
|
||||
.esdhc_base = USDHC2_BASE_ADDR,
|
||||
.max_bus_width = 4,
|
||||
};
|
||||
|
||||
int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
|
||||
ret = gpio_get_value(USDHC2_WP_GPIO);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int tqma6_bb_board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
|
||||
ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd");
|
||||
if (!ret)
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp");
|
||||
if (!ret)
|
||||
gpio_direction_input(USDHC2_WP_GPIO);
|
||||
|
||||
usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
if(fsl_esdhc_initialize(bis, &usdhc2_cfg))
|
||||
puts("WARNING: failed to initialize SD\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Ethernet */
|
||||
#define ENET_PAD_CTRL ( \
|
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_PUE | \
|
||||
PAD_CTL_PKE | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_SLOW \
|
||||
)
|
||||
|
||||
static iomux_v3_cfg_t const enet_pads[] = {
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL),
|
||||
|
||||
/* ENET1 reset */
|
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL),
|
||||
/* ENET1 interrupt */
|
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8)
|
||||
|
||||
static void setup_iomuxc_enet(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
|
||||
|
||||
/* Reset LAN8720 PHY */
|
||||
ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
|
||||
if (!ret)
|
||||
gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
|
||||
udelay(25000);
|
||||
gpio_set_value(ENET_PHY_RESET_GPIO, 1);
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PAD_CTRL ( \
|
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_PUE | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_SLOW \
|
||||
)
|
||||
|
||||
#define GPIO_OD_PAD_CTRL ( \
|
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_PUE | \
|
||||
PAD_CTL_ODE | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_SLOW \
|
||||
)
|
||||
|
||||
static iomux_v3_cfg_t const gpio_pads[] = {
|
||||
/* USB_H_PWR */
|
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL),
|
||||
/* USB_OTG_PWR */
|
||||
NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL),
|
||||
/* PCIE_RST */
|
||||
NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL),
|
||||
/* UART1_PWRON */
|
||||
NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL),
|
||||
/* UART2_PWRON */
|
||||
NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL),
|
||||
/* UART3_PWRON */
|
||||
NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0)
|
||||
#define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22)
|
||||
#define GPIO_PCIE_RST IMX_GPIO_NR(6, 7)
|
||||
#define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8)
|
||||
#define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10)
|
||||
#define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12)
|
||||
|
||||
static void gpio_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
|
||||
|
||||
ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr");
|
||||
if (!ret)
|
||||
gpio_direction_output(GPIO_USB_H_PWR, 1);
|
||||
ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr");
|
||||
if (!ret)
|
||||
gpio_direction_output(GPIO_USB_OTG_PWR, 1);
|
||||
ret = gpio_request(GPIO_PCIE_RST, "pcie-reset");
|
||||
if (!ret)
|
||||
gpio_direction_output(GPIO_PCIE_RST, 1);
|
||||
ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr");
|
||||
if (!ret)
|
||||
gpio_direction_output(GPIO_UART1_PWRON, 0);
|
||||
ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr");
|
||||
if (!ret)
|
||||
gpio_direction_output(GPIO_UART2_PWRON, 0);
|
||||
ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr");
|
||||
if (!ret)
|
||||
gpio_direction_output(GPIO_UART3_PWRON, 0);
|
||||
}
|
||||
|
||||
void tqma6_iomuxc_spi(void)
|
||||
{
|
||||
/* No SPI on this baseboard */
|
||||
}
|
||||
|
||||
int tqma6_bb_board_early_init_f(void)
|
||||
{
|
||||
setup_iomuxc_uart4();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tqma6_bb_board_init(void)
|
||||
{
|
||||
setup_iomuxc_enet();
|
||||
|
||||
gpio_init();
|
||||
|
||||
/* Turn the UART-couplers on one-after-another */
|
||||
gpio_set_value(GPIO_UART1_PWRON, 1);
|
||||
mdelay(10);
|
||||
gpio_set_value(GPIO_UART2_PWRON, 1);
|
||||
mdelay(10);
|
||||
gpio_set_value(GPIO_UART3_PWRON, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tqma6_bb_board_late_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
const char *tqma6_bb_get_boardname(void)
|
||||
{
|
||||
return "WRU-IV";
|
||||
}
|
||||
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
||||
/* 8 bit bus width */
|
||||
{"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
||||
{ NULL, 0 },
|
||||
};
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0)
|
||||
#define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22)
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr");
|
||||
if (!ret)
|
||||
gpio_direction_output(WRU4_USB_H1_PWR, 1);
|
||||
|
||||
ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr");
|
||||
if (!ret)
|
||||
gpio_direction_output(WRU4_USB_OTG_PWR, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_ehci_power(int port, int on)
|
||||
{
|
||||
if (port)
|
||||
gpio_set_value(WRU4_USB_OTG_PWR, on);
|
||||
else
|
||||
gpio_set_value(WRU4_USB_H1_PWR, on);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Device Tree Support
|
||||
*/
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
|
||||
void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
/* TBD */
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
|
||||
125
u-boot/board/tqc/tqma6/tqma6q.cfg
Normal file
125
u-boot/board/tqc/tqma6/tqma6q.cfg
Normal file
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer doc/README.imximage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi, sd (the board has no nand neither onenand)
|
||||
*/
|
||||
#if defined(CONFIG_TQMA6X_MMC_BOOT)
|
||||
BOOT_FROM sd
|
||||
#elif defined(CONFIG_TQMA6X_SPI_BOOT)
|
||||
BOOT_FROM spi
|
||||
#endif
|
||||
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/crm_regs.h"
|
||||
|
||||
/* TQMa6Q/D DDR config Rev. 0100B */
|
||||
/* IOMUX configuration */
|
||||
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
|
||||
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
|
||||
DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
|
||||
DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
|
||||
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
|
||||
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
|
||||
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
|
||||
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
|
||||
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
|
||||
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
||||
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
||||
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
|
||||
|
||||
/* memory interface calibration values */
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304
|
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436
|
||||
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242
|
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440
|
||||
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
||||
|
||||
/* configure memory interface */
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
||||
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
|
||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
||||
|
||||
#include "clocks.cfg"
|
||||
125
u-boot/board/tqc/tqma6/tqma6s.cfg
Normal file
125
u-boot/board/tqc/tqma6/tqma6s.cfg
Normal file
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer doc/README.imximage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi, sd (the board has no nand neither onenand)
|
||||
*/
|
||||
#if defined(CONFIG_TQMA6X_MMC_BOOT)
|
||||
BOOT_FROM sd
|
||||
#elif defined(CONFIG_TQMA6X_SPI_BOOT)
|
||||
BOOT_FROM spi
|
||||
#endif
|
||||
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/crm_regs.h"
|
||||
|
||||
/* TQMa6S DDR config Rev. 0100B */
|
||||
/* IOMUX configuration */
|
||||
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
|
||||
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
|
||||
DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
|
||||
DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
|
||||
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
|
||||
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
|
||||
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
|
||||
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
|
||||
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
|
||||
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
||||
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
|
||||
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
||||
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
|
||||
DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
|
||||
DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
|
||||
DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
|
||||
|
||||
/* memory interface calibration values */
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A
|
||||
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32
|
||||
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000
|
||||
|
||||
/* configure memory interface */
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
||||
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
|
||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
||||
|
||||
#include "clocks.cfg"
|
||||
Reference in New Issue
Block a user