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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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51
u-boot/board/ti/ks2_evm/Kconfig Normal file
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if TARGET_K2E_EVM
config SYS_BOARD
default "ks2_evm"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "k2e_evm"
endif
if TARGET_K2HK_EVM
config SYS_BOARD
default "ks2_evm"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "k2hk_evm"
endif
if TARGET_K2L_EVM
config SYS_BOARD
default "ks2_evm"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "k2l_evm"
endif
if TARGET_K2G_EVM
config SYS_BOARD
default "ks2_evm"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "k2g_evm"
endif

12
u-boot/board/ti/ks2_evm/MAINTAINERS Normal file
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KS2_EVM BOARD
M: Vitaly Andrianov <vitalya@ti.com>
S: Maintained
F: board/ti/ks2_evm/
F: include/configs/k2hk_evm.h
F: configs/k2hk_evm_defconfig
F: include/configs/k2e_evm.h
F: configs/k2e_evm_defconfig
F: include/configs/k2l_evm.h
F: configs/k2l_evm_defconfig
F: include/configs/k2g_evm.h
F: configs/k2g_evm_defconfig

17
u-boot/board/ti/ks2_evm/Makefile Normal file
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#
# KS2-EVM: board Makefile
# (C) Copyright 2012-2015
# Texas Instruments Incorporated, <www.ti.com>
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += board.o
obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
obj-$(CONFIG_K2E_EVM) += board_k2e.o
obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
obj-$(CONFIG_K2L_EVM) += board_k2l.o
obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
obj-$(CONFIG_K2L_EVM) += ddr3_cfg.o
obj-$(CONFIG_K2G_EVM) += board_k2g.o
obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o

174
u-boot/board/ti/ks2_evm/README Normal file
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U-Boot port for Texas Instruments Keystone II EVM boards
========================================================
Author: Murali Karicheri <m-karicheri2@ti.com>
This README has information on the U-Boot port for K2HK, K2E, and K2L EVM boards.
Documentation for this board can be found at
http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html
https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html
The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K.
More details on these SoCs are available at company websites
K2K: http://www.ti.com/product/tci6638k2k
K2H: http://www.ti.com/product/tci6638k2h
The K2E SoC details are available at
http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
The K2L SoC details are available at
http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
Board configuration:
====================
Some of the peripherals that are configured by U-Boot
+------+-------+-------+-----------+-----------+-------+-------+----+
| |DDR3 |NAND |MSM SRAM |ETH ports |UART |I2C |SPI |
+------+-------+-------+-----------+-----------+-------+-------+----+
|K2HK |2 |512MB |6MB |4(2) |2 |3 |3 |
|K2E |4 |512MB |2MB |8(2) |2 |3 |3 |
|K2L |2 |512MB |2MB |4(2) |4 |3 |3 |
+------+-------+-------+-----------+-----------+-------+-------+----+
There are only 2 eth port installed on the boards.
There are separate PLLs to drive clocks to Tetris ARM and Peripherals.
To bring up SMP Linux on this board, there is a boot monitor
code that will be installed in MSMC SRAM. There is command available
to install this image from U-Boot.
The port related files can be found at following folders
keystone2 SoC related files: arch/arm/cpu/armv7/keystone/
EVMs board files: board/ti/k2s_evm/
Board configuration files:
include/configs/k2hk_evm.h
include/configs/k2e_evm.h
include/configs/k2l_evm.h
As U-Boot is migrating to Kconfig there is also board defconfig files
configs/k2e_evm_defconfig
configs/k2hk_evm_defconfig
configs/k2l_evm_defconfig
Supported boot modes:
- SPI NOR boot
- AEMIF NAND boot
- UART boot
Supported image formats:
- u-boot-dtb.bin: for loading and running u-boot-dtb.bin through
Texas Instruments code composure studio (CCS) and for UART boot.
- u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
- MLO: gpimage for programming AEMIF NAND flash for NAND boot
Build instructions:
===================
Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly.
Don't forget to add ARCH=arm and CROSS_COMPILE.
To build u-boot-dtb.bin, u-boot-spi.gph, MLO:
>make k2hk_evm_defconfig
>make
Load and Run U-Boot on keystone EVMs using CCS
=========================================
Need Code Composer Studio (CCS) installed on a PC to load and run u-boot-dtb.bin
on EVM. See instructions at below link for installing CCS on a Windows PC.
http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started#
Installing_Code_Composer_Studio
Use u-boot-dtb.bin from the build folder for loading and running U-Boot binary
on EVM. Follow instructions at
K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup
K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup
to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
and Power ON the EVM. Follow instructions to connect serial port of EVM to
PC and start TeraTerm or Hyper Terminal.
Start CCS on a Windows machine and Launch Target
configuration as instructed at http://processors.wiki.ti.com/index.php/
MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS.
The instructions provided in the above link uses a script for
loading the U-Boot binary on the target EVM. Instead do the following:-
1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D
is connected: Unknown)" at the debug window (This is created once Target
configuration is launched) and select "Connect Target".
2. Once target connect is successful, choose Tools->Load Memory option from the
top level menu. At the Load Memory window, choose the file u-boot-dtb.bin
through "Browse" button and click "next >" button. In the next window, enter
Start address as 0xc001000, choose Type-size "32 bits" and click "Finish"
button.
3. Click View -> Registers from the top level menu to view registers window.
4. From Registers, window expand "Core Registers" to view PC. Edit PC value
to be 0xc001000. From the "Run" top level menu, select "Free Run"
5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as
below and type any key to stop autoboot as instructed :=
U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59)
I2C: ready
Detected SO-DIMM [SQR-SD3T-2G1333SED]
DRAM: 1.1 GiB
NAND: 512 MiB
Net: K2HK_EMAC
Warning: K2HK_EMAC using MAC address from net device
, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3
Hit any key to stop autoboot: 0
SPI NOR Flash programming instructions
======================================
U-Boot image can be flashed to first 512KB of the NOR flash using following
instructions:
1. Start CCS and run U-Boot as described above.
2. Suspend Target. Select Run -> Suspend from top level menu
CortexA15_1 (Free Running)"
3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L
EVM using CCS", but using address 0x87000000.
4. Free Run the target as described earlier (step 4) to get U-Boot prompt
5. At the U-Boot console type following to setup U-Boot environment variables.
setenv addr_uboot 0x87000000
setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
run burn_uboot_spi
Once U-Boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
to "SPI Little Endian Boot mode" as per instruction at
http://processors.wiki.ti.com/index.php/*_Hardware_Setup.
6. Power ON the EVM. The EVM now boots with U-Boot image on the NOR flash.
AEMIF NAND Flash programming instructions
======================================
U-Boot image can be flashed to first 1024KB of the NAND flash using following
instructions:
1. Start CCS and run U-Boot as described above.
2. Suspend Target. Select Run -> Suspend from top level menu
CortexA15_1 (Free Running)"
3. Load MLO binary from build folder on to DDR address 0x87000000
through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
using CCS", but using address 0x87000000.
4. Free Run the target as described earlier (step 4) to get U-Boot prompt
5. At the U-Boot console type following to setup U-Boot environment variables.
setenv filesize <size in hex of MLO rounded to hex 0x10000>
run burn_uboot_nand
Once U-Boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
to "ARM NAND Boot mode" as per instruction at
http://processors.wiki.ti.com/index.php/*_Hardware_Setup.
6. Power ON the EVM. The EVM now boots with U-Boot image on the NAND flash.
Load and Run U-Boot on keystone EVMs using UART download
========================================================
Open BMC and regular UART terminals.
1. On the regular UART port start xmodem transfer of the u-boot-dtb.bin
2. Using BMC terminal set the ARM-UART bootmode and reboot the EVM
BMC> bootmode #4
MBC> reboot
3. When xmodem is complete you should see the U-Boot starts on the UART port

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u-boot/board/ti/ks2_evm/board.c Normal file
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/*
* Keystone : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "board.h"
#include <spl.h>
#include <exports.h>
#include <fdt_support.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/clock.h>
#include <asm/ti-common/ti-aemif.h>
#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_TI_AEMIF)
static struct aemif_config aemif_configs[] = {
{ /* CS0 */
.mode = AEMIF_MODE_NAND,
.wr_setup = 0xf,
.wr_strobe = 0x3f,
.wr_hold = 7,
.rd_setup = 0xf,
.rd_strobe = 0x3f,
.rd_hold = 7,
.turn_around = 3,
.width = AEMIF_WIDTH_8,
},
};
#endif
int dram_init(void)
{
u32 ddr3_size;
ddr3_size = ddr3_init();
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
#if defined(CONFIG_TI_AEMIF)
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
#endif
if (ddr3_size)
ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
return 0;
}
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
#ifndef CONFIG_DM_ETH
int get_eth_env_param(char *env_name)
{
char *env;
int res = -1;
env = getenv(env_name);
if (env)
res = simple_strtol(env, NULL, 0);
return res;
}
int board_eth_init(bd_t *bis)
{
int j;
int res;
int port_num;
char link_type_name[32];
if (cpu_is_k2g())
writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
/* By default, select PA PLL clock as PA clock source */
#ifndef CONFIG_SOC_K2G
if (psc_enable_module(KS2_LPSC_PA))
return -1;
#endif
if (psc_enable_module(KS2_LPSC_CPGMAC))
return -1;
if (psc_enable_module(KS2_LPSC_CRYPTO))
return -1;
if (cpu_is_k2e() || cpu_is_k2l())
pll_pa_clk_sel();
port_num = get_num_eth_ports();
for (j = 0; j < port_num; j++) {
sprintf(link_type_name, "sgmii%d_link_type", j);
res = get_eth_env_param(link_type_name);
if (res >= 0)
eth_priv_cfg[j].sgmii_link_type = res;
keystone2_emac_initialize(&eth_priv_cfg[j]);
}
return 0;
}
#endif
#endif
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
spl_init_keystone_plls();
preloader_console_init();
}
u32 spl_boot_device(void)
{
#if defined(CONFIG_SPL_SPI_LOAD)
return BOOT_DEVICE_SPI;
#else
puts("Unknown boot device\n");
hang();
#endif
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int lpae;
char *env;
char *endp;
int nbanks;
u64 size[2];
u64 start[2];
int nodeoffset;
u32 ddr3a_size;
int unitrd_fixup = 0;
env = getenv("mem_lpae");
lpae = env && simple_strtol(env, NULL, 0);
env = getenv("uinitrd_fixup");
unitrd_fixup = env && simple_strtol(env, NULL, 0);
ddr3a_size = 0;
if (lpae) {
ddr3a_size = ddr3_get_size();
if ((ddr3a_size != 8) && (ddr3a_size != 4))
ddr3a_size = 0;
}
nbanks = 1;
start[0] = bd->bi_dram[0].start;
size[0] = bd->bi_dram[0].size;
/* adjust memory start address for LPAE */
if (lpae) {
start[0] -= CONFIG_SYS_SDRAM_BASE;
start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
}
if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
size[1] = ((u64)ddr3a_size - 2) << 30;
start[1] = 0x880000000;
nbanks++;
}
/* reserve memory at start of bank */
env = getenv("mem_reserve_head");
if (env) {
start[0] += ustrtoul(env, &endp, 0);
size[0] -= ustrtoul(env, &endp, 0);
}
env = getenv("mem_reserve");
if (env)
size[0] -= ustrtoul(env, &endp, 0);
fdt_fixup_memory_banks(blob, start, size, nbanks);
/* Fix up the initrd */
if (lpae && unitrd_fixup) {
int err;
u32 *prop1, *prop2;
u64 initrd_start, initrd_end;
nodeoffset = fdt_path_offset(blob, "/chosen");
if (nodeoffset >= 0) {
prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
"linux,initrd-start", NULL);
prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
"linux,initrd-end", NULL);
if (prop1 && prop2) {
initrd_start = __be32_to_cpu(*prop1);
initrd_start -= CONFIG_SYS_SDRAM_BASE;
initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_start = __cpu_to_be64(initrd_start);
initrd_end = __be32_to_cpu(*prop2);
initrd_end -= CONFIG_SYS_SDRAM_BASE;
initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_end = __cpu_to_be64(initrd_end);
err = fdt_delprop(blob, nodeoffset,
"linux,initrd-start");
if (err < 0)
puts("error deleting initrd-start\n");
err = fdt_delprop(blob, nodeoffset,
"linux,initrd-end");
if (err < 0)
puts("error deleting initrd-end\n");
err = fdt_setprop(blob, nodeoffset,
"linux,initrd-start",
&initrd_start,
sizeof(initrd_start));
if (err < 0)
puts("error adding initrd-start\n");
err = fdt_setprop(blob, nodeoffset,
"linux,initrd-end",
&initrd_end,
sizeof(initrd_end));
if (err < 0)
puts("error adding linux,initrd-end\n");
}
}
}
return 0;
}
void ft_board_setup_ex(void *blob, bd_t *bd)
{
int lpae;
u64 size;
char *env;
u64 *reserve_start;
env = getenv("mem_lpae");
lpae = env && simple_strtol(env, NULL, 0);
if (lpae) {
/*
* the initrd and other reserved memory areas are
* embedded in in the DTB itslef. fix up these addresses
* to 36 bit format
*/
reserve_start = (u64 *)((char *)blob +
fdt_off_mem_rsvmap(blob));
while (1) {
*reserve_start = __cpu_to_be64(*reserve_start);
size = __cpu_to_be64(*(reserve_start + 1));
if (size) {
*reserve_start -= CONFIG_SYS_SDRAM_BASE;
*reserve_start +=
CONFIG_SYS_LPAE_SDRAM_BASE;
*reserve_start =
__cpu_to_be64(*reserve_start);
} else {
break;
}
reserve_start += 2;
}
}
ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
}
#endif /* CONFIG_OF_BOARD_SETUP */

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u-boot/board/ti/ks2_evm/board.h Normal file
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/*
* K2HK EVM : Board common header
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _KS2_BOARD
#define _KS2_BOARD
#include <asm/ti-common/keystone_net.h>
extern struct eth_priv_t eth_priv_cfg[];
int get_num_eth_ports(void);
void spl_init_keystone_plls(void);
#endif

165
u-boot/board/ti/ks2_evm/board_k2e.c Normal file
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/*
* K2E EVM : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 100000000,
[alt_core_clk] = 100000000,
[pa_clk] = 100000000,
[ddr3a_clk] = 100000000,
};
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_800,
[SPD850] = CORE_PLL_850,
[SPD1000] = CORE_PLL_1000,
[SPD1250] = CORE_PLL_1250,
[SPD1350] = CORE_PLL_1350,
[SPD1400] = CORE_PLL_1400,
[SPD1500] = CORE_PLL_1500,
};
/* DEV and ARM speed definitions as specified in DEVSPEED register */
int speeds[DEVSPEED_NUMSPDS] = {
SPD850,
SPD1000,
SPD1250,
SPD1350,
SPD1400,
SPD1500,
SPD1400,
SPD1350,
SPD1250,
SPD1000,
SPD850,
SPD800,
};
s16 divn_val[16] = {
0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};
static struct pll_init_data pa_pll_config =
PASS_PLL_1000;
struct pll_init_data *get_pll_init_data(int pll)
{
int speed;
struct pll_init_data *data;
switch (pll) {
case MAIN_PLL:
speed = get_max_dev_speed(speeds);
data = &core_pll_config[speed];
break;
case PASS_PLL:
data = &pa_pll_config;
break;
default:
data = NULL;
}
return data;
}
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
.int_name = "K2E_EMAC0",
.rx_flow = 0,
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC1",
.rx_flow = 8,
.phy_addr = 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC2",
.rx_flow = 16,
.phy_addr = 2,
.slave_port = 3,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC3",
.rx_flow = 24,
.phy_addr = 3,
.slave_port = 4,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC4",
.rx_flow = 32,
.phy_addr = 4,
.slave_port = 5,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC5",
.rx_flow = 40,
.phy_addr = 5,
.slave_port = 6,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC6",
.rx_flow = 48,
.phy_addr = 6,
.slave_port = 7,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC7",
.rx_flow = 56,
.phy_addr = 7,
.slave_port = 8,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
};
int get_num_eth_ports(void)
{
return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
init_plls();
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
init_plls();
}
#endif

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/*
* K2G EVM : Board initialization
*
* (C) Copyright 2015
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/ti-common/keystone_net.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/mmc_host_def.h>
#include "mux-k2g.h"
#define SYS_CLK 24000000
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = SYS_CLK,
[pa_clk] = SYS_CLK,
[tetris_clk] = SYS_CLK,
[ddr3a_clk] = SYS_CLK,
[uart_clk] = SYS_CLK,
};
static int arm_speeds[DEVSPEED_NUMSPDS] = {
SPD400,
SPD600,
SPD800,
SPD900,
SPD1000,
SPD900,
SPD800,
SPD600,
SPD400,
SPD200,
};
static int dev_speeds[DEVSPEED_NUMSPDS] = {
SPD600,
SPD800,
SPD900,
SPD1000,
SPD900,
SPD800,
SPD600,
SPD400,
};
static struct pll_init_data main_pll_config[NUM_SPDS] = {
[SPD400] = {MAIN_PLL, 100, 3, 2},
[SPD600] = {MAIN_PLL, 300, 6, 2},
[SPD800] = {MAIN_PLL, 200, 3, 2},
[SPD900] = {TETRIS_PLL, 75, 1, 2},
[SPD1000] = {TETRIS_PLL, 250, 3, 2},
};
static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
[SPD200] = {TETRIS_PLL, 250, 3, 10},
[SPD400] = {TETRIS_PLL, 100, 1, 6},
[SPD600] = {TETRIS_PLL, 100, 1, 4},
[SPD800] = {TETRIS_PLL, 400, 3, 4},
[SPD900] = {TETRIS_PLL, 75, 1, 2},
[SPD1000] = {TETRIS_PLL, 250, 3, 2},
};
static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
struct pll_init_data *get_pll_init_data(int pll)
{
int speed;
struct pll_init_data *data = NULL;
switch (pll) {
case MAIN_PLL:
speed = get_max_dev_speed(dev_speeds);
data = &main_pll_config[speed];
break;
case TETRIS_PLL:
speed = get_max_arm_speed(arm_speeds);
data = &tetris_pll_config[speed];
break;
case NSS_PLL:
data = &nss_pll_config;
break;
case UART_PLL:
data = &uart_pll_config;
break;
case DDR3_PLL:
data = &ddr3_pll_config;
break;
default:
data = NULL;
}
return data;
}
s16 divn_val[16] = {
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
if (psc_enable_module(KS2_LPSC_MMC)) {
printf("%s module enabled failed\n", __func__);
return -1;
}
omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
static void k2g_reset_mux_config(void)
{
/* Unlock the reset mux register */
clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
/* lock the reset mux register to prevent any spurious writes. */
setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
}
int board_early_init_f(void)
{
init_plls();
k2g_mux_config();
k2g_reset_mux_config();
/* deassert FLASH_HOLD */
clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
BIT(9));
setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
BIT(9));
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
init_plls();
}
#endif
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
.int_name = "K2G_EMAC",
.rx_flow = 0,
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
.phy_if = PHY_INTERFACE_MODE_RGMII,
},
};
int get_num_eth_ports(void)
{
return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif

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/*
* K2HK EVM : Board initialization
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 122880000,
[alt_core_clk] = 125000000,
[pa_clk] = 122880000,
[tetris_clk] = 125000000,
[ddr3a_clk] = 100000000,
[ddr3b_clk] = 100000000,
};
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_799,
[SPD1000] = CORE_PLL_999,
[SPD1200] = CORE_PLL_1200,
};
s16 divn_val[16] = {
0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};
static struct pll_init_data tetris_pll_config[] = {
[SPD800] = TETRIS_PLL_800,
[SPD1000] = TETRIS_PLL_1000,
[SPD1200] = TETRIS_PLL_1200,
[SPD1350] = TETRIS_PLL_1350,
[SPD1400] = TETRIS_PLL_1400,
};
static struct pll_init_data pa_pll_config =
PASS_PLL_983;
struct pll_init_data *get_pll_init_data(int pll)
{
int speed;
struct pll_init_data *data;
switch (pll) {
case MAIN_PLL:
speed = get_max_dev_speed(speeds);
data = &core_pll_config[speed];
break;
case TETRIS_PLL:
speed = get_max_arm_speed(speeds);
data = &tetris_pll_config[speed];
break;
case PASS_PLL:
data = &pa_pll_config;
break;
default:
data = NULL;
}
return data;
}
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
.int_name = "K2HK_EMAC",
.rx_flow = 22,
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2HK_EMAC1",
.rx_flow = 23,
.phy_addr = 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2HK_EMAC2",
.rx_flow = 24,
.phy_addr = 2,
.slave_port = 3,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2HK_EMAC3",
.rx_flow = 25,
.phy_addr = 3,
.slave_port = 4,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
};
int get_num_eth_ports(void)
{
return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
init_plls();
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
init_plls();
}
#endif

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/*
* K2L EVM : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 122880000,
[alt_core_clk] = 100000000,
[pa_clk] = 122880000,
[tetris_clk] = 122880000,
[ddr3a_clk] = 100000000,
};
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_799,
[SPD1000] = CORE_PLL_1000,
[SPD1200] = CORE_PLL_1198,
};
s16 divn_val[16] = {
0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};
static struct pll_init_data tetris_pll_config[] = {
[SPD800] = TETRIS_PLL_799,
[SPD1000] = TETRIS_PLL_1000,
[SPD1200] = TETRIS_PLL_1198,
[SPD1350] = TETRIS_PLL_1352,
[SPD1400] = TETRIS_PLL_1401,
};
static struct pll_init_data pa_pll_config =
PASS_PLL_983;
struct pll_init_data *get_pll_init_data(int pll)
{
int speed;
struct pll_init_data *data;
switch (pll) {
case MAIN_PLL:
speed = get_max_dev_speed(speeds);
data = &core_pll_config[speed];
break;
case TETRIS_PLL:
speed = get_max_arm_speed(speeds);
data = &tetris_pll_config[speed];
break;
case PASS_PLL:
data = &pa_pll_config;
break;
default:
data = NULL;
}
return data;
}
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
.int_name = "K2L_EMAC",
.rx_flow = 0,
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2L_EMAC1",
.rx_flow = 8,
.phy_addr = 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2L_EMAC2",
.rx_flow = 16,
.phy_addr = 2,
.slave_port = 3,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2L_EMAC3",
.rx_flow = 32,
.phy_addr = 3,
.slave_port = 4,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
};
int get_num_eth_ports(void)
{
return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
init_plls();
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
init_plls();
}
#endif

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u-boot/board/ti/ks2_evm/ddr3_cfg.c Normal file
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/*
* Keystone2: DDR3 configuration
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/ddr3.h>
#include "ddr3_cfg.h"
struct ddr3_phy_config ddr3phy_1600_2g = {
.pllcr = 0x0001C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x0D861A80ul,
.ptr4 = 0x0C827100ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
.dcr_val = ((1 << 10)),
.dtpr0 = 0x9D5CBB66ul,
.dtpr1 = 0x12868300ul,
.dtpr2 = 0x5002D200ul,
.mr0 = 0x00001C70ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000018ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F07A12ul,
.zq0cr1 = 0x0001005Dul,
.zq1cr1 = 0x0001005Bul,
.zq2cr1 = 0x0001005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
struct ddr3_emif_config ddr3_1600_2g = {
.sdcfg = 0x6200CE62ul,
.sdtim1 = 0x166C9855ul,
.sdtim2 = 0x00001D4Aul,
.sdtim3 = 0x435DFF53ul,
.sdtim4 = 0x543F0CFFul,
.zqcfg = 0x70073200ul,
.sdrfc = 0x00001869ul,
};

20
u-boot/board/ti/ks2_evm/ddr3_cfg.h Normal file
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/*
* Keystone2: DDR3 configuration
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DDR3_CFG_H
#define __DDR3_CFG_H
#include <asm/arch/ddr3.h>
extern struct ddr3_phy_config ddr3phy_1600_2g;
extern struct ddr3_emif_config ddr3_1600_2g;
int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb);
#endif /* __DDR3_CFG_H */

48
u-boot/board/ti/ks2_evm/ddr3_k2e.c Normal file
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/*
* Keystone2: DDR3 initialization
*
* (C) Copyright 2014-2015
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
static struct pll_init_data ddr3_400 = DDR3_PLL_400;
static struct pll_init_data ddr3_333 = DDR3_PLL_333;
u32 ddr3_init(void)
{
struct ddr3_spd_cb spd_cb;
if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
printf("Sorry, I don't know how to configure DDR3A.\n"
"Bye :(\n");
for (;;)
;
}
printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
if (spd_cb.ddrspdclock == 1600)
init_pll(&ddr3_400);
else
init_pll(&ddr3_333);
/* Reset DDR3 PHY after PLL enabled */
ddr3_reset_ddrphy();
spd_cb.phy_cfg.zq0cr1 |= 0x10000;
spd_cb.phy_cfg.zq1cr1 |= 0x10000;
spd_cb.phy_cfg.zq2cr1 |= 0x10000;
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);
return (u32)spd_cb.ddr_size_gbyte;
}

64
u-boot/board/ti/ks2_evm/ddr3_k2g.c Normal file
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/*
* K2G: DDR3 initialization
*
* (C) Copyright 2015
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
struct ddr3_phy_config ddr3phy_800_2g = {
.pllcr = 0x000DC000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0,
.ptr3 = 0x06C30D40ul,
.ptr4 = 0x06413880ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
.dcr_val = ((1 << 10)),
.dtpr0 = 0x550F6644ul,
.dtpr1 = 0x328341E0ul,
.dtpr2 = 0x50022A00ul,
.mr0 = 0x00001430ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000018ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F03D09ul,
.zq0cr1 = 0x0001005Dul,
.zq1cr1 = 0x0001005Bul,
.zq2cr1 = 0x0001005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x00000F81ul,
};
struct ddr3_emif_config ddr3_800_2g = {
.sdcfg = 0x62005662ul,
.sdtim1 = 0x0A385033ul,
.sdtim2 = 0x00001CA5ul,
.sdtim3 = 0x21ADFF32ul,
.sdtim4 = 0x533F067Ful,
.zqcfg = 0x70073200ul,
.sdrfc = 0x00000C34ul,
};
u32 ddr3_init(void)
{
/* Reset DDR3 PHY after PLL enabled */
ddr3_reset_ddrphy();
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
return 0;
}
inline int ddr3_get_size(void)
{
return 2;
}

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u-boot/board/ti/ks2_evm/ddr3_k2hk.c Normal file
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/*
* Keystone2: DDR3 initialization
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
u32 ddr3_init(void)
{
u32 ddr3_size;
struct ddr3_spd_cb spd_cb;
if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
printf("Sorry, I don't know how to configure DDR3A.\n"
"Bye :(\n");
for (;;)
;
}
printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
if ((cpu_revision() > 1) ||
(__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) {
printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
if (spd_cb.ddrspdclock == 1600)
init_pll(&ddr3a_400);
else
init_pll(&ddr3a_333);
}
if (cpu_revision() > 0) {
if (cpu_revision() > 1) {
/* PG 2.0 */
/* Reset DDR3A PHY after PLL enabled */
ddr3_reset_ddrphy();
spd_cb.phy_cfg.zq0cr1 |= 0x10000;
spd_cb.phy_cfg.zq1cr1 |= 0x10000;
spd_cb.phy_cfg.zq2cr1 |= 0x10000;
}
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
ddr3_size = spd_cb.ddr_size_gbyte;
} else {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
spd_cb.emif_cfg.sdcfg |= 0x1000;
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
ddr3_size = spd_cb.ddr_size_gbyte / 2;
}
printf("DRAM: %d GiB (includes reported below)\n", ddr3_size);
/* Apply the workaround for PG 1.0 and 1.1 Silicons */
if (cpu_revision() <= 1)
ddr3_err_reset_workaround();
return ddr3_size;
}

30
u-boot/board/ti/ks2_evm/ddr3_k2l.c Normal file
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/*
* Keystone2: DDR3 initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
static struct pll_init_data ddr3_400 = DDR3_PLL_400;
u32 ddr3_init(void)
{
init_pll(&ddr3_400);
/* No SO-DIMM, 2GB discreet DDR */
printf("DRAM: 2 GiB\n");
/* Reset DDR3 PHY after PLL enabled */
ddr3_reset_ddrphy();
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
return 2;
}

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u-boot/board/ti/ks2_evm/mux-k2g.h Normal file
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/*
* K2G EVM: Pinmux configuration
*
* (C) Copyright 2015
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mux-k2g.h>
#include <asm/arch/hardware.h>
struct pin_cfg k2g_evm_pin_cfg[] = {
/* GPMC */
{ 0, MODE(0) }, /* GPMCAD0 */
{ 1, MODE(0) }, /* GPMCAD1 */
{ 2, MODE(0) }, /* GPMCAD2 */
{ 3, MODE(0) }, /* GPMCAD3 */
{ 4, MODE(0) }, /* GPMCAD4 */
{ 5, MODE(0) }, /* GPMCAD5 */
{ 6, MODE(0) }, /* GPMCAD6 */
{ 7, MODE(0) }, /* GPMCAD7 */
{ 8, MODE(0) }, /* GPMCAD8 */
{ 9, MODE(0) }, /* GPMCAD9 */
{ 10, MODE(0) }, /* GPMCAD10 */
{ 11, MODE(0) }, /* GPMCAD11 */
{ 12, MODE(0) }, /* GPMCAD12 */
{ 13, MODE(0) }, /* GPMCAD13 */
{ 14, MODE(0) }, /* GPMCAD14 */
{ 15, MODE(0) }, /* GPMCAD15 */
{ 17, MODE(0) }, /* GPMCADVNALE */
{ 18, MODE(0) }, /* GPMCOENREN */
{ 19, MODE(0) }, /* GPMCWEN */
{ 20, MODE(0) }, /* GPMCBE0NCLE */
{ 22, MODE(0) }, /* GPMCWAIT0 */
{ 24, MODE(0) }, /* GPMCWPN */
{ 26, MODE(0) }, /* GPMCCSN0 */
/* GPIOs */
{ 16, MODE(3) | PIN_IEN }, /* GPIO0_16 - PRSNT1# */
{ 21, MODE(3) | PIN_IEN }, /* GPIO0_21 - DC_BRD_DET */
{ 82, MODE(3) | PIN_IEN }, /* GPIO0_82 - TPS_INT1 */
{ 83, MODE(3) }, /* GPIO0_83 - TPS_SLEEP */
{ 84, MODE(3) }, /* GPIO0_84 - SEL_HDMIn_GPIO */
{ 87, MODE(3) }, /* GPIO0_87 - SD_LP2996A */
{ 106, MODE(3) | PIN_IEN}, /* GPIO0_100 - SOC_INT */
{ 201, MODE(3) | PIN_IEN}, /* GPIO1_26 - GPIO_EXP_INT */
{ 202, MODE(3) }, /* GPIO1_27 - SEL_LCDn_GPIO */
{ 203, MODE(3) | PIN_IEN}, /* GPIO1_28 - SOC_MLB_GPIO2 */
{ 204, MODE(3) | PIN_IEN}, /* GPIO1_29 - SOC_PCIE_WAKEn */
{ 205, MODE(3) | PIN_IEN}, /* GPIO1_30 - BMC_INT1 */
{ 206, MODE(3) | PIN_IEN}, /* GPIO1_31 - HDMI_INTn*/
{ 207, MODE(3) | PIN_IEN}, /* GPIO1_32 - CS2000_AUX_OUT */
{ 208, MODE(3) | PIN_IEN}, /* GPIO1_33 - TEMP_INT */
{ 209, MODE(3) | PIN_IEN}, /* GPIO1_34 - WLAN_IRQ */
{ 216, MODE(3) }, /* GPIO1_41 - FLASH_HOLD */
{ 217, MODE(3) | PIN_IEN}, /* GPIO1_42 - TOUCH_INTn */
/* MLB */
{ 23, MODE(2) }, /* SOC_MLBCLK */
{ 25, MODE(2) }, /* SOC_MLBSIG */
{ 27, MODE(2) }, /* SOC_MLBDAT */
/* DSS */
{ 30, MODE(0) }, /* SOC_DSSDATA23 */
{ 31, MODE(0) }, /* SOC_DSSDATA22 */
{ 32, MODE(0) }, /* SOC_DSSDATA21 */
{ 33, MODE(0) }, /* SOC_DSSDATA20 */
{ 34, MODE(0) }, /* SOC_DSSDATA19 */
{ 35, MODE(0) }, /* SOC_DSSDATA18 */
{ 36, MODE(0) }, /* SOC_DSSDATA17 */
{ 37, MODE(0) }, /* SOC_DSSDATA16 */
{ 38, MODE(0) }, /* SOC_DSSDATA15 */
{ 39, MODE(0) }, /* SOC_DSSDATA14 */
{ 40, MODE(0) }, /* SOC_DSSDATA13 */
{ 41, MODE(0) }, /* SOC_DSSDATA12 */
{ 42, MODE(0) }, /* SOC_DSSDATA11 */
{ 43, MODE(0) }, /* SOC_DSSDATA10 */
{ 44, MODE(0) }, /* SOC_DSSDATA9 */
{ 45, MODE(0) }, /* SOC_DSSDATA8 */
{ 46, MODE(0) }, /* SOC_DSSDATA7 */
{ 47, MODE(0) }, /* SOC_DSSDATA6 */
{ 48, MODE(0) }, /* SOC_DSSDATA5 */
{ 49, MODE(0) }, /* SOC_DSSDATA4 */
{ 50, MODE(0) }, /* SOC_DSSDATA3 */
{ 51, MODE(0) }, /* SOC_DSSDATA2 */
{ 52, MODE(0) }, /* SOC_DSSDATA1 */
{ 53, MODE(0) }, /* SOC_DSSDATA0 */
{ 54, MODE(0) }, /* SOC_DSSVSYNC */
{ 55, MODE(0) }, /* SOC_DSSHSYNC */
{ 56, MODE(0) }, /* SOC_DSSPCLK */
{ 57, MODE(0) }, /* SOC_DSS_DE */
{ 58, MODE(0) }, /* SOC_DSS_FID */
{ 221, MODE(4) }, /* PWM0 - SOC_BACKLIGHT_PWM */
/* MMC1 */
{ 59, MODE(0) }, /* SOC_MMC1_DAT7 */
{ 60, MODE(0) }, /* SOC_MMC1_DAT6 */
{ 61, MODE(0) }, /* SOC_MMC1_DAT5 */
{ 62, MODE(0) }, /* SOC_MMC1_DAT4 */
{ 63, MODE(0) }, /* SOC_MMC1_DAT3 */
{ 64, MODE(0) }, /* SOC_MMC1_DAT2 */
{ 65, MODE(0) }, /* SOC_MMC1_DAT1 */
{ 66, MODE(0) }, /* SOC_MMC1_DAT0 */
{ 67, MODE(0) }, /* SOC_MMC1_CLK */
{ 68, MODE(0) }, /* SOC_MMC1_CMD */
{ 69, MODE(0) }, /* MMC1SDCD TP125 */
{ 70, MODE(0) }, /* SOC_MMC1_SDWP */
{ 71, MODE(0) }, /* MMC1POW TP124 */
/* RGMII */
{ 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */
{ 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */
{ 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */
{ 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */
{ 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */
{ 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */
{ 85, MODE(1) }, /* SOC_RGMII_TXCLK */
{ 91, MODE(1) }, /* SOC_RGMII_TXD3 */
{ 92, MODE(1) }, /* SOC_RGMII_TXD2 */
{ 93, MODE(1) }, /* SOC_RGMII_TXD1 */
{ 94, MODE(1) }, /* SOC_RGMII_TXD0 */
{ 95, MODE(1) }, /* SOC_RGMII_TXCTL */
{ 98, MODE(0) }, /* SOC_MDIO_DATA */
{ 99, MODE(0) }, /* SOC_MDIO_CLK */
/* PWM */
{ 73, MODE(4) }, /* SOC_EHRPWM3A */
{ 74, MODE(4) }, /* SOC_EHRPWM3B */
{ 75, MODE(4) }, /* SOC_EHRPWM3_SYNCI */
{ 76, MODE(4) }, /* SOC_EHRPWM3_SYNCO */
{ 96, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT3 */
{ 198, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT4 */
{ 199, MODE(4) }, /* SOC_EHRPWM4A */
{ 200, MODE(4) }, /* SOC_EHRPWM4B */
{ 218, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT5 */
{ 219, MODE(4) }, /* SOC_EHRPWM5A */
{ 220, MODE(4) }, /* SOC_EHRPWM5B */
{ 222, MODE(4) }, /* SOC_ECAP1_IN_PWM1_OUT */
/* SPI3 */
{ 86, MODE(1) }, /* SOC_SPI3_SCS0 */
{ 88, MODE(1) }, /* SOC_SPI3_CLK */
{ 89, MODE(1) }, /* SOC_SPI3_MISO */
{ 90, MODE(1) }, /* SOC_SPI3_MOSI */
/* CLK */
{ 97, MODE(0) }, /* SMD - TP132 */
/* SPI0 */
{ 100, MODE(0) }, /* SOC_SPI0_SCS0 */
{ 101, MODE(0) }, /* SOC_SPI0_SCS1 */
{ 102, MODE(0) }, /* SOC_SPI0_CLK */
{ 103, MODE(0) }, /* SOC_SPI0_MISO */
{ 104, MODE(0) }, /* SOC_SPI0_MOSI */
/* SPI1 NORFLASH */
{ 105, MODE(0) }, /* SOC_SPI1_SCS0 */
{ 107, MODE(0) }, /* SOC_SPI1_CLK */
{ 108, MODE(0) }, /* SOC_SPI1_MISO */
{ 109, MODE(0) }, /* SOC_SPI1_MOSI */
/* SPI2 */
{ 110, MODE(0) }, /* SOC_SPI2_SCS0 */
{ 111, MODE(1) }, /* SOC_HOUT */
{ 112, MODE(0) }, /* SOC_SPI2_CLK */
{ 113, MODE(0) }, /* SOC_SPI2_MISO */
{ 114, MODE(0) }, /* SOC_SPI2_MOSI */
/* UART0 */
{ 115, MODE(0) }, /* SOC_UART0_RXD */
{ 116, MODE(0) }, /* SOC_UART0_TXD */
{ 117, MODE(0) }, /* SOC_UART0_CTSn */
{ 118, MODE(0) }, /* SOC_UART0_RTSn */
/* UART1 */
{ 119, MODE(0) }, /* SOC_UART1_RXD */
{ 120, MODE(0) }, /* SOC_UART1_TXD */
{ 121, MODE(0) }, /* SOC_UART1_CTSn */
{ 122, MODE(0) }, /* SOC_UART1_RTSn */
/* UART2 */
{ 123, MODE(0) }, /* SOC_UART2_RXD */
{ 124, MODE(0) }, /* SOC_UART2_TXD */
{ 125, MODE(0) }, /* UART0_TXVR_EN */
{ 126, MODE(4) }, /* SOC_CPTS_TS_COMP */
/* DCAN */
{ 127, MODE(0) }, /* SOC_DCAN0_TX */
{ 128, MODE(0) }, /* SOC_DCAN0_RX */
{ 137, MODE(1) }, /* SOC_DCAN1_TX */
{ 138, MODE(1) }, /* SOC_DCAN1_RX */
/* QSPI */
{ 129, MODE(0) }, /* SOC_QSPI_CLK */
{ 130, MODE(0) }, /* SOC_QSPI_RTCLK */
{ 131, MODE(0) }, /* SOC_QSPI_D0 */
{ 132, MODE(0) }, /* SOC_QSPI_D1 */
{ 133, MODE(0) }, /* SOC_QSPI_D2 */
{ 134, MODE(0) }, /* SOC_QSPI_D3 */
{ 135, MODE(0) }, /* SOC_QSPI_CSN0 */
{ 136, MODE(1) }, /* DNI <-> WLAN_SLOW_CLK */
/* MCASP2 */
{ 139, MODE(3) }, /* SOC_MCASP2AXR0 - (GPIO0_108)SOC_LED0 */
{ 140, MODE(4) }, /* SOC_MCASP2AXR1 */
{ 141, MODE(4) }, /* SOC_MCASP2AXR2 */
{ 142, MODE(4) }, /* SOC_MCASP2AXR3 */
{ 143, MODE(4) }, /* SOC_MCASP2AXR4 */
{ 144, MODE(4) }, /* SOC_MCASP2AXR5 */
{ 145, MODE(4) }, /* SOC_McASP2ACLKR */
{ 146, MODE(4) }, /* SOC_McASP2FSR */
{ 147, MODE(4) }, /* SOC_McASP2AHCLKR */
{ 148, MODE(3) }, /* GPIO0_117 - WLAN_TRANS_EN */
{ 149, MODE(4) }, /* SOC_McASP2FSX */
{ 150, MODE(4) }, /* SOC_McASP2AHCLKX */
{ 151, MODE(4) }, /* SOC_McASP2ACLKX */
/* MCASP1 */
{ 152, MODE(4) }, /* SOC_MCASP1ACLKR */
{ 153, MODE(4) }, /* SOC_MCASP1FSR */
{ 154, MODE(4) }, /* SOC_MCASP1AHCLKR */
{ 155, MODE(4) }, /* SOC_MCASP1ACLKX */
{ 156, MODE(4) }, /* SOC_MCASP1FSX */
{ 157, MODE(4) }, /* SOC_MCASP1AHCLKX */
{ 158, MODE(4) }, /* SOC_MCASP1AMUTE */
{ 159, MODE(4) }, /* SOC_MCASP1AXR0 */
{ 160, MODE(4) }, /* SOC_MCASP1AXR1 */
{ 161, MODE(4) }, /* SOC_MCASP1AXR2 */
{ 162, MODE(4) }, /* SOC_MCASP1AXR3 */
{ 163, MODE(4) }, /* SOC_MCASP1AXR4 */
{ 164, MODE(4) }, /* SOC_MCASP1AXR5 */
{ 165, MODE(4) }, /* SOC_MCASP1AXR6 */
{ 166, MODE(4) }, /* SOC_MCASP1AXR7 */
{ 167, MODE(4) }, /* SOC_MCASP1AXR8 */
{ 168, MODE(4) }, /* SOC_MCASP1AXR9 */
/* MCASP0 */
{ 169, MODE(4) }, /* SOC_MCASP0AMUTE */
{ 170, MODE(4) }, /* SOC_MCASP0ACLKR */
{ 171, MODE(4) }, /* SOC_MCASP0FSR */
{ 172, MODE(4) }, /* SOC_MCASP0AHCLKR */
{ 173, MODE(4) }, /* SOC_MCASP0ACLKX */
{ 174, MODE(4) }, /* SOC_MCASP0FSX */
{ 175, MODE(4) }, /* SOC_MCASP0AHCLKX */
{ 176, MODE(4) }, /* SOC_MCASP0AXR0 */
{ 177, MODE(4) }, /* SOC_MCASP0AXR1 */
{ 178, MODE(4) }, /* SOC_MCASP0AXR2 */
{ 179, MODE(4) }, /* SOC_MCASP0AXR3 */
{ 180, MODE(4) }, /* SOC_MCASP0AXR4 */
{ 181, MODE(4) }, /* SOC_MCASP0AXR5 */
{ 182, MODE(4) }, /* SOC_MCASP0AXR6 */
{ 183, MODE(4) }, /* SOC_MCASP0AXR7 */
{ 184, MODE(4) }, /* SOC_MCASP0AXR8 */
{ 185, MODE(4) }, /* SOC_MCASP0AXR9 */
{ 186, MODE(3) }, /* SOC_MCASP0AXR10 - (GPIO1_11)SOC_LED1 */
{ 188, MODE(4) }, /* SOC_MCASP0AXR12 */
{ 189, MODE(4) }, /* SOC_MCASP0AXR13 */
{ 190, MODE(4) }, /* SOC_MCASP0AXR14 */
{ 191, MODE(4) }, /* SOC_MCASP0AXR15 */
/* MMC0 */
{ 192, MODE(2) }, /* SOC_MMC0_DAT3 */
{ 193, MODE(2) }, /* SOC_MMC0_DAT2 */
{ 194, MODE(2) }, /* SOC_MMC0_DAT1 */
{ 195, MODE(2) }, /* SOC_MMC0_DAT0 */
{ 196, MODE(2) }, /* SOC_MMC0_CLK */
{ 197, MODE(2) }, /* SOC_MMC0_CMD */
{ 187, MODE(2) }, /* SOC_MMC0_SDCD */
/* McBSP */
{ 28, MODE(2) | PIN_IEN }, /* SOC_TIMI1 */
{ 29, MODE(2) }, /* SOC_TIMO1 */
{ 210, MODE(2) }, /* SOC_MCBSPDR */
{ 211, MODE(2) }, /* SOC_MCBSPDX */
{ 212, MODE(2) }, /* SOC_MCBSPFSX */
{ 213, MODE(2) }, /* SOC_MCBSPCLKX */
{ 214, MODE(2) }, /* SOC_MCBSPFSR */
{ 215, MODE(2) }, /* SOC_MCBSPCLKR */
/* I2C */
{ 223, MODE(0) }, /* SOC_I2C0_SCL */
{ 224, MODE(0) }, /* SOC_I2C0_SDA */
{ 225, MODE(0) }, /* SOC_I2C1_SCL */
{ 226, MODE(0) }, /* SOC_I2C1_SDA */
{ 227, MODE(0) }, /* SOC_I2C2_SCL */
{ 228, MODE(0) }, /* SOC_I2C2_SDA */
{ 229, MODE(0) }, /* NMIz */
{ 230, MODE(0) }, /* LRESETz */
{ 231, MODE(0) }, /* LRESETNMIENz */
{ 235, MODE(0) },
{ 236, MODE(0) },
{ 237, MODE(0) },
{ 238, MODE(0) },
{ 239, MODE(0) },
{ 240, MODE(0) },
{ 241, MODE(0) },
{ 242, MODE(0) },
{ 243, MODE(0) },
{ 244, MODE(0) },
{ 258, MODE(0) }, /* USB0DRVVBUS */
{ 259, MODE(0) }, /* USB1DRVVBUS */
{ MAX_PIN_N, }
};
void k2g_mux_config(void)
{
configure_pin_mux(k2g_evm_pin_cfg);
}