Kevin/Jibo-Platform-Tools-OLD
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

avionic design with actual uboot and tooling

Browse Source 
submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
u-boot/board/ti/dra7xx/Kconfig Normal file
View File

@@ -0,0 +1,23 @@
if TARGET_DRA7XX_EVM
config SYS_BOARD
default "dra7xx"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "dra7xx_evm"
config CONS_INDEX
int "UART used for console"
range 1 6
default 1
help
The DRA7xx (and AM57x) SoC has a total of 6 UARTs available to it.
Depending on your specific board you may want something other than UART1
here.
source "board/ti/common/Kconfig"
endif

7
u-boot/board/ti/dra7xx/MAINTAINERS Normal file
View File

@@ -0,0 +1,7 @@
DRA7XX BOARD
M: Lokesh Vutla <lokeshvutla@ti.com>
S: Maintained
F: board/ti/dra7xx/
F: include/configs/dra7xx_evm.h
F: configs/dra7xx_evm_defconfig
F: configs/dra7xx_hs_evm_defconfig

8
u-boot/board/ti/dra7xx/Makefile Normal file
View File

@@ -0,0 +1,8 @@
#
# (C) Copyright 2013
# Texas Instruments, <www.ti.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := evm.o

26
u-boot/board/ti/dra7xx/README Normal file
View File

@@ -0,0 +1,26 @@
Summary
=======
This document covers various features of the 'dra7xx_evm' build and some
related uses.
eMMC boot partition use
=======================
It is possible, depending on SYSBOOT configuration to boot from the eMMC
boot partitions using (name depending on documentation referenced)
Alternative Boot operation mode or Boot Sequence Option 1/2. In this
example we load MLO and u-boot.img from the build into DDR and then use
'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
set boot0 as the boot device.
U-Boot # setenv autoload no
U-Boot # usb start
U-Boot # dhcp
U-Boot # mmc dev 1 1
U-Boot # tftp ${loadaddr} dra7xx/MLO
U-Boot # mmc write ${loadaddr} 0 100
U-Boot # tftp ${loadaddr} dra7xx/u-boot.img
U-Boot # mmc write ${loadaddr} 300 400
U-Boot # mmc bootbus 1 2 0 2
U-Boot # mmc partconf 1 1 1 0
U-Boot # mmc rst-function 1 1

836
u-boot/board/ti/dra7xx/evm.c Normal file
View File

@@ -0,0 +1,836 @@
/*
* (C) Copyright 2013
* Texas Instruments Incorporated, <www.ti.com>
*
* Lokesh Vutla <lokeshvutla@ti.com>
*
* Based on previous work by:
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <palmas.h>
#include <sata.h>
#include <linux/string.h>
#include <asm/gpio.h>
#include <usb.h>
#include <linux/usb/gadget.h>
#include <asm/arch/gpio.h>
#include <asm/arch/dra7xx_iodelay.h>
#include <asm/emif.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
#include <environment.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>
#include <miiphy.h>
#include "mux_data.h"
#include "../common/board_detect.h"
#define board_is_dra74x_evm() board_ti_is("5777xCPU")
#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \
(strncmp("H", board_ti_get_rev(), 1) <= 0)
#define board_is_dra72x_revc_or_later() board_is_dra72x_evm() && \
(strncmp("C", board_ti_get_rev(), 1) <= 0)
#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
board_ti_get_emif2_size()
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* GPIO 7_11 */
#define GPIO_DDR_VTT_EN 203
#define SYSINFO_BOARD_NAME_MAX_LEN 37
const struct omap_sysinfo sysinfo = {
"Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
};
static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x427F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x427F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x0000514C,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD113781C,
.sdram_tim2 = 0x30717FE3,
.sdram_tim3 = 0x409F86A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400D,
.emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
.emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
.sdram_config_init = 0x61862BB2,
.sdram_config = 0x61862BB2,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x0000514D,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD1137824,
.sdram_tim2 = 0x30B37FE3,
.sdram_tim3 = 0x409F8AD8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0824400E,
.emif_ddr_phy_ctlr_1 = 0x0E24400E,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
.emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
.emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
.emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x30BF7FDA,
.sdram_tim3 = 0x427F8BA8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x427F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
u64 ram_size;
ram_size = board_ti_get_emif_size();
switch (omap_revision()) {
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
switch (emif_nr) {
case 1:
if (ram_size > CONFIG_MAX_MEM_MAPPED)
*regs = &emif1_ddr3_532_mhz_1cs_2G;
else
*regs = &emif1_ddr3_532_mhz_1cs;
break;
case 2:
if (ram_size > CONFIG_MAX_MEM_MAPPED)
*regs = &emif2_ddr3_532_mhz_1cs_2G;
else
*regs = &emif2_ddr3_532_mhz_1cs;
break;
}
break;
case DRA722_ES1_0:
case DRA722_ES2_0:
if (ram_size < CONFIG_MAX_MEM_MAPPED)
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
else
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
break;
default:
*regs = &emif1_ddr3_532_mhz_1cs;
}
}
static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x80640300,
.dmm_lisa_map_2 = 0xC0500220,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80600100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80740300,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
/*
* DRA722 EVM EMIF1 2GB CONFIGURATION
* EMIF1 4 devices of 512Mb x 8 Micron
*/
const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80700100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
u64 ram_size;
ram_size = board_ti_get_emif_size();
switch (omap_revision()) {
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
if (ram_size > CONFIG_MAX_MEM_MAPPED)
*dmm_lisa_regs = &lisa_map_dra7_2GB;
else
*dmm_lisa_regs = &lisa_map_dra7_1536MB;
break;
case DRA722_ES1_0:
case DRA722_ES2_0:
default:
if (ram_size < CONFIG_MAX_MEM_MAPPED)
*dmm_lisa_regs = &lisa_map_2G_x_2;
else
*dmm_lisa_regs = &lisa_map_2G_x_4;
break;
}
}
struct vcores_data dra752_volts = {
.mpu.value = VDD_MPU_DRA7,
.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.eve.value = VDD_EVE_DRA7,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value = VDD_GPU_DRA7,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value = VDD_CORE_DRA7,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
.iva.value = VDD_IVA_DRA7,
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
struct vcores_data dra722_volts = {
.mpu.value = VDD_MPU_DRA7,
.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.core.value = VDD_CORE_DRA7,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS65917_REG_ADDR_SMPS2,
.core.pmic = &tps659038,
/*
* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
*/
.gpu.value = VDD_GPU_DRA7,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.eve.value = VDD_EVE_DRA7,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.iva.value = VDD_IVA_DRA7,
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
/**
* @brief board_init
*
* @return 0
*/
int board_init(void)
{
gpmc_init();
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
return 0;
}
void dram_init_banksize(void)
{
u64 ram_size;
ram_size = board_ti_get_emif_size();
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
if (ram_size > CONFIG_MAX_MEM_MAPPED) {
gd->bd->bi_dram[1].start = 0x200000000;
gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
}
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
char *name = "unknown";
if (is_dra72x()) {
if (board_is_dra72x_revc_or_later())
name = "dra72x-revc";
else
name = "dra72x";
} else {
name = "dra7xx";
}
set_board_info_env(name);
omap_die_id_serial();
#endif
return 0;
}
#ifdef CONFIG_SPL_BUILD
void do_board_detect(void)
{
int rc;
rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (rc)
printf("ti_i2c_eeprom_init failed %d\n", rc);
}
#else
void do_board_detect(void)
{
char *bname = NULL;
int rc;
rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (rc)
printf("ti_i2c_eeprom_init failed %d\n", rc);
if (board_is_dra74x_evm()) {
bname = "DRA74x EVM";
} else if (board_is_dra72x_evm()) {
bname = "DRA72x EVM";
} else {
/* If EEPROM is not populated */
if (is_dra72x())
bname = "DRA72x EVM";
else
bname = "DRA74x EVM";
}
if (bname)
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
"Board: %s REV %s\n", bname, board_ti_get_rev());
}
#endif /* CONFIG_SPL_BUILD */
void vcores_init(void)
{
if (board_is_dra74x_evm()) {
*omap_vcores = &dra752_volts;
} else if (board_is_dra72x_evm()) {
*omap_vcores = &dra722_volts;
} else {
/* If EEPROM is not populated */
if (is_dra72x())
*omap_vcores = &dra722_volts;
else
*omap_vcores = &dra752_volts;
}
}
void set_muxconf_regs(void)
{
do_set_mux32((*ctrl)->control_padconf_core_base,
early_padconf, ARRAY_SIZE(early_padconf));
}
#ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void)
{
struct pad_conf_entry const *pads, *delta_pads = NULL;
struct iodelay_cfg_entry const *iodelay;
int npads, niodelays, delta_npads = 0;
int ret;
switch (omap_revision()) {
case DRA722_ES1_0:
case DRA722_ES2_0:
pads = dra72x_core_padconf_array_common;
npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
if (board_is_dra72x_revc_or_later()) {
delta_pads = dra72x_rgmii_padconf_array_revc;
delta_npads =
ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
iodelay = dra72_iodelay_cfg_array_revc;
niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
} else {
delta_pads = dra72x_rgmii_padconf_array_revb;
delta_npads =
ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
iodelay = dra72_iodelay_cfg_array_revb;
niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
}
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
pads = dra74x_core_padconf_array;
npads = ARRAY_SIZE(dra74x_core_padconf_array);
iodelay = dra742_es1_1_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
break;
default:
case DRA752_ES2_0:
pads = dra74x_core_padconf_array;
npads = ARRAY_SIZE(dra74x_core_padconf_array);
iodelay = dra742_es2_0_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
/* Setup port1 and port2 for rgmii with 'no-id' mode */
clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
RGMII1_ID_MODE_N_MASK);
break;
}
/* Setup I/O isolation */
ret = __recalibrate_iodelay_start();
if (ret)
goto err;
/* Do the muxing here */
do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
/* Now do the weird minor deltas that should be safe */
if (delta_npads)
do_set_mux32((*ctrl)->control_padconf_core_base,
delta_pads, delta_npads);
/* Setup IOdelay configuration */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
err:
/* Closeup.. remove isolation */
__recalibrate_iodelay_end(ret);
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
#endif
#ifdef CONFIG_USB_DWC3
static struct dwc3_device usb_otg_ss1 = {
.maximum_speed = USB_SPEED_SUPER,
.base = DRA7_USB_OTG_SS1_BASE,
.tx_fifo_resize = false,
.index = 0,
};
static struct dwc3_omap_device usb_otg_ss1_glue = {
.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
.index = 0,
};
static struct ti_usb_phy_device usb_phy1_device = {
.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
.index = 0,
};
static struct dwc3_device usb_otg_ss2 = {
.maximum_speed = USB_SPEED_SUPER,
.base = DRA7_USB_OTG_SS2_BASE,
.tx_fifo_resize = false,
.index = 1,
};
static struct dwc3_omap_device usb_otg_ss2_glue = {
.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
.index = 1,
};
static struct ti_usb_phy_device usb_phy2_device = {
.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
.index = 1,
};
int board_usb_init(int index, enum usb_init_type init)
{
enable_usb_clocks(index);
switch (index) {
case 0:
if (init == USB_INIT_DEVICE) {
usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
} else {
usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
}
ti_usb_phy_uboot_init(&usb_phy1_device);
dwc3_omap_uboot_init(&usb_otg_ss1_glue);
dwc3_uboot_init(&usb_otg_ss1);
break;
case 1:
if (init == USB_INIT_DEVICE) {
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
} else {
usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
}
ti_usb_phy_uboot_init(&usb_phy2_device);
dwc3_omap_uboot_init(&usb_otg_ss2_glue);
dwc3_uboot_init(&usb_otg_ss2);
break;
default:
printf("Invalid Controller Index\n");
}
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
switch (index) {
case 0:
case 1:
ti_usb_phy_uboot_exit(index);
dwc3_uboot_exit(index);
dwc3_omap_uboot_exit(index);
break;
default:
printf("Invalid Controller Index\n");
}
disable_usb_clocks(index);
return 0;
}
int usb_gadget_handle_interrupts(int index)
{
u32 status;
status = dwc3_omap_uboot_interrupt_status(index);
if (status)
dwc3_uboot_handle_interrupt(index);
return 0;
}
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
#ifdef CONFIG_SPL_ENV_SUPPORT
env_init();
env_relocate_spec();
if (getenv_yesno("boot_os") != 1)
return 1;
#endif
return 0;
}
#endif
#ifdef CONFIG_DRIVER_TI_CPSW
extern u32 *const omap_si_rev;
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 2,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 3,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 2,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
int board_eth_init(bd_t *bis)
{
int ret;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
uint32_t ctrl_val;
/* try reading mac address from efuse */
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = mac_hi & 0xFF;
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
mac_addr[5] = mac_lo & 0xFF;
if (!getenv("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = mac_hi & 0xFF;
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
mac_addr[5] = mac_lo & 0xFF;
if (!getenv("eth1addr")) {
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("eth1addr", mac_addr);
}
ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
if (*omap_si_rev == DRA722_ES1_0)
cpsw_data.active_slave = 1;
if (board_is_dra72x_revc_or_later()) {
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
}
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
return ret;
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
/* VTT regulator enable */
static inline void vtt_regulator_enable(void)
{
if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
return;
/* Do not enable VTT for DRA722 */
if (is_dra72x())
return;
/*
* EVM Rev G and later use gpio7_11 for DDR3 termination.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
int board_early_init_f(void)
{
vtt_regulator_enable();
return 0;
}
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (is_dra72x() && !strcmp(name, "dra72-evm"))
return 0;
else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
return 0;
else
return -1;
}
#endif

606
u-boot/board/ti/dra7xx/mux_data.h Normal file
View File

@@ -0,0 +1,606 @@
/*
* (C) Copyright 2013
* Texas Instruments Incorporated, <www.ti.com>
*
* Sricharan R <r.sricharan@ti.com>
* Nishant Kamat <nskamat@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _MUX_DATA_DRA7XX_H_
#define _MUX_DATA_DRA7XX_H_
#include <asm/arch/mux_dra7xx.h>
const struct pad_conf_entry dra72x_core_padconf_array_common[] = {
{GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
{GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
{GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
{GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
{GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
{GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
{GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
{GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
{GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
{GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
{GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
{GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
{GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
{GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
{GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
{GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
{GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
{GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
{GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
{GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
{GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
{GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
{GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
{GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
{GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
{GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
{GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
{GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
{GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
{GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
{GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
{GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
{GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
{GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
{GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
{GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
{GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
{VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_clk0.vin2a_clk0 */
{VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_hsync0.vin2a_hsync0 */
{VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_vsync0.vin2a_vsync0 */
{VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d0.vin2a_d0 */
{VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d1.vin2a_d1 */
{VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d2.vin2a_d2 */
{VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d3.vin2a_d3 */
{VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d4.vin2a_d4 */
{VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d5.vin2a_d5 */
{VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d6.vin2a_d6 */
{VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d7.vin2a_d7 */
{VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d8.vin2a_d8 */
{VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d9.vin2a_d9 */
{VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d10.vin2a_d10 */
{VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d11.vin2a_d11 */
{VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
{VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
{VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
{VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
{VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
{VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
{VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
{VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
{VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
{VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
{VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
{VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
{VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
{VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
{VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
{VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
{VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
{VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
{VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
{VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
{VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
{VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
{VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
{VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
{GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
{GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
{GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
{MCASP1_AXR0, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr0.i2c5_sda */
{MCASP1_AXR1, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.i2c5_scl */
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
{SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
{SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
{SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
{SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
{DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
{DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
{UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
{UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
{UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rxd.mmc4_dat0 */
{UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
{UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
{WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
{WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
};
const struct pad_conf_entry dra72x_rgmii_padconf_array_revb[] = {
{GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
{RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
{RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
{RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
{RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
{RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
{RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
{RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
{RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
{RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
{RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
{RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
{RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
{VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */
{VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */
{VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */
{VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */
{VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */
{VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */
{VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */
{VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */
{VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */
{VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */
{VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */
{VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */
{XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */
{XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */
};
const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = {
{VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
{RGMII0_TXC, (M0 | PIN_OUTPUT)}, /* rgmii0_txc.rgmii0_txc */
{RGMII0_TXCTL, (M0 | PIN_OUTPUT)}, /* rgmii0_txctl.rgmii0_txctl */
{RGMII0_TXD3, (M0 | PIN_OUTPUT)}, /* rgmii0_txd3.rgmii0_txd3 */
{RGMII0_TXD2, (M0 | PIN_OUTPUT)}, /* rgmii0_txd2.rgmii0_txd2 */
{RGMII0_TXD1, (M0 | PIN_OUTPUT)}, /* rgmii0_txd1.rgmii0_txd1 */
{RGMII0_TXD0, (M0 | PIN_OUTPUT)}, /* rgmii0_txd0.rgmii0_txd0 */
{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxc.rgmii0_rxc */
{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxctl.rgmii0_rxctl */
{RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd3.rgmii0_rxd3 */
{RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd2.rgmii0_rxd2 */
{RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd1.rgmii0_rxd1 */
{RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd0.rgmii0_rxd0 */
{VIN2A_D12, (M3 | PIN_OUTPUT)}, /* vin2a_d12.rgmii1_txc */
{VIN2A_D13, (M3 | PIN_OUTPUT)}, /* vin2a_d13.rgmii1_txctl */
{VIN2A_D14, (M3 | PIN_OUTPUT)}, /* vin2a_d14.rgmii1_txd3 */
{VIN2A_D15, (M3 | PIN_OUTPUT)}, /* vin2a_d15.rgmii1_txd2 */
{VIN2A_D16, (M3 | PIN_OUTPUT)}, /* vin2a_d16.rgmii1_txd1 */
{VIN2A_D17, (M3 | PIN_OUTPUT)}, /* vin2a_d17.rgmii1_txd0 */
{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d18.rgmii1_rxc */
{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d19.rgmii1_rxctl */
{VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d20.rgmii1_rxd3 */
{VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d21.rgmii1_rxd2 */
{VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d22.rgmii1_rxd1 */
{VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d23.rgmii1_rxd0 */
{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
};
const struct pad_conf_entry early_padconf[] = {
#if (CONFIG_CONS_INDEX == 1)
{UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
{UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */
#elif (CONFIG_CONS_INDEX == 3)
{UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */
{UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */
#endif
{I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */
{I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */
};
#ifdef CONFIG_IODELAY_RECALIBRATION
const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revb[] = {
{0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
{0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
{0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
{0x714, 196, 1522}, /* RGMMI0_RXD1_IN */
{0x720, 40, 1860}, /* RGMMI0_RXD2_IN */
{0x72C, 0, 1956}, /* RGMMI0_RXD3_IN */
{0x740, 0, 220}, /* RGMMI0_TXC_OUT */
{0x74C, 1820, 180}, /* RGMMI0_TXCTL_OUT */
{0x758, 1740, 440}, /* RGMMI0_TXD0_OUT */
{0x764, 1740, 240}, /* RGMMI0_TXD1_OUT */
{0x770, 1680, 380}, /* RGMMI0_TXD2_OUT */
{0x77C, 1740, 440}, /* RGMMI0_TXD3_OUT */
/* These values are for using RGMII1 configuration on VIN2a_x pins. */
{0xAB0, 596, 0}, /* CFG_VIN2A_D18_IN */
{0xABC, 314, 980}, /* CFG_VIN2A_D19_IN */
{0xAD4, 241, 1536}, /* CFG_VIN2A_D20_IN */
{0xAE0, 103, 1689}, /* CFG_VIN2A_D21_IN */
{0xAEC, 161, 1563}, /* CFG_VIN2A_D22_IN */
{0xAF8, 0, 1613}, /* CFG_VIN2A_D23_IN */
{0xA70, 0, 200}, /* CFG_VIN2A_D12_OUT */
{0xA7C, 1560, 140}, /* CFG_VIN2A_D13_OUT */
{0xA88, 1700, 0}, /* CFG_VIN2A_D14_OUT */
{0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */
{0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */
{0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */
{0x144, 0, 0}, /* CFG_GPMC_A13_IN */
{0x150, 2062, 2277}, /* CFG_GPMC_A14_IN */
{0x15C, 1960, 2289}, /* CFG_GPMC_A15_IN */
{0x168, 2058, 2386}, /* CFG_GPMC_A16_IN */
{0x170, 0, 0 }, /* CFG_GPMC_A16_OUT */
{0x174, 2062, 2350}, /* CFG_GPMC_A17_IN */
{0x188, 0, 0}, /* CFG_GPMC_A18_OUT */
{0x374, 121, 0}, /* CFG_GPMC_CS2_OUT */
};
const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revc[] = {
{0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
{0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
{0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
{0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
{0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
{0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
{0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
};
#endif
const struct pad_conf_entry dra74x_core_padconf_array[] = {
{GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
{GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
{GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
{GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
{GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
{GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
{GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
{GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
{GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
{GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
{GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
{GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
{GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
{GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
{GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
{GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
{GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
{GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
{GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
{GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
{GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
{GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
{GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
{GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
{GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
{GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
{GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
{GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
{GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
{GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
{GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
{GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
{GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
{GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
{GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
{GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
{GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
{VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */
{VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */
{VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_fld0.vin1a_fld0 */
{VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_hsync0.vin1a_hsync0 */
{VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_vsync0.vin1a_vsync0 */
{VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d0.vin1a_d0 */
{VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d1.vin1a_d1 */
{VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d2.vin1a_d2 */
{VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d3.vin1a_d3 */
{VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d4.vin1a_d4 */
{VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d5.vin1a_d5 */
{VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d6.vin1a_d6 */
{VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d7.vin1a_d7 */
{VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d8.vin1a_d8 */
{VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d9.vin1a_d9 */
{VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d10.vin1a_d10 */
{VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d11.vin1a_d11 */
{VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d12.vin1a_d12 */
{VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d13.vin1a_d13 */
{VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d14.vin1a_d14 */
{VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d15.vin1a_d15 */
{VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d16.vin1a_d16 */
{VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d17.vin1a_d17 */
{VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d18.vin1a_d18 */
{VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d19.vin1a_d19 */
{VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d20.vin1a_d20 */
{VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d21.vin1a_d21 */
{VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d22.vin1a_d22 */
{VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d23.vin1a_d23 */
{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
{VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
{VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
{VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
{VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
{VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
{VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
{VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
{VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
{VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
{VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
{VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
{VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
{VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
{VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
{VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
{VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
{VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
{VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
{VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
{VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
{VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
{VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
{VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
{VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
{VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
{VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
{VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
{VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
{VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
{VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
{VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
{RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
{RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
{RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
{RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
{GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
{GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
{GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
{MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.mcasp1_aclkx */
{MCASP1_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.mcasp1_fsx */
{MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp1_axr0.mcasp1_axr0 */
{MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.mcasp1_axr1 */
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
{GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
{SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
{SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
{SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
{SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
{DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
{DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
{UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
{UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
{UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
{UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
{UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
{I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */
{I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */
{WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
{WAKEUP2, (M14)}, /* Wakeup2.gpio1_2 */
};
#ifdef CONFIG_IODELAY_RECALIBRATION
const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
{0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
{0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
{0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
{0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
{0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
{0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
{0x0740, 0, 0}, /* CFG_RGMII0_TXC_OUT */
{0x074C, 1560, 120}, /* CFG_RGMII0_TXCTL_OUT */
{0x0758, 1570, 120}, /* CFG_RGMII0_TXD0_OUT */
{0x0764, 1500, 120}, /* CFG_RGMII0_TXD1_OUT */
{0x0770, 1775, 120}, /* CFG_RGMII0_TXD2_OUT */
{0x077C, 1875, 120}, /* CFG_RGMII0_TXD3_OUT */
{0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
{0x08DC, 2600, 0}, /* CFG_VIN1A_D0_IN */
{0x08E8, 2652, 46}, /* CFG_VIN1A_D10_IN */
{0x08F4, 2541, 0}, /* CFG_VIN1A_D11_IN */
{0x0900, 2603, 574}, /* CFG_VIN1A_D12_IN */
{0x090C, 2548, 443}, /* CFG_VIN1A_D13_IN */
{0x0918, 2624, 598}, /* CFG_VIN1A_D14_IN */
{0x0924, 2535, 1027}, /* CFG_VIN1A_D15_IN */
{0x0930, 2526, 818}, /* CFG_VIN1A_D16_IN */
{0x093C, 2623, 797}, /* CFG_VIN1A_D17_IN */
{0x0948, 2578, 888}, /* CFG_VIN1A_D18_IN */
{0x0954, 2574, 1008}, /* CFG_VIN1A_D19_IN */
{0x0960, 2527, 123}, /* CFG_VIN1A_D1_IN */
{0x096C, 2577, 737}, /* CFG_VIN1A_D20_IN */
{0x0978, 2627, 616}, /* CFG_VIN1A_D21_IN */
{0x0984, 2573, 777}, /* CFG_VIN1A_D22_IN */
{0x0990, 2730, 67}, /* CFG_VIN1A_D23_IN */
{0x099C, 2509, 303}, /* CFG_VIN1A_D2_IN */
{0x09A8, 2494, 267}, /* CFG_VIN1A_D3_IN */
{0x09B4, 2474, 0}, /* CFG_VIN1A_D4_IN */
{0x09C0, 2556, 181}, /* CFG_VIN1A_D5_IN */
{0x09CC, 2516, 195}, /* CFG_VIN1A_D6_IN */
{0x09D8, 2589, 210}, /* CFG_VIN1A_D7_IN */
{0x09E4, 2624, 75}, /* CFG_VIN1A_D8_IN */
{0x09F0, 2704, 14}, /* CFG_VIN1A_D9_IN */
{0x09FC, 2469, 55}, /* CFG_VIN1A_DE0_IN */
{0x0A08, 2557, 264}, /* CFG_VIN1A_FLD0_IN */
{0x0A14, 2465, 269}, /* CFG_VIN1A_HSYNC0_IN */
{0x0A20, 2411, 348}, /* CFG_VIN1A_VSYNC0_IN */
{0x0A70, 150, 0}, /* CFG_VIN2A_D12_OUT */
{0x0A7C, 1500, 0}, /* CFG_VIN2A_D13_OUT */
{0x0A88, 1600, 0}, /* CFG_VIN2A_D14_OUT */
{0x0A94, 900, 0}, /* CFG_VIN2A_D15_OUT */
{0x0AA0, 680, 0}, /* CFG_VIN2A_D16_OUT */
{0x0AAC, 500, 0}, /* CFG_VIN2A_D17_OUT */
{0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
{0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
{0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
{0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
{0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
{0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
{0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
{0x0150, 1976, 1389}, /* CFG_GPMC_A14_IN */
{0x015C, 1872, 1408}, /* CFG_GPMC_A15_IN */
{0x0168, 1914, 1506}, /* CFG_GPMC_A16_IN */
{0x0170, 57, 0}, /* CFG_GPMC_A16_OUT */
{0x0174, 1904, 1471}, /* CFG_GPMC_A17_IN */
{0x0188, 1690, 0}, /* CFG_GPMC_A18_OUT */
{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
};
const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
{0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */
{0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */
{0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */
{0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */
{0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */
{0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */
{0x0740, 70, 70}, /* CFG_RGMII0_TXC_OUT */
{0x074C, 35, 70}, /* CFG_RGMII0_TXCTL_OUT */
{0x0758, 100, 130}, /* CFG_RGMII0_TXD0_OUT */
{0x0764, 0, 70}, /* CFG_RGMII0_TXD1_OUT */
{0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
{0x077C, 100, 130}, /* CFG_RGMII0_TXD3_OUT */
{0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
{0x08DC, 2105, 619}, /* CFG_VIN1A_D0_IN */
{0x08E8, 2107, 739}, /* CFG_VIN1A_D10_IN */
{0x08F4, 2005, 788}, /* CFG_VIN1A_D11_IN */
{0x0900, 2059, 1297}, /* CFG_VIN1A_D12_IN */
{0x090C, 2027, 1141}, /* CFG_VIN1A_D13_IN */
{0x0918, 2071, 1332}, /* CFG_VIN1A_D14_IN */
{0x0924, 1995, 1764}, /* CFG_VIN1A_D15_IN */
{0x0930, 1999, 1542}, /* CFG_VIN1A_D16_IN */
{0x093C, 2072, 1540}, /* CFG_VIN1A_D17_IN */
{0x0948, 2034, 1629}, /* CFG_VIN1A_D18_IN */
{0x0954, 2026, 1761}, /* CFG_VIN1A_D19_IN */
{0x0960, 2017, 757}, /* CFG_VIN1A_D1_IN */
{0x096C, 2037, 1469}, /* CFG_VIN1A_D20_IN */
{0x0978, 2077, 1349}, /* CFG_VIN1A_D21_IN */
{0x0984, 2022, 1545}, /* CFG_VIN1A_D22_IN */
{0x0990, 2168, 784}, /* CFG_VIN1A_D23_IN */
{0x099C, 1996, 962}, /* CFG_VIN1A_D2_IN */
{0x09A8, 1993, 901}, /* CFG_VIN1A_D3_IN */
{0x09B4, 2098, 499}, /* CFG_VIN1A_D4_IN */
{0x09C0, 2038, 844}, /* CFG_VIN1A_D5_IN */
{0x09CC, 2002, 863}, /* CFG_VIN1A_D6_IN */
{0x09D8, 2063, 873}, /* CFG_VIN1A_D7_IN */
{0x09E4, 2088, 759}, /* CFG_VIN1A_D8_IN */
{0x09F0, 2152, 701}, /* CFG_VIN1A_D9_IN */
{0x09FC, 1926, 728}, /* CFG_VIN1A_DE0_IN */
{0x0A08, 2043, 937}, /* CFG_VIN1A_FLD0_IN */
{0x0A14, 1978, 909}, /* CFG_VIN1A_HSYNC0_IN */
{0x0A20, 1926, 987}, /* CFG_VIN1A_VSYNC0_IN */
{0x0A70, 140, 0}, /* CFG_VIN2A_D12_OUT */
{0x0A7C, 90, 70}, /* CFG_VIN2A_D13_OUT */
{0x0A88, 0, 0}, /* CFG_VIN2A_D14_OUT */
{0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
{0x0AA0, 0, 70}, /* CFG_VIN2A_D16_OUT */
{0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
{0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */
{0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */
{0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */
{0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */
{0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */
{0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */
{0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
{0x0150, 2575, 966}, /* CFG_GPMC_A14_IN */
{0x015C, 2503, 889}, /* CFG_GPMC_A15_IN */
{0x0168, 2528, 1007}, /* CFG_GPMC_A16_IN */
{0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
{0x0174, 2533, 980}, /* CFG_GPMC_A17_IN */
{0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */
{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
};
#endif
#endif /* _MUX_DATA_DRA7XX_H_ */