avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
23
u-boot/board/ti/am57xx/Kconfig
Normal file
23
u-boot/board/ti/am57xx/Kconfig
Normal file
@@ -0,0 +1,23 @@
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if TARGET_AM57XX_EVM
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config SYS_BOARD
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default "am57xx"
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config SYS_VENDOR
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default "ti"
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config SYS_CONFIG_NAME
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default "am57xx_evm"
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config CONS_INDEX
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int "UART used for console"
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range 1 6
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default 3
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help
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The AM57x (and DRA7xx) SoC has a total of 6 UARTs available to it.
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Depending on your specific board you may want something other than UART3
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here.
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source "board/ti/common/Kconfig"
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endif
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7
u-boot/board/ti/am57xx/MAINTAINERS
Normal file
7
u-boot/board/ti/am57xx/MAINTAINERS
Normal file
@@ -0,0 +1,7 @@
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AM57XX EVM
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M: Felipe Balbi <balbi@ti.com>
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S: Maintained
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F: board/ti/am57xx/
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F: include/configs/am57xx_evm.h
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F: configs/am57xx_evm_defconfig
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F: configs/am57xx_evm_nodt_defconfig
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8
u-boot/board/ti/am57xx/Makefile
Normal file
8
u-boot/board/ti/am57xx/Makefile
Normal file
@@ -0,0 +1,8 @@
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#
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# (C) Copyright 2014
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# Texas Instruments, <www.ti.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := board.o
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752
u-boot/board/ti/am57xx/board.c
Normal file
752
u-boot/board/ti/am57xx/board.c
Normal file
@@ -0,0 +1,752 @@
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/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
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*
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* Author: Felipe Balbi <balbi@ti.com>
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*
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* Based on board/ti/dra7xx/evm.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <palmas.h>
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#include <sata.h>
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#include <usb.h>
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#include <asm/omap_common.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dra7xx_iodelay.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sata.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/omap.h>
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#include <environment.h>
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#include <usb.h>
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#include <linux/usb/gadget.h>
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#include <dwc3-uboot.h>
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#include <dwc3-omap-uboot.h>
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#include <ti-usb-phy-uboot.h>
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#include "../common/board_detect.h"
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#include "mux_data.h"
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#define board_is_x15() board_ti_is("BBRDX15_")
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#define board_is_am572x_evm() board_ti_is("AM572PM_")
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#define board_is_am572x_idk() board_ti_is("AM572IDK")
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#ifdef CONFIG_DRIVER_TI_CPSW
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#include <cpsw.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* GPIO 7_11 */
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#define GPIO_DDR_VTT_EN 203
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#define SYSINFO_BOARD_NAME_MAX_LEN 45
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const struct omap_sysinfo sysinfo = {
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"Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
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};
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static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
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.dmm_lisa_map_3 = 0x80740300,
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.is_ma_present = 0x1
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};
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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{
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*dmm_lisa_regs = &beagle_x15_lisa_regs;
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}
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static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
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.sdram_config_init = 0x61851b32,
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.sdram_config = 0x61851b32,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xcccf36ab,
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.sdram_tim2 = 0x308f7fda,
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.sdram_tim3 = 0x409f88a8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x5007190b,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400b,
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.emif_ddr_phy_ctlr_1 = 0x0e24400b,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
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.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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/* Ext phy ctrl regs 1-35 */
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static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
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0x10040100,
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0x00910091,
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0x00950095,
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0x009B009B,
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0x009E009E,
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0x00980098,
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0x00340034,
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0x00350035,
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0x00340034,
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0x00310031,
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0x00340034,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x00480048,
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0x004A004A,
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0x00520052,
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0x00550055,
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0x00500050,
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0x00000000,
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0x00600020,
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0x40011080,
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0x08102040,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0
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};
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static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
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.sdram_config_init = 0x61851b32,
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.sdram_config = 0x61851b32,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xcccf36b3,
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.sdram_tim2 = 0x308f7fda,
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.sdram_tim3 = 0x407f88a8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x5007190b,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400b,
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.emif_ddr_phy_ctlr_1 = 0x0e24400b,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
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.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
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0x10040100,
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0x00910091,
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0x00950095,
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0x009B009B,
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0x009E009E,
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||||
0x00980098,
|
||||
0x00340034,
|
||||
0x00350035,
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||||
0x00340034,
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||||
0x00310031,
|
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0x00340034,
|
||||
0x007F007F,
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||||
0x007F007F,
|
||||
0x007F007F,
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||||
0x007F007F,
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||||
0x007F007F,
|
||||
0x00480048,
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||||
0x004A004A,
|
||||
0x00520052,
|
||||
0x00550055,
|
||||
0x00500050,
|
||||
0x00000000,
|
||||
0x00600020,
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||||
0x40011080,
|
||||
0x08102040,
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||||
0x0,
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||||
0x0,
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||||
0x0,
|
||||
0x0,
|
||||
0x0,
|
||||
0x0,
|
||||
0x0,
|
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0x0,
|
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0x0,
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0x0
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};
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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{
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switch (emif_nr) {
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case 1:
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*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
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break;
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case 2:
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*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
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||||
break;
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||||
}
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}
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void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
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{
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switch (emif_nr) {
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case 1:
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*regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
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||||
*size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
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break;
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||||
case 2:
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*regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
|
||||
*size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
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break;
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}
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||||
}
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||||
|
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struct vcores_data beagle_x15_volts = {
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.mpu.value = VDD_MPU_DRA7,
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.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
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.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
||||
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
|
||||
.mpu.pmic = &tps659038,
|
||||
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
|
||||
|
||||
.eve.value = VDD_EVE_DRA7,
|
||||
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
|
||||
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
||||
.eve.addr = TPS659038_REG_ADDR_SMPS45,
|
||||
.eve.pmic = &tps659038,
|
||||
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
|
||||
|
||||
.gpu.value = VDD_GPU_DRA7,
|
||||
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
|
||||
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
||||
.gpu.addr = TPS659038_REG_ADDR_SMPS45,
|
||||
.gpu.pmic = &tps659038,
|
||||
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
|
||||
|
||||
.core.value = VDD_CORE_DRA7,
|
||||
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
|
||||
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
||||
.core.addr = TPS659038_REG_ADDR_SMPS6,
|
||||
.core.pmic = &tps659038,
|
||||
|
||||
.iva.value = VDD_IVA_DRA7,
|
||||
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
|
||||
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
||||
.iva.addr = TPS659038_REG_ADDR_SMPS45,
|
||||
.iva.pmic = &tps659038,
|
||||
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
|
||||
};
|
||||
|
||||
struct vcores_data am572x_idk_volts = {
|
||||
.mpu.value = VDD_MPU_DRA7,
|
||||
.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
|
||||
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
||||
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
|
||||
.mpu.pmic = &tps659038,
|
||||
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
|
||||
|
||||
.eve.value = VDD_EVE_DRA7,
|
||||
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
|
||||
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
||||
.eve.addr = TPS659038_REG_ADDR_SMPS45,
|
||||
.eve.pmic = &tps659038,
|
||||
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
|
||||
|
||||
.gpu.value = VDD_GPU_DRA7,
|
||||
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
|
||||
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
||||
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
|
||||
.gpu.pmic = &tps659038,
|
||||
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
|
||||
|
||||
.core.value = VDD_CORE_DRA7,
|
||||
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
|
||||
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
||||
.core.addr = TPS659038_REG_ADDR_SMPS7,
|
||||
.core.pmic = &tps659038,
|
||||
|
||||
.iva.value = VDD_IVA_DRA7,
|
||||
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
|
||||
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
||||
.iva.addr = TPS659038_REG_ADDR_SMPS8,
|
||||
.iva.pmic = &tps659038,
|
||||
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/* No env to setup for SPL */
|
||||
static inline void setup_board_eeprom_env(void) { }
|
||||
|
||||
/* Override function to read eeprom information */
|
||||
void do_board_detect(void)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
|
||||
CONFIG_EEPROM_CHIP_ADDRESS);
|
||||
if (rc)
|
||||
printf("ti_i2c_eeprom_init failed %d\n", rc);
|
||||
}
|
||||
|
||||
#else /* CONFIG_SPL_BUILD */
|
||||
|
||||
/* Override function to read eeprom information: actual i2c read done by SPL*/
|
||||
void do_board_detect(void)
|
||||
{
|
||||
char *bname = NULL;
|
||||
int rc;
|
||||
|
||||
rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
|
||||
CONFIG_EEPROM_CHIP_ADDRESS);
|
||||
if (rc)
|
||||
printf("ti_i2c_eeprom_init failed %d\n", rc);
|
||||
|
||||
if (board_is_x15())
|
||||
bname = "BeagleBoard X15";
|
||||
else if (board_is_am572x_evm())
|
||||
bname = "AM572x EVM";
|
||||
else if (board_is_am572x_idk())
|
||||
bname = "AM572x IDK";
|
||||
|
||||
if (bname)
|
||||
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
|
||||
"Board: %s REV %s\n", bname, board_ti_get_rev());
|
||||
}
|
||||
|
||||
static void setup_board_eeprom_env(void)
|
||||
{
|
||||
char *name = "beagle_x15";
|
||||
int rc;
|
||||
|
||||
rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
|
||||
CONFIG_EEPROM_CHIP_ADDRESS);
|
||||
if (rc)
|
||||
goto invalid_eeprom;
|
||||
|
||||
if (board_is_am572x_evm())
|
||||
name = "am57xx_evm";
|
||||
else if (board_is_am572x_idk())
|
||||
name = "am572x_idk";
|
||||
else
|
||||
printf("Unidentified board claims %s in eeprom header\n",
|
||||
board_ti_get_name());
|
||||
|
||||
invalid_eeprom:
|
||||
set_board_info_env(name);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
void vcores_init(void)
|
||||
{
|
||||
if (board_is_am572x_idk())
|
||||
*omap_vcores = &am572x_idk_volts;
|
||||
else
|
||||
*omap_vcores = &beagle_x15_volts;
|
||||
}
|
||||
|
||||
void hw_data_init(void)
|
||||
{
|
||||
*prcm = &dra7xx_prcm;
|
||||
*dplls_data = &dra7xx_dplls;
|
||||
*ctrl = &dra7xx_ctrl;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gpmc_init();
|
||||
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
setup_board_eeprom_env();
|
||||
|
||||
/*
|
||||
* DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
|
||||
* This is the POWERHOLD-in-Low behavior.
|
||||
*/
|
||||
palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
do_set_mux32((*ctrl)->control_padconf_core_base,
|
||||
early_padconf, ARRAY_SIZE(early_padconf));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IODELAY_RECALIBRATION
|
||||
void recalibrate_iodelay(void)
|
||||
{
|
||||
const struct pad_conf_entry *pconf;
|
||||
const struct iodelay_cfg_entry *iod;
|
||||
int pconf_sz, iod_sz;
|
||||
|
||||
if (board_is_am572x_idk()) {
|
||||
pconf = core_padconf_array_essential_am572x_idk;
|
||||
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
|
||||
iod = iodelay_cfg_array_am572x_idk;
|
||||
iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
|
||||
} else {
|
||||
/* Common for X15/GPEVM */
|
||||
pconf = core_padconf_array_essential_x15;
|
||||
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
|
||||
iod = iodelay_cfg_array_x15;
|
||||
iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
|
||||
}
|
||||
|
||||
__recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
omap_mmc_init(0, 0, 0, -1, -1);
|
||||
omap_mmc_init(1, 0, 0, -1, -1);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* break into full u-boot on 'c' */
|
||||
if (serial_tstc() && serial_getc() == 'c')
|
||||
return 1;
|
||||
|
||||
#ifdef CONFIG_SPL_ENV_SUPPORT
|
||||
env_init();
|
||||
env_relocate_spec();
|
||||
if (getenv_yesno("boot_os") != 1)
|
||||
return 1;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_DWC3
|
||||
static struct dwc3_device usb_otg_ss1 = {
|
||||
.maximum_speed = USB_SPEED_SUPER,
|
||||
.base = DRA7_USB_OTG_SS1_BASE,
|
||||
.tx_fifo_resize = false,
|
||||
.index = 0,
|
||||
};
|
||||
|
||||
static struct dwc3_omap_device usb_otg_ss1_glue = {
|
||||
.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
|
||||
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
|
||||
.index = 0,
|
||||
};
|
||||
|
||||
static struct ti_usb_phy_device usb_phy1_device = {
|
||||
.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
|
||||
.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
|
||||
.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
|
||||
.index = 0,
|
||||
};
|
||||
|
||||
static struct dwc3_device usb_otg_ss2 = {
|
||||
.maximum_speed = USB_SPEED_HIGH,
|
||||
.base = DRA7_USB_OTG_SS2_BASE,
|
||||
.tx_fifo_resize = false,
|
||||
.index = 1,
|
||||
};
|
||||
|
||||
static struct dwc3_omap_device usb_otg_ss2_glue = {
|
||||
.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
|
||||
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
|
||||
.index = 1,
|
||||
};
|
||||
|
||||
static struct ti_usb_phy_device usb_phy2_device = {
|
||||
.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
|
||||
.index = 1,
|
||||
};
|
||||
|
||||
int usb_gadget_handle_interrupts(int index)
|
||||
{
|
||||
u32 status;
|
||||
|
||||
status = dwc3_omap_uboot_interrupt_status(index);
|
||||
if (status)
|
||||
dwc3_uboot_handle_interrupt(index);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_USB_DWC3 */
|
||||
|
||||
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
|
||||
int board_usb_init(int index, enum usb_init_type init)
|
||||
{
|
||||
enable_usb_clocks(index);
|
||||
switch (index) {
|
||||
case 0:
|
||||
if (init == USB_INIT_DEVICE) {
|
||||
printf("port %d can't be used as device\n", index);
|
||||
disable_usb_clocks(index);
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
if (init == USB_INIT_DEVICE) {
|
||||
#ifdef CONFIG_USB_DWC3
|
||||
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
|
||||
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
|
||||
ti_usb_phy_uboot_init(&usb_phy2_device);
|
||||
dwc3_omap_uboot_init(&usb_otg_ss2_glue);
|
||||
dwc3_uboot_init(&usb_otg_ss2);
|
||||
#endif
|
||||
} else {
|
||||
printf("port %d can't be used as host\n", index);
|
||||
disable_usb_clocks(index);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
printf("Invalid Controller Index\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_usb_cleanup(int index, enum usb_init_type init)
|
||||
{
|
||||
#ifdef CONFIG_USB_DWC3
|
||||
switch (index) {
|
||||
case 0:
|
||||
case 1:
|
||||
if (init == USB_INIT_DEVICE) {
|
||||
ti_usb_phy_uboot_exit(index);
|
||||
dwc3_uboot_exit(index);
|
||||
dwc3_omap_uboot_exit(index);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
printf("Invalid Controller Index\n");
|
||||
}
|
||||
#endif
|
||||
disable_usb_clocks(index);
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
|
||||
|
||||
#ifdef CONFIG_DRIVER_TI_CPSW
|
||||
|
||||
/* Delay value to add to calibrated value */
|
||||
#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
|
||||
#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
|
||||
#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
|
||||
#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
|
||||
#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
|
||||
#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
|
||||
#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
|
||||
#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
|
||||
#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
|
||||
#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
|
||||
|
||||
static void cpsw_control(int enabled)
|
||||
{
|
||||
/* VTP can be added here */
|
||||
}
|
||||
|
||||
static struct cpsw_slave_data cpsw_slaves[] = {
|
||||
{
|
||||
.slave_reg_ofs = 0x208,
|
||||
.sliver_reg_ofs = 0xd80,
|
||||
.phy_addr = 1,
|
||||
},
|
||||
{
|
||||
.slave_reg_ofs = 0x308,
|
||||
.sliver_reg_ofs = 0xdc0,
|
||||
.phy_addr = 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct cpsw_platform_data cpsw_data = {
|
||||
.mdio_base = CPSW_MDIO_BASE,
|
||||
.cpsw_base = CPSW_BASE,
|
||||
.mdio_div = 0xff,
|
||||
.channels = 8,
|
||||
.cpdma_reg_ofs = 0x800,
|
||||
.slaves = 1,
|
||||
.slave_data = cpsw_slaves,
|
||||
.ale_reg_ofs = 0xd00,
|
||||
.ale_entries = 1024,
|
||||
.host_port_reg_ofs = 0x108,
|
||||
.hw_stats_reg_ofs = 0x900,
|
||||
.bd_ram_ofs = 0x2000,
|
||||
.mac_control = (1 << 5),
|
||||
.control = cpsw_control,
|
||||
.host_port_num = 0,
|
||||
.version = CPSW_CTRL_VERSION_2,
|
||||
};
|
||||
|
||||
static u64 mac_to_u64(u8 mac[6])
|
||||
{
|
||||
int i;
|
||||
u64 addr = 0;
|
||||
|
||||
for (i = 0; i < 6; i++) {
|
||||
addr <<= 8;
|
||||
addr |= mac[i];
|
||||
}
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
static void u64_to_mac(u64 addr, u8 mac[6])
|
||||
{
|
||||
mac[5] = addr;
|
||||
mac[4] = addr >> 8;
|
||||
mac[3] = addr >> 16;
|
||||
mac[2] = addr >> 24;
|
||||
mac[1] = addr >> 32;
|
||||
mac[0] = addr >> 40;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
uint8_t mac_addr[6];
|
||||
uint32_t mac_hi, mac_lo;
|
||||
uint32_t ctrl_val;
|
||||
int i;
|
||||
u64 mac1, mac2;
|
||||
u8 mac_addr1[6], mac_addr2[6];
|
||||
int num_macs;
|
||||
|
||||
/* try reading mac address from efuse */
|
||||
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
|
||||
mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
|
||||
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
|
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||
mac_addr[2] = mac_hi & 0xFF;
|
||||
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
|
||||
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
|
||||
mac_addr[5] = mac_lo & 0xFF;
|
||||
|
||||
if (!getenv("ethaddr")) {
|
||||
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
|
||||
|
||||
if (is_valid_ethaddr(mac_addr))
|
||||
eth_setenv_enetaddr("ethaddr", mac_addr);
|
||||
}
|
||||
|
||||
mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
|
||||
mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
|
||||
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
|
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||
mac_addr[2] = mac_hi & 0xFF;
|
||||
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
|
||||
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
|
||||
mac_addr[5] = mac_lo & 0xFF;
|
||||
|
||||
if (!getenv("eth1addr")) {
|
||||
if (is_valid_ethaddr(mac_addr))
|
||||
eth_setenv_enetaddr("eth1addr", mac_addr);
|
||||
}
|
||||
|
||||
ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
|
||||
ctrl_val |= 0x22;
|
||||
writel(ctrl_val, (*ctrl)->control_core_control_io1);
|
||||
|
||||
/* The phy address for the AM572x IDK are different than x15 */
|
||||
if (board_is_am572x_idk()) {
|
||||
cpsw_data.slave_data[0].phy_addr = 0;
|
||||
cpsw_data.slave_data[1].phy_addr = 1;
|
||||
}
|
||||
|
||||
ret = cpsw_register(&cpsw_data);
|
||||
if (ret < 0)
|
||||
printf("Error %d registering CPSW switch\n", ret);
|
||||
|
||||
/*
|
||||
* Export any Ethernet MAC addresses from EEPROM.
|
||||
* On AM57xx the 2 MAC addresses define the address range
|
||||
*/
|
||||
board_ti_get_eth_mac_addr(0, mac_addr1);
|
||||
board_ti_get_eth_mac_addr(1, mac_addr2);
|
||||
|
||||
if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
|
||||
mac1 = mac_to_u64(mac_addr1);
|
||||
mac2 = mac_to_u64(mac_addr2);
|
||||
|
||||
/* must contain an address range */
|
||||
num_macs = mac2 - mac1 + 1;
|
||||
/* <= 50 to protect against user programming error */
|
||||
if (num_macs > 0 && num_macs <= 50) {
|
||||
for (i = 0; i < num_macs; i++) {
|
||||
u64_to_mac(mac1 + i, mac_addr);
|
||||
if (is_valid_ethaddr(mac_addr)) {
|
||||
eth_setenv_enetaddr_by_index("eth",
|
||||
i + 2,
|
||||
mac_addr);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
||||
/* VTT regulator enable */
|
||||
static inline void vtt_regulator_enable(void)
|
||||
{
|
||||
if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
|
||||
return;
|
||||
|
||||
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
|
||||
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
vtt_regulator_enable();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
if (board_is_x15() && !strcmp(name, "am57xx-beagle-x15"))
|
||||
return 0;
|
||||
else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15"))
|
||||
return 0;
|
||||
else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk"))
|
||||
return 0;
|
||||
else
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
594
u-boot/board/ti/am57xx/mux_data.h
Normal file
594
u-boot/board/ti/am57xx/mux_data.h
Normal file
@@ -0,0 +1,594 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
|
||||
*
|
||||
* Author: Felipe Balbi <balbi@ti.com>
|
||||
*
|
||||
* Based on board/ti/dra7xx/evm.c
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _MUX_DATA_BEAGLE_X15_H_
|
||||
#define _MUX_DATA_BEAGLE_X15_H_
|
||||
|
||||
#include <asm/arch/mux_dra7xx.h>
|
||||
|
||||
const struct pad_conf_entry core_padconf_array_essential_x15[] = {
|
||||
{GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */
|
||||
{GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */
|
||||
{GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */
|
||||
{GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */
|
||||
{GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */
|
||||
{GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */
|
||||
{GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */
|
||||
{GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */
|
||||
{GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */
|
||||
{GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */
|
||||
{GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */
|
||||
{GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */
|
||||
{GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */
|
||||
{GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */
|
||||
{GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */
|
||||
{GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */
|
||||
{GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */
|
||||
{GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */
|
||||
{GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */
|
||||
{GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin3a_d19 */
|
||||
{GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin3a_d20 */
|
||||
{GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vin3a_d21 */
|
||||
{GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin3a_d22 */
|
||||
{GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin3a_d23 */
|
||||
{GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vin3a_hsync0 */
|
||||
{GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin3a_vsync0 */
|
||||
{GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin3a_de0 */
|
||||
{GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin3a_fld0 */
|
||||
{GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */
|
||||
{GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */
|
||||
{GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */
|
||||
{GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */
|
||||
{GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */
|
||||
{GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */
|
||||
{GPMC_A18, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a18.gpio2_8 */
|
||||
{GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
|
||||
{GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
|
||||
{GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
|
||||
{GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
|
||||
{GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
|
||||
{GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
|
||||
{GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
|
||||
{GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
|
||||
{GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
|
||||
{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
|
||||
{GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */
|
||||
{GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */
|
||||
{GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.vin3a_clk0 */
|
||||
{GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */
|
||||
{GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
|
||||
{GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
|
||||
{GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */
|
||||
{GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */
|
||||
{GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */
|
||||
{GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */
|
||||
{VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */
|
||||
{VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */
|
||||
{VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */
|
||||
{VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */
|
||||
{VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */
|
||||
{VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */
|
||||
{VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */
|
||||
{VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */
|
||||
{VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
|
||||
{VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d11.gpio3_15 */
|
||||
{VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */
|
||||
{VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */
|
||||
{VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */
|
||||
{VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */
|
||||
{VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */
|
||||
{VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d21.vin1a_d21 */
|
||||
{VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */
|
||||
{VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */
|
||||
{VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */
|
||||
{VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
|
||||
{VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */
|
||||
{VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */
|
||||
{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
|
||||
{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
|
||||
{VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */
|
||||
{VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */
|
||||
{VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */
|
||||
{VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */
|
||||
{VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */
|
||||
{VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */
|
||||
{VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */
|
||||
{VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */
|
||||
{VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */
|
||||
{VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */
|
||||
{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
|
||||
{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
|
||||
{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
|
||||
{VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
|
||||
{VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
|
||||
{VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
|
||||
{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
|
||||
{VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
|
||||
{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
|
||||
{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
|
||||
{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
|
||||
{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
|
||||
{VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
|
||||
{VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
|
||||
{VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
|
||||
{VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
|
||||
{VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
|
||||
{VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
|
||||
{VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
|
||||
{VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
|
||||
{VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
|
||||
{VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
|
||||
{VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
|
||||
{VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
|
||||
{VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
|
||||
{VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
|
||||
{VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
|
||||
{VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
|
||||
{VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
|
||||
{VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
|
||||
{VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
|
||||
{VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
|
||||
{VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
|
||||
{VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
|
||||
{VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
|
||||
{VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
|
||||
{VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
|
||||
{VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
|
||||
{VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
|
||||
{VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
|
||||
{VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
|
||||
{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */
|
||||
{MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */
|
||||
{RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */
|
||||
{UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */
|
||||
{UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */
|
||||
{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
|
||||
{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
|
||||
{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
|
||||
{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
|
||||
{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
|
||||
{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
|
||||
{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
|
||||
{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
|
||||
{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
|
||||
{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
|
||||
{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
|
||||
{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
|
||||
{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
|
||||
{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
|
||||
{GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */
|
||||
{GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */
|
||||
{GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */
|
||||
{XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.clkout2 */
|
||||
{XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */
|
||||
{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
|
||||
{XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
|
||||
{MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */
|
||||
{MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */
|
||||
{MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */
|
||||
{MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */
|
||||
{MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
|
||||
{MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
|
||||
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
|
||||
{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
|
||||
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
|
||||
{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
|
||||
{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
|
||||
{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
|
||||
{MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.gpio5_10 */
|
||||
{MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.gpio5_11 */
|
||||
{MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.gpio5_12 */
|
||||
{MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */
|
||||
{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.mcasp7_axr0 */
|
||||
{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
|
||||
{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.mcasp7_aclkx */
|
||||
{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.mcasp7_fsx */
|
||||
{MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */
|
||||
{MCASP2_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.mcasp2_fsx */
|
||||
{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
|
||||
{MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */
|
||||
{MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */
|
||||
{MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */
|
||||
{MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.mcasp2_axr2 */
|
||||
{MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.mcasp2_axr3 */
|
||||
{MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */
|
||||
{MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */
|
||||
{MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */
|
||||
{MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.mcasp2_axr7 */
|
||||
{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
|
||||
{MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */
|
||||
{MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */
|
||||
{MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */
|
||||
{MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.uart8_rxd */
|
||||
{MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */
|
||||
{MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */
|
||||
{MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */
|
||||
{MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.uart9_rxd */
|
||||
{MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */
|
||||
{MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */
|
||||
{MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */
|
||||
{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
|
||||
{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
|
||||
{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
|
||||
{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
|
||||
{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
|
||||
{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
|
||||
{MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.mmc1_sdcd */
|
||||
{MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
|
||||
{GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */
|
||||
{GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
|
||||
{MMC3_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_clk.mmc3_clk */
|
||||
{MMC3_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.mmc3_cmd */
|
||||
{MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.mmc3_dat0 */
|
||||
{MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.mmc3_dat1 */
|
||||
{MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.mmc3_dat2 */
|
||||
{MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.mmc3_dat3 */
|
||||
{MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */
|
||||
{MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */
|
||||
{MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */
|
||||
{MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */
|
||||
{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
|
||||
{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
|
||||
{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
|
||||
{SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
|
||||
{SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */
|
||||
{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
|
||||
{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
|
||||
{SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */
|
||||
{SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */
|
||||
{SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */
|
||||
{SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */
|
||||
{DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
|
||||
{DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
|
||||
{UART1_RXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_rxd.uart1_rxd */
|
||||
{UART1_TXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_txd.uart1_txd */
|
||||
{UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.Driveroff */
|
||||
{UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* N/A.Driveroff */
|
||||
{UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.Driveroff */
|
||||
{UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
|
||||
{UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
|
||||
{I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
|
||||
{I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
|
||||
{WAKEUP0, (M0 | PULL_UP)}, /* Wakeup0.Wakeup0 */
|
||||
{WAKEUP1, (M0)}, /* Wakeup1.Wakeup1 */
|
||||
{WAKEUP2, (M0)}, /* Wakeup2.Wakeup2 */
|
||||
{WAKEUP3, (M0 | PULL_UP)}, /* Wakeup3.Wakeup3 */
|
||||
{ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
|
||||
{RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
|
||||
{RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */
|
||||
};
|
||||
|
||||
const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
|
||||
{GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
|
||||
{GPMC_A1, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
|
||||
{GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
|
||||
{GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
|
||||
{GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
|
||||
{GPMC_A5, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
|
||||
{GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
|
||||
{GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
|
||||
{GPMC_A8, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
|
||||
{GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
|
||||
{GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
|
||||
{GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
|
||||
{GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
|
||||
{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
|
||||
{GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
|
||||
{GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
|
||||
{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
|
||||
{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
|
||||
{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
|
||||
{GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
|
||||
{GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
|
||||
{GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
|
||||
{GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
|
||||
{GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
|
||||
{GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
|
||||
{GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
|
||||
{GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
|
||||
{GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
|
||||
{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
|
||||
{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
|
||||
{VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */
|
||||
{VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */
|
||||
{VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */
|
||||
{VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */
|
||||
{VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
|
||||
{VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */
|
||||
{VIN1A_D13, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d13.gpio3_17 */
|
||||
{VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */
|
||||
{VIN1A_D15, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d15.gpio3_19 */
|
||||
{VIN1A_D17, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d17.gpio3_21 */
|
||||
{VIN1A_D18, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
|
||||
{VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */
|
||||
{VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */
|
||||
{VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
|
||||
{VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
|
||||
{VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
|
||||
{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
|
||||
{VIN2A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_vsync0.gpio4_0 */
|
||||
{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
|
||||
{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
|
||||
{VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.ecap1 */
|
||||
{VIN2A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.gpio4_4 */
|
||||
{VIN2A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.gpio4_5 */
|
||||
{VIN2A_D5, (M13 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.pr1_pru1_gpo2 */
|
||||
{VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */
|
||||
{VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.pr1_mii_mii1_txen */
|
||||
{VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.pr1_mii_mii1_txd3 */
|
||||
{VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.pr1_mii_mii1_txd2 */
|
||||
{VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
|
||||
{VIN2A_D11, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.pr1_mdio_data */
|
||||
{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
|
||||
{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
|
||||
{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
|
||||
{VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
|
||||
{VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
|
||||
{VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
|
||||
{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
|
||||
{VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
|
||||
{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
|
||||
{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
|
||||
{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
|
||||
{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
|
||||
{VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
|
||||
{VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
|
||||
{VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
|
||||
{VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
|
||||
{VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
|
||||
{VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
|
||||
{VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
|
||||
{VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
|
||||
{VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
|
||||
{VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
|
||||
{VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
|
||||
{VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
|
||||
{VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
|
||||
{VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
|
||||
{VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
|
||||
{VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
|
||||
{VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
|
||||
{VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
|
||||
{VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
|
||||
{VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
|
||||
{VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
|
||||
{VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
|
||||
{VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
|
||||
{VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
|
||||
{VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
|
||||
{VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
|
||||
{VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
|
||||
{VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
|
||||
{VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
|
||||
{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */
|
||||
{MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */
|
||||
{RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)}, /* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */
|
||||
{UART3_RXD, (M11 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.pr1_mii0_rxdv */
|
||||
{UART3_TXD, (M11 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.rp1_mii_mr0_clk */
|
||||
{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
|
||||
{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
|
||||
{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
|
||||
{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
|
||||
{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
|
||||
{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
|
||||
{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
|
||||
{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
|
||||
{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
|
||||
{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
|
||||
{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
|
||||
{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
|
||||
{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
|
||||
{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
|
||||
{GPIO6_14, (M14 | PIN_OUTPUT_PULLUP)}, /* gpio6_14.gpio6_14 */
|
||||
{GPIO6_15, (M0 | PIN_OUTPUT_PULLUP)}, /* gpio6_15.gpio6_15 */
|
||||
{GPIO6_16, (M0 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6)_16 */
|
||||
{XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
|
||||
{XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
|
||||
{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.i6_19 */
|
||||
{XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
|
||||
{MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
|
||||
{MCASP1_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.pr2_mdio_data */
|
||||
{MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.gpio5_0 */
|
||||
{MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.gpio5_1 */
|
||||
{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
|
||||
{MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
|
||||
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
|
||||
{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
|
||||
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
|
||||
{MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr5.gpio5_7 */
|
||||
{MCASP1_AXR6, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */
|
||||
{MCASP1_AXR7, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */
|
||||
{MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.pr2_mii0_txen */
|
||||
{MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.pr2_mii0_txd3 */
|
||||
{MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.pr2_mii0_txd2 */
|
||||
{MCASP1_AXR11, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr11.pr2_mii0_txd1 */
|
||||
{MCASP1_AXR12, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.pr2_mii0_txd0 */
|
||||
{MCASP1_AXR13, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
|
||||
{MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp1_axr14.pr2_mii0_rxdv */
|
||||
{MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
|
||||
{MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
|
||||
{MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
|
||||
{MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
|
||||
{MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp2_axr3.pr2_mii0_rxlink */
|
||||
{MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.gpio1_4 */
|
||||
{MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.gpio6_7 */
|
||||
{MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.gpio2_29 */
|
||||
{MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.gpio1_5 */
|
||||
{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
|
||||
{MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
|
||||
{MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
|
||||
{MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
|
||||
{MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.spi3_sclk */
|
||||
{MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.spi3_d1 */
|
||||
{MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
|
||||
{MCASP5_ACLKX, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
|
||||
{MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},/* mcasp5_fsx.pr2_pru1_gpi2 */
|
||||
{MCASP5_AXR0, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.pr2_pru1_gpo3 */
|
||||
{MCASP5_AXR1, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr1.pr2_pru1_gpo4 */
|
||||
{GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
|
||||
{GPIO6_11, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
|
||||
{MMC3_CLK, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
|
||||
{MMC3_CMD, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
|
||||
{MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
|
||||
{MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
|
||||
{MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
|
||||
{MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
|
||||
{MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
|
||||
{MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
|
||||
{MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
|
||||
{MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
|
||||
{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
|
||||
{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
|
||||
{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
|
||||
{SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
|
||||
{SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs1.gpio7_11 */
|
||||
{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
|
||||
{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
|
||||
{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
|
||||
{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
|
||||
{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
|
||||
{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
|
||||
{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
|
||||
{MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
|
||||
{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
|
||||
{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
|
||||
{DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
|
||||
{DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
|
||||
{UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
|
||||
{UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
|
||||
{UART1_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_rxd.gpio7_22 */
|
||||
{UART1_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio7_23 */
|
||||
{I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
|
||||
{I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
|
||||
{ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
|
||||
{RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
|
||||
{TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
|
||||
{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
|
||||
{TDO, (M0 | PIN_INPUT_PULLUP)}, /* tdo.tdo */
|
||||
{TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
|
||||
{TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
|
||||
{RTCK, (M0 | PIN_INPUT)}, /* rtck.rtck */
|
||||
{EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
|
||||
{EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
|
||||
{RESETN, (M0 | PIN_OUTPUT_PULLUP)}, /* resetn.resetn */
|
||||
{RSTOUTN, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rstoutn.rstoutn */
|
||||
};
|
||||
|
||||
const struct pad_conf_entry early_padconf[] = {
|
||||
{UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
|
||||
{UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
|
||||
{I2C1_SDA, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SDA */
|
||||
{I2C1_SCL, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SCL */
|
||||
};
|
||||
|
||||
#ifdef CONFIG_IODELAY_RECALIBRATION
|
||||
const struct iodelay_cfg_entry iodelay_cfg_array_x15[] = {
|
||||
{0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
|
||||
{0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
|
||||
{0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
|
||||
{0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */
|
||||
{0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */
|
||||
{0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */
|
||||
{0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */
|
||||
{0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */
|
||||
{0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */
|
||||
{0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */
|
||||
{0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */
|
||||
{0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */
|
||||
{0x0264, 2466, 0}, /* CFG_GPMC_AD0_IN */
|
||||
{0x0270, 2523, 0}, /* CFG_GPMC_AD10_IN */
|
||||
{0x027C, 2453, 0}, /* CFG_GPMC_AD11_IN */
|
||||
{0x0288, 2285, 0}, /* CFG_GPMC_AD12_IN */
|
||||
{0x0294, 2206, 0}, /* CFG_GPMC_AD13_IN */
|
||||
{0x02A0, 1898, 0}, /* CFG_GPMC_AD14_IN */
|
||||
{0x02AC, 2473, 0}, /* CFG_GPMC_AD15_IN */
|
||||
{0x02B8, 2307, 0}, /* CFG_GPMC_AD1_IN */
|
||||
{0x02C4, 2691, 0}, /* CFG_GPMC_AD2_IN */
|
||||
{0x02D0, 2384, 0}, /* CFG_GPMC_AD3_IN */
|
||||
{0x02DC, 2462, 0}, /* CFG_GPMC_AD4_IN */
|
||||
{0x02E8, 2335, 0}, /* CFG_GPMC_AD5_IN */
|
||||
{0x02F4, 2370, 0}, /* CFG_GPMC_AD6_IN */
|
||||
{0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */
|
||||
{0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */
|
||||
{0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */
|
||||
{0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
|
||||
{0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
|
||||
{0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
|
||||
{0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
|
||||
{0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
|
||||
{0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
|
||||
{0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */
|
||||
{0x074C, 11, 60}, /* CFG_RGMII0_TXCTL_OUT */
|
||||
{0x0758, 7, 120}, /* CFG_RGMII0_TXD0_OUT */
|
||||
{0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
|
||||
{0x0770, 276, 120}, /* CFG_RGMII0_TXD2_OUT */
|
||||
{0x077C, 440, 120}, /* CFG_RGMII0_TXD3_OUT */
|
||||
{0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
|
||||
{0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
|
||||
{0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */
|
||||
{0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */
|
||||
{0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
|
||||
{0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
|
||||
{0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
|
||||
{0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
|
||||
{0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
|
||||
{0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
|
||||
{0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
|
||||
{0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
|
||||
};
|
||||
|
||||
const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
|
||||
{0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
|
||||
{0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
|
||||
{0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
|
||||
{0x0138, 2605, 45}, /* CFG_GPMC_A12_IN */
|
||||
{0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
|
||||
{0x0150, 1976, 1389}, /* CFG_GPMC_A14_IN */
|
||||
{0x015C, 1872, 1408}, /* CFG_GPMC_A15_IN */
|
||||
{0x0168, 1914, 1506}, /* CFG_GPMC_A16_IN */
|
||||
{0x0170, 57, 0}, /* CFG_GPMC_A16_OUT */
|
||||
{0x0174, 1904, 1471}, /* CFG_GPMC_A17_IN */
|
||||
{0x0188, 1690, 0}, /* CFG_GPMC_A18_OUT */
|
||||
{0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */
|
||||
{0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */
|
||||
{0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */
|
||||
{0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */
|
||||
{0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */
|
||||
{0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */
|
||||
{0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */
|
||||
{0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */
|
||||
{0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */
|
||||
{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
|
||||
{0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
|
||||
{0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
|
||||
{0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
|
||||
{0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
|
||||
{0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
|
||||
{0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
|
||||
{0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */
|
||||
{0x074C, 201, 60}, /* CFG_RGMII0_TXCTL_OUT */
|
||||
{0x0758, 229, 120}, /* CFG_RGMII0_TXD0_OUT */
|
||||
{0x0764, 141, 0}, /* CFG_RGMII0_TXD1_OUT */
|
||||
{0x0770, 495, 120}, /* CFG_RGMII0_TXD2_OUT */
|
||||
{0x077C, 660, 120}, /* CFG_RGMII0_TXD3_OUT */
|
||||
{0x0A70, 65, 70}, /* CFG_VIN2A_D12_OUT */
|
||||
{0x0A7C, 125, 70}, /* CFG_VIN2A_D13_OUT */
|
||||
{0x0A88, 0, 70}, /* CFG_VIN2A_D14_OUT */
|
||||
{0x0A94, 0, 70}, /* CFG_VIN2A_D15_OUT */
|
||||
{0x0AA0, 65, 70}, /* CFG_VIN2A_D16_OUT */
|
||||
{0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
|
||||
{0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */
|
||||
{0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */
|
||||
{0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */
|
||||
{0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */
|
||||
{0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */
|
||||
{0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */
|
||||
};
|
||||
#endif
|
||||
#endif /* _MUX_DATA_BEAGLE_X15_H_ */
|
||||
Reference in New Issue
Block a user