avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
34
u-boot/board/ti/am335x/Kconfig
Normal file
34
u-boot/board/ti/am335x/Kconfig
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@@ -0,0 +1,34 @@
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if TARGET_AM335X_EVM
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config SYS_BOARD
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default "am335x"
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config SYS_VENDOR
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default "ti"
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config SYS_SOC
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default "am33xx"
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config SYS_CONFIG_NAME
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default "am335x_evm"
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config CONS_INDEX
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int "UART used for console"
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range 1 6
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default 1
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help
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The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
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in documentation, etc) available to it. Depending on your specific
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board you may want something other than UART0 as for example the IDK
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uses UART3 so enter 4 here.
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config NOR
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bool "Support for NOR flash"
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help
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The AM335x SoC supports having a NOR flash connected to the GPMC.
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In practice this is seen as a NOR flash module connected to the
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"memory cape" for the BeagleBone family.
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source "board/ti/common/Kconfig"
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endif
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12
u-boot/board/ti/am335x/MAINTAINERS
Normal file
12
u-boot/board/ti/am335x/MAINTAINERS
Normal file
@@ -0,0 +1,12 @@
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AM335X BOARD
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M: Tom Rini <trini@konsulko.com>
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S: Maintained
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F: board/ti/am335x/
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F: include/configs/am335x_evm.h
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F: configs/am335x_boneblack_defconfig
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F: configs/am335x_boneblack_vboot_defconfig
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F: configs/am335x_evm_defconfig
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F: configs/am335x_evm_nor_defconfig
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F: configs/am335x_evm_norboot_defconfig
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F: configs/am335x_evm_spiboot_defconfig
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F: configs/am335x_evm_usbspl_defconfig
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13
u-boot/board/ti/am335x/Makefile
Normal file
13
u-boot/board/ti/am335x/Makefile
Normal file
@@ -0,0 +1,13 @@
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#
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# Makefile
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#
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# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
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obj-y := mux.o
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endif
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obj-y += board.o
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205
u-boot/board/ti/am335x/README
Normal file
205
u-boot/board/ti/am335x/README
Normal file
@@ -0,0 +1,205 @@
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Summary
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=======
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This document covers various features of the 'am335x_evm' build, and some of
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the related build targets (am335x_evm_uartN, etc).
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Hardware
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========
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The binary produced by this board supports, based on parsing of the EEPROM
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documented in TI's reference designs:
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- AM335x GP EVM
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- AM335x EVM SK
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- Beaglebone White
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- Beaglebone Black
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Customization
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=============
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Given that all of the above boards are reference platforms (and the
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Beaglebone platforms are OSHA), it is likely that this platform code and
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configuration will be used as the basis of a custom platform. It is
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worth noting that aside from things such as NAND or MMC only being
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required if a custom platform makes use of these blocks, the following
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are required, depending on design:
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- GPIO is only required if DDR3 power is controlled in a way similar to
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EVM SK
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- SPI is only required for SPI flash, or exposing the SPI bus.
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The following blocks are required:
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- I2C, to talk with the PMIC and ensure that we do not run afoul of
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errata 1.0.24.
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When removing options as part of customization,
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CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
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needs and to remove no longer relevant options as in some cases we
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define additional text blocks (such as for NAND or DFU strings). Also
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note that all of the SPL options are grouped together, rather than with
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the IP blocks, so both areas will need their choices updated to reflect
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the custom design.
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NAND
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====
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The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In
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this example to program the NAND we assume that an SD card has been
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inserted with the files to write in the first SD slot and that mtdparts
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have been configured correctly for the board. All images are first loaded
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into memory, then written to NAND.
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Step-1: Building u-boot for NAND boot
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Set following CONFIGxx options for NAND device.
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CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page
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CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page
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CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block
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CONFIG_SYS_NAND_ECCPOS ECC map for NAND page
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CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand)
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Step-2: Flashing NAND via MMC/SD
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# select BOOTSEL to MMC/SD boot and boot from MMC/SD card
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U-Boot # mmc rescan
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# erase flash
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U-Boot # nand erase.chip
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U-Boot # env default -f -a
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U-Boot # saveenv
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# flash MLO. Redundant copies of MLO are kept for failsafe
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U-Boot # load mmc 0 0x82000000 MLO
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U-Boot # nand write 0x82000000 0x00000 0x20000
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U-Boot # nand write 0x82000000 0x20000 0x20000
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U-Boot # nand write 0x82000000 0x40000 0x20000
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U-Boot # nand write 0x82000000 0x60000 0x20000
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# flash u-boot.img
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U-Boot # load mmc 0 0x82000000 u-boot.img
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U-Boot # nand write 0x82000000 0x80000 0x60000
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# flash kernel image
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U-Boot # load mmc 0 0x82000000 uImage
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U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize}
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# flash filesystem image
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U-Boot # load mmc 0 0x82000000 filesystem.img
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U-Boot # nand write 0x82000000 ${loadaddress} 0x300000
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Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
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The device should boot from images flashed on NAND device.
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NOR
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===
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The Beaglebone White can be equipped with a "memory cape" that in turn can
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have a NOR module plugged into it. In this case it is then possible to
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program and boot from NOR. Note that due to how U-Boot is designed we
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must build a specific version of U-Boot that knows we have NOR flash. This
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build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot'
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build that will assume that the environment is on NOR rather than NAND. In
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the following example we assume that and SD card has been populated with
|
||||
MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the
|
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'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a
|
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binary must be written to the start of NOR, with no header or similar
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prepended. In the following example we use a size of 512KiB (0x80000)
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as that is how much space we set aside before the environment, as per
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the config file.
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U-Boot # mmc rescan
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U-Boot # load mmc 0 ${loadaddr} u-boot.bin
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U-Boot # protect off 08000000 +80000
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U-Boot # erase 08000000 +80000
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U-Boot # cp.b ${loadaddr} 08000000 ${filesize}
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Falcon Mode
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===========
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||||
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The default build includes "Falcon Mode" (see doc/README.falcon) via NAND,
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eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is
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||||
to read a 'c' on the console while in SPL at any point prior to loading the
|
||||
OS payload (so as soon as possible) to opt to booting full U-Boot. Also
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||||
note that while one can program Falcon Mode "in place" great care needs to
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||||
be taken by the user to not 'brick' their setup. As these are all eval
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||||
boards with multiple boot methods, recovery should not be an issue in this
|
||||
worst-case however.
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||||
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||||
Falcon Mode: eMMC
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||||
=================
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||||
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||||
The recommended layout in this case is:
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||||
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||||
MMC BLOCKS |--------------------------------| LOCATION IN BYTES
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||||
0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000
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0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000
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||||
0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000
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0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000
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0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000
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0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000
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0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000
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||||
Note that when we run 'spl export' it will prepare to boot the kernel.
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This includes relocation of the uImage from where we loaded it to the entry
|
||||
point defined in the header. As these locations overlap by default, it
|
||||
would leave us with an image that if written to MMC will not boot, so
|
||||
instead of using the loadaddr variable we use 0x81000000 in the following
|
||||
example. In this example we are loading from the network, for simplicity,
|
||||
and assume a valid partition table already exists and 'mmc dev' has already
|
||||
been run to select the correct device. Also note that if you previously
|
||||
had a FAT partition (such as on a Beaglebone Black) it is not enough to
|
||||
write garbage into the area, you must delete it from the partition table
|
||||
first.
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||||
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||||
# Ensure we are able to talk with this mmc device
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U-Boot # mmc rescan
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U-Boot # tftp 81000000 am335x/MLO
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# Write to two of the backup locations ROM uses
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U-Boot # mmc write 81000000 100 100
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U-Boot # mmc write 81000000 200 100
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# Write U-Boot to the location set in the config
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U-Boot # tftp 81000000 am335x/u-boot.img
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U-Boot # mmc write 81000000 300 400
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# Load kernel and device tree into memory, perform export
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U-Boot # tftp 81000000 am335x/uImage
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U-Boot # run findfdt
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U-Boot # tftp ${fdtaddr} am335x/${fdtfile}
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U-Boot # run mmcargs
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U-Boot # spl export fdt 81000000 - ${fdtaddr}
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# Write the updated device tree to MMC
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||||
U-Boot # mmc write ${fdtaddr} 80 80
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# Write the uImage to MMC
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||||
U-Boot # mmc write 81000000 900 2000
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||||
Falcon Mode: FAT SD cards
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||||
=========================
|
||||
|
||||
In this case the additional file is written to the filesystem. In this
|
||||
example we assume that the uImage and device tree to be used are already on
|
||||
the FAT filesystem (only the uImage MUST be for this to function
|
||||
afterwards) along with a Falcon Mode aware MLO and the FAT partition has
|
||||
already been created and marked bootable:
|
||||
|
||||
U-Boot # mmc rescan
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||||
# Load kernel and device tree into memory, perform export
|
||||
U-Boot # load mmc 0:1 ${loadaddr} uImage
|
||||
U-Boot # run findfdt
|
||||
U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile}
|
||||
U-Boot # run mmcargs
|
||||
U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
|
||||
|
||||
This will print a number of lines and then end with something like:
|
||||
Using Device Tree in place at 80f80000, end 80f85928
|
||||
Using Device Tree in place at 80f80000, end 80f88928
|
||||
So then you:
|
||||
|
||||
U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928
|
||||
|
||||
Falcon Mode: NAND
|
||||
=================
|
||||
|
||||
In this case the additional data is written to another partition of the
|
||||
NAND. In this example we assume that the uImage and device tree to be are
|
||||
already located on the NAND somewhere (such as filesystem or mtd partition)
|
||||
along with a Falcon Mode aware MLO written to the correct locations for
|
||||
booting and mtdparts have been configured correctly for the board:
|
||||
|
||||
U-Boot # nand read ${loadaddr} kernel
|
||||
U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
|
||||
U-Boot # run nandargs
|
||||
U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
|
||||
U-Boot # nand erase.part u-boot-spl-os
|
||||
U-Boot # nand write ${fdtaddr} u-boot-spl-os
|
||||
777
u-boot/board/ti/am335x/board.c
Normal file
777
u-boot/board/ti/am335x/board.c
Normal file
@@ -0,0 +1,777 @@
|
||||
/*
|
||||
* board.c
|
||||
*
|
||||
* Board functions for TI AM335X based boards
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <spl.h>
|
||||
#include <serial.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/omap.h>
|
||||
#include <asm/arch/ddr_defs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/clk_synthesizer.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/mmc_host_def.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/emif.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <cpsw.h>
|
||||
#include <power/tps65217.h>
|
||||
#include <power/tps65910.h>
|
||||
#include <environment.h>
|
||||
#include <watchdog.h>
|
||||
#include <environment.h>
|
||||
#include "../common/board_detect.h"
|
||||
#include "board.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* GPIO that controls power to DDR on EVM-SK */
|
||||
#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
|
||||
#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
|
||||
#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
|
||||
#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
|
||||
#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
|
||||
#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
|
||||
#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) || \
|
||||
(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Read header information from EEPROM into global structure.
|
||||
*/
|
||||
static inline int __maybe_unused read_eeprom(void)
|
||||
{
|
||||
return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_DM_SERIAL
|
||||
struct serial_device *default_serial_console(void)
|
||||
{
|
||||
if (board_is_icev2())
|
||||
return &eserial4_device;
|
||||
else
|
||||
return &eserial1_device;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
static const struct ddr_data ddr2_data = {
|
||||
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
|
||||
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
|
||||
.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr2_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT47H128M16RT25E_RATIO,
|
||||
|
||||
.cmd1csratio = MT47H128M16RT25E_RATIO,
|
||||
|
||||
.cmd2csratio = MT47H128M16RT25E_RATIO,
|
||||
};
|
||||
|
||||
static const struct emif_regs ddr2_emif_reg_data = {
|
||||
.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
|
||||
.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
|
||||
.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
|
||||
.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
|
||||
.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
|
||||
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
|
||||
};
|
||||
|
||||
static const struct ddr_data ddr3_data = {
|
||||
.datardsratio0 = MT41J128MJT125_RD_DQS,
|
||||
.datawdsratio0 = MT41J128MJT125_WR_DQS,
|
||||
.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
|
||||
.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
|
||||
};
|
||||
|
||||
static const struct ddr_data ddr3_beagleblack_data = {
|
||||
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
|
||||
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
|
||||
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
|
||||
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
|
||||
};
|
||||
|
||||
static const struct ddr_data ddr3_evm_data = {
|
||||
.datardsratio0 = MT41J512M8RH125_RD_DQS,
|
||||
.datawdsratio0 = MT41J512M8RH125_WR_DQS,
|
||||
.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
|
||||
.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
|
||||
};
|
||||
|
||||
static const struct ddr_data ddr3_icev2_data = {
|
||||
.datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
|
||||
.datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
|
||||
.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
|
||||
.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr3_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT41J128MJT125_RATIO,
|
||||
.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
|
||||
|
||||
.cmd1csratio = MT41J128MJT125_RATIO,
|
||||
.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
|
||||
|
||||
.cmd2csratio = MT41J128MJT125_RATIO,
|
||||
.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
|
||||
.cmd1csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
|
||||
.cmd2csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT41J512M8RH125_RATIO,
|
||||
.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
|
||||
|
||||
.cmd1csratio = MT41J512M8RH125_RATIO,
|
||||
.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
|
||||
|
||||
.cmd2csratio = MT41J512M8RH125_RATIO,
|
||||
.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT41J128MJT125_RATIO_400MHz,
|
||||
.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
|
||||
|
||||
.cmd1csratio = MT41J128MJT125_RATIO_400MHz,
|
||||
.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
|
||||
|
||||
.cmd2csratio = MT41J128MJT125_RATIO_400MHz,
|
||||
.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
|
||||
};
|
||||
|
||||
static struct emif_regs ddr3_emif_reg_data = {
|
||||
.sdram_config = MT41J128MJT125_EMIF_SDCFG,
|
||||
.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
|
||||
.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
|
||||
.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
|
||||
.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
|
||||
.zq_config = MT41J128MJT125_ZQ_CFG,
|
||||
.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
|
||||
PHY_EN_DYN_PWRDN,
|
||||
};
|
||||
|
||||
static struct emif_regs ddr3_beagleblack_emif_reg_data = {
|
||||
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
|
||||
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
|
||||
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
|
||||
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
|
||||
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
|
||||
.zq_config = MT41K256M16HA125E_ZQ_CFG,
|
||||
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
|
||||
};
|
||||
|
||||
static struct emif_regs ddr3_evm_emif_reg_data = {
|
||||
.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
|
||||
.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
|
||||
.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
|
||||
.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
|
||||
.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
|
||||
.zq_config = MT41J512M8RH125_ZQ_CFG,
|
||||
.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
|
||||
PHY_EN_DYN_PWRDN,
|
||||
};
|
||||
|
||||
static struct emif_regs ddr3_icev2_emif_reg_data = {
|
||||
.sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
|
||||
.ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
|
||||
.sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
|
||||
.sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
|
||||
.sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
|
||||
.zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
|
||||
.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
|
||||
PHY_EN_DYN_PWRDN,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* break into full u-boot on 'c' */
|
||||
if (serial_tstc() && serial_getc() == 'c')
|
||||
return 1;
|
||||
|
||||
#ifdef CONFIG_SPL_ENV_SUPPORT
|
||||
env_init();
|
||||
env_relocate_spec();
|
||||
if (getenv_yesno("boot_os") != 1)
|
||||
return 1;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define OSC (V_OSCK/1000000)
|
||||
const struct dpll_params dpll_ddr = {
|
||||
266, OSC-1, 1, -1, -1, -1, -1};
|
||||
const struct dpll_params dpll_ddr_evm_sk = {
|
||||
303, OSC-1, 1, -1, -1, -1, -1};
|
||||
const struct dpll_params dpll_ddr_bone_black = {
|
||||
400, OSC-1, 1, -1, -1, -1, -1};
|
||||
|
||||
void am33xx_spl_board_init(void)
|
||||
{
|
||||
int mpu_vdd;
|
||||
|
||||
if (read_eeprom() < 0)
|
||||
puts("Could not get board ID.\n");
|
||||
|
||||
/* Get the frequency */
|
||||
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
|
||||
|
||||
if (board_is_bone() || board_is_bone_lt()) {
|
||||
/* BeagleBone PMIC Code */
|
||||
int usb_cur_lim;
|
||||
|
||||
/*
|
||||
* Only perform PMIC configurations if board rev > A1
|
||||
* on Beaglebone White
|
||||
*/
|
||||
if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
|
||||
return;
|
||||
|
||||
if (i2c_probe(TPS65217_CHIP_PM))
|
||||
return;
|
||||
|
||||
/*
|
||||
* On Beaglebone White we need to ensure we have AC power
|
||||
* before increasing the frequency.
|
||||
*/
|
||||
if (board_is_bone()) {
|
||||
uchar pmic_status_reg;
|
||||
if (tps65217_reg_read(TPS65217_STATUS,
|
||||
&pmic_status_reg))
|
||||
return;
|
||||
if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
|
||||
puts("No AC power, disabling frequency switch\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Override what we have detected since we know if we have
|
||||
* a Beaglebone Black it supports 1GHz.
|
||||
*/
|
||||
if (board_is_bone_lt())
|
||||
dpll_mpu_opp100.m = MPUPLL_M_1000;
|
||||
|
||||
/*
|
||||
* Increase USB current limit to 1300mA or 1800mA and set
|
||||
* the MPU voltage controller as needed.
|
||||
*/
|
||||
if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
|
||||
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
|
||||
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
|
||||
} else {
|
||||
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
|
||||
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
|
||||
}
|
||||
|
||||
if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
|
||||
TPS65217_POWER_PATH,
|
||||
usb_cur_lim,
|
||||
TPS65217_USB_INPUT_CUR_LIMIT_MASK))
|
||||
puts("tps65217_reg_write failure\n");
|
||||
|
||||
/* Set DCDC3 (CORE) voltage to 1.125V */
|
||||
if (tps65217_voltage_update(TPS65217_DEFDCDC3,
|
||||
TPS65217_DCDC_VOLT_SEL_1125MV)) {
|
||||
puts("tps65217_voltage_update failure\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set CORE Frequencies to OPP100 */
|
||||
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
|
||||
|
||||
/* Set DCDC2 (MPU) voltage */
|
||||
if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
|
||||
puts("tps65217_voltage_update failure\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
|
||||
* Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
|
||||
*/
|
||||
if (board_is_bone()) {
|
||||
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
|
||||
TPS65217_DEFLS1,
|
||||
TPS65217_LDO_VOLTAGE_OUT_3_3,
|
||||
TPS65217_LDO_MASK))
|
||||
puts("tps65217_reg_write failure\n");
|
||||
} else {
|
||||
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
|
||||
TPS65217_DEFLS1,
|
||||
TPS65217_LDO_VOLTAGE_OUT_1_8,
|
||||
TPS65217_LDO_MASK))
|
||||
puts("tps65217_reg_write failure\n");
|
||||
}
|
||||
|
||||
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
|
||||
TPS65217_DEFLS2,
|
||||
TPS65217_LDO_VOLTAGE_OUT_3_3,
|
||||
TPS65217_LDO_MASK))
|
||||
puts("tps65217_reg_write failure\n");
|
||||
} else {
|
||||
int sil_rev;
|
||||
|
||||
/*
|
||||
* The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
|
||||
* MPU frequencies we support we use a CORE voltage of
|
||||
* 1.1375V. For MPU voltage we need to switch based on
|
||||
* the frequency we are running at.
|
||||
*/
|
||||
if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Depending on MPU clock and PG we will need a different
|
||||
* VDD to drive at that speed.
|
||||
*/
|
||||
sil_rev = readl(&cdev->deviceid) >> 28;
|
||||
mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
|
||||
dpll_mpu_opp100.m);
|
||||
|
||||
/* Tell the TPS65910 to use i2c */
|
||||
tps65910_set_i2c_control();
|
||||
|
||||
/* First update MPU voltage. */
|
||||
if (tps65910_voltage_update(MPU, mpu_vdd))
|
||||
return;
|
||||
|
||||
/* Second, update the CORE voltage. */
|
||||
if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
|
||||
return;
|
||||
|
||||
/* Set CORE Frequencies to OPP100 */
|
||||
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
|
||||
}
|
||||
|
||||
/* Set MPU Frequency to what we detected now that voltages are set */
|
||||
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
|
||||
}
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
enable_i2c0_pin_mux();
|
||||
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
|
||||
if (read_eeprom() < 0)
|
||||
puts("Could not get board ID.\n");
|
||||
|
||||
if (board_is_evm_sk())
|
||||
return &dpll_ddr_evm_sk;
|
||||
else if (board_is_bone_lt() || board_is_icev2())
|
||||
return &dpll_ddr_bone_black;
|
||||
else if (board_is_evm_15_or_later())
|
||||
return &dpll_ddr_evm_sk;
|
||||
else
|
||||
return &dpll_ddr;
|
||||
}
|
||||
|
||||
void set_uart_mux_conf(void)
|
||||
{
|
||||
#if CONFIG_CONS_INDEX == 1
|
||||
enable_uart0_pin_mux();
|
||||
#elif CONFIG_CONS_INDEX == 2
|
||||
enable_uart1_pin_mux();
|
||||
#elif CONFIG_CONS_INDEX == 3
|
||||
enable_uart2_pin_mux();
|
||||
#elif CONFIG_CONS_INDEX == 4
|
||||
enable_uart3_pin_mux();
|
||||
#elif CONFIG_CONS_INDEX == 5
|
||||
enable_uart4_pin_mux();
|
||||
#elif CONFIG_CONS_INDEX == 6
|
||||
enable_uart5_pin_mux();
|
||||
#endif
|
||||
}
|
||||
|
||||
void set_mux_conf_regs(void)
|
||||
{
|
||||
if (read_eeprom() < 0)
|
||||
puts("Could not get board ID.\n");
|
||||
|
||||
enable_board_pin_mux();
|
||||
}
|
||||
|
||||
const struct ctrl_ioregs ioregs_evmsk = {
|
||||
.cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
|
||||
.cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
const struct ctrl_ioregs ioregs_bonelt = {
|
||||
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
const struct ctrl_ioregs ioregs_evm15 = {
|
||||
.cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
|
||||
.cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
const struct ctrl_ioregs ioregs = {
|
||||
.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
if (read_eeprom() < 0)
|
||||
puts("Could not get board ID.\n");
|
||||
|
||||
if (board_is_evm_sk()) {
|
||||
/*
|
||||
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
|
||||
* This is safe enough to do on older revs.
|
||||
*/
|
||||
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
|
||||
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
|
||||
}
|
||||
|
||||
if (board_is_icev2()) {
|
||||
gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
|
||||
gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
|
||||
}
|
||||
|
||||
if (board_is_evm_sk())
|
||||
config_ddr(303, &ioregs_evmsk, &ddr3_data,
|
||||
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
|
||||
else if (board_is_bone_lt())
|
||||
config_ddr(400, &ioregs_bonelt,
|
||||
&ddr3_beagleblack_data,
|
||||
&ddr3_beagleblack_cmd_ctrl_data,
|
||||
&ddr3_beagleblack_emif_reg_data, 0);
|
||||
else if (board_is_evm_15_or_later())
|
||||
config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
|
||||
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
|
||||
else if (board_is_icev2())
|
||||
config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
|
||||
&ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
|
||||
0);
|
||||
else
|
||||
config_ddr(266, &ioregs, &ddr2_data,
|
||||
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
||||
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
||||
static void request_and_set_gpio(int gpio, char *name)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = gpio_request(gpio, name);
|
||||
if (ret < 0) {
|
||||
printf("%s: Unable to request %s\n", __func__, name);
|
||||
return;
|
||||
}
|
||||
|
||||
ret = gpio_direction_output(gpio, 0);
|
||||
if (ret < 0) {
|
||||
printf("%s: Unable to set %s as output\n", __func__, name);
|
||||
goto err_free_gpio;
|
||||
}
|
||||
|
||||
gpio_set_value(gpio, 1);
|
||||
|
||||
return;
|
||||
|
||||
err_free_gpio:
|
||||
gpio_free(gpio);
|
||||
}
|
||||
|
||||
#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N);
|
||||
|
||||
/**
|
||||
* RMII mode on ICEv2 board needs 50MHz clock. Given the clock
|
||||
* synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
|
||||
* PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
|
||||
* give 50MHz output for Eth0 and 1.
|
||||
*/
|
||||
static struct clk_synth cdce913_data = {
|
||||
.id = 0x81,
|
||||
.capacitor = 0x90,
|
||||
.mux = 0x6d,
|
||||
.pdiv2 = 0x2,
|
||||
.pdiv3 = 0x2,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Basic board specific setup. Pinmux has been handled already.
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
hw_watchdog_init();
|
||||
#endif
|
||||
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
|
||||
gpmc_init();
|
||||
#endif
|
||||
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD))
|
||||
int rv;
|
||||
|
||||
if (board_is_icev2()) {
|
||||
REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
|
||||
REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL);
|
||||
REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
|
||||
REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
|
||||
|
||||
rv = setup_clock_synthesizer(&cdce913_data);
|
||||
if (rv) {
|
||||
printf("Clock synthesizer setup failed %d\n", rv);
|
||||
return rv;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INIT
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
int rc;
|
||||
char *name = NULL;
|
||||
|
||||
rc = read_eeprom();
|
||||
if (rc)
|
||||
puts("Could not get board ID.\n");
|
||||
|
||||
if (board_is_bbg1())
|
||||
name = "BBG1";
|
||||
set_board_info_env(name);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DM_ETH
|
||||
|
||||
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
||||
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
||||
static void cpsw_control(int enabled)
|
||||
{
|
||||
/* VTP can be added here */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static struct cpsw_slave_data cpsw_slaves[] = {
|
||||
{
|
||||
.slave_reg_ofs = 0x208,
|
||||
.sliver_reg_ofs = 0xd80,
|
||||
.phy_addr = 0,
|
||||
},
|
||||
{
|
||||
.slave_reg_ofs = 0x308,
|
||||
.sliver_reg_ofs = 0xdc0,
|
||||
.phy_addr = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct cpsw_platform_data cpsw_data = {
|
||||
.mdio_base = CPSW_MDIO_BASE,
|
||||
.cpsw_base = CPSW_BASE,
|
||||
.mdio_div = 0xff,
|
||||
.channels = 8,
|
||||
.cpdma_reg_ofs = 0x800,
|
||||
.slaves = 1,
|
||||
.slave_data = cpsw_slaves,
|
||||
.ale_reg_ofs = 0xd00,
|
||||
.ale_entries = 1024,
|
||||
.host_port_reg_ofs = 0x108,
|
||||
.hw_stats_reg_ofs = 0x900,
|
||||
.bd_ram_ofs = 0x2000,
|
||||
.mac_control = (1 << 5),
|
||||
.control = cpsw_control,
|
||||
.host_port_num = 0,
|
||||
.version = CPSW_CTRL_VERSION_2,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
|
||||
defined(CONFIG_SPL_BUILD)) || \
|
||||
((defined(CONFIG_DRIVER_TI_CPSW) || \
|
||||
defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
|
||||
!defined(CONFIG_SPL_BUILD))
|
||||
|
||||
/*
|
||||
* This function will:
|
||||
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
|
||||
* in the environment
|
||||
* Perform fixups to the PHY present on certain boards. We only need this
|
||||
* function in:
|
||||
* - SPL with either CPSW or USB ethernet support
|
||||
* - Full U-Boot, with either CPSW or USB ethernet
|
||||
* Build in only these cases to avoid warnings about unused variables
|
||||
* when we build an SPL that has neither option but full U-Boot will.
|
||||
*/
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rv, n = 0;
|
||||
uint8_t mac_addr[6];
|
||||
uint32_t mac_hi, mac_lo;
|
||||
__maybe_unused struct ti_am_eeprom *header;
|
||||
|
||||
/* try reading mac address from efuse */
|
||||
mac_lo = readl(&cdev->macid0l);
|
||||
mac_hi = readl(&cdev->macid0h);
|
||||
mac_addr[0] = mac_hi & 0xFF;
|
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||
mac_addr[4] = mac_lo & 0xFF;
|
||||
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||
|
||||
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
||||
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
||||
if (!getenv("ethaddr")) {
|
||||
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
|
||||
|
||||
if (is_valid_ethaddr(mac_addr))
|
||||
eth_setenv_enetaddr("ethaddr", mac_addr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRIVER_TI_CPSW
|
||||
|
||||
mac_lo = readl(&cdev->macid1l);
|
||||
mac_hi = readl(&cdev->macid1h);
|
||||
mac_addr[0] = mac_hi & 0xFF;
|
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||
mac_addr[4] = mac_lo & 0xFF;
|
||||
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||
|
||||
if (!getenv("eth1addr")) {
|
||||
if (is_valid_ethaddr(mac_addr))
|
||||
eth_setenv_enetaddr("eth1addr", mac_addr);
|
||||
}
|
||||
|
||||
if (read_eeprom() < 0)
|
||||
puts("Could not get board ID.\n");
|
||||
|
||||
if (board_is_bone() || board_is_bone_lt() ||
|
||||
board_is_idk()) {
|
||||
writel(MII_MODE_ENABLE, &cdev->miisel);
|
||||
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
|
||||
PHY_INTERFACE_MODE_MII;
|
||||
} else if (board_is_icev2()) {
|
||||
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
|
||||
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
|
||||
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
|
||||
cpsw_slaves[0].phy_addr = 1;
|
||||
cpsw_slaves[1].phy_addr = 3;
|
||||
} else {
|
||||
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
|
||||
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
|
||||
PHY_INTERFACE_MODE_RGMII;
|
||||
}
|
||||
|
||||
rv = cpsw_register(&cpsw_data);
|
||||
if (rv < 0)
|
||||
printf("Error %d registering CPSW switch\n", rv);
|
||||
else
|
||||
n += rv;
|
||||
#endif
|
||||
|
||||
/*
|
||||
*
|
||||
* CPSW RGMII Internal Delay Mode is not supported in all PVT
|
||||
* operating points. So we must set the TX clock delay feature
|
||||
* in the AR8051 PHY. Since we only support a single ethernet
|
||||
* device in U-Boot, we only do this for the first instance.
|
||||
*/
|
||||
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
|
||||
#define AR8051_PHY_DEBUG_DATA_REG 0x1e
|
||||
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
|
||||
#define AR8051_RGMII_TX_CLK_DLY 0x100
|
||||
|
||||
if (board_is_evm_sk() || board_is_gp_evm()) {
|
||||
const char *devname;
|
||||
devname = miiphy_get_current_dev();
|
||||
|
||||
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
|
||||
AR8051_DEBUG_RGMII_CLK_DLY_REG);
|
||||
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
|
||||
AR8051_RGMII_TX_CLK_DLY);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_USB_ETHER) && \
|
||||
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
|
||||
if (is_valid_ethaddr(mac_addr))
|
||||
eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
|
||||
|
||||
rv = usb_eth_initialize(bis);
|
||||
if (rv < 0)
|
||||
printf("Error %d registering USB_ETHER\n", rv);
|
||||
else
|
||||
n += rv;
|
||||
#endif
|
||||
return n;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_DM_ETH */
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
|
||||
return 0;
|
||||
else if (board_is_bone() && !strcmp(name, "am335x-bone"))
|
||||
return 0;
|
||||
else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
|
||||
return 0;
|
||||
else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
|
||||
return 0;
|
||||
else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
|
||||
return 0;
|
||||
else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
|
||||
return 0;
|
||||
else
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
69
u-boot/board/ti/am335x/board.h
Normal file
69
u-boot/board/ti/am335x/board.h
Normal file
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* board.h
|
||||
*
|
||||
* TI AM335x boards information header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
static inline int board_is_bone(void)
|
||||
{
|
||||
return board_ti_is("A335BONE");
|
||||
}
|
||||
|
||||
static inline int board_is_bone_lt(void)
|
||||
{
|
||||
return board_ti_is("A335BNLT");
|
||||
}
|
||||
|
||||
static inline int board_is_bbg1(void)
|
||||
{
|
||||
return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4);
|
||||
}
|
||||
|
||||
static inline int board_is_evm_sk(void)
|
||||
{
|
||||
return board_ti_is("A335X_SK");
|
||||
}
|
||||
|
||||
static inline int board_is_idk(void)
|
||||
{
|
||||
return !strncmp(board_ti_get_config(), "SKU#02", 6);
|
||||
}
|
||||
|
||||
static inline int board_is_gp_evm(void)
|
||||
{
|
||||
return board_ti_is("A33515BB");
|
||||
}
|
||||
|
||||
static inline int board_is_evm_15_or_later(void)
|
||||
{
|
||||
return (board_is_gp_evm() &&
|
||||
strncmp("1.5", board_ti_get_rev(), 3) <= 0);
|
||||
}
|
||||
|
||||
static inline int board_is_icev2(void)
|
||||
{
|
||||
return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* We have three pin mux functions that must exist. We must be able to enable
|
||||
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
|
||||
* main pinmux function that can be overridden to enable all other pinmux that
|
||||
* is required on the board.
|
||||
*/
|
||||
void enable_uart0_pin_mux(void);
|
||||
void enable_uart1_pin_mux(void);
|
||||
void enable_uart2_pin_mux(void);
|
||||
void enable_uart3_pin_mux(void);
|
||||
void enable_uart4_pin_mux(void);
|
||||
void enable_uart5_pin_mux(void);
|
||||
void enable_i2c0_pin_mux(void);
|
||||
void enable_board_pin_mux(void);
|
||||
#endif
|
||||
403
u-boot/board/ti/am335x/mux.c
Normal file
403
u-boot/board/ti/am335x/mux.c
Normal file
@@ -0,0 +1,403 @@
|
||||
/*
|
||||
* mux.c
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/io.h>
|
||||
#include <i2c.h>
|
||||
#include "../common/board_detect.h"
|
||||
#include "board.h"
|
||||
|
||||
static struct module_pin_mux uart0_pin_mux[] = {
|
||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart1_pin_mux[] = {
|
||||
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
|
||||
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart2_pin_mux[] = {
|
||||
{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
|
||||
{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart3_pin_mux[] = {
|
||||
{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart4_pin_mux[] = {
|
||||
{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
|
||||
{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart5_pin_mux[] = {
|
||||
{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
|
||||
{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc0_pin_mux[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||
{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
|
||||
{OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||
{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc1_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
|
||||
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
|
||||
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
|
||||
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
|
||||
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
|
||||
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
|
||||
{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
|
||||
{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux i2c1_pin_mux[] = {
|
||||
{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
||||
{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux spi0_pin_mux[] = {
|
||||
{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
|
||||
{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
|
||||
{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
|
||||
{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux gpio0_7_pin_mux[] = {
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux gpio0_18_pin_mux[] = {
|
||||
{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux rgmii1_pin_mux[] = {
|
||||
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
|
||||
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
|
||||
{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
|
||||
{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
|
||||
{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
|
||||
{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
|
||||
{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
|
||||
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
|
||||
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
|
||||
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
|
||||
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
|
||||
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mii1_pin_mux[] = {
|
||||
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
|
||||
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
|
||||
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
|
||||
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
|
||||
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
|
||||
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
|
||||
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
|
||||
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
|
||||
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
|
||||
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
|
||||
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
|
||||
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
|
||||
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux rmii1_pin_mux[] = {
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
|
||||
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */
|
||||
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */
|
||||
{OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */
|
||||
{OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */
|
||||
{OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */
|
||||
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */
|
||||
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */
|
||||
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
static struct module_pin_mux nand_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
|
||||
{OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
|
||||
{OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
|
||||
{OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
|
||||
{OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
|
||||
{OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
|
||||
{OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
|
||||
{OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
|
||||
#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
|
||||
{OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
|
||||
{OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
|
||||
{OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
|
||||
{OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
|
||||
{OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
|
||||
{OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
|
||||
{OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
|
||||
{OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
|
||||
#endif
|
||||
{OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
|
||||
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
|
||||
{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
|
||||
{OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
|
||||
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
|
||||
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
|
||||
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
|
||||
{-1},
|
||||
};
|
||||
#elif defined(CONFIG_NOR)
|
||||
static struct module_pin_mux bone_norcape_pin_mux[] = {
|
||||
{OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
|
||||
{OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
|
||||
{OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
|
||||
{OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
|
||||
{OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
|
||||
{OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
|
||||
{OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
|
||||
{OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
|
||||
{OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
|
||||
{OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
|
||||
{OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
|
||||
{OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
|
||||
{OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
|
||||
{OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
|
||||
{OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
|
||||
{OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
|
||||
{OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
|
||||
{OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
|
||||
{OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
|
||||
{OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
|
||||
{OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
|
||||
{OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
|
||||
{OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
|
||||
{OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
|
||||
{OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
|
||||
{OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
|
||||
{OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
|
||||
{OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
|
||||
{OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
|
||||
{OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
|
||||
{-1},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct module_pin_mux uart3_icev2_pin_mux[] = {
|
||||
{OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
|
||||
{OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
#if defined(CONFIG_NOR_BOOT)
|
||||
void enable_norboot_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(bone_norcape_pin_mux);
|
||||
}
|
||||
#endif
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart1_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart1_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart2_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart2_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart3_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart3_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart4_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart4_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart5_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart5_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
}
|
||||
|
||||
/*
|
||||
* The AM335x GP EVM, if daughter card(s) are connected, can have 8
|
||||
* different profiles. These profiles determine what peripherals are
|
||||
* valid and need pinmux to be configured.
|
||||
*/
|
||||
#define PROFILE_NONE 0x0
|
||||
#define PROFILE_0 (1 << 0)
|
||||
#define PROFILE_1 (1 << 1)
|
||||
#define PROFILE_2 (1 << 2)
|
||||
#define PROFILE_3 (1 << 3)
|
||||
#define PROFILE_4 (1 << 4)
|
||||
#define PROFILE_5 (1 << 5)
|
||||
#define PROFILE_6 (1 << 6)
|
||||
#define PROFILE_7 (1 << 7)
|
||||
#define PROFILE_MASK 0x7
|
||||
#define PROFILE_ALL 0xFF
|
||||
|
||||
/* CPLD registers */
|
||||
#define I2C_CPLD_ADDR 0x35
|
||||
#define CFG_REG 0x10
|
||||
|
||||
static unsigned short detect_daughter_board_profile(void)
|
||||
{
|
||||
unsigned short val;
|
||||
|
||||
if (i2c_probe(I2C_CPLD_ADDR))
|
||||
return PROFILE_NONE;
|
||||
|
||||
if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
|
||||
return PROFILE_NONE;
|
||||
|
||||
return (1 << (val & PROFILE_MASK));
|
||||
}
|
||||
|
||||
void enable_board_pin_mux(void)
|
||||
{
|
||||
/* Do board-specific muxes. */
|
||||
if (board_is_bone()) {
|
||||
/* Beaglebone pinmux */
|
||||
configure_module_pin_mux(mii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
#if defined(CONFIG_NAND)
|
||||
configure_module_pin_mux(nand_pin_mux);
|
||||
#elif defined(CONFIG_NOR)
|
||||
configure_module_pin_mux(bone_norcape_pin_mux);
|
||||
#else
|
||||
configure_module_pin_mux(mmc1_pin_mux);
|
||||
#endif
|
||||
} else if (board_is_gp_evm()) {
|
||||
/* General Purpose EVM */
|
||||
unsigned short profile = detect_daughter_board_profile();
|
||||
configure_module_pin_mux(rgmii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
/* In profile #2 i2c1 and spi0 conflict. */
|
||||
if (profile & ~PROFILE_2)
|
||||
configure_module_pin_mux(i2c1_pin_mux);
|
||||
/* Profiles 2 & 3 don't have NAND */
|
||||
#ifdef CONFIG_NAND
|
||||
if (profile & ~(PROFILE_2 | PROFILE_3))
|
||||
configure_module_pin_mux(nand_pin_mux);
|
||||
#endif
|
||||
else if (profile == PROFILE_2) {
|
||||
configure_module_pin_mux(mmc1_pin_mux);
|
||||
configure_module_pin_mux(spi0_pin_mux);
|
||||
}
|
||||
} else if (board_is_idk()) {
|
||||
/* Industrial Motor Control (IDK) */
|
||||
configure_module_pin_mux(mii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_no_cd_pin_mux);
|
||||
} else if (board_is_evm_sk()) {
|
||||
/* Starter Kit EVM */
|
||||
configure_module_pin_mux(i2c1_pin_mux);
|
||||
configure_module_pin_mux(gpio0_7_pin_mux);
|
||||
configure_module_pin_mux(rgmii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_pin_mux_sk_evm);
|
||||
} else if (board_is_bone_lt()) {
|
||||
/* Beaglebone LT pinmux */
|
||||
configure_module_pin_mux(mii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
|
||||
configure_module_pin_mux(nand_pin_mux);
|
||||
#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
|
||||
configure_module_pin_mux(bone_norcape_pin_mux);
|
||||
#else
|
||||
configure_module_pin_mux(mmc1_pin_mux);
|
||||
#endif
|
||||
} else if (board_is_icev2()) {
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
configure_module_pin_mux(gpio0_18_pin_mux);
|
||||
configure_module_pin_mux(uart3_icev2_pin_mux);
|
||||
configure_module_pin_mux(rmii1_pin_mux);
|
||||
configure_module_pin_mux(spi0_pin_mux);
|
||||
} else {
|
||||
puts("Unknown board, cannot configure pinmux.");
|
||||
hang();
|
||||
}
|
||||
}
|
||||
158
u-boot/board/ti/am335x/u-boot.lds
Normal file
158
u-boot/board/ti/am335x/u-boot.lds
Normal file
@@ -0,0 +1,158 @@
|
||||
/*
|
||||
* Copyright (c) 2004-2008 Texas Instruments
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.__image_copy_start)
|
||||
*(.vectors)
|
||||
CPUDIR/start.o (.text*)
|
||||
board/ti/am335x/built-in.o (.text*)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : {
|
||||
*(.data*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
. = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.__efi_runtime_start : {
|
||||
*(.__efi_runtime_start)
|
||||
}
|
||||
|
||||
.efi_runtime : {
|
||||
*(efi_runtime_text)
|
||||
*(efi_runtime_data)
|
||||
}
|
||||
|
||||
.__efi_runtime_stop : {
|
||||
*(.__efi_runtime_stop)
|
||||
}
|
||||
|
||||
.efi_runtime_rel_start :
|
||||
{
|
||||
*(.__efi_runtime_rel_start)
|
||||
}
|
||||
|
||||
.efi_runtime_rel : {
|
||||
*(.relefi_runtime_text)
|
||||
*(.relefi_runtime_data)
|
||||
}
|
||||
|
||||
.efi_runtime_rel_stop :
|
||||
{
|
||||
*(.__efi_runtime_rel_stop)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.image_copy_end :
|
||||
{
|
||||
*(.__image_copy_end)
|
||||
}
|
||||
|
||||
.rel_dyn_start :
|
||||
{
|
||||
*(.__rel_dyn_start)
|
||||
}
|
||||
|
||||
.rel.dyn : {
|
||||
*(.rel*)
|
||||
}
|
||||
|
||||
.rel_dyn_end :
|
||||
{
|
||||
*(.__rel_dyn_end)
|
||||
}
|
||||
|
||||
.hash : { *(.hash*) }
|
||||
|
||||
.end :
|
||||
{
|
||||
*(.__end)
|
||||
}
|
||||
|
||||
_image_binary_end = .;
|
||||
|
||||
/*
|
||||
* Deprecated: this MMU section is used by pxa at present but
|
||||
* should not be used by new boards/CPUs.
|
||||
*/
|
||||
. = ALIGN(4096);
|
||||
.mmutable : {
|
||||
*(.mmutable)
|
||||
}
|
||||
|
||||
/*
|
||||
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
|
||||
* __bss_base and __bss_limit are for linker only (overlay ordering)
|
||||
*/
|
||||
|
||||
.bss_start __rel_dyn_start (OVERLAY) : {
|
||||
KEEP(*(.__bss_start));
|
||||
__bss_base = .;
|
||||
}
|
||||
|
||||
.bss __bss_base (OVERLAY) : {
|
||||
*(.bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_limit = .;
|
||||
}
|
||||
|
||||
.bss_end __bss_limit (OVERLAY) : {
|
||||
KEEP(*(.__bss_end));
|
||||
}
|
||||
|
||||
.dynsym _image_binary_end : { *(.dynsym) }
|
||||
.dynbss : { *(.dynbss) }
|
||||
.dynstr : { *(.dynstr*) }
|
||||
.dynamic : { *(.dynamic*) }
|
||||
.gnu.hash : { *(.gnu.hash) }
|
||||
.plt : { *(.plt*) }
|
||||
.interp : { *(.interp*) }
|
||||
.gnu : { *(.gnu*) }
|
||||
.ARM.exidx : { *(.ARM.exidx*) }
|
||||
}
|
||||
Reference in New Issue
Block a user