avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
12
u-boot/board/technexion/twister/Kconfig
Normal file
12
u-boot/board/technexion/twister/Kconfig
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@@ -0,0 +1,12 @@
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if TARGET_TWISTER
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config SYS_BOARD
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default "twister"
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config SYS_VENDOR
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default "technexion"
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config SYS_CONFIG_NAME
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default "twister"
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endif
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6
u-boot/board/technexion/twister/MAINTAINERS
Normal file
6
u-boot/board/technexion/twister/MAINTAINERS
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@@ -0,0 +1,6 @@
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TWISTER BOARD
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M: Stefano Babic <sbabic@denx.de>
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S: Maintained
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F: board/technexion/twister/
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F: include/configs/twister.h
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F: configs/twister_defconfig
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9
u-boot/board/technexion/twister/Makefile
Normal file
9
u-boot/board/technexion/twister/Makefile
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@@ -0,0 +1,9 @@
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#
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# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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#
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# Based on ti/evm/Makefile
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := twister.o
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162
u-boot/board/technexion/twister/twister.c
Normal file
162
u-boot/board/technexion/twister/twister.c
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@@ -0,0 +1,162 @@
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/*
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* Copyright (C) 2011
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* Copyright (C) 2009 TechNexion Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/omap_gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <i2c.h>
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#include <spl.h>
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#include <mmc.h>
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#include <asm/gpio.h>
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#ifdef CONFIG_USB_EHCI
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#include <usb.h>
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#include <asm/ehci-omap.h>
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#endif
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#include "twister.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* Timing definitions for Ethernet Controller */
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static const u32 gpmc_smc911[] = {
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NET_GPMC_CONFIG1,
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NET_GPMC_CONFIG2,
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NET_GPMC_CONFIG3,
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NET_GPMC_CONFIG4,
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NET_GPMC_CONFIG5,
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NET_GPMC_CONFIG6,
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};
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static const u32 gpmc_XR16L2751[] = {
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XR16L2751_GPMC_CONFIG1,
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XR16L2751_GPMC_CONFIG2,
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XR16L2751_GPMC_CONFIG3,
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XR16L2751_GPMC_CONFIG4,
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XR16L2751_GPMC_CONFIG5,
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XR16L2751_GPMC_CONFIG6,
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};
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#ifdef CONFIG_USB_EHCI
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
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};
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
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}
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int ehci_hcd_stop(int index)
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{
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return omap_ehci_hcd_stop();
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}
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#endif
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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/* Chip select 1 and 3 are used for XR16L2751 UART controller */
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enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1],
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XR16L2751_UART1_BASE, GPMC_SIZE_16M);
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enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3],
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XR16L2751_UART2_BASE, GPMC_SIZE_16M);
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gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET");
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gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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int misc_init_r(void)
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{
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char *eth_addr;
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struct tam3517_module_info info;
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int ret;
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omap_die_id_display();
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eth_addr = getenv("ethaddr");
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if (eth_addr)
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return 0;
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TAM3517_READ_EEPROM(&info, ret);
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if (!ret)
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TAM3517_READ_MAC_FROM_EEPROM(&info);
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return 0;
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}
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#endif
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_TWISTER();
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}
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int board_eth_init(bd_t *bis)
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{
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davinci_emac_initialize();
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/* init cs for extern lan */
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enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
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CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
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if (smc911x_initialize(0, CONFIG_SMC911X_BASE) <= 0)
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printf("\nError initializing SMC911x controlleri\n");
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return 0;
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}
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#if defined(CONFIG_OMAP_HSMMC) && \
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!defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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#ifdef CONFIG_SPL_OS_BOOT
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/*
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* Do board specific preperation before SPL
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* Linux boot
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*/
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void spl_board_prepare_for_linux(void)
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{
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/* init cs for extern lan */
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enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
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CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
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}
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int spl_start_uboot(void)
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{
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int val = 0;
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if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
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gpio_direction_input(SPL_OS_BOOT_KEY);
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val = gpio_get_value(SPL_OS_BOOT_KEY);
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gpio_free(SPL_OS_BOOT_KEY);
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}
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return val;
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}
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#endif
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401
u-boot/board/technexion/twister/twister.h
Normal file
401
u-boot/board/technexion/twister/twister.h
Normal file
@@ -0,0 +1,401 @@
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/*
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* Copyright (C) 2011
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* Copyright (C) 2010 TechNexion Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TAM3517_H_
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#define _TAM3517_H_
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const omap3_sysinfo sysinfo = {
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DDR_DISCRETE,
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"TAM3517 TWISTER Board",
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"NAND",
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};
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#define XR16L2751_GPMC_CONFIG1 0x00000000
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#define XR16L2751_GPMC_CONFIG2 0x001e1e01
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#define XR16L2751_GPMC_CONFIG3 0x00080300
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#define XR16L2751_GPMC_CONFIG4 0x1c091c09
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#define XR16L2751_GPMC_CONFIG5 0x04181f1f
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#define XR16L2751_GPMC_CONFIG6 0x00000FCF
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#define XR16L2751_UART1_BASE 0x21000000
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#define XR16L2751_UART2_BASE 0x23000000
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/* GPIO used to select between U-Boot and kernel */
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#define SPL_OS_BOOT_KEY 55
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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* PTD - Pull type Down
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* M0 - Mode 0
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* The commented string gives the final mux configuration for that pin
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*/
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#define MUX_TWISTER() \
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/* SDRC */\
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_CKE0), (M0)) \
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MUX_VAL(CP(SDRC_CKE1), (M0)) \
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MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
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/*sdrc_strben_dly0*/\
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MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
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/*sdrc_strben_dly1*/\
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/* GPMC */\
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MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
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||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
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||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M2)) /*PWM9*/\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
|
||||
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
|
||||
/* DSS */\
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
|
||||
/* CAMERA */\
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
|
||||
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
|
||||
/* MMC */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
|
||||
/* CardDetect */\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
|
||||
/* McBSP */\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) /*GPIO_116*/ \
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_152*/\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) /*GPIO_155*/\
|
||||
/* UART */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) /*GPIO_163*/ \
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) /*GPIO_164*/\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
|
||||
/* I2C */\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
|
||||
/* McSPI */\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
|
||||
/* CCDC */\
|
||||
MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
|
||||
/* RMII */\
|
||||
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
|
||||
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
|
||||
MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
|
||||
/* HECC */\
|
||||
MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
|
||||
/* HSUSB */\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
|
||||
/* HDQ */\
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
|
||||
/* Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
|
||||
/* - GPIO30 */\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
|
||||
/* - VIO_1V8*/\
|
||||
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
|
||||
/* JTAG */\
|
||||
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
|
||||
MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
|
||||
/* ETK (ES2 onwards) */\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
|
||||
/* hsusb1_stp */ \
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
|
||||
/* hsusb1_clk */\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
|
||||
/* hsusb1_dir */\
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
|
||||
/* hsusb1_nxt */\
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
|
||||
/* Die to Die */\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user