avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
6
u-boot/board/seco/mx6quq7/MAINTAINERS
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6
u-boot/board/seco/mx6quq7/MAINTAINERS
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@@ -0,0 +1,6 @@
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MX6QUQ7 BOARD
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M: Boris Brezillon <boris.brezillon@free-electrons.com>
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S: Maintained
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F: board/seco/mx6quq7/
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F: include/configs/secomx6quq7.h
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F: configs/secomx6quq7_defconfig
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7
u-boot/board/seco/mx6quq7/Makefile
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7
u-boot/board/seco/mx6quq7/Makefile
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#
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# (C) Copyright 2015 ECA Sinters
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mx6quq7.o
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173
u-boot/board/seco/mx6quq7/mx6quq7-2g.cfg
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173
u-boot/board/seco/mx6quq7/mx6quq7-2g.cfg
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/*
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* Copyright (C) 2013 Seco USA Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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#define __ASSEMBLY__
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#include <config.h>
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#include "asm/arch/mx6-ddr.h"
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#include "asm/arch/iomux.h"
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#include "asm/arch/crm_regs.h"
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/* DDR IO TYPE */
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DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
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DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
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/* DATA STROBE */
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DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
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DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028
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/* DATA */
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DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
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DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B4DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B5DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B6DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B7DS, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028
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/* ADDRESS */
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DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028
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DATA 4, MX6_IOM_DRAM_CAS, 0x00000028
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DATA 4, MX6_IOM_DRAM_RAS, 0x00000028
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/* CONTROL */
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DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
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DATA 4, MX6_IOM_DRAM_RESET, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028
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/* CLOCK */
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DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
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/*
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* DDR3 SETTINGS
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* Read Data Bit Delay
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*/
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
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/* Write Leveling */
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
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/* DQS gating, read delay, write delay calibration values */
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C
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/* Read calibration */
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137
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DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45
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/* write calibration */
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741
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DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C
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/* Complete calibration by forced measurement: */
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
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/*
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* MMDC init:
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* in DDR3, 64-bit mode, only MMDC0 is init
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*/
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
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DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
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DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
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/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
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/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */
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DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
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/* Initialize DDR3 on CS_0 and CS_1 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
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/* P0 01c */
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/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
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/*ZQ - Calibrationi */
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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/* set the default clock gate to save power */
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DATA 4, CCM_CCGR0, 0x00C03F3F
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DATA 4, CCM_CCGR1, 0x0030FC03
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DATA 4, CCM_CCGR2, 0x0FFFC000
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DATA 4, CCM_CCGR3, 0x3FF00000
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DATA 4, CCM_CCGR4, 0x00FFF300
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DATA 4, CCM_CCGR5, 0x0F0000C3
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DATA 4, CCM_CCGR6, 0x000003FF
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
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DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
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179
u-boot/board/seco/mx6quq7/mx6quq7.c
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179
u-boot/board/seco/mx6quq7/mx6quq7.c
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@@ -0,0 +1,179 @@
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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* Copyright (C) 2015 ECA Sinters
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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* Modified by: Boris Brezillon <boris.brezillon@free-electrons.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/boot_mode.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <linux/fb.h>
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#include <ipu_pixfmt.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <micrel.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <i2c.h>
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#include "../common/mx6.h"
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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int board_early_init_f(void)
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{
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seco_mx6_setup_uart_iomux();
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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seco_mx6_rgmii_rework(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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uint32_t base = IMX_FEC_BASE;
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struct mii_dev *bus = NULL;
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struct phy_device *phydev = NULL;
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int ret = 0;
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seco_mx6_setup_enet_iomux();
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#ifdef CONFIG_FEC_MXC
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bus = fec_get_miibus(base, -1);
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if (!bus)
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return -ENOMEM;
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/* scan phy 4,5,6,7 */
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phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
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if (!phydev) {
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free(bus);
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return -ENOMEM;
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}
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printf("using phy at %d\n", phydev->addr);
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ret = fec_probe(bis, -1, base, bus, phydev);
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if (ret) {
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free(phydev);
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free(bus);
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printf("FEC MXC: %s:failed\n", __func__);
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}
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#endif
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return ret;
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}
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#define USDHC4_CD_GPIO IMX_GPIO_NR(2, 6)
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static struct fsl_esdhc_cfg usdhc_cfg[2] = {
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{USDHC3_BASE_ADDR, 0, 4},
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{USDHC4_BASE_ADDR, 0, 4},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC3_BASE_ADDR:
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ret = 1; /* Assume eMMC is always present */
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break;
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case USDHC4_BASE_ADDR:
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ret = !gpio_get_value(USDHC4_CD_GPIO);
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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u32 index = 0;
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int ret;
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/*
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* Following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 eMMC on Board
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* mmc1 Ext SD
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*/
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for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
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switch (index) {
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case 0:
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seco_mx6_setup_usdhc_iomux(3);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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break;
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case 1:
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seco_mx6_setup_usdhc_iomux(4);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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break;
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default:
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printf("Warning: %d exceed maximum number of SD ports %d\n",
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index + 1, CONFIG_SYS_FSL_USDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D4__GPIO2_IO04 |
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MUX_PAD_CTRL(NO_PAD_CTRL));
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gpio_direction_output(IMX_GPIO_NR(2, 4), 0);
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/* Set Low */
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gpio_set_value(IMX_GPIO_NR(2, 4), 0);
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udelay(1000);
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/* Set High */
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gpio_set_value(IMX_GPIO_NR(2, 4), 1);
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: SECO uQ7\n");
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return 0;
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}
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Reference in New Issue
Block a user