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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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12
u-boot/board/renesas/r7780mp/Kconfig Normal file
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if TARGET_R7780MP
config SYS_BOARD
default "r7780mp"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "r7780mp"
endif

7
u-boot/board/renesas/r7780mp/MAINTAINERS Normal file
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R7780MP BOARD
M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
S: Maintained
F: board/renesas/r7780mp/
F: include/configs/r7780mp.h
F: configs/r7780mp_defconfig

9
u-boot/board/renesas/r7780mp/Makefile Normal file
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#
# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
#
# board/r7780mp/Makefile
#
# SPDX-License-Identifier: GPL-2.0+
obj-y := r7780mp.o
obj-y += lowlevel_init.o

357
u-boot/board/renesas/r7780mp/lowlevel_init.S Normal file
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/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu
*
* u-boot/board/r7780mp/lowlevel_init.S
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <asm/processor.h>
#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
.text
.align 2
lowlevel_init:
write32 CCR_A, CCR_D /* Address of Cache Control Register */
/* Instruction Cache Invalidate */
write32 FRQCR_A, FRQCR_D /* Frequency control register */
/* pin_multi_setting */
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
write32 BBG_PMSR1_A, BBG_PMSR1_D
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
write32 BBG_PMSR2_A, BBG_PMSR2_D
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
write32 BBG_PMSR3_A, BBG_PMSR3_D
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
write32 BBG_PMSR4_A, BBG_PMSR4_D
write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
write32 BBG_PMSRG_A, BBG_PMSRG_D
/* cpg_setting */
write32 FRQCR_A, FRQCR_D
write32 DLLCSR_A, DLLCSR_D
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
/* wait 200us */
mov.l REPEAT0_R3, r3
mov #0, r2
repeat0:
add #1, r2
cmp/hs r3, r2
bf repeat0
nop
/* bsc_setting */
write32 MMSELR_A, MMSELR_D
write32 BCR_A, BCR_D
write32 CS0BCR_A, CS0BCR_D
write32 CS1BCR_A, CS1BCR_D
write32 CS2BCR_A, CS2BCR_D
write32 CS4BCR_A, CS4BCR_D
write32 CS5BCR_A, CS5BCR_D
write32 CS6BCR_A, CS6BCR_D
write32 CS0WCR_A, CS0WCR_D
write32 CS1WCR_A, CS1WCR_D
write32 CS2WCR_A, CS2WCR_D
write32 CS4WCR_A, CS4WCR_D
write32 CS5WCR_A, CS5WCR_D
write32 CS6WCR_A, CS6WCR_D
write32 CS5PCR_A, CS5PCR_D
write32 CS6PCR_A, CS6PCR_D
/* ddr_setting */
/* wait 200us */
mov.l REPEAT0_R3, r3
mov #0, r2
repeat1:
add #1, r2
cmp/hs r3, r2
bf repeat1
nop
mov.l MIM_U_A, r0
mov.l MIM_U_D, r1
synco
mov.l r1, @r0
synco
mov.l MIM_L_A, r0
mov.l MIM_L_D0, r1
synco
mov.l r1, @r0
synco
mov.l STR_L_A, r0
mov.l STR_L_D, r1
synco
mov.l r1, @r0
synco
mov.l SDR_L_A, r0
mov.l SDR_L_D, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
nop
mov.l SCR_L_A, r0
mov.l SCR_L_D0, r1
synco
mov.l r1, @r0
synco
mov.l SCR_L_A, r0
mov.l SCR_L_D1, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l EMRS_A, r0
mov.l EMRS_D, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l MRS1_A, r0
mov.l MRS1_D, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A, r0
mov.l SCR_L_D2, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A, r0
mov.l SCR_L_D3, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A, r0
mov.l SCR_L_D4, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l MRS2_A, r0
mov.l MRS2_D, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A, r0
mov.l SCR_L_D5, r1
synco
mov.l r1, @r0
synco
/* wait 200us */
mov.l REPEAT0_R1, r3
mov #0, r2
repeat2:
add #1, r2
cmp/hs r3, r2
bf repeat2
synco
mov.l MIM_L_A, r0
mov.l MIM_L_D1, r1
synco
mov.l r1, @r0
synco
rts
nop
.align 4
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA507
RWTCNT_D: .word 0x5A00
.align 2
BBG_PMMR_A: .long 0xFF800010
BBG_PMSR1_A: .long 0xFF800014
BBG_PMSR2_A: .long 0xFF800018
BBG_PMSR3_A: .long 0xFF80001C
BBG_PMSR4_A: .long 0xFF800020
BBG_PMSRG_A: .long 0xFF800024
BBG_PMMR_D_PMSR1: .long 0xffffbffd
BBG_PMSR1_D: .long 0x00004002
BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
BBG_PMSR2_D: .long 0x03de5800
BBG_PMMR_D_PMSR3: .long 0xfffffff8
BBG_PMSR3_D: .long 0x00000007
BBG_PMMR_D_PMSR4: .long 0xdffdfff9
BBG_PMSR4_D: .long 0x20020006
BBG_PMMR_D_PMSRG: .long 0xffffffff
BBG_PMSRG_D: .long 0x00000000
FRQCR_A: .long FRQCR
DLLCSR_A: .long 0xffc40010
FRQCR_D: .long 0x40233035
DLLCSR_D: .long 0x00000000
/* for DDR-SDRAM */
MIM_U_A: .long MIM_1
MIM_L_A: .long MIM_2
SCR_U_A: .long SCR_1
SCR_L_A: .long SCR_2
STR_U_A: .long STR_1
STR_L_A: .long STR_2
SDR_U_A: .long SDR_1
SDR_L_A: .long SDR_2
EMRS_A: .long 0xFEC02000
MRS1_A: .long 0xFEC00B08
MRS2_A: .long 0xFEC00308
MIM_U_D: .long 0x00004000
MIM_L_D0: .long 0x03e80009
MIM_L_D1: .long 0x03e80209
SCR_L_D0: .long 0x3
SCR_L_D1: .long 0x2
SCR_L_D2: .long 0x2
SCR_L_D3: .long 0x4
SCR_L_D4: .long 0x4
SCR_L_D5: .long 0x0
STR_L_D: .long 0x000f0000
SDR_L_D: .long 0x00000400
EMRS_D: .long 0x0
MRS1_D: .long 0x0
MRS2_D: .long 0x0
/* Cache Controller */
CCR_A: .long CCR
MMUCR_A: .long MMUCR
RWTCNT_A: .long WTCNT
CCR_D: .long 0x0000090b
CCR_D_2: .long 0x00000103
MMUCR_D: .long 0x00000004
MSTPCR0_D: .long 0x00001001
MSTPCR2_D: .long 0xffffffff
/* local Bus State Controller */
MMSELR_A: .long MMSELR
BCR_A: .long BCR
CS0BCR_A: .long CS0BCR
CS1BCR_A: .long CS1BCR
CS2BCR_A: .long CS2BCR
CS4BCR_A: .long CS4BCR
CS5BCR_A: .long CS5BCR
CS6BCR_A: .long CS6BCR
CS0WCR_A: .long CS0WCR
CS1WCR_A: .long CS1WCR
CS2WCR_A: .long CS2WCR
CS4WCR_A: .long CS4WCR
CS5WCR_A: .long CS5WCR
CS6WCR_A: .long CS6WCR
CS5PCR_A: .long CS5PCR
CS6PCR_A: .long CS6PCR
MMSELR_D: .long 0xA5A50003
BCR_D: .long 0x00000000
CS0BCR_D: .long 0x77777770
CS1BCR_D: .long 0x77777670
CS2BCR_D: .long 0x77777770
CS4BCR_D: .long 0x77777770
CS5BCR_D: .long 0x77777670
CS6BCR_D: .long 0x77777770
CS0WCR_D: .long 0x00020006
CS1WCR_D: .long 0x00232304
CS2WCR_D: .long 0x7777770F
CS4WCR_D: .long 0x7777770F
CS5WCR_D: .long 0x00101006
CS6WCR_D: .long 0x77777703
CS5PCR_D: .long 0x77000000
CS6PCR_D: .long 0x77000000
REPEAT0_R3: .long 0x00002000
REPEAT0_R1: .long 0x0000200

73
u-boot/board/renesas/r7780mp/r7780mp.c Normal file
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/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ide.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <netdev.h>
#include "r7780mp.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
#if defined(CONFIG_R7780MP)
puts("BOARD: Renesas Solutions R7780MP\n");
#else
puts("BOARD: Renesas Solutions R7780RP\n");
#endif
return 0;
}
int board_init(void)
{
/* SCIF Enable */
writew(0x0, PHCR);
return 0;
}
int dram_init(void)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
return 0;
}
void led_set_state(unsigned short value)
{
}
void ide_set_reset(int idereset)
{
/* if reset = 1 IDE reset will be asserted */
if (idereset) {
writew(0x432, FPGA_CFCTL);
#if defined(CONFIG_R7780MP)
writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW);
#else
writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW);
#endif
writew(0x01, FPGA_CFCDINTCLR);
}
}
static struct pci_controller hose;
void pci_init_board(void)
{
pci_sh7780_init(&hose);
}
int board_eth_init(bd_t *bis)
{
/* return >= 0 if a chip is found, the board's AX88796L is n2k-based */
return ne2k_register() + pci_eth_init(bis);
}

41
u-boot/board/renesas/r7780mp/r7780mp.h Normal file
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/*
* Copyright (C) 2007 Nobuhiro Iwamatsu
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* u-boot/board/r7780mp/r7780mp.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BOARD_R7780MP_R7780MP_H_
#define _BOARD_R7780MP_R7780MP_H_
/* R7780MP's FPGA register map */
#define FPGA_BASE 0xa4000000
#define FPGA_IRLMSK (FPGA_BASE + 0x00)
#define FPGA_IRLMON (FPGA_BASE + 0x02)
#define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
#define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
#define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
#define FPGA_RSTCTL (FPGA_BASE + 0x0C)
#define FPGA_PCIBD (FPGA_BASE + 0x0E)
#define FPGA_PCICD (FPGA_BASE + 0x10)
#define FPGA_EXTGIO (FPGA_BASE + 0x16)
#define FPGA_IVDRMON (FPGA_BASE + 0x18)
#define FPGA_IVDRCR (FPGA_BASE + 0x1A)
#define FPGA_OBLED (FPGA_BASE + 0x1C)
#define FPGA_OBSW (FPGA_BASE + 0x1E)
#define FPGA_TPCTL (FPGA_BASE + 0x100)
#define FPGA_TPDCKCTL (FPGA_BASE + 0x102)
#define FPGA_TPCLR (FPGA_BASE + 0x104)
#define FPGA_TPXPOS (FPGA_BASE + 0x106)
#define FPGA_TPYPOS (FPGA_BASE + 0x108)
#define FPGA_DBSW (FPGA_BASE + 0x200)
#define FPGA_VERSION (FPGA_BASE + 0x700)
#define FPGA_CFCTL (FPGA_BASE + 0x300)
#define FPGA_CFPOW (FPGA_BASE + 0x302)
#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304)
#define FPGA_PMR (FPGA_BASE + 0x900)
#endif /* _BOARD_R7780RP_R7780RP_H_ */