avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions

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if TARGET_AP121
config SYS_VENDOR
default "qca"
config SYS_BOARD
default "ap121"
config SYS_CONFIG_NAME
default "ap121"
config SYS_TEXT_BASE
default 0x9f000000
config SYS_DCACHE_SIZE
default 32768
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 65536
config SYS_ICACHE_LINE_SIZE
default 32
endif

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AP121 BOARD
M: Wills Wang <wills.wang@live.com>
S: Maintained
F: board/qca/ap121/
F: include/configs/ap121.h
F: configs/ap121_defconfig

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#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = ap121.o

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/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/ddr.h>
#include <mach/ath79.h>
#include <debug_uart.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
void __iomem *regs;
u32 val;
regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
MAP_NOCACHE);
/*
* GPIO9 as input, GPIO10 as output
*/
val = readl(regs + AR71XX_GPIO_REG_OE);
val &= ~AR933X_GPIO(9);
val |= AR933X_GPIO(10);
writel(val, regs + AR71XX_GPIO_REG_OE);
/*
* Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
*/
val = readl(regs + AR71XX_GPIO_REG_FUNC);
val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
writel(val, regs + AR71XX_GPIO_REG_FUNC);
}
#endif
int board_early_init_f(void)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
ddr_init();
ath79_eth_reset();
return 0;
}