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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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12
u-boot/board/logicpd/am3517evm/Kconfig Normal file
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if TARGET_AM3517_EVM
config SYS_BOARD
default "am3517evm"
config SYS_VENDOR
default "logicpd"
config SYS_CONFIG_NAME
default "am3517_evm"
endif

6
u-boot/board/logicpd/am3517evm/MAINTAINERS Normal file
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AM3517EVM BOARD
M: Vaibhav Hiremath <hvaibhav@ti.com>
S: Maintained
F: board/logicpd/am3517evm/
F: include/configs/am3517_evm.h
F: configs/am3517_evm_defconfig

11
u-boot/board/logicpd/am3517evm/Makefile Normal file
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#
# Author: Vaibhav Hiremath <hvaibhav@ti.com>
#
# Based on ti/evm/Makefile
#
# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := am3517evm.o

177
u-boot/board/logicpd/am3517evm/am3517evm.c Normal file
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/*
* am3517evm.c - board file for TI's AM3517 family of devices.
*
* Author: Vaibhav Hiremath <hvaibhav@ti.com>
*
* Based on ti/evm/evm.c
*
* Copyright (C) 2010
* Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/omap_musb.h>
#include <asm/arch/am35x_def.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/musb.h>
#include <asm/mach-types.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
#include <i2c.h>
#include <netdev.h>
#include "am3517evm.h"
DECLARE_GLOBAL_DATA_PTR;
#define AM3517_IP_SW_RESET 0x48002598
#define CPGMACSS_SW_RST (1 << 1)
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
return 0;
}
#ifdef CONFIG_USB_MUSB_AM35X
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
.num_eps = 16,
.ram_bits = 12,
};
static struct omap_musb_board_data musb_board_data = {
.set_phy_power = am35x_musb_phy_power,
.clear_irq = am35x_musb_clear_irq,
.reset = am35x_musb_reset,
};
static struct musb_hdrc_platform_data musb_plat = {
#if defined(CONFIG_USB_MUSB_HOST)
.mode = MUSB_HOST,
#elif defined(CONFIG_USB_MUSB_GADGET)
.mode = MUSB_PERIPHERAL,
#else
#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
#endif
.config = &musb_config,
.power = 250,
.platform_ops = &am35x_ops,
.board_data = &musb_board_data,
};
static void am3517_evm_musb_init(void)
{
/*
* Set up USB clock/mode in the DEVCONF2 register.
* USB2.0 PHY reference clock is 13 MHz
*/
clrsetbits_le32(&am35x_scm_general_regs->devconf2,
CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
CONF2_VBDTCTEN | CONF2_DATPOL);
musb_register(&musb_plat, &musb_board_data,
(void *)AM35XX_IPSS_USBOTGSS_BASE);
}
#else
#define am3517_evm_musb_init() do {} while (0)
#endif
/*
* Routine: misc_init_r
* Description: Init i2c, ethernet, etc... (done here so udelay works)
*/
int misc_init_r(void)
{
volatile unsigned int ctr;
u32 reset;
#ifdef CONFIG_SYS_I2C_OMAP34XX
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
omap_die_id_display();
am3517_evm_musb_init();
/* activate PHY reset */
gpio_direction_output(30, 0);
gpio_set_value(30, 0);
ctr = 0;
do {
udelay(1000);
ctr++;
} while (ctr < 300);
/* deactivate PHY reset */
gpio_set_value(30, 1);
/* allow the PHY to stabilize and settle down */
ctr = 0;
do {
udelay(1000);
ctr++;
} while (ctr < 300);
/* ensure that the module is out of reset */
reset = readl(AM3517_IP_SW_RESET);
reset &= (~CPGMACSS_SW_RST);
writel(reset,AM3517_IP_SW_RESET);
return 0;
}
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_AM3517EVM();
}
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
rv = cpu_eth_init(bis);
if (rv > 0)
n += rv;
rv = usb_eth_initialize(bis);
if (rv > 0)
n += rv;
return n;
}
#endif

393
u-boot/board/logicpd/am3517evm/am3517evm.h Normal file
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/*
* am3517evm.h - Header file for the AM3517 EVM.
*
* Author: Vaibhav Hiremath <hvaibhav@ti.com>
*
* Based on ti/evm/evm.h
*
* Copyright (C) 2010
* Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _AM3517EVM_H_
#define _AM3517EVM_H_
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"AM3517EVM Board",
"NAND",
};
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
#define MUX_AM3517EVM() \
/* SDRC */\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_CKE0), (M0)) \
MUX_VAL(CP(SDRC_CKE1), (M0)) \
/*sdrc_strben_dly0*/\
MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly1*/\
MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
/* GPMC */\
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
/* - ETH_nRESET*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
/* DSS */\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
/* CAMERA */\
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
/* - CAM_RESET*/\
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
/* MMC */\
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
/* WriteProtect */\
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*CardDetect*/\
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \
/* McBSP */\
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
/* - LCD_INI*/\
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
/* - LCD_ENVDD */\
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
/* - LCD_QVGA/nVGA */\
MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
/* - LCD_RESB */\
/* UART */\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
\
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
/* I2C */\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
/* McSPI */\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
/* - LAN_INTR*/\
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \
\
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
/* CCDC */\
MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
/* RMII */\
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
/* HECC */\
MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
/* HSUSB */\
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
/* HDQ */\
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
/* Control and debug */\
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
/*SYS_nRESWARM */\
MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \
/* - GPIO30 */\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
/* - PEN_IRQ */\
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
/* - VIO_1V8*/\
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
/* ETK (ES2 onwards) */\
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \
/* Die to Die */\
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
#endif

12
u-boot/board/logicpd/omap3som/Kconfig Normal file
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@@ -0,0 +1,12 @@
if TARGET_OMAP3_LOGIC
config SYS_BOARD
default "omap3som"
config SYS_VENDOR
default "logicpd"
config SYS_CONFIG_NAME
default "omap3_logic"
endif

6
u-boot/board/logicpd/omap3som/MAINTAINERS Normal file
View File

@@ -0,0 +1,6 @@
OMAP3SOM BOARD
M: Adam Ford <aford173@gmail.com>
S: Maintained
F: board/logicpd/omap3som/
F: include/configs/omap3_logic.h
F: configs/omap3_logic_defconfig

8
u-boot/board/logicpd/omap3som/Makefile Normal file
View File

@@ -0,0 +1,8 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := omap3logic.o

621
u-boot/board/logicpd/omap3som/omap3logic.c Normal file
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@@ -0,0 +1,621 @@
/*
* (C) Copyright 2011
* Logic Product Development <www.logicpd.com>
*
* Author :
* Peter Barada <peter.barada@logicpd.com>
*
* Derived from Beagle Board and 3430 SDP code by
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <ns16550.h>
#include <netdev.h>
#include <flash.h>
#include <nand.h>
#include <i2c.h>
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include <linux/mtd/nand.h>
#include <asm/omap_musb.h>
#include <asm/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
#include "omap3logic.h"
DECLARE_GLOBAL_DATA_PTR;
#define CONTROL_WKUP_CTRL 0x48002a5c
#define GPIO_IO_PWRDNZ (1 << 6)
#define PBIASLITEVMODE1 (1 << 8)
/*
* two dimensional array of strucures containining board name and Linux
* machine IDs; row it selected based on CPU column is slected based
* on hsusb0_data5 pin having a pulldown resistor
*/
static const struct ns16550_platdata omap3logic_serial = {
.base = OMAP34XX_UART1,
.reg_shift = 2,
.clock = V_NS16550_CLK
};
U_BOOT_DEVICE(omap3logic_uart) = {
"ns16550_serial",
&omap3logic_serial
};
static struct board_id {
char *name;
int machine_id;
} boards[2][2] = {
{
{
.name = "OMAP35xx SOM LV",
.machine_id = MACH_TYPE_OMAP3530_LV_SOM,
},
{
.name = "OMAP35xx Torpedo",
.machine_id = MACH_TYPE_OMAP3_TORPEDO,
},
},
{
{
.name = "DM37xx SOM LV",
.machine_id = MACH_TYPE_DM3730_SOM_LV,
},
{
.name = "DM37xx Torpedo",
.machine_id = MACH_TYPE_DM3730_TORPEDO,
},
},
};
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
return serial_tstc() && serial_getc() == 'c';
}
#endif
#if defined(CONFIG_SPL_BUILD)
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on the first bank. This
* provides the timing values back to the function that configures
* the memory.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
timings->mr = MICRON_V_MR_165;
/* 256MB DDR */
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
}
#endif
#ifdef CONFIG_USB_MUSB_OMAP2PLUS
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
.num_eps = 16,
.ram_bits = 12,
};
static struct omap_musb_board_data musb_board_data = {
.interface_type = MUSB_INTERFACE_ULPI,
};
static struct musb_hdrc_platform_data musb_plat = {
#if defined(CONFIG_USB_MUSB_HOST)
.mode = MUSB_HOST,
#elif defined(CONFIG_USB_MUSB_GADGET)
.mode = MUSB_PERIPHERAL,
#else
#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
#endif
.config = &musb_config,
.power = 100,
.platform_ops = &omap2430_ops,
.board_data = &musb_board_data,
};
#endif
/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
int misc_init_r(void)
{
t2_t *t2_base = (t2_t *)T2_BASE;
u32 pbias_lite;
/* set up dual-voltage GPIOs to 1.8V */
pbias_lite = readl(&t2_base->pbias_lite);
pbias_lite &= ~PBIASLITEVMODE1;
pbias_lite |= PBIASLITEPWRDNZ1;
writel(pbias_lite, &t2_base->pbias_lite);
if (get_cpu_family() == CPU_OMAP36XX)
writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
CONTROL_WKUP_CTRL);
twl4030_power_init();
omap_die_id_display();
putc('\n');
#ifdef CONFIG_USB_MUSB_OMAP2PLUS
musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
#endif
return 0;
}
/*
* BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
*/
#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
struct board_id *board;
unsigned int val;
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
/*
* To identify between a SOM LV and Torpedo module,
* a pulldown resistor is on hsusb0_data5 for the SOM LV module.
* Drive the pin (and let it soak), then read it back.
* If the pin is still high its a Torpedo. If low its a SOM LV
*/
/* Mux hsusb0_data5 as a GPIO */
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
/*
* Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
* will drain the voltage.
*/
gpio_direction_output(BOARD_ID_GPIO, 0);
gpio_set_value(BOARD_ID_GPIO, 1);
/* Let it soak for a bit */
sdelay(0x100);
/*
* Read state of BOARD_ID_GPIO as an input and if its set.
* If so the board is a Torpedo
*/
gpio_direction_input(BOARD_ID_GPIO);
val = gpio_get_value(BOARD_ID_GPIO);
gpio_free(BOARD_ID_GPIO);
board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
printf("Board: %s\n", board->name);
/* Set the machine_id passed to Linux */
gd->bd->bi_arch_number = board->machine_id;
}
/* restore hsusb0_data5 pin as hsusb0_data5 */
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
switch (gd->bd->bi_arch_number) {
case MACH_TYPE_DM3730_TORPEDO:
setenv("fdtimage", "logicpd-torpedo-37xx-devkit.dtb");
break;
case MACH_TYPE_DM3730_SOM_LV:
setenv("fdtimage", "logicpd-som-lv-37xx-devkit.dtb");
break;
case MACH_TYPE_OMAP3_TORPEDO:
setenv("fdtimage", "logicpd-torpedo-35xx-devkit.dtb");
break;
case MACH_TYPE_OMAP3530_LV_SOM:
setenv("fdtimage", "logicpd-som-lv-35xx-devkit.dtb");
break;
default:
/* unknown machine type */
break;
}
return 0;
}
#endif
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_GENERIC_MMC)
void board_mmc_power_init(void)
{
twl4030_power_mmc_init(0);
}
#endif
#ifdef CONFIG_SMC911X
/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
static const u32 gpmc_lan92xx_config[] = {
NET_LAN92XX_GPMC_CONFIG1,
NET_LAN92XX_GPMC_CONFIG2,
NET_LAN92XX_GPMC_CONFIG3,
NET_LAN92XX_GPMC_CONFIG4,
NET_LAN92XX_GPMC_CONFIG5,
NET_LAN92XX_GPMC_CONFIG6,
};
int board_eth_init(bd_t *bis)
{
enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
#endif
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/
MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /*CAM_HS */
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /*CAM_VS */
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /*CAM_XCLKA*/
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /*CAM_PCLK*/
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)); /*GPIO_98*/
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /*CAM_D0*/
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /*CAM_D1*/
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /*CAM_D2*/
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /*CAM_D3*/
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /*CAM_D4*/
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /*CAM_D5*/
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /*CAM_D6*/
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /*CAM_D7*/
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /*CAM_D8*/
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /*CAM_D9*/
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /*CAM_D10*/
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /*CAM_D11*/
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /*CAM_XCLKB*/
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /*GPIO_167*/
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /*CAM_STROBE*/
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /*CSI2_DX0*/
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /*CSI2_DY0*/
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /*CSI2_DX1*/
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /*CSI2_DY1*/
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /*McBSP2_FSX*/
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)); /*McBSP2_CLKX*/
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /*McBSP2_DR*/
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /*McBSP2_DX*/
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /*MMC2_CLK*/
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /*MMC2_CMD*/
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /*MMC2_DAT0*/
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /*MMC2_DAT1*/
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /*MMC2_DAT2*/
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /*MMC2_DAT3*/
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)); /*MMC2_DAT4*/
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)); /*MMC2_DAT5*/
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)); /*MMC2_DAT6 */
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)); /*MMC2_DAT7*/
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)); /*McBSP3_DX*/
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)); /*McBSP3_DR*/
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)); /*McBSP3_CLKX*/
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)); /*McBSP3_FSX*/
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /*UART2_CTS*/
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /*UART2_RTS*/
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /*UART2_TX*/
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /*UART2_RX*/
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)); /*GPIO_153*/
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKR*/
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)); /*MCBSP1_FSR*/
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)); /*MCBSP1_DX*/
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /*MCBSP1_DR*/
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)); /*MCBSP_CLKS*/
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)); /*MCBSP1_FSX*/
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKX*/
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); /*UART3_CTS_*/
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); /*UART3_RTS_SD */
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX_IRRX*/
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX_IRTX*/
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /*I2C4_SCL*/
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /*I2C4_SDA*/
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /*HDQ_SIO*/
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)); /*McSPI1_CLK*/
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)); /*McSPI1_SIMO */
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)); /*McSPI1_SOMI */
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)); /*McSPI1_CS0*/
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)); /*GPIO_175*/
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)); /*GPIO_176*/
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*McSPI1_CS3*/
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*McSPI2_CLK*/
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*McSPI2_SIMO*/
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*McSPI2_SOMI*/
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*McSPI2_CS0*/
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*McSPI2_CS1*/
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /*GPIO_2*/
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /*GPIO_3 */
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /*GPIO_4*/
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /*GPIO_5*/
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /*GPIO_6*/
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /*GPIO_7*/
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*SYS_OFF_MODE*/
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*SYS_CLKOUT1*/
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); /*SYS_CLKOUT2*/
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/
}

31
u-boot/board/logicpd/omap3som/omap3logic.h Normal file
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/*
* (C) Copyright 2011
* Logic Product Development <www.logicpd.com>
*
* Author:
* Peter Barada <peter.barada@logicpd.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _OMAP3LOGIC_H_
#define _OMAP3LOGIC_H_
/*
* OMAP3 GPMC register settings for CS1 LAN922x
*/
#define NET_LAN92XX_GPMC_CONFIG1 0x00001000
#define NET_LAN92XX_GPMC_CONFIG2 0x00080801
#define NET_LAN92XX_GPMC_CONFIG3 0x00000000
#define NET_LAN92XX_GPMC_CONFIG4 0x08010801
#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
#define NET_LAN92XX_GPMC_CONFIG6 0x03000280
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"Logic DM37x/OMAP35x reference board",
"NAND",
};
#endif

12
u-boot/board/logicpd/zoom1/Kconfig Normal file
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if TARGET_OMAP3_ZOOM1
config SYS_BOARD
default "zoom1"
config SYS_VENDOR
default "logicpd"
config SYS_CONFIG_NAME
default "omap3_zoom1"
endif

6
u-boot/board/logicpd/zoom1/MAINTAINERS Normal file
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@@ -0,0 +1,6 @@
ZOOM1 BOARD
M: Nishanth Menon <nm@ti.com>
S: Maintained
F: board/logicpd/zoom1/
F: include/configs/omap3_zoom1.h
F: configs/omap3_zoom1_defconfig

8
u-boot/board/logicpd/zoom1/Makefile Normal file
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@@ -0,0 +1,8 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := zoom1.o

16
u-boot/board/logicpd/zoom1/config.mk Normal file
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#
# (C) Copyright 2006-2008
# Texas Instruments, <www.ti.com>
#
# Zoom MDK uses OMAP3 (ARM-CortexA8) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# SPDX-License-Identifier: GPL-2.0+
#
# Physical Address:
# 8000'0000 (bank0)
# A000/0000 (bank1)
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
# For use with external or internal boots.

144
u-boot/board/logicpd/zoom1/zoom1.c Normal file
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/*
* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
*
* Author :
* Nishanth Menon <nm@ti.com>
*
* Derived from Beagle Board and 3430 SDP code by
* Sunil Kumar <sunilsaini05@gmail.com>
* Shashi Ranjan <shashiranjanmca05@gmail.com>
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <ns16550.h>
#include <netdev.h>
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-types.h>
#include "zoom1.h"
DECLARE_GLOBAL_DATA_PTR;
/* gpmc_cfg is initialized by gpmc_init and we use it here */
extern struct gpmc *gpmc_cfg;
/* GPMC definitions for Ethenet Controller LAN9211 */
static const u32 gpmc_lab_enet[] = {
ZOOM1_ENET_GPMC_CONF1,
ZOOM1_ENET_GPMC_CONF2,
ZOOM1_ENET_GPMC_CONF3,
ZOOM1_ENET_GPMC_CONF4,
ZOOM1_ENET_GPMC_CONF5,
ZOOM1_ENET_GPMC_CONF6,
/*CONF7- computed as params */
};
static const struct ns16550_platdata zoom1_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK
};
U_BOOT_DEVICE(zoom1_uart) = {
"ns16550_serial",
&zoom1_serial
};
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* CS1 is Ethernet LAN9211 */
enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
DEBUG_BASE, GPMC_SIZE_16M);
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
return 0;
}
/*
* Routine: misc_init_r
* Description: Configure zoom board specific configurations
*/
int misc_init_r(void)
{
twl4030_power_init();
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
omap_die_id_display();
/*
* Board Reset
* The board is reset by holding the red button on the
* top right front face for eight seconds.
*/
twl4030_power_reset_init();
return 0;
}
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
/* platform specific muxes */
MUX_ZOOM1_MDK();
}
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
void board_mmc_power_init(void)
{
twl4030_power_mmc_init(0);
}
#endif
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
#define STR_ENV_ETHADDR "ethaddr"
struct eth_device *dev;
uchar eth_addr[6];
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
dev = eth_get_dev_by_index(0);
if (dev) {
eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
} else {
printf("zoom1: Couldn't get eth device\n");
rc = -1;
}
}
#endif
return rc;
}
#endif

123
u-boot/board/logicpd/zoom1/zoom1.h Normal file
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/*
* (C) Copyright 2008
* Texas Instruments
* Nishanth Menon <nm@ti.com>
*
* Derived from: board/omap3/beagle/beagle.h
* Dirk Behme <dirk.behme@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BOARD_ZOOM1_H_
#define _BOARD_ZOOM1_H_
const omap3_sysinfo sysinfo = {
DDR_STACKED,
"OMAP3 Zoom MDK Rev 1",
"NAND",
};
#define ZOOM1_ENET_GPMC_CONF1 0x00611000
#define ZOOM1_ENET_GPMC_CONF2 0x001F1F01
#define ZOOM1_ENET_GPMC_CONF3 0x00080803
#define ZOOM1_ENET_GPMC_CONF4 0x1D091D09
#define ZOOM1_ENET_GPMC_CONF5 0x041D1F1F
#define ZOOM1_ENET_GPMC_CONF6 0x1D0904C4
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
#define MUX_ZOOM1_MDK() \
/*SDRC*/\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
/*GPMC*/\
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /*GPMC_nWP*/\
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /*GPMC_WAIT0*/\
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/
#endif /* _BOARD_ZOOM_H_ */