avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
12
u-boot/board/isee/igep00x0/Kconfig
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12
u-boot/board/isee/igep00x0/Kconfig
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@@ -0,0 +1,12 @@
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if TARGET_OMAP3_IGEP00X0
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config SYS_BOARD
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default "igep00x0"
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config SYS_VENDOR
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default "isee"
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config SYS_CONFIG_NAME
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default "omap3_igep00x0"
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endif
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14
u-boot/board/isee/igep00x0/MAINTAINERS
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14
u-boot/board/isee/igep00x0/MAINTAINERS
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@@ -0,0 +1,14 @@
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IGEP00X0 BOARD
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M: Enric Balletbo i Serra <eballetbo@gmail.com>
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S: Maintained
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F: board/isee/igep00x0/
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F: include/configs/omap3_igep00x0.h
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F: configs/igep0020_defconfig
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F: configs/igep0030_defconfig
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F: configs/igep0032_defconfig
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IGEP0020_NAND BOARD
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#M: -
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S: Maintained
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F: configs/igep0020_nand_defconfig
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F: configs/igep0030_nand_defconfig
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8
u-boot/board/isee/igep00x0/Makefile
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8
u-boot/board/isee/igep00x0/Makefile
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@@ -0,0 +1,8 @@
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := igep00x0.o
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214
u-boot/board/isee/igep00x0/igep00x0.c
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214
u-boot/board/isee/igep00x0/igep00x0.c
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@@ -0,0 +1,214 @@
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/*
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* (C) Copyright 2010
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* ISEE 2007 SL, <www.iseebcn.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <status_led.h>
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#include <dm.h>
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#include <ns16550.h>
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#include <twl4030.h>
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#include <netdev.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-types.h>
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#include "igep00x0.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CMD_NET)
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/* GPMC definitions for LAN9221 chips */
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static const u32 gpmc_lan_config[] = {
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NET_LAN9221_GPMC_CONFIG1,
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NET_LAN9221_GPMC_CONFIG2,
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NET_LAN9221_GPMC_CONFIG3,
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NET_LAN9221_GPMC_CONFIG4,
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NET_LAN9221_GPMC_CONFIG5,
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NET_LAN9221_GPMC_CONFIG6,
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};
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#endif
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static const struct ns16550_platdata igep_serial = {
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.base = OMAP34XX_UART3,
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.reg_shift = 2,
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.clock = V_NS16550_CLK
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};
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U_BOOT_DEVICE(igep_uart) = {
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"ns16550_serial",
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&igep_serial
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};
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
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status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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/*
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* Routine: omap_rev_string
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* Description: For SPL builds output board rev
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*/
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void omap_rev_string(void)
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{
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}
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on both banks.
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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timings->mr = MICRON_V_MR_165;
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#ifdef CONFIG_BOOT_NAND
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timings->mcfg = MICRON_V_MCFG_200(256 << 20);
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timings->ctrla = MICRON_V_ACTIMA_200;
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timings->ctrlb = MICRON_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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#else
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if (get_cpu_family() == CPU_OMAP34XX) {
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timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
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timings->ctrla = NUMONYX_V_ACTIMA_165;
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timings->ctrlb = NUMONYX_V_ACTIMB_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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} else {
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timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
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timings->ctrla = NUMONYX_V_ACTIMA_200;
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timings->ctrlb = NUMONYX_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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}
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#endif
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}
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#endif
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#if defined(CONFIG_CMD_NET)
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static void reset_net_chip(int gpio)
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{
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if (!gpio_request(gpio, "eth nrst")) {
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gpio_direction_output(gpio, 1);
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udelay(1);
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gpio_set_value(gpio, 0);
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udelay(40);
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gpio_set_value(gpio, 1);
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mdelay(10);
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}
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}
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/*
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* Routine: setup_net_chip
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* Description: Setting up the configuration GPMC registers specific to the
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* Ethernet hardware.
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*/
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static void setup_net_chip(void)
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{
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struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
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enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
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CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
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/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
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writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
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/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
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writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
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/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
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writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
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&ctrl_base->gpmc_nadv_ale);
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reset_net_chip(64);
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}
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#else
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static inline void setup_net_chip(void) {}
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#endif
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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#if defined(CONFIG_GENERIC_MMC)
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void board_mmc_power_init(void)
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{
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twl4030_power_mmc_init(0);
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}
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#endif
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void set_fdt(void)
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{
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switch (gd->bd->bi_arch_number) {
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case MACH_TYPE_IGEP0020:
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setenv("fdtfile", "omap3-igep0020.dtb");
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break;
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case MACH_TYPE_IGEP0030:
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setenv("fdtfile", "omap3-igep0030.dtb");
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break;
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}
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}
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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twl4030_power_init();
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setup_net_chip();
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omap_die_id_display();
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set_fdt();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_DEFAULT();
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#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
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MUX_IGEP0020();
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#endif
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#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
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MUX_IGEP0030();
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#endif
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}
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#if defined(CONFIG_CMD_NET)
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SMC911X
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return smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#else
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return 0;
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#endif
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}
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#endif
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149
u-boot/board/isee/igep00x0/igep00x0.h
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149
u-boot/board/isee/igep00x0/igep00x0.h
Normal file
@@ -0,0 +1,149 @@
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/*
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* (C) Copyright 2010
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* ISEE 2007 SL, <www.iseebcn.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _IGEP00X0_H_
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#define _IGEP00X0_H_
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const omap3_sysinfo sysinfo = {
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DDR_STACKED,
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#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
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"IGEPv2",
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#endif
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#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
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"IGEP COM MODULE/ELECTRON",
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#endif
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#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
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"IGEP COM PROTON",
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#endif
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#if defined(CONFIG_ENV_IS_IN_ONENAND)
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"ONENAND",
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#else
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"NAND",
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#endif
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};
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static void setup_net_chip(void);
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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* PTD - Pull type Down
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* M0 - Mode 0
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* The commented string gives the final mux configuration for that pin
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*/
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#define MUX_DEFAULT()\
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
|
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
|
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
|
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
|
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
|
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
|
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
|
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
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||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
|
||||
#endif
|
||||
|
||||
#define MUX_IGEP0020() \
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
|
||||
|
||||
#define MUX_IGEP0030() \
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */
|
||||
Reference in New Issue
Block a user