avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
22
u-boot/board/hisilicon/hikey/Kconfig
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22
u-boot/board/hisilicon/hikey/Kconfig
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@@ -0,0 +1,22 @@
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if TARGET_HIKEY
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config SYS_BOARD
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default "hikey"
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config SYS_VENDOR
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default "hisilicon"
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config SYS_SOC
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default "hi6220"
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config SYS_CONFIG_NAME
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default "hikey"
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config CONS_INDEX
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int "UART used for console"
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range 1 4
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default 4
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help
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The hi6220 SoC has 5 UARTs. For example to use UART0 enter 1 here.
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endif
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6
u-boot/board/hisilicon/hikey/MAINTAINERS
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6
u-boot/board/hisilicon/hikey/MAINTAINERS
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@@ -0,0 +1,6 @@
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HIKEY BOARD
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M: Peter Griffin <peter.griffin@linaro.org>
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S: Maintained
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F: board/hisilicon/hikey
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F: include/configs/hikey.h
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F: configs/hikey_defconfig
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8
u-boot/board/hisilicon/hikey/Makefile
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8
u-boot/board/hisilicon/hikey/Makefile
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@@ -0,0 +1,8 @@
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := hikey.o
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260
u-boot/board/hisilicon/hikey/README
Normal file
260
u-boot/board/hisilicon/hikey/README
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@@ -0,0 +1,260 @@
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Introduction
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============
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HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: -
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* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
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* ARM Mali 450-MP4 GPU
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* 1GB 800MHz LPDDR3 DRAM
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* 4GB eMMC Flash Storage
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* microSD
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* 802.11a/b/g/n WiFi, Bluetooth
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The HiKey schematic can be found here: -
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https://github.com/96boards/documentation/blob/master/hikey/96Boards-Hikey-Rev-A1.pdf
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A SoC datasheet can be found here: -
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https://github.com/96boards/documentation/blob/master/hikey/
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Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
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Currently the u-boot port supports: -
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* USB
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* eMMC
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* SD card
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* GPIO
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The HiKey U-Boot port has been tested with l-loader, booting ATF, which then boots
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U-Boot as the bl33.bin executable.
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Compile from source
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===================
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First get all the sources
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> mkdir -p ~/hikey/src ~/hikey/bin
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> cd ~/hikey/src
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> git clone https://github.com/96boards/edk2.git
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> git clone https://github.com/96boards/arm-trusted-firmware.git
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> git clone https://github.com/96boards/l-loader.git
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> git clone https://github.com/96boards/burn-boot.git
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Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source.
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The latest version can be obtained from the edk2 repo.
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> cp edk2/HisiPkg/HiKeyPkg/NonFree/mcuimage.bin ~/hikey/bin/
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Get nvme.img binary (check this link is still the latest)
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> wget -P ~/hikey/bin https://builds.96boards.org/releases/reference-platform/debian/hikey/16.03/bootloader/nvme.img
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Compile U-Boot
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==============
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> cd ~/hikey/src/u-boot
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> make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
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> make CROSS_COMPILE=aarch64-linux-gnu-
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> cp u-boot.bin ~/hikey/bin
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Compile ARM Trusted Firmware (ATF)
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==================================
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> cd ~/hikey/src/atf
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> make CROSS_COMPILE=aarch64-linux-gnu- all fip \
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BL30=~/hikey/bin/mcuimage.bin \
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BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
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Copy resulting binaries
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> cp build/hikey/debug/bl1.bin ~/hikey/bin
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> cp build/hikey/debug/fip.bin ~/hikey/bin
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Compile l-loader
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===============
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> cd ~/hikey/l-loader
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> make BL1=~/hikey/bin/bl1.bin all
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> cp *.img ~/hikey/bin
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> cp l-loader.bin ~/hikey.bin
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These instructions are adapted from
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https://github.com/96boards/documentation/wiki/HiKeyUEFI
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FLASHING
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========
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1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
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the hisi-idt.py utility.
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The command below assumes HiKey enumerated as the first USB serial port
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> sudo ~/hikey/burn_boot/hisi-idt.py -d /dev/ttyUSB0 --img1=~/hikey/bin/l-loader.bin
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2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device by plugging a USB A to mini B
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cable from your PC to the USB OTG port of HiKey (on some boards I've found this to be unreliable).
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> sudo fastboot devices
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0123456789ABCDEF fastboot
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3. Flash the images
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> sudo fastboot flash ptable ~/hikey/bin/ptable.img
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> sudo fastboot flash fastboot ~/hikey/bin/fip.bin
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> sudo fastboot flash nvme ~/hikey/bin/nvme.img
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4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
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have ATF, booting u-boot from eMMC. On 'new' boards I've had to do the
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flashing twice in the past to avoid an ATF error.
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Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
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will get 'dwc_otg_core_host_init: Timeout!' errors.
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See working boot trace below (by default trace is now output to UART3 not UART0 on latest
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ATF, U-Boot and Kernel sources): -
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debug EMMC boot: send RST_N .
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debug EMMC boot: start eMMC boot......
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load fastboot1!
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Switch to aarch64 mode. CPU0 executes at 0xf9801000!
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INFO: BL1: 0xf9810000 - 0xf9817000 [size = 28672]
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NOTICE: Booting Trusted Firmware
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NOTICE: BL1: v1.1(debug):e8b7174
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NOTICE: BL1: Built : 19:16:44, Sep 8 2015
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INFO: BL1: RAM 0xf9810000 - 0xf9817000
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NOTICE: syspll frequency:1190494208Hz
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NOTICE: succeed to init lpddr3 rank0 dram phy
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INFO: lpddr3_freq_init, set ddrc 533mhz
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INFO: init ddr3 rank0
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INFO: ddr3 rank1 init pass
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INFO: lpddr3_freq_init, set ddrc 800mhz
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INFO: init ddr3 rank0
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INFO: ddr3 rank1 init pass
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INFO: Elpida DDR
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INFO: ddr test value:0xa5a55a5a
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INFO: Hisilicon HiKey platform is initialized
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INFO: Using FIP
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INFO: Loading file 'bl2.bin' at address 0xf9818000
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INFO: File 'bl2.bin' loaded: 0xf9818000 - 0xf9821100
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NOTICE: BL1: Booting BL2
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INFO: BL1: BL2 address = 0xf9818000
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INFO: BL1: BL2 spsr = 0x3c5
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INFO: [BDID] [fff91c18] midr: 0x410fd033
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INFO: [BDID] [fff91c1c] board type: 0
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INFO: [BDID] [fff91c20] board id: 0x2b
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INFO: init_acpu_dvfs: pmic version 17
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INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00.
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INFO: acpu_dvfs_volt_init: success!
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INFO: acpu_dvfs_set_freq: support freq num is 5
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INFO: acpu_dvfs_set_freq: start prof is 0x4
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INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5
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INFO: acpu_dvfs_set_freq: voltage:
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INFO: - 0: 0x49
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INFO: - 1: 0x49
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INFO: - 2: 0x50
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INFO: - 3: 0x60
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INFO: - 4: 0x78
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NOTICE: acpu_dvfs_set_freq: set acpu freq success!NOTICE: BL2: v1.1(debug):e8b7174
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NOTICE: BL2: Built : 19:16:46, Sep 8 2015
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INFO: BL2: Loading BL3-0
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INFO: Using FIP
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INFO: Loading file 'bl30.bin' at address 0x1000000
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INFO: Skip reserving memory: 0x1000000 - 0x1023270
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INFO: File 'bl30.bin' loaded: 0x1000000 - 0x1023270
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INFO: bl2_plat_handle_bl30: [1000000] 3a334d43 34313032 2f38302f 30203133
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INFO: bl2_plat_handle_bl30: [10000c8] 0 0 b 0
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INFO: bl2_plat_handle_bl30: [1000190] 17 0 0 0
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INFO: bl2_plat_handle_bl30: [1023260] 0 0 0 0
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INFO: hisi_mcu_load_image: mcu sections 0:
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INFO: hisi_mcu_load_image: src = 0x1000200
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INFO: hisi_mcu_load_image: dst = 0xf6000000
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INFO: hisi_mcu_load_image: size = 512
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INFO: hisi_mcu_load_image: [SRC 0x1000200] 0x7600 0x201 0x1eae1 0x1ea71
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INFO: hisi_mcu_load_image: [DST 0xf6000000] 0x7600 0x201 0x1eae1 0x1ea71
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INFO: hisi_mcu_load_image: mcu sections 1:
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INFO: hisi_mcu_load_image: src = 0x1000400
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INFO: hisi_mcu_load_image: dst = 0xf6000200
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INFO: hisi_mcu_load_image: size = 27828
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INFO: hisi_mcu_load_image: [SRC 0x1000400] 0xbf00bf00 0x4815b672 0x48154780 0x60014915
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||||
INFO: hisi_mcu_load_image: [DST 0xf6000200] 0xbf00bf00 0x4815b672 0x48154780 0x60014915
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INFO: hisi_mcu_load_image: mcu sections 2:
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||||
INFO: hisi_mcu_load_image: src = 0x10070b4
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INFO: hisi_mcu_load_image: dst = 0xf6007200
|
||||
INFO: hisi_mcu_load_image: size = 1024
|
||||
INFO: hisi_mcu_load_image: [SRC 0x10070b4] 0x55 0x0 0x0 0x0
|
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INFO: hisi_mcu_load_image: [DST 0xf6007200] 0x55 0x0 0x0 0x0
|
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INFO: hisi_mcu_load_image: mcu sections 3:
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INFO: hisi_mcu_load_image: src = 0x10074b4
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INFO: hisi_mcu_load_image: dst = 0xfff8e000
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INFO: hisi_mcu_load_image: size = 12704
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||||
INFO: hisi_mcu_load_image: [SRC 0x10074b4] 0x55 0x0 0x0 0x0
|
||||
INFO: hisi_mcu_load_image: [DST 0xfff8e000] 0x55 0x0 0x0 0x0
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INFO: hisi_mcu_load_image: mcu sections 4:
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||||
INFO: hisi_mcu_load_image: src = 0x100a654
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||||
INFO: hisi_mcu_load_image: dst = 0x5e00000
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INFO: hisi_mcu_load_image: size = 82912
|
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INFO: hisi_mcu_load_image: [SRC 0x100a654] 0x4ff0e92d 0x2cc5f645 0x2600b0ab 0x2c7cf6c0
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INFO: hisi_mcu_load_image: [DST 0x5e00000] 0x4ff0e92d 0x2cc5f645 0x2600b0ab 0x2c7cf6c0
|
||||
INFO: hisi_mcu_load_image: mcu sections 5:
|
||||
INFO: hisi_mcu_load_image: src = 0x101ea34
|
||||
INFO: hisi_mcu_load_image: dst = 0x5e143e0
|
||||
INFO: hisi_mcu_load_image: size = 12816
|
||||
INFO: hisi_mcu_load_image: [SRC 0x101ea34] 0x33323130 0x37363534 0x42413938 0x46454443
|
||||
INFO: hisi_mcu_load_image: [DST 0x5e143e0] 0x33323130 0x37363534 0x42413938 0x46454443
|
||||
INFO: hisi_mcu_load_image: mcu sections 6:
|
||||
INFO: hisi_mcu_load_image: src = 0x1021c44
|
||||
INFO: hisi_mcu_load_image: dst = 0x5e1c1d0
|
||||
INFO: hisi_mcu_load_image: size = 3060
|
||||
INFO: hisi_mcu_load_image: [SRC 0x1021c44] 0x0 0x0 0x0 0x0
|
||||
INFO: hisi_mcu_load_image: [DST 0x5e1c1d0] 0x0 0x0 0x0 0x0
|
||||
INFO: hisi_mcu_load_image: mcu sections 7:
|
||||
INFO: hisi_mcu_load_image: src = 0x1022838
|
||||
INFO: hisi_mcu_load_image: dst = 0x5e1cdc4
|
||||
INFO: hisi_mcu_load_image: size = 2616
|
||||
INFO: hisi_mcu_load_image: [SRC 0x1022838] 0xf80000a0 0x0 0xf80000ac 0x0
|
||||
INFO: hisi_mcu_load_image: [DST 0x5e1cdc4] 0xf80000a0 0x0 0xf80000ac 0x0
|
||||
INFO: hisi_mcu_start_run: AO_SC_SYS_CTRL2=0
|
||||
INFO: bl2_plat_handle_bl30: mcu pc is 42933301
|
||||
INFO: bl2_plat_handle_bl30: AO_SC_PERIPH_CLKSTAT4 is 39018f09
|
||||
INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
|
||||
INFO: BL2: Loading BL3-1
|
||||
INFO: Using FIP
|
||||
INFO: Loading file 'bl31.bin' at address 0xf9858000
|
||||
INFO: File 'bl31.bin' loaded: 0xf9858000 - 0xf9861010
|
||||
INFO: BL2: Loading BL3-2
|
||||
INFO: Using FIP
|
||||
WARNING: Failed to access image 'bl32.bin' (-1)
|
||||
WARNING: Failed to load BL3-2 (-1)
|
||||
INFO: BL2: Loading BL3-3
|
||||
INFO: Using FIP
|
||||
INFO: Loading file 'bl33.bin' at address 0x35000000
|
||||
INFO: File 'bl33.bin' loaded: 0x35000000 - 0x3504c468
|
||||
NOTICE: BL1: Booting BL3-1
|
||||
INFO: BL1: BL3-1 address = 0xf9858000
|
||||
INFO: BL1: BL3-1 spsr = 0x3cd
|
||||
INFO: BL1: BL3-1 params address = 0xf9821920
|
||||
INFO: BL1: BL3-1 plat params address = 0x0
|
||||
NOTICE: BL3-1: v1.1(debug):e8b7174
|
||||
NOTICE: BL3-1: Built : 19:16:49, Sep 8 2015
|
||||
INFO: BL3-1: Initializing runtime services
|
||||
INFO: BL3-1: Preparing for EL3 exit to normal world
|
||||
INFO: BL3-1: Next image address = 0x35000000
|
||||
INFO: BL3-1: Next image spsr = 0x3c9
|
||||
|
||||
U-Boot 2015.10-rc2 (Sep 08 2015 - 20:29:33 +0100)hikey
|
||||
|
||||
DRAM: 1008 MiB
|
||||
HI6553 PMIC init
|
||||
MMC: config_sd_carddetect: SD card not present
|
||||
HiKey DWMMC: 0, HiKey DWMMC: 1
|
||||
Card did not respond to voltage select!
|
||||
** Bad device mmc 1 **
|
||||
Using default environment
|
||||
|
||||
In: serial
|
||||
Out: serial
|
||||
Err: serial
|
||||
Net: Net Initialization Skipped
|
||||
No ethernet found.
|
||||
Hit any key to stop autoboot: 0
|
||||
starting USB...
|
||||
USB0: Core Release: 3.00a
|
||||
scanning bus 0 for devices... 2 USB Device(s) found
|
||||
scanning usb for storage devices... 0 Storage Device(s) found
|
||||
scanning usb for ethernet devices... 0 Ethernet Device(s) found
|
||||
42
u-boot/board/hisilicon/hikey/build-tf.mak
Normal file
42
u-boot/board/hisilicon/hikey/build-tf.mak
Normal file
@@ -0,0 +1,42 @@
|
||||
CROSS_COMPILE := aarch64-linux-gnu-
|
||||
output_dir := $(PWD)/../bin
|
||||
makejobs := $(shell grep '^processor' /proc/cpuinfo | sort -u | wc -l)
|
||||
makethreads := $(shell dc -e "$(makejobs) 1 + p")
|
||||
make_options := GCC49_AARCH64_PREFIX=$CROSS_COMPILE \
|
||||
-j$(makethreads) -l$(makejobs)
|
||||
|
||||
BL30_HIKEY := $(output_dir)/mcuimage.bin
|
||||
BL33_HIKEY := $(output_dir)/u-boot-hikey.bin
|
||||
|
||||
.PHONY: help
|
||||
help:
|
||||
@echo "**** Common Makefile ****"
|
||||
@echo "example:"
|
||||
@echo "make -f build-tf.mak build"
|
||||
|
||||
.PHONY: have-crosscompiler
|
||||
have-crosscompiler:
|
||||
@echo -n "Check that $(CROSS_COMPILE)gcc is available..."
|
||||
@which $(CROSS_COMPILE)gcc > /dev/null ; \
|
||||
if [ ! $$? -eq 0 ] ; then \
|
||||
echo "ERROR: cross-compiler $(CROSS_COMPILE)gcc not in PATH=$$PATH!" ; \
|
||||
echo "ABORTING." ; \
|
||||
exit 1 ; \
|
||||
else \
|
||||
echo "OK" ;\
|
||||
fi
|
||||
|
||||
build: have-crosscompiler FORCE
|
||||
@echo "Build TF for Hikey..."
|
||||
rm -rf build/
|
||||
CROSS_COMPILE=$(CROSS_COMPILE) \
|
||||
make all fip \
|
||||
BL30=$(BL30_HIKEY) \
|
||||
BL33=$(BL33_HIKEY) \
|
||||
DEBUG=1 \
|
||||
PLAT=hikey
|
||||
@echo "Copy resulting binaries..."
|
||||
cp build/hikey/debug/bl1.bin $(output_dir)/bl1-hikey.bin
|
||||
cp build/hikey/debug/fip.bin $(output_dir)/fip-hikey.bin
|
||||
|
||||
FORCE:
|
||||
449
u-boot/board/hisilicon/hikey/hikey.c
Normal file
449
u-boot/board/hisilicon/hikey/hikey.c
Normal file
@@ -0,0 +1,449 @@
|
||||
/*
|
||||
* (C) Copyright 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dm/platform_data/serial_pl01x.h>
|
||||
#include <errno.h>
|
||||
#include <malloc.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <usb.h>
|
||||
#include <power/hi6553_pmic.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <asm/arch/dwmmc.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/periph.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/hi6220.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
|
||||
/*TODO drop this table in favour of device tree */
|
||||
static const struct hikey_gpio_platdata hi6220_gpio[] = {
|
||||
{ 0, HI6220_GPIO_BASE(0)},
|
||||
{ 1, HI6220_GPIO_BASE(1)},
|
||||
{ 2, HI6220_GPIO_BASE(2)},
|
||||
{ 3, HI6220_GPIO_BASE(3)},
|
||||
{ 4, HI6220_GPIO_BASE(4)},
|
||||
{ 5, HI6220_GPIO_BASE(5)},
|
||||
{ 6, HI6220_GPIO_BASE(6)},
|
||||
{ 7, HI6220_GPIO_BASE(7)},
|
||||
{ 8, HI6220_GPIO_BASE(8)},
|
||||
{ 9, HI6220_GPIO_BASE(9)},
|
||||
{ 10, HI6220_GPIO_BASE(10)},
|
||||
{ 11, HI6220_GPIO_BASE(11)},
|
||||
{ 12, HI6220_GPIO_BASE(12)},
|
||||
{ 13, HI6220_GPIO_BASE(13)},
|
||||
{ 14, HI6220_GPIO_BASE(14)},
|
||||
{ 15, HI6220_GPIO_BASE(15)},
|
||||
{ 16, HI6220_GPIO_BASE(16)},
|
||||
{ 17, HI6220_GPIO_BASE(17)},
|
||||
{ 18, HI6220_GPIO_BASE(18)},
|
||||
{ 19, HI6220_GPIO_BASE(19)},
|
||||
|
||||
};
|
||||
|
||||
U_BOOT_DEVICES(hi6220_gpios) = {
|
||||
{ "gpio_hi6220", &hi6220_gpio[0] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[1] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[2] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[3] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[4] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[5] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[6] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[7] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[8] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[9] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[10] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[11] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[12] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[13] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[14] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[15] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[16] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[17] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[18] },
|
||||
{ "gpio_hi6220", &hi6220_gpio[19] },
|
||||
};
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if !CONFIG_IS_ENABLED(OF_CONTROL)
|
||||
|
||||
static const struct pl01x_serial_platdata serial_platdata = {
|
||||
#if CONFIG_CONS_INDEX == 1
|
||||
.base = HI6220_UART0_BASE,
|
||||
#elif CONFIG_CONS_INDEX == 4
|
||||
.base = HI6220_UART3_BASE,
|
||||
#else
|
||||
#error "Unsupported console index value."
|
||||
#endif
|
||||
.type = TYPE_PL011,
|
||||
.clock = 19200000
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(hikey_seriala) = {
|
||||
.name = "serial_pl01x",
|
||||
.platdata = &serial_platdata,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct mm_region hikey_mem_map[] = {
|
||||
{
|
||||
.base = 0x0UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.base = 0x80000000UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = hikey_mem_map;
|
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
||||
int board_uart_init(void)
|
||||
{
|
||||
switch (CONFIG_CONS_INDEX) {
|
||||
case 1:
|
||||
hi6220_pinmux_config(PERIPH_ID_UART0);
|
||||
break;
|
||||
case 4:
|
||||
hi6220_pinmux_config(PERIPH_ID_UART3);
|
||||
break;
|
||||
default:
|
||||
debug("%s: Unsupported UART selected\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
board_uart_init();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
struct peri_sc_periph_regs *peri_sc =
|
||||
(struct peri_sc_periph_regs *)HI6220_PERI_BASE;
|
||||
|
||||
struct alwayson_sc_regs *ao_sc =
|
||||
(struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
|
||||
|
||||
/* status offset from enable reg */
|
||||
#define STAT_EN_OFF 0x2
|
||||
|
||||
void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
data = readl(clk_base);
|
||||
data |= bitfield;
|
||||
|
||||
writel(bitfield, clk_base);
|
||||
do {
|
||||
data = readl(clk_base + STAT_EN_OFF);
|
||||
} while ((data & bitfield) == 0);
|
||||
}
|
||||
|
||||
/* status offset from disable reg */
|
||||
#define STAT_DIS_OFF 0x1
|
||||
|
||||
void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
data = readl(clk_base);
|
||||
data |= bitfield;
|
||||
|
||||
writel(data, clk_base);
|
||||
do {
|
||||
data = readl(clk_base + STAT_DIS_OFF);
|
||||
} while (data & bitfield);
|
||||
}
|
||||
|
||||
#define EYE_PATTERN 0x70533483
|
||||
|
||||
int board_usb_init(int index, enum usb_init_type init)
|
||||
{
|
||||
unsigned int data;
|
||||
|
||||
/* enable USB clock */
|
||||
hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
|
||||
|
||||
/* take usb IPs out of reset */
|
||||
writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
|
||||
PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
|
||||
&peri_sc->rst0_dis);
|
||||
do {
|
||||
data = readl(&peri_sc->rst0_stat);
|
||||
data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
|
||||
PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
|
||||
} while (data);
|
||||
|
||||
/*CTRL 5*/
|
||||
data = readl(&peri_sc->ctrl5);
|
||||
data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
|
||||
data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
|
||||
data |= 0x300;
|
||||
writel(data, &peri_sc->ctrl5);
|
||||
|
||||
/*CTRL 4*/
|
||||
|
||||
/* configure USB PHY */
|
||||
data = readl(&peri_sc->ctrl4);
|
||||
|
||||
/* make PHY out of low power mode */
|
||||
data &= ~PERI_CTRL4_PICO_SIDDQ;
|
||||
data &= ~PERI_CTRL4_PICO_OGDISABLE;
|
||||
data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
|
||||
writel(data, &peri_sc->ctrl4);
|
||||
|
||||
writel(EYE_PATTERN, &peri_sc->ctrl8);
|
||||
|
||||
mdelay(5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int config_sd_carddetect(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* configure GPIO8 as nopull */
|
||||
writel(0, 0xf8001830);
|
||||
|
||||
gpio_request(8, "SD CD");
|
||||
|
||||
gpio_direction_input(8);
|
||||
ret = gpio_get_value(8);
|
||||
|
||||
if (!ret) {
|
||||
printf("%s: SD card present\n", __func__);
|
||||
return 1;
|
||||
}
|
||||
|
||||
printf("%s: SD card not present\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void mmc1_init_pll(void)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
/* select SYSPLL as the source of MMC1 */
|
||||
/* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
|
||||
writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
|
||||
do {
|
||||
data = readl(&peri_sc->clk0_sel);
|
||||
} while (!(data & (1 << 11)));
|
||||
|
||||
/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
|
||||
writel(1 << 30, &peri_sc->clk0_sel);
|
||||
do {
|
||||
data = readl(&peri_sc->clk0_sel);
|
||||
} while (data & (1 << 14));
|
||||
|
||||
hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
|
||||
|
||||
hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
|
||||
|
||||
do {
|
||||
/* 1.2GHz / 50 = 24MHz */
|
||||
writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
|
||||
data = readl(&peri_sc->clkcfg8bit2);
|
||||
} while ((data & 0x31) != 0x31);
|
||||
}
|
||||
|
||||
static void mmc1_reset_clk(void)
|
||||
{
|
||||
unsigned int data;
|
||||
|
||||
/* disable mmc1 bus clock */
|
||||
hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
|
||||
|
||||
/* enable mmc1 bus clock */
|
||||
hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
|
||||
|
||||
/* reset mmc1 clock domain */
|
||||
writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
|
||||
|
||||
/* bypass mmc1 clock phase */
|
||||
data = readl(&peri_sc->ctrl2);
|
||||
data |= 3 << 2;
|
||||
writel(data, &peri_sc->ctrl2);
|
||||
|
||||
/* disable low power */
|
||||
data = readl(&peri_sc->ctrl13);
|
||||
data |= 1 << 4;
|
||||
writel(data, &peri_sc->ctrl13);
|
||||
do {
|
||||
data = readl(&peri_sc->rst0_stat);
|
||||
} while (!(data & PERI_RST0_MMC1));
|
||||
|
||||
/* unreset mmc0 clock domain */
|
||||
writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
|
||||
do {
|
||||
data = readl(&peri_sc->rst0_stat);
|
||||
} while (data & PERI_RST0_MMC1);
|
||||
}
|
||||
|
||||
/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
|
||||
static void hi6220_pmussi_init(void)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
/* Take PMUSSI out of reset */
|
||||
writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
|
||||
&ao_sc->rst4_dis);
|
||||
do {
|
||||
data = readl(&ao_sc->rst4_stat);
|
||||
} while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
|
||||
|
||||
/* set PMU SSI clock latency for read operation */
|
||||
data = readl(&ao_sc->mcu_subsys_ctrl3);
|
||||
data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
|
||||
data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
|
||||
writel(data, &ao_sc->mcu_subsys_ctrl3);
|
||||
|
||||
/* enable PMUSSI clock */
|
||||
data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
|
||||
ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
|
||||
|
||||
hi6220_clk_enable(data, &ao_sc->clk5_en);
|
||||
|
||||
/* Output high to PMIC on PWR_HOLD_GPIO0_0 */
|
||||
gpio_request(0, "PWR_HOLD_GPIO0_0");
|
||||
gpio_direction_output(0, 1);
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GENERIC_MMC
|
||||
|
||||
static int init_dwmmc(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
#ifdef CONFIG_DWMMC
|
||||
|
||||
/* mmc0 clocks are already configured by ATF */
|
||||
ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
|
||||
if (ret)
|
||||
printf("%s: Error configuring pinmux for eMMC (%d)\n"
|
||||
, __func__, ret);
|
||||
|
||||
ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
|
||||
if (ret)
|
||||
printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
|
||||
|
||||
|
||||
/* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
|
||||
mmc1_init_pll();
|
||||
mmc1_reset_clk();
|
||||
|
||||
ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
|
||||
if (ret)
|
||||
printf("%s: Error configuring pinmux for eMMC (%d)\n"
|
||||
, __func__, ret);
|
||||
|
||||
config_sd_carddetect();
|
||||
|
||||
ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
|
||||
if (ret)
|
||||
printf("%s: Error adding SD port (%d)\n", __func__, ret);
|
||||
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* setup board specific PMIC */
|
||||
int power_init_board(void)
|
||||
{
|
||||
/* init the hi6220 pmussi ip */
|
||||
hi6220_pmussi_init();
|
||||
|
||||
power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* add the eMMC and sd ports */
|
||||
ret = init_dwmmc();
|
||||
|
||||
if (ret)
|
||||
debug("init_dwmmc failed\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
/*
|
||||
* Reserve regions below from DT memory node (which gets generated
|
||||
* by U-Boot from the dram banks in arch_fixup_fdt() before booting
|
||||
* the kernel. This will then match the kernel hikey dts memory node.
|
||||
*
|
||||
* 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
|
||||
* 0x05f0,1000 - 0x05f0,1fff: Reboot reason
|
||||
* 0x06df,f000 - 0x06df,ffff: Mailbox message data
|
||||
* 0x0740,f000 - 0x0740,ffff: MCU firmware section
|
||||
* 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
|
||||
* 0x3e00,0000 - 0x3fff,ffff: OP-TEE
|
||||
*/
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = 0x05e00000;
|
||||
|
||||
gd->bd->bi_dram[1].start = 0x05f00000;
|
||||
gd->bd->bi_dram[1].size = 0x00001000;
|
||||
|
||||
gd->bd->bi_dram[2].start = 0x05f02000;
|
||||
gd->bd->bi_dram[2].size = 0x00efd000;
|
||||
|
||||
gd->bd->bi_dram[3].start = 0x06e00000;
|
||||
gd->bd->bi_dram[3].size = 0x0060f000;
|
||||
|
||||
gd->bd->bi_dram[4].start = 0x07410000;
|
||||
gd->bd->bi_dram[4].size = 0x1aaf0000;
|
||||
|
||||
gd->bd->bi_dram[5].start = 0x22000000;
|
||||
gd->bd->bi_dram[5].size = 0x1c000000;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
writel(0x48698284, &ao_sc->stat0);
|
||||
wfi();
|
||||
}
|
||||
Reference in New Issue
Block a user