avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
18
u-boot/board/ge/bx50v3/Kconfig
Normal file
18
u-boot/board/ge/bx50v3/Kconfig
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@@ -0,0 +1,18 @@
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if TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
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config IMX_CONFIG
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default "board/ge/bx50v3/bx50v3.cfg"
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config SYS_BOARD
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default "bx50v3"
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config SYS_VENDOR
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default "ge"
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config SYS_SOC
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default "mx6"
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config SYS_CONFIG_NAME
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default "ge_bx50v3"
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endif
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8
u-boot/board/ge/bx50v3/MAINTAINERS
Normal file
8
u-boot/board/ge/bx50v3/MAINTAINERS
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@@ -0,0 +1,8 @@
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GE_BX50V3 BOARD
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M: Martin Donnelly <martin.donnelly@ge.com>
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S: Maintained
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F: board/ge/bx50v3/
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F: include/configs/ge_bx50v3.h
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F: configs/ge_b450v3_defconfig
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F: configs/ge_b650v3_defconfig
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F: configs/ge_b850v3_defconfig
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8
u-boot/board/ge/bx50v3/Makefile
Normal file
8
u-boot/board/ge/bx50v3/Makefile
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@@ -0,0 +1,8 @@
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#
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# Copyright 2015 Timesys Corporation
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# Copyright 2015 General Electric Company
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := bx50v3.o
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629
u-boot/board/ge/bx50v3/bx50v3.c
Normal file
629
u-boot/board/ge/bx50v3/bx50v3.c
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@@ -0,0 +1,629 @@
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/*
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* Copyright 2015 Timesys Corporation
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* Copyright 2015 General Electric Company
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/video.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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#include <pwm.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_HYS)
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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static iomux_v3_cfg_t const uart3_pads[] = {
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MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart4_pads[] = {
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MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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/* AR8033 PHY Reset */
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MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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/* Reset AR8033 PHY */
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gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
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udelay(500);
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gpio_set_value(IMX_GPIO_NR(1, 28), 1);
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}
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const ecspi1_pads[] = {
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MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
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.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
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.gp = IMX_GPIO_NR(5, 27)
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},
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.sda = {
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.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
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.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
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.gp = IMX_GPIO_NR(5, 26)
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}
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};
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static struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
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.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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static struct i2c_pads_info i2c_pad_info3 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
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.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
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.gp = IMX_GPIO_NR(1, 3)
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
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.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
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.gp = IMX_GPIO_NR(1, 6)
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}
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};
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#ifdef CONFIG_MXC_SPI
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
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}
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static void setup_spi(void)
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{
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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
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}
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#endif
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static iomux_v3_cfg_t const pcie_pads[] = {
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MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
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};
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|
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static void setup_pcie(void)
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{
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imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
|
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}
|
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|
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
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imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
|
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}
|
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|
||||
#ifdef CONFIG_FSL_ESDHC
|
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struct fsl_esdhc_cfg usdhc_cfg[3] = {
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{USDHC2_BASE_ADDR},
|
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{USDHC3_BASE_ADDR},
|
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{USDHC4_BASE_ADDR},
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};
|
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|
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#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
|
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#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
|
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int board_mmc_getcd(struct mmc *mmc)
|
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
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case USDHC2_BASE_ADDR:
|
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ret = !gpio_get_value(USDHC2_CD_GPIO);
|
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break;
|
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case USDHC3_BASE_ADDR:
|
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ret = 1; /* eMMC is always present */
|
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break;
|
||||
case USDHC4_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC4_CD_GPIO);
|
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break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
break;
|
||||
case 2:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
||||
gpio_direction_input(USDHC4_CD_GPIO);
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||||
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
break;
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||||
default:
|
||||
printf("Warning: you configured more USDHC controllers\n"
|
||||
"(%d) then supported by the board (%d)\n",
|
||||
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int mx6_rgmii_rework(struct phy_device *phydev)
|
||||
{
|
||||
/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
|
||||
/* set device address 0x7 */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
|
||||
/* offset 0x8016: CLK_25M Clock Select */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
|
||||
/* enable register write, no post increment, address 0x7 */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
|
||||
/* set to 125 MHz from local PLL source */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
|
||||
|
||||
/* rgmii tx clock delay enable */
|
||||
/* set debug port address: SerDes Test and System Mode Control */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
/* enable rgmii tx clock delay */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
mx6_rgmii_rework(phydev);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_VIDEO_IPUV3)
|
||||
static iomux_v3_cfg_t const backlight_pads[] = {
|
||||
/* Power for LVDS Display */
|
||||
MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
|
||||
/* Backlight enable for LVDS display */
|
||||
MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
|
||||
/* backlight PWM brightness control */
|
||||
MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void do_enable_hdmi(struct display_info_t const *dev)
|
||||
{
|
||||
imx_enable_hdmi_phy();
|
||||
}
|
||||
|
||||
int board_cfb_skip(void)
|
||||
{
|
||||
gpio_direction_output(LVDS_POWER_GP, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int detect_baseboard(struct display_info_t const *dev)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
|
||||
IS_ENABLED(CONFIG_TARGET_GE_B650V3))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct display_info_t const displays[] = {{
|
||||
.bus = -1,
|
||||
.addr = -1,
|
||||
.pixfmt = IPU_PIX_FMT_RGB24,
|
||||
.detect = detect_baseboard,
|
||||
.enable = NULL,
|
||||
.mode = {
|
||||
.name = "G121X1-L03",
|
||||
.refresh = 60,
|
||||
.xres = 1024,
|
||||
.yres = 768,
|
||||
.pixclock = 15385,
|
||||
.left_margin = 20,
|
||||
.right_margin = 300,
|
||||
.upper_margin = 30,
|
||||
.lower_margin = 8,
|
||||
.hsync_len = 1,
|
||||
.vsync_len = 1,
|
||||
.sync = FB_SYNC_EXT,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} }, {
|
||||
.bus = -1,
|
||||
.addr = 3,
|
||||
.pixfmt = IPU_PIX_FMT_RGB24,
|
||||
.detect = detect_hdmi,
|
||||
.enable = do_enable_hdmi,
|
||||
.mode = {
|
||||
.name = "HDMI",
|
||||
.refresh = 60,
|
||||
.xres = 1024,
|
||||
.yres = 768,
|
||||
.pixclock = 15385,
|
||||
.left_margin = 220,
|
||||
.right_margin = 40,
|
||||
.upper_margin = 21,
|
||||
.lower_margin = 7,
|
||||
.hsync_len = 60,
|
||||
.vsync_len = 10,
|
||||
.sync = FB_SYNC_EXT,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
|
||||
static void enable_videopll(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
s32 timeout = 100000;
|
||||
|
||||
setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
|
||||
|
||||
/* set video pll to 910MHz (24MHz * (37+11/12))
|
||||
* video pll post div to 910/4 = 227.5MHz
|
||||
*/
|
||||
clrsetbits_le32(&ccm->analog_pll_video,
|
||||
BM_ANADIG_PLL_VIDEO_DIV_SELECT |
|
||||
BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
|
||||
BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
|
||||
BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
|
||||
|
||||
writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
|
||||
writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
|
||||
|
||||
clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
|
||||
|
||||
while (timeout--)
|
||||
if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
|
||||
break;
|
||||
|
||||
if (timeout < 0)
|
||||
printf("Warning: video pll lock timeout!\n");
|
||||
|
||||
clrsetbits_le32(&ccm->analog_pll_video,
|
||||
BM_ANADIG_PLL_VIDEO_BYPASS,
|
||||
BM_ANADIG_PLL_VIDEO_ENABLE);
|
||||
}
|
||||
|
||||
static void setup_display_b850v3(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
|
||||
enable_videopll();
|
||||
|
||||
/* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
|
||||
clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
|
||||
|
||||
imx_setup_hdmi();
|
||||
|
||||
/* Set LDB_DI0 as clock source for IPU_DI0 */
|
||||
clrsetbits_le32(&mxc_ccm->chsccdr,
|
||||
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
|
||||
(CHSCCDR_CLK_SEL_LDB_DI0 <<
|
||||
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
|
||||
|
||||
/* Turn on IPU LDB DI0 clocks */
|
||||
setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
|
||||
|
||||
enable_ipu_clock();
|
||||
|
||||
writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
|
||||
IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
|
||||
IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
|
||||
IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
|
||||
IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
|
||||
IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
|
||||
IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
|
||||
IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
|
||||
IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
|
||||
IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
|
||||
&iomux->gpr[2]);
|
||||
|
||||
clrbits_le32(&iomux->gpr[3],
|
||||
IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
|
||||
IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
|
||||
IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
|
||||
}
|
||||
|
||||
static void setup_display_bx50v3(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
|
||||
/* When a reset/reboot is performed the display power needs to be turned
|
||||
* off for atleast 500ms. The boot time is ~300ms, we need to wait for
|
||||
* an additional 200ms here. Unfortunately we use external PMIC for
|
||||
* doing the reset, so can not differentiate between POR vs soft reset
|
||||
*/
|
||||
mdelay(200);
|
||||
|
||||
/* IPU1 DI0 clock is 480/7 = 68.5 MHz */
|
||||
setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
|
||||
|
||||
/* Set LDB_DI0 as clock source for IPU_DI0 */
|
||||
clrsetbits_le32(&mxc_ccm->chsccdr,
|
||||
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
|
||||
(CHSCCDR_CLK_SEL_LDB_DI0 <<
|
||||
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
|
||||
|
||||
/* Turn on IPU LDB DI0 clocks */
|
||||
setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
|
||||
|
||||
enable_ipu_clock();
|
||||
|
||||
writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
|
||||
IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
|
||||
IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
|
||||
IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
|
||||
IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
|
||||
&iomux->gpr[2]);
|
||||
|
||||
clrsetbits_le32(&iomux->gpr[3],
|
||||
IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
|
||||
(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
|
||||
IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
|
||||
|
||||
/* backlights off until needed */
|
||||
imx_iomux_v3_setup_multiple_pads(backlight_pads,
|
||||
ARRAY_SIZE(backlight_pads));
|
||||
gpio_direction_input(LVDS_POWER_GP);
|
||||
gpio_direction_input(LVDS_BACKLIGHT_GP);
|
||||
}
|
||||
#endif /* CONFIG_VIDEO_IPUV3 */
|
||||
|
||||
/*
|
||||
* Do not overwrite the console
|
||||
* Use always serial for U-Boot console
|
||||
*/
|
||||
int overwrite_console(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
setup_iomux_enet();
|
||||
setup_pcie();
|
||||
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const misc_pads[] = {
|
||||
MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
||||
MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
||||
MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
||||
MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
||||
MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
||||
MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
||||
};
|
||||
#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
|
||||
#define WIFI_EN IMX_GPIO_NR(6, 14)
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(misc_pads,
|
||||
ARRAY_SIZE(misc_pads));
|
||||
|
||||
setup_iomux_uart();
|
||||
|
||||
#if defined(CONFIG_VIDEO_IPUV3)
|
||||
if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
|
||||
/* Set LDB clock to Video PLL */
|
||||
select_ldb_di_clock_source(MXC_PLL5_CLK);
|
||||
else
|
||||
/* Set LDB clock to USB PLL */
|
||||
select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gpio_direction_output(SUS_S3_OUT, 1);
|
||||
gpio_direction_output(WIFI_EN, 1);
|
||||
#if defined(CONFIG_VIDEO_IPUV3)
|
||||
if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
|
||||
setup_display_b850v3();
|
||||
else
|
||||
setup_display_bx50v3();
|
||||
#endif
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
setup_spi();
|
||||
#endif
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
||||
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_IPUV3
|
||||
/* We need at least 200ms between power on and backlight on
|
||||
* as per specifications from CHI MEI */
|
||||
mdelay(250);
|
||||
|
||||
/* enable backlight PWM 1 */
|
||||
pwm_init(0, 0, 0);
|
||||
|
||||
/* duty cycle 5000000ns, period: 5000000ns */
|
||||
pwm_config(0, 5000000, 5000000);
|
||||
|
||||
/* Backlight Power */
|
||||
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
|
||||
|
||||
pwm_enable(0);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("BOARD: %s\n", CONFIG_BOARD_NAME);
|
||||
return 0;
|
||||
}
|
||||
151
u-boot/board/ge/bx50v3/bx50v3.cfg
Normal file
151
u-boot/board/ge/bx50v3/bx50v3.cfg
Normal file
@@ -0,0 +1,151 @@
|
||||
/*
|
||||
*
|
||||
* Copyright 2015 Timesys Corporation.
|
||||
* Copyright 2015 General Electric Company
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer doc/README.imximage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
IMAGE_VERSION 2
|
||||
BOOT_FROM sd
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/crm_regs.h"
|
||||
|
||||
/* DDR IO */
|
||||
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
|
||||
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
|
||||
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
||||
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
||||
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
|
||||
|
||||
/* Calibrations */
|
||||
/* ZQ */
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
|
||||
/* write leveling */
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
|
||||
/* Read DQS Gating calibration */
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C
|
||||
/* Read calibration */
|
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032
|
||||
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042
|
||||
/* Write calibration */
|
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E
|
||||
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E
|
||||
/* read data bit delay */
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
|
||||
|
||||
/* Complete calibration by forced measurment */
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
||||
|
||||
/* MMDC init */
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
|
||||
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x008F1023
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000
|
||||
|
||||
/* Initialize Micron MT41J128M */
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00408031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00408039
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
|
||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
||||
|
||||
/* set the default clock gate to save power */
|
||||
DATA 4, CCM_CCGR0, 0x00C03F3F
|
||||
DATA 4, CCM_CCGR1, 0x0030FC03
|
||||
DATA 4, CCM_CCGR2, 0x0FFFC000
|
||||
DATA 4, CCM_CCGR3, 0x3FF00000
|
||||
DATA 4, CCM_CCGR4, 0x00FFF300
|
||||
DATA 4, CCM_CCGR5, 0x0F0000C3
|
||||
DATA 4, CCM_CCGR6, 0x000003FF
|
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
|
||||
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
|
||||
|
||||
/*
|
||||
* Setup CCM_CCOSR register as follows:
|
||||
*
|
||||
* cko1_en 1 --> CKO1 enabled
|
||||
* cko1_div 111 --> divide by 8
|
||||
* cko1_sel 1011 --> ahb_clk_root
|
||||
*
|
||||
* This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
|
||||
*/
|
||||
DATA 4, CCM_CCOSR, 0x000000fb
|
||||
Reference in New Issue
Block a user