avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/board/gdsys/405ep/405ep.c

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+	return gd->arch.fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+	if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+		puts("       Waiting for FPGA-DONE timed out.\n");
+	if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+		puts("       FPGA reflection test failed.\n");
+}
+
+int board_early_init_f(void)
+{
+	unsigned k;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->arch.fpga_state[k] = 0;
+
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
+	 * -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	unsigned k;
+	unsigned ctr;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->arch.fpga_state[k] = 0;
+
+	/*
+	 * reset FPGA
+	 */
+	gd405ep_init();
+
+	gd405ep_set_fpga_reset(1);
+
+	gd405ep_setup_hw();
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ctr = 0;
+		while (!gd405ep_get_fpga_done(k)) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_DONE_FAILED;
+				break;
+			}
+		}
+	}
+
+	udelay(10);
+
+	gd405ep_set_fpga_reset(0);
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		/*
+		 * wait for fpga out of reset
+		 */
+		ctr = 0;
+		while (1) {
+			u16 val;
+
+			FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
+
+			FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+			if (val == REFLECTION_TESTPATTERN_INV)
+				break;
+
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_REFLECTION_FAILED;
+				break;
+			}
+		}
+	}
+
+	return 0;
+}

u-boot/board/gdsys/405ep/405ep.h

@@ -0,0 +1,10 @@
+#ifndef __405EP_H_
+#define __405EP_H_
+
+/* functions to be provided by board implementation */
+void gd405ep_init(void);
+void gd405ep_set_fpga_reset(unsigned state);
+void gd405ep_setup_hw(void);
+int gd405ep_get_fpga_done(unsigned fpga);
+
+#endif /* __405EP_H_ */

u-boot/board/gdsys/405ep/Kconfig

@@ -0,0 +1,51 @@
+if TARGET_DLVISION_10G
+
+config SYS_BOARD
+	default "405ep"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "dlvision-10g"
+
+endif
+
+if TARGET_IO
+
+config SYS_BOARD
+	default "405ep"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "io"
+
+endif
+
+if TARGET_IOCON
+
+config SYS_BOARD
+	default "405ep"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "iocon"
+
+endif
+
+if TARGET_NEO
+
+config SYS_BOARD
+	default "405ep"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "neo"
+
+endif

u-boot/board/gdsys/405ep/MAINTAINERS

@@ -0,0 +1,12 @@
+405EP BOARD
+M:	Dirk Eibach <eibach@gdsys.de>
+S:	Maintained
+F:	board/gdsys/405ep/
+F:	include/configs/dlvision-10g.h
+F:	configs/dlvision-10g_defconfig
+F:	include/configs/io.h
+F:	configs/io_defconfig
+F:	include/configs/iocon.h
+F:	configs/iocon_defconfig
+F:	include/configs/neo.h
+F:	configs/neo_defconfig

u-boot/board/gdsys/405ep/Makefile

@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := 405ep.o
+obj-$(CONFIG_NEO) += neo.o
+obj-$(CONFIG_IO) += io.o
+obj-$(CONFIG_IOCON) += iocon.o
+obj-$(CONFIG_DLVISION_10G) += dlvision-10g.o

u-boot/board/gdsys/405ep/dlvision-10g.c

@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
+
+#define LATCH2_MC2_PRESENT_N 0x0080
+
+enum {
+	UNITTYPE_MAIN = 1<<0,
+	UNITTYPE_SERVER = 1<<1,
+	UNITTYPE_DISPLAYPORT = 1<<2,
+};
+
+enum {
+	HWVER_101 = 0,
+	HWVER_110 = 1,
+	HWVER_130 = 2,
+	HWVER_140 = 3,
+	HWVER_150 = 4,
+	HWVER_160 = 5,
+	HWVER_170 = 6,
+};
+
+enum {
+	AUDIO_NONE = 0,
+	AUDIO_TX = 1,
+	AUDIO_RX = 2,
+	AUDIO_RXTX = 3,
+};
+
+enum {
+	SYSCLK_156250 = 2,
+};
+
+enum {
+	RAM_NONE = 0,
+	RAM_DDR2_32 = 1,
+	RAM_DDR2_64 = 2,
+};
+
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int misc_init_r(void)
+{
+	/* startup fans */
+	dtt_init();
+
+	return 0;
+}
+
+static unsigned int get_hwver(void)
+{
+	u16 latch3 = in_le16((void *)LATCH3_BASE);
+
+	return latch3 & 0x0003;
+}
+
+static unsigned int get_mc2_present(void)
+{
+	u16 latch2 = in_le16((void *)LATCH2_BASE);
+
+	return !(latch2 & LATCH2_MC2_PRESENT_N);
+}
+
+static void print_fpga_info(unsigned dev)
+{
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_rs232;
+	unsigned feature_audio;
+	unsigned feature_sysclock;
+	unsigned feature_ramconfig;
+	unsigned feature_carrier_speed;
+	unsigned feature_carriers;
+	unsigned feature_video_channels;
+	int fpga_state = get_fpga_state(dev);
+
+	printf("FPGA%d: ", dev);
+
+	FPGA_GET_REG(dev, versions, &versions);
+	FPGA_GET_REG(dev, fpga_version, &fpga_version);
+	FPGA_GET_REG(dev, fpga_features, &fpga_features);
+
+	hardware_version = versions & 0x000f;
+
+	if (fpga_state
+	    && !((hardware_version == HWVER_101)
+		 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
+		puts("not available\n");
+		print_fpga_state(dev);
+		return;
+	}
+
+	unit_type = (versions >> 4) & 0x000f;
+	hardware_version = versions & 0x000f;
+	feature_rs232 = fpga_features & (1<<11);
+	feature_audio = (fpga_features >> 9) & 0x0003;
+	feature_sysclock = (fpga_features >> 7) & 0x0003;
+	feature_ramconfig = (fpga_features >> 5) & 0x0003;
+	feature_carrier_speed = fpga_features & (1<<4);
+	feature_carriers = (fpga_features >> 2) & 0x0003;
+	feature_video_channels = fpga_features & 0x0003;
+
+	if (unit_type & UNITTYPE_MAIN)
+		printf("Mainchannel ");
+	else
+		printf("Videochannel ");
+
+	if (unit_type & UNITTYPE_SERVER)
+		printf("Serverside ");
+	else
+		printf("Userside ");
+
+	if (unit_type & UNITTYPE_DISPLAYPORT)
+		printf("DisplayPort");
+	else
+		printf("DVI-DL");
+
+	switch (hardware_version) {
+	case HWVER_101:
+		printf(" HW-Ver 1.01\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10-1.20\n");
+		break;
+
+	case HWVER_130:
+		printf(" HW-Ver 1.30\n");
+		break;
+
+	case HWVER_140:
+		printf(" HW-Ver 1.40-1.43\n");
+		break;
+
+	case HWVER_150:
+		printf(" HW-Ver 1.50\n");
+		break;
+
+	case HWVER_160:
+		printf(" HW-Ver 1.60-1.61\n");
+		break;
+
+	case HWVER_170:
+		printf(" HW-Ver 1.70\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %sRS232", feature_rs232 ? "" : "no ");
+
+	switch (feature_audio) {
+	case AUDIO_NONE:
+		printf(", no audio");
+		break;
+
+	case AUDIO_TX:
+		printf(", audio tx");
+		break;
+
+	case AUDIO_RX:
+		printf(", audio rx");
+		break;
+
+	case AUDIO_RXTX:
+		printf(", audio rx+tx");
+		break;
+
+	default:
+		printf(", audio %d(not supported)", feature_audio);
+		break;
+	}
+
+	switch (feature_sysclock) {
+	case SYSCLK_156250:
+		printf(", clock 156.25 MHz");
+		break;
+
+	default:
+		printf(", clock %d(not supported)", feature_sysclock);
+		break;
+	}
+
+	puts(",\n       ");
+
+	switch (feature_ramconfig) {
+	case RAM_NONE:
+		printf("no RAM");
+		break;
+
+	case RAM_DDR2_32:
+		printf("RAM 32 bit DDR2");
+		break;
+
+	case RAM_DDR2_64:
+		printf("RAM 64 bit DDR2");
+		break;
+
+	default:
+		printf("RAM %d(not supported)", feature_ramconfig);
+		break;
+	}
+
+	printf(", %d carrier(s) %s", feature_carriers,
+		feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
+
+	printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: ");
+
+	puts("DLVision 10G");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	u16 versions;
+
+	FPGA_GET_REG(0, versions, &versions);
+
+	print_fpga_info(0);
+	if (get_mc2_present())
+		print_fpga_info(1);
+
+	if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER)
+		return 0;
+
+	if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
+		osd_probe(0);
+
+	if (get_mc2_present() &&
+	    (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
+		osd_probe(1);
+
+	return 0;
+}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+	if (state) {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+	} else {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+	}
+}
+
+void gd405ep_setup_hw(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+	return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}

u-boot/board/gdsys/405ep/io.c

@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <dtt.h>
+#include <miiphy.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+#define PHYREG_CONTROL				0
+#define PHYREG_PAGE_ADDRESS			22
+#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1	16
+#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26
+
+enum {
+	UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+	HWVER_100 = 0,
+	HWVER_110 = 1,
+	HWVER_121 = 2,
+	HWVER_122 = 3,
+};
+
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int misc_init_r(void)
+{
+	/* startup fans */
+	dtt_init();
+
+	return 0;
+}
+
+int configure_gbit_phy(unsigned char addr)
+{
+	unsigned short value;
+
+	/* select page 2 */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PAGE_ADDRESS, 0x0002))
+		goto err_out;
+	/* disable SGMII autonegotiation */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
+		goto err_out;
+	/* select page 0 */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PAGE_ADDRESS, 0x0000))
+		goto err_out;
+	/* switch from powerdown to normal operation */
+	if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
+		goto err_out;
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
+		goto err_out;
+	/* reset phy so settings take effect */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_CONTROL, 0x9140))
+		goto err_out;
+
+	return 0;
+
+err_out:
+	printf("Error writing to the PHY addr=%02x\n", addr);
+	return -1;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: CATCenter Io");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+static void print_fpga_info(void)
+{
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_channels;
+	unsigned feature_expansion;
+
+	FPGA_GET_REG(0, versions, &versions);
+	FPGA_GET_REG(0, fpga_version, &fpga_version);
+	FPGA_GET_REG(0, fpga_features, &fpga_features);
+
+	unit_type = (versions & 0xf000) >> 12;
+	hardware_version = versions & 0x000f;
+	feature_channels = fpga_features & 0x007f;
+	feature_expansion = fpga_features & (1<<15);
+
+	puts("FPGA:  ");
+
+	switch (unit_type) {
+	case UNITTYPE_CCD_SWITCH:
+		printf("CCD-Switch");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf(" HW-Ver 1.00\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	case HWVER_121:
+		printf(" HW-Ver 1.21\n");
+		break;
+
+	case HWVER_122:
+		printf(" HW-Ver 1.22\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %d channel(s)", feature_channels);
+
+	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+}
+
+/*
+ * setup Gbit PHYs
+ */
+int last_stage_init(void)
+{
+	unsigned int k;
+
+	print_fpga_info();
+
+	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
+		bb_miiphy_read, bb_miiphy_write);
+
+	for (k = 0; k < 32; ++k)
+		configure_gbit_phy(k);
+
+	/* take fpga serdes blocks out of reset */
+	FPGA_SET_REG(0, quad_serdes_reset, 0);
+
+	return 0;
+}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+	if (state) {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+	} else {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+	}
+}
+
+void gd405ep_setup_hw(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+	return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}

u-boot/board/gdsys/405ep/iocon.c

@@ -0,0 +1,654 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+#include "../common/mclink.h"
+#include "../common/phy.h"
+
+#include <i2c.h>
+#include <pca953x.h>
+#include <pca9698.h>
+
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+#define MAX_MUX_CHANNELS 2
+
+enum {
+	UNITTYPE_MAIN_SERVER = 0,
+	UNITTYPE_MAIN_USER = 1,
+	UNITTYPE_VIDEO_SERVER = 2,
+	UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+	HWVER_100 = 0,
+	HWVER_104 = 1,
+	HWVER_110 = 2,
+	HWVER_120 = 3,
+	HWVER_200 = 4,
+	HWVER_210 = 5,
+	HWVER_220 = 6,
+	HWVER_230 = 7,
+};
+
+enum {
+	FPGA_HWVER_200 = 0,
+	FPGA_HWVER_210 = 1,
+};
+
+enum {
+	COMPRESSION_NONE = 0,
+	COMPRESSION_TYPE1_DELTA = 1,
+	COMPRESSION_TYPE1_TYPE2_DELTA = 3,
+};
+
+enum {
+	AUDIO_NONE = 0,
+	AUDIO_TX = 1,
+	AUDIO_RX = 2,
+	AUDIO_RXTX = 3,
+};
+
+enum {
+	SYSCLK_147456 = 0,
+};
+
+enum {
+	RAM_DDR2_32 = 0,
+	RAM_DDR3_32 = 1,
+};
+
+enum {
+	CARRIER_SPEED_1G = 0,
+	CARRIER_SPEED_2_5G = 1,
+};
+
+enum {
+	MCFPGA_DONE = 1 << 0,
+	MCFPGA_INIT_N = 1 << 1,
+	MCFPGA_PROGRAM_N = 1 << 2,
+	MCFPGA_UPDATE_ENABLE_N = 1 << 3,
+	MCFPGA_RESET_N = 1 << 4,
+};
+
+enum {
+	GPIO_MDC = 1 << 14,
+	GPIO_MDIO = 1 << 15,
+};
+
+unsigned int mclink_fpgacount;
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+	int res;
+
+	switch (fpga) {
+	case 0:
+		out_le16(reg, data);
+		break;
+	default:
+		res = mclink_send(fpga - 1, regoff, data);
+		if (res < 0) {
+			printf("mclink_send reg %02lx data %04x returned %d\n",
+			       regoff, data, res);
+			return res;
+		}
+		break;
+	}
+
+	return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+	int res;
+
+	switch (fpga) {
+	case 0:
+		*data = in_le16(reg);
+		break;
+	default:
+		if (fpga > mclink_fpgacount)
+			return -EINVAL;
+		res = mclink_receive(fpga - 1, regoff, data);
+		if (res < 0) {
+			printf("mclink_receive reg %02lx returned %d\n",
+			       regoff, res);
+			return res;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: ");
+
+	puts("IoCon");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
+{
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_compression;
+	unsigned feature_osd;
+	unsigned feature_audio;
+	unsigned feature_sysclock;
+	unsigned feature_ramconfig;
+	unsigned feature_carrier_speed;
+	unsigned feature_carriers;
+	unsigned feature_video_channels;
+
+	int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM;
+
+	FPGA_GET_REG(fpga, versions, &versions);
+	FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+	FPGA_GET_REG(fpga, fpga_features, &fpga_features);
+
+	unit_type = (versions & 0xf000) >> 12;
+	feature_compression = (fpga_features & 0xe000) >> 13;
+	feature_osd = fpga_features & (1<<11);
+	feature_audio = (fpga_features & 0x0600) >> 9;
+	feature_sysclock = (fpga_features & 0x0180) >> 7;
+	feature_ramconfig = (fpga_features & 0x0060) >> 5;
+	feature_carrier_speed = fpga_features & (1<<4);
+	feature_carriers = (fpga_features & 0x000c) >> 2;
+	feature_video_channels = fpga_features & 0x0003;
+
+	if (legacy)
+		printf("legacy ");
+
+	switch (unit_type) {
+	case UNITTYPE_MAIN_USER:
+		printf("Mainchannel");
+		break;
+
+	case UNITTYPE_VIDEO_USER:
+		printf("Videochannel");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	if (unit_type == UNITTYPE_MAIN_USER) {
+		if (legacy)
+			hardware_version =
+				(in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
+		else
+			hardware_version =
+				  (!!pca9698_get_value(0x20, 24) << 0)
+				| (!!pca9698_get_value(0x20, 25) << 1)
+				| (!!pca9698_get_value(0x20, 26) << 2)
+				| (!!pca9698_get_value(0x20, 27) << 3);
+		switch (hardware_version) {
+		case HWVER_100:
+			printf(" HW-Ver 1.00,");
+			break;
+
+		case HWVER_104:
+			printf(" HW-Ver 1.04,");
+			break;
+
+		case HWVER_110:
+			printf(" HW-Ver 1.10,");
+			break;
+
+		case HWVER_120:
+			printf(" HW-Ver 1.20-1.21,");
+			break;
+
+		case HWVER_200:
+			printf(" HW-Ver 2.00,");
+			break;
+
+		case HWVER_210:
+			printf(" HW-Ver 2.10,");
+			break;
+
+		case HWVER_220:
+			printf(" HW-Ver 2.20,");
+			break;
+
+		case HWVER_230:
+			printf(" HW-Ver 2.30,");
+			break;
+
+		default:
+			printf(" HW-Ver %d(not supported),",
+			       hardware_version);
+			break;
+		}
+		if (rgmii2_present)
+			printf(" RGMII2,");
+	}
+
+	if (unit_type == UNITTYPE_VIDEO_USER) {
+		hardware_version = versions & 0x000f;
+		switch (hardware_version) {
+		case FPGA_HWVER_200:
+			printf(" HW-Ver 2.00,");
+			break;
+
+		case FPGA_HWVER_210:
+			printf(" HW-Ver 2.10,");
+			break;
+
+		default:
+			printf(" HW-Ver %d(not supported),",
+			       hardware_version);
+			break;
+		}
+	}
+
+	printf(" FPGA V %d.%02d\n       features:",
+	       fpga_version / 100, fpga_version % 100);
+
+
+	switch (feature_compression) {
+	case COMPRESSION_NONE:
+		printf(" no compression");
+		break;
+
+	case COMPRESSION_TYPE1_DELTA:
+		printf(" type1-deltacompression");
+		break;
+
+	case COMPRESSION_TYPE1_TYPE2_DELTA:
+		printf(" type1-deltacompression, type2-inlinecompression");
+		break;
+
+	default:
+		printf(" compression %d(not supported)", feature_compression);
+		break;
+	}
+
+	printf(", %sosd", feature_osd ? "" : "no ");
+
+	switch (feature_audio) {
+	case AUDIO_NONE:
+		printf(", no audio");
+		break;
+
+	case AUDIO_TX:
+		printf(", audio tx");
+		break;
+
+	case AUDIO_RX:
+		printf(", audio rx");
+		break;
+
+	case AUDIO_RXTX:
+		printf(", audio rx+tx");
+		break;
+
+	default:
+		printf(", audio %d(not supported)", feature_audio);
+		break;
+	}
+
+	puts(",\n       ");
+
+	switch (feature_sysclock) {
+	case SYSCLK_147456:
+		printf("clock 147.456 MHz");
+		break;
+
+	default:
+		printf("clock %d(not supported)", feature_sysclock);
+		break;
+	}
+
+	switch (feature_ramconfig) {
+	case RAM_DDR2_32:
+		printf(", RAM 32 bit DDR2");
+		break;
+
+	case RAM_DDR3_32:
+		printf(", RAM 32 bit DDR3");
+		break;
+
+	default:
+		printf(", RAM %d(not supported)", feature_ramconfig);
+		break;
+	}
+
+	printf(", %d carrier(s) %s", feature_carriers,
+	       feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
+
+	printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+int last_stage_init(void)
+{
+	int slaves;
+	unsigned int k;
+	unsigned int mux_ch;
+	unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
+	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+	u16 fpga_features;
+	int feature_carrier_speed;
+	bool ch0_rgmii2_present = false;
+
+	FPGA_GET_REG(0, fpga_features, &fpga_features);
+	feature_carrier_speed = fpga_features & (1<<4);
+
+	if (!legacy) {
+		/* Turn on Parade DP501 */
+		pca9698_direction_output(0x20, 9, 1);
+
+		ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+	}
+
+	/* wait for FPGA done; then reset FPGA */
+	for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
+		unsigned int ctr = 0;
+
+		if (i2c_probe(mclink_controllers[k]))
+			continue;
+
+		while (!(pca953x_get_val(mclink_controllers[k])
+		       & MCFPGA_DONE)) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				printf("no done for mclink_controller %d\n", k);
+				break;
+			}
+		}
+
+		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
+		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
+		udelay(10);
+		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
+				MCFPGA_RESET_N);
+	}
+
+	if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
+		miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
+				bb_miiphy_write);
+		for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
+			if ((mux_ch == 1) && !ch0_rgmii2_present)
+				continue;
+
+			setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
+		}
+	}
+
+	/* give slave-PLLs and Parade DP501 some time to be up and running */
+	udelay(500000);
+
+	mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
+	slaves = mclink_probe();
+	mclink_fpgacount = 0;
+
+	print_fpga_info(0, ch0_rgmii2_present);
+	osd_probe(0);
+
+	if (slaves <= 0)
+		return 0;
+
+	mclink_fpgacount = slaves;
+
+	for (k = 1; k <= slaves; ++k) {
+		FPGA_GET_REG(k, fpga_features, &fpga_features);
+		feature_carrier_speed = fpga_features & (1<<4);
+
+		print_fpga_info(k, false);
+		osd_probe(k);
+		if (feature_carrier_speed == CARRIER_SPEED_1G) {
+			miiphy_register(bb_miiphy_buses[k].name,
+					bb_miiphy_read, bb_miiphy_write);
+			setup_88e1518(bb_miiphy_buses[k].name, 0);
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ * (these may look all too simple but make iocon.h much more readable)
+ */
+void fpga_gpio_set(unsigned int bus, int pin)
+{
+	FPGA_SET_REG(bus, gpio.set, pin);
+}
+
+void fpga_gpio_clear(unsigned int bus, int pin)
+{
+	FPGA_SET_REG(bus, gpio.clear, pin);
+}
+
+int fpga_gpio_get(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus, gpio.read, &val);
+
+	return val & pin;
+}
+
+void gd405ep_init(void)
+{
+	unsigned int k;
+
+	if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
+		for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+			gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
+	} else {
+		pca9698_direction_output(0x20, 4, 1);
+	}
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+	if (legacy) {
+		if (state) {
+			out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+			out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+		} else {
+			out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+			out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+		}
+	} else {
+		pca9698_set_value(0x20, 4, state ? 0 : 1);
+	}
+}
+
+void gd405ep_setup_hw(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+	if (legacy)
+		return in_le16((void *)LATCH2_BASE)
+		       & CONFIG_SYS_FPGA_DONE(fpga);
+	else
+		return pca9698_get_value(0x20, 20);
+}
+
+/*
+ * FPGA MII bitbang implementation
+ */
+
+struct fpga_mii {
+	unsigned fpga;
+	int mdio;
+} fpga_mii[] = {
+	{ 0, 1},
+	{ 1, 1},
+	{ 2, 1},
+	{ 3, 1},
+};
+
+static int mii_dummy_init(struct bb_miiphy_bus *bus)
+{
+	return 0;
+}
+
+static int mii_mdio_active(struct bb_miiphy_bus *bus)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	if (fpga_mii->mdio)
+		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+	else
+		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+	return 0;
+}
+
+static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+
+	return 0;
+}
+
+static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	if (v)
+		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+	else
+		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+	fpga_mii->mdio = v;
+
+	return 0;
+}
+
+static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+	u16 gpio;
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
+
+	*v = ((gpio & GPIO_MDIO) != 0);
+
+	return 0;
+}
+
+static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	if (v)
+		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
+	else
+		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
+
+	return 0;
+}
+
+static int mii_delay(struct bb_miiphy_bus *bus)
+{
+	udelay(1);
+
+	return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+	{
+		.name = "board0",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[0],
+	},
+	{
+		.name = "board1",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[1],
+	},
+	{
+		.name = "board2",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[2],
+	},
+	{
+		.name = "board3",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[3],
+	},
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+			  sizeof(bb_miiphy_buses[0]);

u-boot/board/gdsys/405ep/neo.c

@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+enum {
+	UNITTYPE_CCX16 = 1,
+	UNITTYPE_CCIP216 = 2,
+};
+
+enum {
+	HWVER_300 = 3,
+};
+
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int misc_init_r(void)
+{
+	/* startup fans */
+	dtt_init();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: CATCenter Neo");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+static void print_fpga_info(void)
+{
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
+	int fpga_state = get_fpga_state(0);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_channels;
+
+	puts("FPGA:  ");
+	if (fpga_state & FPGA_STATE_DONE_FAILED) {
+		printf(" done timed out\n");
+		return;
+	}
+
+	if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
+		printf(" refelectione test failed\n");
+		return;
+	}
+
+	FPGA_GET_REG(0, versions, &versions);
+	FPGA_GET_REG(0, fpga_version, &fpga_version);
+	FPGA_GET_REG(0, fpga_features, &fpga_features);
+
+	unit_type = (versions & 0xf000) >> 12;
+	hardware_version = versions & 0x000f;
+	feature_channels = fpga_features & 0x007f;
+
+	switch (unit_type) {
+	case UNITTYPE_CCX16:
+		printf("CCX-Switch");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_300:
+		printf(" HW-Ver 3.00-3.12\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %d channel(s)\n", feature_channels);
+}
+
+int last_stage_init(void)
+{
+	print_fpga_info();
+
+	return 0;
+}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+	if (state) {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+	} else {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+	}
+}
+
+void gd405ep_setup_hw(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+	/*
+	 * Neo hardware has no FPGA-DONE GPIO
+	 */
+	return 1;
+}

u-boot/board/gdsys/405ex/405ex.c

@@ -0,0 +1,252 @@
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#include <gdsys_fpga.h>
+
+#include "405ex.h"
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+	return gd->arch.fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+	if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+		puts("       Waiting for FPGA-DONE timed out.\n");
+	if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+		puts("       FPGA reflection test failed.\n");
+}
+
+int board_early_init_f(void)
+{
+	u32 val;
+
+	/*--------------------------------------------------------------------+
+	 | Interrupt controller setup
+	 +--------------------------------------------------------------------+
+	+---------------------------------------------------------------------+
+	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
+	+---------+-----------------------------------+-------+-------+-------+
+	| IRQ 00  | UART0                             | High  | Level | Non   |
+	| IRQ 01  | UART1                             | High  | Level | Non   |
+	| IRQ 02  | IIC0                              | High  | Level | Non   |
+	| IRQ 03  | TBD                               | High  | Level | Non   |
+	| IRQ 04  | TBD                               | High  | Level | Non   |
+	| IRQ 05  | EBM                               | High  | Level | Non   |
+	| IRQ 06  | BGI                               | High  | Level | Non   |
+	| IRQ 07  | IIC1                              | Rising| Edge  | Non   |
+	| IRQ 08  | SPI                               | High  | Lvl/ed| Non   |
+	| IRQ 09  | External IRQ 0 - (PCI-Express)    | pgm H | Pgm   | Non   |
+	| IRQ 10  | MAL TX EOB                        | High  | Level | Non   |
+	| IRQ 11  | MAL RX EOB                        | High  | Level | Non   |
+	| IRQ 12  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
+	| IRQ 13  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
+	| IRQ 14  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
+	| IRQ 15  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
+	| IRQ 16  | PCIE0 AL                          | high  | Level | Non   |
+	| IRQ 17  | PCIE0 VPD access                  | rising| Edge  | Non   |
+	| IRQ 18  | PCIE0 hot reset request           | rising| Edge  | Non   |
+	| IRQ 19  | PCIE0 hot reset request           | faling| Edge  | Non   |
+	| IRQ 20  | PCIE0 TCR                         | High  | Level | Non   |
+	| IRQ 21  | PCIE0 MSI level0                  | High  | Level | Non   |
+	| IRQ 22  | PCIE0 MSI level1                  | High  | Level | Non   |
+	| IRQ 23  | Security EIP-94                   | High  | Level | Non   |
+	| IRQ 24  | EMAC0 interrupt                   | High  | Level | Non   |
+	| IRQ 25  | EMAC1 interrupt                   | High  | Level | Non   |
+	| IRQ 26  | PCIE0 MSI level2                  | High  | Level | Non   |
+	| IRQ 27  | External IRQ 4                    | pgm H | Pgm   | Non   |
+	| IRQ 28  | UIC2 Non-critical Int.            | High  | Level | Non   |
+	| IRQ 29  | UIC2 Critical Interrupt           | High  | Level | Crit. |
+	| IRQ 30  | UIC1 Non-critical Int.            | High  | Level | Non   |
+	| IRQ 31  | UIC1 Critical Interrupt           | High  | Level | Crit. |
+	|----------------------------------------------------------------------
+	| IRQ 32  | MAL Serr                          | High  | Level | Non   |
+	| IRQ 33  | MAL Txde                          | High  | Level | Non   |
+	| IRQ 34  | MAL Rxde                          | High  | Level | Non   |
+	| IRQ 35  | PCIE0 bus master VC0              |falling| Edge  | Non   |
+	| IRQ 36  | PCIE0 DCR Error                   | High  | Level | Non   |
+	| IRQ 37  | EBC                               | High  |Lvl Edg| Non   |
+	| IRQ 38  | NDFC                              | High  | Level | Non   |
+	| IRQ 39  | GPT Compare Timer 8               | Risin | Edge  | Non   |
+	| IRQ 40  | GPT Compare Timer 9               | Risin | Edge  | Non   |
+	| IRQ 41  | PCIE1 AL                          | high  | Level | Non   |
+	| IRQ 42  | PCIE1 VPD access                  | rising| edge  | Non   |
+	| IRQ 43  | PCIE1 hot reset request           | rising| Edge  | Non   |
+	| IRQ 44  | PCIE1 hot reset request           | faling| Edge  | Non   |
+	| IRQ 45  | PCIE1 TCR                         | High  | Level | Non   |
+	| IRQ 46  | PCIE1 bus master VC0              |falling| Edge  | Non   |
+	| IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
+	| IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
+	| IRQ 49  | Ext. IRQ 7                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 50  | Ext. IRQ 8 -                      |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 51  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
+	| IRQ 52  | GPT Compare Timer 5               | high  | Edge  | Non   |
+	| IRQ 53  | GPT Compare Timer 6               | high  | Edge  | Non   |
+	| IRQ 54  | GPT Compare Timer 7               | high  | Edge  | Non   |
+	| IRQ 55  | Serial ROM                        | High  | Level | Non   |
+	| IRQ 56  | GPT Decrement Pulse               | High  | Level | Non   |
+	| IRQ 57  | Ext. IRQ 2                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 58  | Ext. IRQ 5                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 59  | Ext. IRQ 6                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 60  | EMAC0 Wake-up                     | High  | Level | Non   |
+	| IRQ 61  | Ext. IRQ 1                        |pgm/Fal|pgm/Lvl| Non   |
+	| IRQ 62  | EMAC1 Wake-up                     | High  | Level | Non   |
+	|----------------------------------------------------------------------
+	| IRQ 64  | PE0 AL                            | High  | Level | Non   |
+	| IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 68  | PE0 TCR                           | High  | Level | Non   |
+	| IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
+	| IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 72  | PE1 AL                            | High  | Level | Non   |
+	| IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 76  | PE1 TCR                           | High  | Level | Non   |
+	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
+	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
+	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
+	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
+	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
+	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
+	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
+	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
+	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
+	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
+	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
+	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
+	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
+	|---------------------------------------------------------------------
+	+---------+-----------------------------------+-------+-------+------*/
+	/*--------------------------------------------------------------------+
+	 | Initialise UIC registers.  Clear all interrupts.  Disable all
+	 | interrupts.
+	 | Set critical interrupt values.  Set interrupt polarities.  Set
+	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
+	 | interrupts again.
+	 +-------------------------------------------------------------------*/
+
+	mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
+	mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
+	mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+	mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
+	mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+	mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+	mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
+	mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
+
+	mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
+	mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
+	mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+	mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
+	mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
+	mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+	mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */
+	mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
+
+	mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
+	mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */
+				   /* Except cascade UIC0 and UIC1 */
+	mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+	mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
+	mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
+	mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+	mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */
+	mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
+
+	/*
+	 * Note: Some cores are still in reset when the chip starts, so
+	 * take them out of reset
+	 */
+	mtsdr(SDR0_SRST, 0);
+
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 */
+	val = SDR0_PFC1_GPT_FREQ;
+	mtsdr(SDR0_PFC1, val);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	unsigned k;
+	unsigned ctr;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->arch.fpga_state[k] = 0;
+
+	/*
+	 * reset FPGA
+	 */
+	gd405ex_init();
+
+	gd405ex_set_fpga_reset(1);
+
+	gd405ex_setup_hw();
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ctr = 0;
+		while (!gd405ex_get_fpga_done(k)) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_DONE_FAILED;
+				break;
+			}
+		}
+	}
+
+	udelay(10);
+
+	gd405ex_set_fpga_reset(0);
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		/*
+		 * wait for fpga out of reset
+		 */
+		ctr = 0;
+		while (1) {
+			u16 val;
+
+			FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
+
+			FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+			if (val == REFLECTION_TESTPATTERN_INV)
+				break;
+
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_REFLECTION_FAILED;
+				break;
+			}
+		}
+	}
+
+	return 0;
+}

u-boot/board/gdsys/405ex/405ex.h

@@ -0,0 +1,10 @@
+#ifndef __405EX_H_
+#define __405EX_H_
+
+/* functions to be provided by board implementation */
+void gd405ex_init(void);
+void gd405ex_set_fpga_reset(unsigned state);
+void gd405ex_setup_hw(void);
+int gd405ex_get_fpga_done(unsigned fpga);
+
+#endif /* __405EX_H_ */

u-boot/board/gdsys/405ex/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_IO64
+
+config SYS_BOARD
+	default "405ex"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "io64"
+
+endif

u-boot/board/gdsys/405ex/MAINTAINERS

@@ -0,0 +1,6 @@
+405EX BOARD
+M:	Dirk Eibach <eibach@gdsys.de>
+S:	Maintained
+F:	board/gdsys/405ex/
+F:	include/configs/io64.h
+F:	configs/io64_defconfig

u-boot/board/gdsys/405ex/Makefile

@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := 405ex.o
+obj-$(CONFIG_IO64) += io64.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o

u-boot/board/gdsys/405ex/chip_config.c

@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"333-nor", "NOR  CPU: 333 PLB: 166 OPB:  83 EBC:  83",
+		{
+			0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"400-133-nor", "NOR  CPU: 400 PLB: 133 OPB:  66 EBC:  66",
+		{
+			0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"400-200-66-nor", "NOR  CPU: 400 PLB: 200 OPB:  66 EBC:  66",
+		{
+			0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"400-nor", "NOR  CPU: 400 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"533-nor", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
+		{
+			0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"533-nand", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
+		{
+			0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"600-nand", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"666-nor", "NOR  CPU: 666 PLB: 222 OPB: 111 EBC: 111",
+		{
+			0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);

u-boot/board/gdsys/405ex/io64.c

@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * based on kilauea.c
+ * by Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/ppc4xx-gpio.h>
+#include <flash.h>
+
+#include <pca9698.h>
+
+#include "405ex.h"
+#include <gdsys_fpga.h>
+
+#include <miiphy.h>
+#include <i2c.h>
+#include <dtt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PHYREG_CONTROL				0
+#define PHYREG_PAGE_ADDRESS			22
+#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1	16
+#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26
+#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1	17
+#define PHYREG_PG2_MAC_SPECIFIC_CONTROL		21
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
+
+enum {
+	UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+	HWVER_100 = 0,
+	HWVER_110 = 1,
+};
+
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+static inline void blank_string(int size)
+{
+	int i;
+
+	for (i = 0; i < size; i++)
+		putc('\b');
+	for (i = 0; i < size; i++)
+		putc(' ');
+	for (i = 0; i < size; i++)
+		putc('\b');
+}
+
+/*
+ * Board early initialization function
+ */
+int misc_init_r(void)
+{
+	/* startup fans */
+	dtt_init();
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      -CONFIG_SYS_MONITOR_LEN,
+		      0xffffffff,
+		      &flash_info[0]);
+#endif
+
+	return 0;
+}
+
+static void print_fpga_info(unsigned dev)
+{
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
+	int fpga_state = get_fpga_state(dev);
+
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_channels;
+	unsigned feature_expansion;
+
+	FPGA_GET_REG(dev, versions, &versions);
+	FPGA_GET_REG(dev, fpga_version, &fpga_version);
+	FPGA_GET_REG(dev, fpga_features, &fpga_features);
+
+	printf("FPGA%d: ", dev);
+	if (fpga_state & FPGA_STATE_PLATFORM)
+		printf("(legacy) ");
+
+	if (fpga_state & FPGA_STATE_DONE_FAILED) {
+		printf(" done timed out\n");
+		return;
+	}
+
+	if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
+		printf(" refelectione test failed\n");
+		return;
+	}
+
+	unit_type = (versions & 0xf000) >> 12;
+	hardware_version = versions & 0x000f;
+	feature_channels = fpga_features & 0x007f;
+	feature_expansion = fpga_features & (1<<15);
+
+	switch (unit_type) {
+	case UNITTYPE_CCD_SWITCH:
+		printf("CCD-Switch");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf(" HW-Ver 1.00\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %d channel(s)", feature_channels);
+
+	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: CATCenter Io64\n");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	return 0;
+}
+
+int configure_gbit_phy(char *bus, unsigned char addr)
+{
+	unsigned short value;
+
+	/* select page 0 */
+	if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
+		goto err_out;
+	/* switch to powerdown */
+	if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+		&value))
+		goto err_out;
+	if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+		value | 0x0004))
+		goto err_out;
+	/* select page 2 */
+	if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
+		goto err_out;
+	/* disable SGMII autonegotiation */
+	if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48))
+		goto err_out;
+	/* select page 0 */
+	if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
+		goto err_out;
+	/* switch from powerdown to normal operation */
+	if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+		&value))
+		goto err_out;
+	if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+		value & ~0x0004))
+		goto err_out;
+	/* reset phy so settings take effect */
+	if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140))
+		goto err_out;
+
+	return 0;
+
+err_out:
+	printf("Error writing to the PHY addr=%02x\n", addr);
+	return -1;
+}
+
+int verify_gbit_phy(char *bus, unsigned char addr)
+{
+	unsigned short value;
+
+	/* select page 2 */
+	if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
+		goto err_out;
+	/* verify SGMII link status */
+	if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value))
+		goto err_out;
+	if (!(value & (1 << 10)))
+		return -2;
+
+	return 0;
+
+err_out:
+	printf("Error writing to the PHY addr=%02x\n", addr);
+	return -1;
+}
+
+int last_stage_init(void)
+{
+	unsigned int k;
+	unsigned int fpga;
+	int failed = 0;
+	char str_phys[] = "Setup PHYs -";
+	char str_serdes[] = "Start SERDES blocks";
+	char str_channels[] = "Start FPGA channels";
+	char str_locks[] = "Verify SERDES locks";
+	char str_hicb[] = "Verify HICB status";
+	char str_status[] = "Verify PHY status -";
+	char slash[] = "\\|/-\\|/-";
+
+	print_fpga_info(0);
+	print_fpga_info(1);
+
+	/* setup Gbit PHYs */
+	puts("TRANS: ");
+	puts(str_phys);
+	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
+		bb_miiphy_read, bb_miiphy_write);
+
+	for (k = 0; k < 32; ++k) {
+		configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
+		putc('\b');
+		putc(slash[k % 8]);
+	}
+
+	miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME,
+		bb_miiphy_read, bb_miiphy_write);
+
+	for (k = 0; k < 32; ++k) {
+		configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
+		putc('\b');
+		putc(slash[k % 8]);
+	}
+	blank_string(strlen(str_phys));
+
+	/* take fpga serdes blocks out of reset */
+	puts(str_serdes);
+	udelay(500000);
+	FPGA_SET_REG(0, quad_serdes_reset, 0);
+	FPGA_SET_REG(1, quad_serdes_reset, 0);
+	blank_string(strlen(str_serdes));
+
+	/* take channels out of reset */
+	puts(str_channels);
+	udelay(500000);
+	for (fpga = 0; fpga < 2; ++fpga) {
+		for (k = 0; k < 32; ++k)
+			FPGA_SET_REG(fpga, ch[k].config_int, 0);
+	}
+	blank_string(strlen(str_channels));
+
+	/* verify channels serdes lock */
+	puts(str_locks);
+	udelay(500000);
+	for (fpga = 0; fpga < 2; ++fpga) {
+		for (k = 0; k < 32; ++k) {
+			u16 status;
+			FPGA_GET_REG(fpga, ch[k].status_int, &status);
+			if (!(status & (1 << 4))) {
+				failed = 1;
+				printf("fpga %d channel %d: no serdes lock\n",
+					fpga, k);
+			}
+			/* reset events */
+			FPGA_SET_REG(fpga, ch[k].status_int, 0);
+		}
+	}
+	blank_string(strlen(str_locks));
+
+	/* verify hicb_status */
+	puts(str_hicb);
+	for (fpga = 0; fpga < 2; ++fpga) {
+		for (k = 0; k < 32; ++k) {
+			u16 status;
+			FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status);
+			if (status)
+				printf("fpga %d hicb %d: hicb status %04x\n",
+					fpga, k, status);
+			/* reset events */
+			FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0);
+		}
+	}
+	blank_string(strlen(str_hicb));
+
+	/* verify phy status */
+	puts(str_status);
+	for (k = 0; k < 32; ++k) {
+		if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
+			printf("verify baseboard phy %d failed\n", k);
+			failed = 1;
+		}
+		putc('\b');
+		putc(slash[k % 8]);
+	}
+	for (k = 0; k < 32; ++k) {
+		if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
+			printf("verify extensionboard phy %d failed\n", k);
+			failed = 1;
+		}
+		putc('\b');
+		putc(slash[k % 8]);
+	}
+	blank_string(strlen(str_status));
+
+	printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
+
+	return 0;
+}
+
+void gd405ex_init(void)
+{
+	unsigned int k;
+
+	if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
+		for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+			gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
+	} else {
+		pca9698_direction_output(0x22, 39, 1);
+	}
+}
+
+void gd405ex_set_fpga_reset(unsigned state)
+{
+	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+	if (legacy) {
+		if (state) {
+			out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+			out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+		} else {
+			out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+			out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+		}
+	} else {
+		pca9698_set_value(0x22, 39, state ? 0 : 1);
+	}
+}
+
+void gd405ex_setup_hw(void)
+{
+	gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1);
+}
+
+int gd405ex_get_fpga_done(unsigned fpga)
+{
+	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+	if (legacy)
+		return in_le16((void *)LATCH3_BASE)
+			& CONFIG_SYS_FPGA_DONE(fpga);
+	else
+		return pca9698_get_value(0x22, fpga ? 9 : 8);
+}

u-boot/board/gdsys/common/Makefile

@@ -0,0 +1,19 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
+obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
+obj-$(CONFIG_IO) += miiphybb.o
+obj-$(CONFIG_IO64) += miiphybb.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o
+obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o
+obj-$(CONFIG_CONTROLCENTERD) += dp501.o
+obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
+obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
+obj-$(CONFIG_STRIDER) += fanctrl.o
+obj-$(CONFIG_STRIDER_CON) += osd.o
+obj-$(CONFIG_STRIDER_CON_DP) += osd.o

u-boot/board/gdsys/common/adv7611.c

@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#define ADV7611_I2C_ADDR 0x4c
+#define ADV7611_RDINFO 0x2051
+
+/*
+ * ADV7611 I2C Addresses in u-boot notation
+ */
+enum {
+	CP_I2C_ADDR = 0x22,
+	DPLL_I2C_ADDR = 0x26,
+	KSV_I2C_ADDR = 0x32,
+	HDMI_I2C_ADDR = 0x34,
+	EDID_I2C_ADDR = 0x36,
+	INFOFRAME_I2C_ADDR = 0x3e,
+	CEC_I2C_ADDR = 0x40,
+	IO_I2C_ADDR = ADV7611_I2C_ADDR,
+};
+
+/*
+ * Global Control Registers
+ */
+enum {
+	IO_RD_INFO_MSB = 0xea,
+	IO_RD_INFO_LSB = 0xeb,
+	IO_CEC_ADDR = 0xf4,
+	IO_INFOFRAME_ADDR = 0xf5,
+	IO_DPLL_ADDR = 0xf8,
+	IO_KSV_ADDR = 0xf9,
+	IO_EDID_ADDR = 0xfa,
+	IO_HDMI_ADDR = 0xfb,
+	IO_CP_ADDR = 0xfd,
+};
+
+int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C;
+
+int adv7611_probe(unsigned int screen)
+{
+	int old_bus = i2c_get_bus_num();
+	unsigned int rd_info;
+	int res = 0;
+
+	i2c_set_bus_num(adv7611_i2c[screen]);
+
+	rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8)
+		  | i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB);
+
+	if (rd_info != ADV7611_RDINFO) {
+		res = -1;
+		goto out;
+	}
+
+	/*
+	 * set I2C addresses to default values
+	 */
+	i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1);
+	i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1);
+	i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1);
+	i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1);
+	i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1);
+	i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1);
+	i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1);
+
+	/*
+	 * do magic initialization sequence from
+	 * "ADV7611 Register Settings Recommendations Revision 1.5"
+	 * with most registers undocumented
+	 */
+	i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00);
+	i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03);
+	i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08);
+	i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f);
+	i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70);
+	i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda);
+	i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01);
+	i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98);
+	i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44);
+
+	/*
+	 * IO_REG_02, default 0xf0
+	 *
+	 * INP_COLOR_SPACE (IO, Address 0x02[7:4])
+	 * default: 0b1111 auto
+	 * set to : 0b0001 force RGB (range 0 to 255) input
+	 *
+	 * RGB_OUT (IO, Address 0x02[1])
+	 * default: 0 YPbPr color space output
+	 * set to : 1 RGB color space output
+	 */
+	i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12);
+
+	/*
+	 * IO_REG_03, default 0x00
+	 *
+	 * OP_FORMAT_SEL (IO, Address 0x03[7:0])
+	 * default: 0x00 8-bit SDR ITU-656 mode
+	 * set to : 0x40 24-bit 4:4:4 SDR mode
+	 */
+	i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40);
+
+	/*
+	 * IO_REG_05, default 0x2c
+	 *
+	 * AVCODE_INSERT_EN (IO, Address 0x05[2])
+	 * default: 1 insert AV codes into data stream
+	 * set to : 0 do not insert AV codes into data stream
+	 */
+	i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28);
+
+	/*
+	 * IO_REG_0C, default 0x62
+	 *
+	 * POWER_DOWN (IO, Address 0x0C[5])
+	 * default: 1 chip is powered down
+	 * set to : 0 chip is operational
+	 */
+	i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42);
+
+	/*
+	 * IO_REG_15, default 0xbe
+	 *
+	 * TRI_SYNCS (IO, Address 0x15[3)
+	 * TRI_LLC (IO, Address 0x15[2])
+	 * TRI_PIX (IO, Address 0x15[1])
+	 * default: 1 video output pins are tristate
+	 * set to : 0 video output pins are active
+	 */
+	i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0);
+
+	/*
+	 * HDMI_REGISTER_02H, default 0xff
+	 *
+	 * CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0])
+	 * default: 1 disable termination
+	 * set to : 0 enable termination
+	 * Future options are:
+	 * - use the chips automatic termination control
+	 * - set this manually on cable detect
+	 * but at the moment this seems a safe default.
+	 */
+	i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe);
+
+	/*
+	 * HDMI_CP_CNTRL_1, default 0x01
+	 *
+	 * HDMI_FRUN_EN (CP, Address 0xBA[0])
+	 * default: 1 Enable the free run feature in HDMI mode
+	 * set to : 0 Disable the free run feature in HDMI mode
+	 */
+	i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00);
+
+	/*
+	 * INT1_CONFIGURATION, default 0x20
+	 *
+	 * INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6])
+	 * default: 00 Interrupt signal is active for 4 Xtal periods
+	 * set to : 11 Active until cleared
+	 *
+	 * INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0])
+	 * default: 00 Open drain
+	 * set to : 10 Drives high when active
+	 */
+	i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2);
+
+out:
+	i2c_set_bus_num(old_bus);
+
+	return res;
+}

u-boot/board/gdsys/common/adv7611.h

@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ADV7611_H_
+#define _ADV7611_H_
+
+int adv7611_probe(unsigned int screen);
+
+#endif

u-boot/board/gdsys/common/ch7301.c

@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Chrontel CH7301C DVI Transmitter */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+
+#define CH7301_I2C_ADDR 0x75
+
+enum {
+	CH7301_CM = 0x1c,		/* Clock Mode Register */
+	CH7301_IC = 0x1d,		/* Input Clock Register */
+	CH7301_GPIO = 0x1e,		/* GPIO Control Register */
+	CH7301_IDF = 0x1f,		/* Input Data Format Register */
+	CH7301_CD = 0x20,		/* Connection Detect Register */
+	CH7301_DC = 0x21,		/* DAC Control Register */
+	CH7301_HPD = 0x23,		/* Hot Plug Detection Register */
+	CH7301_TCTL = 0x31,		/* DVI Control Input Register */
+	CH7301_TPCP = 0x33,		/* DVI PLL Charge Pump Ctrl Register */
+	CH7301_TPD = 0x34,		/* DVI PLL Divide Register */
+	CH7301_TPVT = 0x35,		/* DVI PLL Supply Control Register */
+	CH7301_TPF = 0x36,		/* DVI PLL Filter Register */
+	CH7301_TCT = 0x37,		/* DVI Clock Test Register */
+	CH7301_TSTP = 0x48,		/* Test Pattern Register */
+	CH7301_PM = 0x49,		/* Power Management register */
+	CH7301_VID = 0x4a,		/* Version ID Register */
+	CH7301_DID = 0x4b,		/* Device ID Register */
+	CH7301_DSP = 0x56,		/* DVI Sync polarity Register */
+};
+
+int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+
+int ch7301_probe(unsigned screen, bool power)
+{
+	u8 value;
+
+	i2c_set_bus_num(ch7301_i2c[screen]);
+	if (i2c_probe(CH7301_I2C_ADDR))
+		return -1;
+
+	value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+	if (value != 0x17)
+		return -1;
+
+	if (power) {
+		i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+		i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+		i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+		i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+		i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+	} else {
+		i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00);
+		i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01);
+	}
+
+	return 0;
+}

u-boot/board/gdsys/common/ch7301.h

@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CH7301_H_
+#define _CH7301_H_
+
+int ch7301_probe(unsigned screen, bool power);
+
+#endif

u-boot/board/gdsys/common/cmd_ioloop.c

@@ -0,0 +1,296 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+
+#include <gdsys_fpga.h>
+
+enum {
+	STATE_TX_PACKET_BUILDING = 1<<0,
+	STATE_TX_TRANSMITTING = 1<<1,
+	STATE_TX_BUFFER_FULL = 1<<2,
+	STATE_TX_ERR = 1<<3,
+	STATE_RECEIVE_TIMEOUT = 1<<4,
+	STATE_PROC_RX_STORE_TIMEOUT = 1<<5,
+	STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6,
+	STATE_RX_DIST_ERR = 1<<7,
+	STATE_RX_LENGTH_ERR = 1<<8,
+	STATE_RX_FRAME_CTR_ERR = 1<<9,
+	STATE_RX_FCS_ERR = 1<<10,
+	STATE_RX_PACKET_DROPPED = 1<<11,
+	STATE_RX_DATA_LAST = 1<<12,
+	STATE_RX_DATA_FIRST = 1<<13,
+	STATE_RX_DATA_AVAILABLE = 1<<15,
+};
+
+enum {
+	CTRL_PROC_RECEIVE_ENABLE = 1<<12,
+	CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15,
+};
+
+enum {
+	IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5,
+	IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6,
+	IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7,
+	IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8,
+};
+
+struct io_generic_packet {
+	u16 target_address;
+	u16 source_address;
+	u8 packet_type;
+	u8 bc;
+	u16 packet_length;
+} __attribute__((__packed__));
+
+unsigned long long rx_ctr;
+unsigned long long tx_ctr;
+unsigned long long err_ctr;
+
+static void io_check_status(unsigned int fpga, u16 status, bool silent)
+{
+	u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
+		   STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
+		   STATE_RX_PACKET_DROPPED | STATE_TX_ERR;
+
+	if (!(status & mask)) {
+		FPGA_SET_REG(fpga, ep.rx_tx_status, status);
+		return;
+	}
+
+	err_ctr++;
+	FPGA_SET_REG(fpga, ep.rx_tx_status, status);
+
+	if (silent)
+		return;
+
+	if (status & STATE_RX_PACKET_DROPPED)
+		printf("RX_PACKET_DROPPED, status %04x\n", status);
+
+	if (status & STATE_RX_DIST_ERR)
+		printf("RX_DIST_ERR\n");
+	if (status & STATE_RX_LENGTH_ERR)
+		printf("RX_LENGTH_ERR\n");
+	if (status & STATE_RX_FRAME_CTR_ERR)
+		printf("RX_FRAME_CTR_ERR\n");
+	if (status & STATE_RX_FCS_ERR)
+		printf("RX_FCS_ERR\n");
+
+	if (status & STATE_TX_ERR)
+		printf("TX_ERR\n");
+}
+
+static void io_send(unsigned int fpga, unsigned int size)
+{
+	unsigned int k;
+	struct io_generic_packet packet = {
+		.source_address = 1,
+		.packet_type = 1,
+		.packet_length = size,
+	};
+	u16 *p = (u16 *)&packet;
+
+	for (k = 0; k < sizeof(packet) / 2; ++k)
+		FPGA_SET_REG(fpga, ep.transmit_data, *p++);
+
+	for (k = 0; k < (size + 1) / 2; ++k)
+		FPGA_SET_REG(fpga, ep.transmit_data, k);
+
+	FPGA_SET_REG(fpga, ep.rx_tx_control,
+		     CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
+
+	tx_ctr++;
+}
+
+static void io_receive(unsigned int fpga)
+{
+	unsigned int k = 0;
+	u16 rx_tx_status;
+
+	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+	while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
+		u16 rx;
+
+		if (rx_tx_status & STATE_RX_DATA_LAST)
+			rx_ctr++;
+
+		FPGA_GET_REG(fpga, ep.receive_data, &rx);
+
+		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+		++k;
+	}
+}
+
+static void io_reflect(unsigned int fpga)
+{
+	u16 buffer[128];
+
+	unsigned int k = 0;
+	unsigned int n;
+	u16 rx_tx_status;
+
+	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+	while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
+		FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]);
+		if (rx_tx_status & STATE_RX_DATA_LAST)
+			break;
+
+		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+	}
+
+	if (!k)
+		return;
+
+	for (n = 0; n < k; ++n)
+		FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]);
+
+	FPGA_SET_REG(fpga, ep.rx_tx_control,
+		     CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
+
+	tx_ctr++;
+}
+
+/*
+ * FPGA io-endpoint reflector
+ *
+ * Syntax:
+ *	ioreflect {fpga} {reportrate}
+ */
+int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int fpga;
+	unsigned int rate = 0;
+	unsigned long long last_seen = 0;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	fpga = simple_strtoul(argv[1], NULL, 10);
+
+	/*
+	 * If another parameter, it is the report rate in packets.
+	 */
+	if (argc > 2)
+		rate = simple_strtoul(argv[2], NULL, 10);
+
+	/* enable receive path */
+	FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
+
+	/* set device address to dummy 1*/
+	FPGA_SET_REG(fpga, ep.device_address, 1);
+
+	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+	while (1) {
+		u16 top_int;
+		u16 rx_tx_status;
+
+		FPGA_GET_REG(fpga, top_interrupt, &top_int);
+		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+		io_check_status(fpga, rx_tx_status, true);
+		if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
+		    (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
+			io_reflect(fpga);
+
+		if (rate) {
+			if (!(tx_ctr % rate) && (tx_ctr != last_seen))
+				printf("refl %llu, err %llu\n", tx_ctr,
+				       err_ctr);
+			last_seen = tx_ctr;
+		}
+
+		if (ctrlc())
+			break;
+	}
+
+	return 0;
+}
+
+/*
+ * FPGA io-endpoint looptest
+ *
+ * Syntax:
+ *	ioloop {fpga} {size} {rate}
+ */
+#define DISP_LINE_LEN	16
+int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int fpga;
+	unsigned int size;
+	unsigned int rate = 0;
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	/*
+	 * FPGA is specified since argc > 2
+	 */
+	fpga = simple_strtoul(argv[1], NULL, 10);
+
+	/*
+	 * packet size is specified since argc > 2
+	 */
+	size = simple_strtoul(argv[2], NULL, 10);
+
+	/*
+	 * If another parameter, it is the test rate in packets per second.
+	 */
+	if (argc > 3)
+		rate = simple_strtoul(argv[3], NULL, 10);
+
+	/* enable receive path */
+	FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
+
+	/* set device address to dummy 1*/
+	FPGA_SET_REG(fpga, ep.device_address, 1);
+
+	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+	while (1) {
+		u16 top_int;
+		u16 rx_tx_status;
+
+		FPGA_GET_REG(fpga, top_interrupt, &top_int);
+		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+		io_check_status(fpga, rx_tx_status, false);
+		if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
+			io_send(fpga, size);
+		if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
+			io_receive(fpga);
+
+		if (rate) {
+			if (ctrlc())
+				break;
+			udelay(1000000 / rate);
+			if (!(tx_ctr % rate))
+				printf("d %lld, tx %llu, rx %llu, err %llu\n",
+				       tx_ctr - rx_ctr, tx_ctr, rx_ctr,
+				       err_ctr);
+		}
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	ioloop,	4,	0,	do_ioloop,
+	"fpga io-endpoint looptest",
+	"fpga packetsize [packets/sec]"
+);
+
+U_BOOT_CMD(
+	ioreflect, 3,	0,	do_ioreflect,
+	"fpga io-endpoint reflector",
+	"fpga reportrate"
+);

u-boot/board/gdsys/common/dp501.c

@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+
+#define DP501_I2C_ADDR 0x08
+
+#ifdef CONFIG_SYS_DP501_I2C
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
+#endif
+
+#ifdef CONFIG_SYS_DP501_BASE
+int dp501_base[] = CONFIG_SYS_DP501_BASE;
+#endif
+
+static void dp501_setbits(u8 addr, u8 reg, u8 mask)
+{
+	u8 val;
+
+	val = i2c_reg_read(addr, reg);
+	setbits_8(&val, mask);
+	i2c_reg_write(addr, reg, val);
+}
+
+static void dp501_clrbits(u8 addr, u8 reg, u8 mask)
+{
+	u8 val;
+
+	val = i2c_reg_read(addr, reg);
+	clrbits_8(&val, mask);
+	i2c_reg_write(addr, reg, val);
+}
+
+static int dp501_detect_cable_adapter(u8 addr)
+{
+	u8 val = i2c_reg_read(addr, 0x00);
+
+	return !(val & 0x04);
+}
+
+static void dp501_link_training(u8 addr)
+{
+	u8 val;
+	u8 link_bw;
+	u8 max_lane_cnt;
+	u8 lane_cnt;
+
+	val = i2c_reg_read(addr, 0x51);
+	if (val >= 0x0a)
+		link_bw = 0x0a;
+	else
+		link_bw = 0x06;
+	if (link_bw != val)
+		printf("DP sink supports %d Mbps link rate, set to %d Mbps\n",
+		       val * 270, link_bw * 270);
+	i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */
+	val = i2c_reg_read(addr, 0x52);
+	max_lane_cnt = val & 0x1f;
+	if (max_lane_cnt >= 4)
+		lane_cnt = 4;
+	else
+		lane_cnt = max_lane_cnt;
+	if (lane_cnt != max_lane_cnt)
+		printf("DP sink supports %d lanes, set to %d lanes\n",
+		       max_lane_cnt, lane_cnt);
+	i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */
+	val = i2c_reg_read(addr, 0x53);
+	i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */
+
+	i2c_reg_write(addr, 0x5f, 0x0d); /* start training */
+}
+
+void dp501_powerup(u8 addr)
+{
+	dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
+	dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
+	i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
+	dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
+	dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
+	i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
+	dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
+	dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+	dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */
+
+#ifdef CONFIG_SYS_DP501_VCAPCTRL0
+	i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
+#else
+	i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
+#endif
+
+#ifdef CONFIG_SYS_DP501_DIFFERENTIAL
+	i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
+	i2c_reg_write(addr + 2, 0x25, 0x04);
+	i2c_reg_write(addr + 2, 0x26, 0x10);
+#else
+	i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
+#endif
+
+	i2c_reg_write(addr + 2, 0x1a, 0x04); /* SPDIF input method TTL */
+
+	i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
+	i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
+	i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
+	i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
+	i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
+	i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
+	dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
+	i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
+	i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
+	i2c_reg_write(addr, 0x87, 0x7f); /* set retry counter as 7
+					    retry interval 400us */
+
+	if (dp501_detect_cable_adapter(addr)) {
+		printf("DVI/HDMI cable adapter detected\n");
+		i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */
+		dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
+	} else {
+		printf("no DVI/HDMI cable adapter detected\n");
+		dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
+
+		dp501_link_training(addr);
+	}
+}
+
+void dp501_powerdown(u8 addr)
+{
+	dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
+}
+
+
+int dp501_probe(unsigned screen, bool power)
+{
+#ifdef CONFIG_SYS_DP501_BASE
+	uint8_t dp501_addr = dp501_base[screen];
+#else
+	uint8_t dp501_addr = DP501_I2C_ADDR;
+#endif
+
+#ifdef CONFIG_SYS_DP501_I2C
+	i2c_set_bus_num(dp501_i2c[screen]);
+#endif
+
+	if (i2c_probe(dp501_addr))
+		return -1;
+
+	dp501_powerup(dp501_addr);
+
+	return 0;
+}

u-boot/board/gdsys/common/dp501.h

@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DP501_H_
+#define _DP501_H_
+
+void dp501_powerup(u8 addr);
+void dp501_powerdown(u8 addr);
+int dp501_probe(unsigned screen, bool power);
+
+#endif

u-boot/board/gdsys/common/fanctrl.c

@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+enum {
+	FAN_CONFIG = 0x03,
+	FAN_TACHLIM_LSB = 0x48,
+	FAN_TACHLIM_MSB = 0x49,
+	FAN_PWM_FREQ = 0x4D,
+};
+
+void init_fan_controller(u8 addr)
+{
+	int val;
+
+	/* set PWM Frequency to 2.5% resolution */
+	i2c_reg_write(addr, FAN_PWM_FREQ, 20);
+
+	/* set Tachometer Limit */
+	i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10);
+	i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a);
+
+	/* enable Tach input */
+	val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
+	i2c_reg_write(addr, FAN_CONFIG, val);
+}

u-boot/board/gdsys/common/fanctrl.h

@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FANCTRL_H_
+#define _FANCTRL_H_
+
+void init_fan_controller(u8 addr);
+
+#endif

u-boot/board/gdsys/common/fpga.c

@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <gdsys_fpga.h>
+
+#include <asm/io.h>
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+	out_le16(reg, data);
+
+	return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+	*data = in_le16(reg);
+
+	return 0;
+}

u-boot/board/gdsys/common/ihs_mdio.c

@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <gdsys_fpga.h>
+#include <miiphy.h>
+
+#include "ihs_mdio.h"
+
+static int ihs_mdio_idle(struct mii_dev *bus)
+{
+	struct ihs_mdio_info *info = bus->priv;
+	u16 val;
+	unsigned int ctr = 0;
+
+	do {
+		FPGA_GET_REG(info->fpga, mdio.control, &val);
+		udelay(100);
+		if (ctr++ > 10)
+			return -1;
+	} while (!(val & (1 << 12)));
+
+	return 0;
+}
+
+static int ihs_mdio_reset(struct mii_dev *bus)
+{
+	ihs_mdio_idle(bus);
+
+	return 0;
+}
+
+static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr,
+			 int regnum)
+{
+	struct ihs_mdio_info *info = bus->priv;
+	u16 val;
+
+	ihs_mdio_idle(bus);
+
+	FPGA_SET_REG(info->fpga, mdio.control,
+		     ((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10));
+
+	/* wait for rx data available */
+	udelay(100);
+
+	FPGA_GET_REG(info->fpga, mdio.rx_data, &val);
+
+	return val;
+}
+
+static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
+			  int regnum, u16 value)
+{
+	struct ihs_mdio_info *info = bus->priv;
+
+	ihs_mdio_idle(bus);
+
+	FPGA_SET_REG(info->fpga, mdio.address_data, value);
+	FPGA_SET_REG(info->fpga, mdio.control,
+		     ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10));
+
+	return 0;
+}
+
+int ihs_mdio_init(struct ihs_mdio_info *info)
+{
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate FSL MDIO bus\n");
+		return -1;
+	}
+
+	bus->read = ihs_mdio_read;
+	bus->write = ihs_mdio_write;
+	bus->reset = ihs_mdio_reset;
+	strcpy(bus->name, info->name);
+
+	bus->priv = info;
+
+	return mdio_register(bus);
+}

u-boot/board/gdsys/common/ihs_mdio.h

@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _IHS_MDIO_H_
+#define _IHS_MDIO_H_
+
+struct ihs_mdio_info {
+	u32 fpga;
+	char *name;
+};
+
+int ihs_mdio_init(struct ihs_mdio_info *info);
+
+#endif

u-boot/board/gdsys/common/ioep-fpga.c

@@ -0,0 +1,237 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <gdsys_fpga.h>
+
+enum {
+	UNITTYPE_MAIN_SERVER = 0,
+	UNITTYPE_MAIN_USER = 1,
+	UNITTYPE_VIDEO_SERVER = 2,
+	UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+	UNITTYPEPCB_DVI = 0,
+	UNITTYPEPCB_DP_165 = 1,
+	UNITTYPEPCB_DP_300 = 2,
+	UNITTYPEPCB_HDMI = 3,
+};
+
+enum {
+	COMPRESSION_NONE = 0,
+	COMPRESSION_TYPE_1 = 1,
+	COMPRESSION_TYPE_1_2 = 3,
+	COMPRESSION_TYPE_1_2_3 = 7,
+};
+
+enum {
+	AUDIO_NONE = 0,
+	AUDIO_TX = 1,
+	AUDIO_RX = 2,
+	AUDIO_RXTX = 3,
+};
+
+enum {
+	SYSCLK_147456 = 0,
+};
+
+enum {
+	RAM_DDR2_32 = 0,
+	RAM_DDR3_32 = 1,
+	RAM_DDR3_48 = 2,
+};
+
+enum {
+	CARRIER_SPEED_1G = 0,
+	CARRIER_SPEED_2_5G = 1,
+};
+
+bool ioep_fpga_has_osd(unsigned int fpga)
+{
+	u16 fpga_features;
+	unsigned feature_osd;
+
+	FPGA_GET_REG(0, fpga_features, &fpga_features);
+	feature_osd = fpga_features & (1<<11);
+
+	return feature_osd;
+}
+
+void ioep_fpga_print_info(unsigned int fpga)
+{
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
+	unsigned unit_type;
+	unsigned unit_type_pcb_video;
+	unsigned feature_compression;
+	unsigned feature_osd;
+	unsigned feature_audio;
+	unsigned feature_sysclock;
+	unsigned feature_ramconfig;
+	unsigned feature_carrier_speed;
+	unsigned feature_carriers;
+	unsigned feature_video_channels;
+
+	FPGA_GET_REG(fpga, versions, &versions);
+	FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+	FPGA_GET_REG(fpga, fpga_features, &fpga_features);
+
+	unit_type = (versions & 0xf000) >> 12;
+	unit_type_pcb_video = (versions & 0x01c0) >> 6;
+	feature_compression = (fpga_features & 0xe000) >> 13;
+	feature_osd = fpga_features & (1<<11);
+	feature_audio = (fpga_features & 0x0600) >> 9;
+	feature_sysclock = (fpga_features & 0x0180) >> 7;
+	feature_ramconfig = (fpga_features & 0x0060) >> 5;
+	feature_carrier_speed = fpga_features & (1<<4);
+	feature_carriers = (fpga_features & 0x000c) >> 2;
+	feature_video_channels = fpga_features & 0x0003;
+
+	switch (unit_type) {
+	case UNITTYPE_MAIN_SERVER:
+	case UNITTYPE_MAIN_USER:
+		printf("Mainchannel");
+		break;
+
+	case UNITTYPE_VIDEO_SERVER:
+	case UNITTYPE_VIDEO_USER:
+		printf("Videochannel");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (unit_type) {
+	case UNITTYPE_MAIN_SERVER:
+	case UNITTYPE_VIDEO_SERVER:
+		printf(" Server");
+		if (versions & (1<<4))
+			printf(" UC");
+		break;
+
+	case UNITTYPE_MAIN_USER:
+	case UNITTYPE_VIDEO_USER:
+		printf(" User");
+		break;
+
+	default:
+		break;
+	}
+
+	if (versions & (1<<5))
+		printf(" Fiber");
+	else
+		printf(" CAT");
+
+	switch (unit_type_pcb_video) {
+	case UNITTYPEPCB_DVI:
+		printf(" DVI,");
+		break;
+
+	case UNITTYPEPCB_DP_165:
+		printf(" DP 165MPix/s,");
+		break;
+
+	case UNITTYPEPCB_DP_300:
+		printf(" DP 300MPix/s,");
+		break;
+
+	case UNITTYPEPCB_HDMI:
+		printf(" HDMI,");
+		break;
+	}
+
+	printf(" FPGA V %d.%02d\n       features:",
+	       fpga_version / 100, fpga_version % 100);
+
+
+	switch (feature_compression) {
+	case COMPRESSION_NONE:
+		printf(" no compression");
+		break;
+
+	case COMPRESSION_TYPE_1:
+		printf(" compression type1(delta)");
+		break;
+
+	case COMPRESSION_TYPE_1_2:
+		printf(" compression type1(delta), type2(inline)");
+		break;
+
+	case COMPRESSION_TYPE_1_2_3:
+		printf(" compression type1(delta), type2(inline), type3(intempo)");
+		break;
+
+	default:
+		printf(" compression %d(not supported)", feature_compression);
+		break;
+	}
+
+	printf(", %sosd", feature_osd ? "" : "no ");
+
+	switch (feature_audio) {
+	case AUDIO_NONE:
+		printf(", no audio");
+		break;
+
+	case AUDIO_TX:
+		printf(", audio tx");
+		break;
+
+	case AUDIO_RX:
+		printf(", audio rx");
+		break;
+
+	case AUDIO_RXTX:
+		printf(", audio rx+tx");
+		break;
+
+	default:
+		printf(", audio %d(not supported)", feature_audio);
+		break;
+	}
+
+	puts(",\n       ");
+
+	switch (feature_sysclock) {
+	case SYSCLK_147456:
+		printf("clock 147.456 MHz");
+		break;
+
+	default:
+		printf("clock %d(not supported)", feature_sysclock);
+		break;
+	}
+
+	switch (feature_ramconfig) {
+	case RAM_DDR2_32:
+		printf(", RAM 32 bit DDR2");
+		break;
+
+	case RAM_DDR3_32:
+		printf(", RAM 32 bit DDR3");
+		break;
+
+	case RAM_DDR3_48:
+		printf(", RAM 48 bit DDR3");
+		break;
+
+	default:
+		printf(", RAM %d(not supported)", feature_ramconfig);
+		break;
+	}
+
+	printf(", %d carrier(s) %s", feature_carriers,
+	       feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
+
+	printf(", %d video channel(s)\n", feature_video_channels);
+}

u-boot/board/gdsys/common/ioep-fpga.h

@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _IOEP_FPGA_H_
+#define _IOEP_FPGA_H_
+
+void ioep_fpga_print_info(unsigned int fpga);
+bool ioep_fpga_has_osd(unsigned int fpga);
+
+#endif

u-boot/board/gdsys/common/mclink.c

@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+
+#include <gdsys_fpga.h>
+
+enum {
+	MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7,
+	MCINT_TX_ERROR_EV = 1 << 9,
+	MCINT_TX_BUFFER_FREE = 1 << 10,
+	MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11,
+	MCINT_RX_ERROR_EV = 1 << 13,
+	MCINT_RX_CONTENT_AVAILABLE = 1 << 14,
+	MCINT_RX_PACKET_RECEIVED_EV = 1 << 15,
+};
+
+int mclink_probe(void)
+{
+	unsigned int k;
+	int slaves = 0;
+
+	for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) {
+		int timeout = 0;
+		unsigned int ctr = 0;
+		u16 mc_status;
+
+		FPGA_GET_REG(k, mc_status, &mc_status);
+
+		if (!(mc_status & (1 << 15)))
+			break;
+
+		FPGA_SET_REG(k, mc_control, 0x8000);
+
+		FPGA_GET_REG(k, mc_status, &mc_status);
+		while (!(mc_status & (1 << 14))) {
+			udelay(100);
+			if (ctr++ > 500) {
+				timeout = 1;
+				break;
+			}
+			FPGA_GET_REG(k, mc_status, &mc_status);
+		}
+		if (timeout)
+			break;
+
+		printf("waited %d us for mclink %d to come up\n", ctr * 100, k);
+
+		slaves++;
+	}
+
+	return slaves;
+}
+
+int mclink_send(u8 slave, u16 addr, u16 data)
+{
+	unsigned int ctr = 0;
+	u16 int_status;
+	u16 rx_cmd_status;
+	u16 rx_cmd;
+
+	/* reset interrupt status */
+	FPGA_GET_REG(0, mc_int, &int_status);
+	FPGA_SET_REG(0, mc_int, int_status);
+
+	/* send */
+	FPGA_SET_REG(0, mc_tx_address, addr);
+	FPGA_SET_REG(0, mc_tx_data, data);
+	FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14);
+	FPGA_SET_REG(0, mc_control, 0x8001);
+
+	/* wait for reply */
+	FPGA_GET_REG(0, mc_int, &int_status);
+	while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) {
+		udelay(100);
+		if (ctr++ > 3)
+			return -ETIMEDOUT;
+		FPGA_GET_REG(0, mc_int, &int_status);
+	}
+
+	FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
+	rx_cmd = (rx_cmd_status >> 12) & 0x03;
+	if (rx_cmd != 0)
+		printf("mclink_send: received cmd %d, expected %d\n", rx_cmd,
+		       0);
+
+	return 0;
+}
+
+int mclink_receive(u8 slave, u16 addr, u16 *data)
+{
+	u16 rx_cmd_status;
+	u16 rx_cmd;
+	u16 int_status;
+	unsigned int ctr = 0;
+
+	/* send read request */
+	FPGA_SET_REG(0, mc_tx_address, addr);
+	FPGA_SET_REG(0, mc_tx_cmd,
+		     ((slave & 0x03) << 14) | (1 << 12) | (1 << 0));
+	FPGA_SET_REG(0, mc_control, 0x8001);
+
+
+	/* wait for reply */
+	FPGA_GET_REG(0, mc_int, &int_status);
+	while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) {
+		udelay(100);
+		if (ctr++ > 3)
+			return -ETIMEDOUT;
+		FPGA_GET_REG(0, mc_int, &int_status);
+	}
+
+	/* check reply */
+	FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
+	if ((rx_cmd_status >> 14) != slave) {
+		printf("mclink_receive: reply from slave %d, expected %d\n",
+		       rx_cmd_status >> 14, slave);
+		return -EINVAL;
+	}
+
+	rx_cmd = (rx_cmd_status >> 12) & 0x03;
+	if (rx_cmd != 1) {
+		printf("mclink_send: received cmd %d, expected %d\n",
+		       rx_cmd, 1);
+		return -EIO;
+	}
+
+	FPGA_GET_REG(0, mc_rx_data, data);
+
+	return 0;
+}

u-boot/board/gdsys/common/mclink.h

@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MCLINK_H_
+#define _MCLINK_H_
+
+int mclink_probe(void);
+int mclink_send(u8 slave, u16 addr, u16 data);
+int mclink_receive(u8 slave, u16 addr, u16 *data);
+
+#endif

u-boot/board/gdsys/common/miiphybb.c

@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include <asm/io.h>
+
+struct io_bb_pinset {
+	int mdio;
+	int mdc;
+};
+
+static int io_bb_mii_init(struct bb_miiphy_bus *bus)
+{
+	return 0;
+}
+
+static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+	struct io_bb_pinset *pins = bus->priv;
+
+	out_be32((void *)GPIO0_TCR,
+		in_be32((void *)GPIO0_TCR) | pins->mdio);
+
+	return 0;
+}
+
+static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+	struct io_bb_pinset *pins = bus->priv;
+
+	out_be32((void *)GPIO0_TCR,
+		in_be32((void *)GPIO0_TCR) & ~pins->mdio);
+
+	return 0;
+}
+
+static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+	struct io_bb_pinset *pins = bus->priv;
+
+	if (v)
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) | pins->mdio);
+	else
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) & ~pins->mdio);
+
+	return 0;
+}
+
+static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+	struct io_bb_pinset *pins = bus->priv;
+
+	*v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
+
+	return 0;
+}
+
+static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+	struct io_bb_pinset *pins = bus->priv;
+
+	if (v)
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) | pins->mdc);
+	else
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) & ~pins->mdc);
+
+	return 0;
+}
+
+static int io_bb_delay(struct bb_miiphy_bus *bus)
+{
+	udelay(1);
+
+	return 0;
+}
+
+struct io_bb_pinset io_bb_pinsets[] = {
+	{
+		.mdio = CONFIG_SYS_MDIO_PIN,
+		.mdc = CONFIG_SYS_MDC_PIN,
+	},
+#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
+	{
+		.mdio = CONFIG_SYS_MDIO1_PIN,
+		.mdc = CONFIG_SYS_MDC1_PIN,
+	},
+#endif
+};
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+	{
+		.name = CONFIG_SYS_GBIT_MII_BUSNAME,
+		.init = io_bb_mii_init,
+		.mdio_active = io_bb_mdio_active,
+		.mdio_tristate = io_bb_mdio_tristate,
+		.set_mdio = io_bb_set_mdio,
+		.get_mdio = io_bb_get_mdio,
+		.set_mdc = io_bb_set_mdc,
+		.delay = io_bb_delay,
+		.priv = &io_bb_pinsets[0],
+	},
+#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
+	{
+		.name = CONFIG_SYS_GBIT_MII1_BUSNAME,
+		.init = io_bb_mii_init,
+		.mdio_active = io_bb_mdio_active,
+		.mdio_tristate = io_bb_mdio_tristate,
+		.set_mdio = io_bb_set_mdio,
+		.get_mdio = io_bb_get_mdio,
+		.set_mdc = io_bb_set_mdc,
+		.delay = io_bb_delay,
+		.priv = &io_bb_pinsets[1],
+	},
+#endif
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+			  sizeof(bb_miiphy_buses[0]);

u-boot/board/gdsys/common/osd.c

@@ -0,0 +1,500 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <malloc.h>
+
+#include "ch7301.h"
+#include "dp501.h"
+#include <gdsys_fpga.h>
+
+#define ICS8N3QV01_I2C_ADDR 0x6E
+#define ICS8N3QV01_FREF 114285000
+#define ICS8N3QV01_FREF_LL 114285000LL
+#define ICS8N3QV01_F_DEFAULT_0 156250000LL
+#define ICS8N3QV01_F_DEFAULT_1 125000000LL
+#define ICS8N3QV01_F_DEFAULT_2 100000000LL
+#define ICS8N3QV01_F_DEFAULT_3  25175000LL
+
+#define SIL1178_MASTER_I2C_ADDRESS 0x38
+#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+
+#define PIXCLK_640_480_60 25180000
+#define MAX_X_CHARS 53
+#define MAX_Y_CHARS 26
+
+#ifdef CONFIG_SYS_OSD_DH
+#define MAX_OSD_SCREEN 8
+#define OSD_DH_BASE 4
+#else
+#define MAX_OSD_SCREEN 4
+#endif
+
+#ifdef CONFIG_SYS_OSD_DH
+#define OSD_SET_REG(screen, fld, val) \
+	do { \
+		if (screen >= OSD_DH_BASE) \
+			FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
+		else \
+			FPGA_SET_REG(screen, osd0.fld, val); \
+	} while (0)
+#else
+#define OSD_SET_REG(screen, fld, val) \
+		FPGA_SET_REG(screen, osd0.fld, val)
+#endif
+
+#ifdef CONFIG_SYS_OSD_DH
+#define OSD_GET_REG(screen, fld, val) \
+	do {					\
+		if (screen >= OSD_DH_BASE) \
+			FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
+		else \
+			FPGA_GET_REG(screen, osd0.fld, val); \
+	} while (0)
+#else
+#define OSD_GET_REG(screen, fld, val) \
+		FPGA_GET_REG(screen, osd0.fld, val)
+#endif
+
+unsigned int base_width;
+unsigned int base_height;
+size_t bufsize;
+u16 *buf;
+
+unsigned int osd_screen_mask = 0;
+
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
+#endif
+
+#ifdef CONFIG_SYS_SIL1178_I2C
+int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
+static void mpc92469ac_calc_parameters(unsigned int fout,
+	unsigned int *post_div, unsigned int *feedback_div)
+{
+	unsigned int n = *post_div;
+	unsigned int m = *feedback_div;
+	unsigned int a;
+	unsigned int b = 14745600 / 16;
+
+	if (fout < 50169600)
+		n = 8;
+	else if (fout < 100339199)
+		n = 4;
+	else if (fout < 200678399)
+		n = 2;
+	else
+		n = 1;
+
+	a = fout * n + (b / 2); /* add b/2 for proper rounding */
+
+	m = a / b;
+
+	*post_div = n;
+	*feedback_div = m;
+}
+
+static void mpc92469ac_set(unsigned screen, unsigned int fout)
+{
+	unsigned int n;
+	unsigned int m;
+	unsigned int bitval = 0;
+	mpc92469ac_calc_parameters(fout, &n, &m);
+
+	switch (n) {
+	case 1:
+		bitval = 0x00;
+		break;
+	case 2:
+		bitval = 0x01;
+		break;
+	case 4:
+		bitval = 0x02;
+		break;
+	case 8:
+		bitval = 0x03;
+		break;
+	}
+
+	FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
+}
+#endif
+
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+
+static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
+{
+	unsigned long long n;
+	unsigned long long mint;
+	unsigned long long mfrac;
+	u8 reg_a, reg_b, reg_c, reg_d, reg_f;
+	unsigned long long fout_calc;
+
+	if (index > 3)
+		return 0;
+
+	reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
+	reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
+	reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
+	reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
+	reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
+
+	mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
+	mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
+		| (reg_d >> 7);
+	n = reg_d & 0x7f;
+
+	fout_calc = (mint * ICS8N3QV01_FREF_LL
+		     + mfrac * ICS8N3QV01_FREF_LL / 262144LL
+		     + ICS8N3QV01_FREF_LL / 524288LL
+		     + n / 2)
+		    / n
+		    * 1000000
+		    / (1000000 - 100);
+
+	return fout_calc;
+}
+
+
+static void ics8n3qv01_calc_parameters(unsigned int fout,
+	unsigned int *_mint, unsigned int *_mfrac,
+	unsigned int *_n)
+{
+	unsigned int n;
+	unsigned int foutiic;
+	unsigned int fvcoiic;
+	unsigned int mint;
+	unsigned long long mfrac;
+
+	n = (2215000000U + fout / 2) / fout;
+	if ((n & 1) && (n > 5))
+		n -= 1;
+
+	foutiic = fout - (fout / 10000);
+	fvcoiic = foutiic * n;
+
+	mint = fvcoiic / 114285000;
+	if ((mint < 17) || (mint > 63))
+		printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
+
+	mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
+		/ 114285000LL;
+
+	*_mint = mint;
+	*_mfrac = mfrac;
+	*_n = n;
+}
+
+static void ics8n3qv01_set(unsigned int fout)
+{
+	unsigned int n;
+	unsigned int mint;
+	unsigned int mfrac;
+	unsigned int fout_calc;
+	unsigned long long fout_prog;
+	long long off_ppm;
+	u8 reg0, reg4, reg8, reg12, reg18, reg20;
+
+	fout_calc = ics8n3qv01_get_fout_calc(1);
+	off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
+		  / ICS8N3QV01_F_DEFAULT_1;
+	printf("       PLL is off by %lld ppm\n", off_ppm);
+	fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
+		    / ICS8N3QV01_F_DEFAULT_1;
+	ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
+
+	reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+	reg0 |= (mint & 0x1f) << 1;
+	reg0 |= (mfrac >> 17) & 0x01;
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
+
+	reg4 = mfrac >> 9;
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
+
+	reg8 = mfrac >> 1;
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
+
+	reg12 = mfrac << 7;
+	reg12 |= n & 0x7f;
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
+
+	reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+	reg18 |= 0x20;
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
+
+	reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+	reg20 |= mint & (1 << 5);
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
+}
+#endif
+
+static int osd_write_videomem(unsigned screen, unsigned offset,
+	u16 *data, size_t charcount)
+{
+	unsigned int k;
+
+	for (k = 0; k < charcount; ++k) {
+		if (offset + k >= bufsize)
+			return -1;
+#ifdef CONFIG_SYS_OSD_DH
+		if (screen >= OSD_DH_BASE)
+			FPGA_SET_REG(screen - OSD_DH_BASE,
+				     videomem1[offset + k], data[k]);
+		else
+			FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
+#else
+		FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
+#endif
+	}
+
+	return charcount;
+}
+
+static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned screen;
+
+	if (argc < 5) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned charcount;
+		unsigned len;
+		u8 color;
+		unsigned int k;
+		char *text;
+		int res;
+
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		color = simple_strtoul(argv[3], NULL, 16);
+		text = argv[4];
+		charcount = strlen(text);
+		len = (charcount > bufsize) ? bufsize : charcount;
+
+		for (k = 0; k < len; ++k)
+			buf[k] = (text[k] << 8) | color;
+
+		res = osd_write_videomem(screen, y * base_width + x, buf, len);
+		if (res < 0)
+			return res;
+
+		OSD_SET_REG(screen, control, 0x0049);
+	}
+
+	return 0;
+}
+
+int osd_probe(unsigned screen)
+{
+	u16 version;
+	u16 features;
+	int old_bus = i2c_get_bus_num();
+	bool pixclock_present = false;
+	bool output_driver_present = false;
+
+	OSD_GET_REG(0, version, &version);
+	OSD_GET_REG(0, features, &features);
+
+	base_width = ((features & 0x3f00) >> 8) + 1;
+	base_height = (features & 0x001f) + 1;
+	bufsize = base_width * base_height;
+	buf = malloc(sizeof(u16) * bufsize);
+	if (!buf)
+		return -1;
+
+#ifdef CONFIG_SYS_OSD_DH
+	printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+	       (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
+	       (screen > 3) ? 1 : 0, version/100, version%100, base_width,
+	       base_height);
+#else
+	printf("OSD%d:  Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+	       screen, version/100, version%100, base_width, base_height);
+#endif
+	/* setup pixclock */
+
+#ifdef CONFIG_SYS_MPC92469AC
+	pixclock_present = true;
+	mpc92469ac_set(screen, PIXCLK_640_480_60);
+#endif
+
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+	i2c_set_bus_num(ics8n3qv01_i2c[screen]);
+	if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
+		ics8n3qv01_set(PIXCLK_640_480_60);
+		pixclock_present = true;
+	}
+#endif
+
+	if (!pixclock_present)
+		printf("       no pixelclock found\n");
+
+	/* setup output driver */
+
+#ifdef CONFIG_SYS_CH7301_I2C
+	if (!ch7301_probe(screen, true))
+		output_driver_present = true;
+#endif
+
+#ifdef CONFIG_SYS_SIL1178_I2C
+	i2c_set_bus_num(sil1178_i2c[screen]);
+	if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
+		if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) {
+			/*
+			 * magic initialization sequence,
+			 * adapted from datasheet
+			 */
+			i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+			output_driver_present = true;
+		}
+	}
+#endif
+
+#ifdef CONFIG_SYS_DP501_I2C
+	if (!dp501_probe(screen, true))
+		output_driver_present = true;
+#endif
+
+	if (!output_driver_present)
+		printf("       no output driver found\n");
+
+	OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1));
+	OSD_SET_REG(screen, x_pos, 0x007f);
+	OSD_SET_REG(screen, y_pos, 0x005f);
+
+	if (pixclock_present && output_driver_present)
+		osd_screen_mask |= 1 << screen;
+
+	i2c_set_bus_num(old_bus);
+
+	return 0;
+}
+
+int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned screen;
+
+	if ((argc < 4) || (strlen(argv[3]) % 4)) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned k;
+		u16 buffer[base_width];
+		char *rp;
+		u16 *wp = buffer;
+		unsigned count = (argc > 4) ?
+			simple_strtoul(argv[4], NULL, 16) : 1;
+
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		rp = argv[3];
+
+
+		while (*rp) {
+			char substr[5];
+
+			memcpy(substr, rp, 4);
+			substr[4] = 0;
+			*wp = simple_strtoul(substr, NULL, 16);
+
+			rp += 4;
+			wp++;
+			if (wp - buffer > base_width)
+				break;
+		}
+
+		for (k = 0; k < count; ++k) {
+			unsigned offset =
+				y * base_width + x + k * (wp - buffer);
+			osd_write_videomem(screen, offset, buffer,
+				wp - buffer);
+		}
+
+		OSD_SET_REG(screen, control, 0x0049);
+	}
+
+	return 0;
+}
+
+int osd_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned screen;
+	unsigned x;
+	unsigned y;
+
+	if (argc < 3) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	x = simple_strtoul(argv[1], NULL, 16);
+	y = simple_strtoul(argv[2], NULL, 16);
+
+	if (!x || (x > 64) || (x > MAX_X_CHARS) ||
+	    !y || (y > 32) || (y > MAX_Y_CHARS)) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
+
+		OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
+		OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
+		OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	osdw, 5, 0, osd_write,
+	"write 16-bit hex encoded buffer to osd memory",
+	"pos_x pos_y buffer count\n"
+);
+
+U_BOOT_CMD(
+	osdp, 5, 0, osd_print,
+	"write ASCII buffer to osd memory",
+	"pos_x pos_y color text\n"
+);
+
+U_BOOT_CMD(
+	osdsize, 3, 0, osd_size,
+	"set OSD XY size in characters",
+	"size_x(max. " __stringify(MAX_X_CHARS)
+	") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
+);

u-boot/board/gdsys/common/osd.h

@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _OSD_H_
+#define _OSD_H_
+
+int ch7301_probe(unsigned screen, bool power);
+int osd_probe(unsigned screen);
+
+#endif

u-boot/board/gdsys/common/phy.c

@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <miiphy.h>
+
+enum {
+	MIICMD_SET,
+	MIICMD_MODIFY,
+	MIICMD_VERIFY_VALUE,
+	MIICMD_WAIT_FOR_VALUE,
+};
+
+struct mii_setupcmd {
+	u8 token;
+	u8 reg;
+	u16 data;
+	u16 mask;
+	u32 timeout;
+};
+
+/*
+ * verify we are talking to a 88e1518
+ */
+struct mii_setupcmd verify_88e1518[] = {
+	{ MIICMD_SET, 22, 0x0000 },
+	{ MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff },
+	{ MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
+};
+
+/*
+ * workaround for erratum mentioned in 88E1518 release notes
+ */
+struct mii_setupcmd fixup_88e1518[] = {
+	{ MIICMD_SET, 22, 0x00ff },
+	{ MIICMD_SET, 17, 0x214b },
+	{ MIICMD_SET, 16, 0x2144 },
+	{ MIICMD_SET, 17, 0x0c28 },
+	{ MIICMD_SET, 16, 0x2146 },
+	{ MIICMD_SET, 17, 0xb233 },
+	{ MIICMD_SET, 16, 0x214d },
+	{ MIICMD_SET, 17, 0xcc0c },
+	{ MIICMD_SET, 16, 0x2159 },
+	{ MIICMD_SET, 22, 0x00fb },
+	{ MIICMD_SET,  7, 0xc00d },
+	{ MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * default initialization:
+ * - set RGMII receive timing to "receive clock transition when data stable"
+ * - set RGMII transmit timing to "transmit clock internally delayed"
+ * - set RGMII output impedance target to 78,8 Ohm
+ * - run output impedance calibration
+ * - set autonegotiation advertise to 1000FD only
+ */
+struct mii_setupcmd default_88e1518[] = {
+	{ MIICMD_SET, 22, 0x0002 },
+	{ MIICMD_MODIFY, 21, 0x0030, 0x0030 },
+	{ MIICMD_MODIFY, 25, 0x0000, 0x0003 },
+	{ MIICMD_MODIFY, 24, 0x8000, 0x8000 },
+	{ MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 },
+	{ MIICMD_SET, 22, 0x0000 },
+	{ MIICMD_MODIFY, 4, 0x0000, 0x01e0 },
+	{ MIICMD_MODIFY, 9, 0x0200, 0x0300 },
+};
+
+/*
+ * turn off CLK125 for PHY daughterboard
+ */
+struct mii_setupcmd ch1fix_88e1518[] = {
+	{ MIICMD_SET, 22, 0x0002 },
+	{ MIICMD_MODIFY, 16, 0x0006, 0x0006 },
+	{ MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * perform copper software reset
+ */
+struct mii_setupcmd swreset_88e1518[] = {
+	{ MIICMD_SET, 22, 0x0000 },
+	{ MIICMD_MODIFY, 0, 0x8000, 0x8000 },
+	{ MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 },
+};
+
+/*
+ * special one for 88E1514:
+ * Force SGMII to Copper mode
+ */
+struct mii_setupcmd mii_to_copper_88e1514[] = {
+	{ MIICMD_SET, 22, 0x0012 },
+	{ MIICMD_MODIFY, 20, 0x0001, 0x0007 },
+	{ MIICMD_MODIFY, 20, 0x8000, 0x8000 },
+	{ MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * turn off SGMII auto-negotiation
+ */
+struct mii_setupcmd sgmii_autoneg_off_88e1518[] = {
+	{ MIICMD_SET, 22, 0x0001 },
+	{ MIICMD_MODIFY, 0, 0x0000, 0x1000 },
+	{ MIICMD_MODIFY, 0, 0x8000, 0x8000 },
+	{ MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * invert LED2 polarity
+ */
+struct mii_setupcmd invert_led2_88e1514[] = {
+	{ MIICMD_SET, 22, 0x0003 },
+	{ MIICMD_MODIFY, 17, 0x0030, 0x0010 },
+	{ MIICMD_SET, 22, 0x0000 },
+};
+
+static int process_setupcmd(const char *bus, unsigned char addr,
+			    struct mii_setupcmd *setupcmd)
+{
+	int res;
+	u8 reg = setupcmd->reg;
+	u16 data = setupcmd->data;
+	u16 mask = setupcmd->mask;
+	u32 timeout = setupcmd->timeout;
+	u16 orig_data;
+	unsigned long start;
+
+	debug("mii %s:%u reg %2u ", bus, addr, reg);
+
+	switch (setupcmd->token) {
+	case MIICMD_MODIFY:
+		res = miiphy_read(bus, addr, reg, &orig_data);
+		if (res)
+			break;
+		debug("is %04x. (value %04x mask %04x) ", orig_data, data,
+		      mask);
+		data = (orig_data & ~mask) | (data & mask);
+		/* fallthrough */
+	case MIICMD_SET:
+		debug("=> %04x\n", data);
+		res = miiphy_write(bus, addr, reg, data);
+		break;
+	case MIICMD_VERIFY_VALUE:
+		res = miiphy_read(bus, addr, reg, &orig_data);
+		if (res)
+			break;
+		if ((orig_data & mask) != (data & mask))
+			res = -1;
+		debug("(value %04x mask %04x) == %04x? %s\n", data, mask,
+		      orig_data, res ? "FAIL" : "PASS");
+		break;
+	case MIICMD_WAIT_FOR_VALUE:
+		res = -1;
+		start = get_timer(0);
+		while ((res != 0) && (get_timer(start) < timeout)) {
+			res = miiphy_read(bus, addr, reg, &orig_data);
+			if (res)
+				continue;
+			if ((orig_data & mask) != (data & mask))
+				res = -1;
+		}
+		debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data,
+		      mask, orig_data, res ? "FAIL" : "PASS",
+		      get_timer(start));
+		break;
+	default:
+		res = -1;
+		break;
+	}
+
+	return res;
+}
+
+static int process_setup(const char *bus, unsigned char addr,
+			    struct mii_setupcmd *setupcmd, unsigned int count)
+{
+	int res = 0;
+	unsigned int k;
+
+	for (k = 0; k < count; ++k) {
+		res = process_setupcmd(bus, addr, &setupcmd[k]);
+		if (res) {
+			printf("mii cmd %u on bus %s addr %u failed, aborting setup\n",
+			       setupcmd[k].token, bus, addr);
+			break;
+		}
+	}
+
+	return res;
+}
+
+int setup_88e1518(const char *bus, unsigned char addr)
+{
+	int res;
+
+	res = process_setup(bus, addr,
+			    verify_88e1518, ARRAY_SIZE(verify_88e1518));
+	if (res)
+		return res;
+
+	res = process_setup(bus, addr,
+			    fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
+	if (res)
+		return res;
+
+	res = process_setup(bus, addr,
+			    default_88e1518, ARRAY_SIZE(default_88e1518));
+	if (res)
+		return res;
+
+	if (addr) {
+		res = process_setup(bus, addr,
+				    ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
+		if (res)
+			return res;
+	}
+
+	res = process_setup(bus, addr,
+			    swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
+	if (res)
+		return res;
+
+	return 0;
+}
+
+int setup_88e1514(const char *bus, unsigned char addr)
+{
+	int res;
+
+	res = process_setup(bus, addr,
+			    verify_88e1518, ARRAY_SIZE(verify_88e1518));
+	if (res)
+		return res;
+
+	res = process_setup(bus, addr,
+			    fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
+	if (res)
+		return res;
+
+	res = process_setup(bus, addr,
+			    mii_to_copper_88e1514,
+			    ARRAY_SIZE(mii_to_copper_88e1514));
+	if (res)
+		return res;
+
+	res = process_setup(bus, addr,
+			    sgmii_autoneg_off_88e1518,
+			    ARRAY_SIZE(sgmii_autoneg_off_88e1518));
+	if (res)
+		return res;
+
+	res = process_setup(bus, addr,
+			    invert_led2_88e1514,
+			    ARRAY_SIZE(invert_led2_88e1514));
+	if (res)
+		return res;
+
+	res = process_setup(bus, addr,
+			    default_88e1518, ARRAY_SIZE(default_88e1518));
+	if (res)
+		return res;
+
+	if (addr) {
+		res = process_setup(bus, addr,
+				    ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
+		if (res)
+			return res;
+	}
+
+	res = process_setup(bus, addr,
+			    swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
+	if (res)
+		return res;
+
+	return 0;
+}

u-boot/board/gdsys/common/phy.h

@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PHY_H_
+#define _PHY_H_
+
+int setup_88e1514(const char *bus, unsigned char addr);
+int setup_88e1518(const char *bus, unsigned char addr);
+
+#endif

u-boot/board/gdsys/dlvision/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_DLVISION
+
+config SYS_BOARD
+	default "dlvision"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "dlvision"
+
+endif

u-boot/board/gdsys/dlvision/MAINTAINERS

@@ -0,0 +1,6 @@
+DLVISION BOARD
+M:	Dirk Eibach <eibach@gdsys.de>
+S:	Maintained
+F:	board/gdsys/dlvision/
+F:	include/configs/dlvision.h
+F:	configs/dlvision_defconfig

u-boot/board/gdsys/dlvision/Makefile

@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= dlvision.o

u-boot/board/gdsys/dlvision/dlvision.c

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+enum {
+	HWTYPE_DLVISION_CPU = 0,
+	HWTYPE_DLVISION_CON = 1,
+};
+
+#define HWREV_100	6
+
+int board_early_init_f(void)
+{
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
+	 * -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
+
+	/*
+	 * setup io-latches
+	 */
+	out_le16((void *)CONFIG_SYS_LATCH_BASE, 0x00f0);
+	out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0x0002);
+	out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x200), 0x0000);
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char buf[64];
+	int i = getenv_f("serial#", buf, sizeof(buf));
+	u8 channel2_msr = in_8((void *)CONFIG_UART_BASE + 0x26);
+	u8 channel3_msr = in_8((void *)CONFIG_UART_BASE + 0x36);
+	u8 channel7_msr = in_8((void *)CONFIG_UART_BASE + 0x76);
+	u8 unit_type;
+	u8 local_con;
+	u8 audio;
+	u8 hardware_version;
+
+	printf("Board: ");
+
+	unit_type = (channel2_msr & 0x80) ? 0x01 : 0x00;
+	local_con = (channel2_msr & 0x20) ? 0x01 : 0x00;
+	audio = (channel3_msr & 0x20) ? 0x01 : 0x00;
+	hardware_version =
+		  ((channel7_msr & 0x20) ? 0x01 : 0x00)
+		| ((channel7_msr & 0x80) ? 0x02 : 0x00)
+		| ((channel7_msr & 0x40) ? 0x04 : 0x00);
+
+	switch (unit_type) {
+	case HWTYPE_DLVISION_CON:
+		printf("DL-Vision-CON");
+		break;
+
+	case HWTYPE_DLVISION_CPU:
+		printf("DL-Vision-CPU");
+		break;
+
+	default:
+		printf("UnitType %d, unsupported", unit_type);
+		break;
+	}
+
+	if (i > 0) {
+		puts(", serial# ");
+		puts(buf);
+	}
+	puts("\n       ");
+
+	switch (hardware_version) {
+	case HWREV_100:
+		printf("HW-Ver 1.00");
+		break;
+
+	default:
+		printf("HW-Ver %d, unsupported",
+		       hardware_version);
+		break;
+	}
+
+	if (local_con)
+		printf(", local console");
+
+	if (audio)
+		printf(", audio support");
+
+	puts("\n");
+
+	return 0;
+}

u-boot/board/gdsys/gdppc440etx/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_GDPPC440ETX
+
+config SYS_BOARD
+	default "gdppc440etx"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "gdppc440etx"
+
+endif

u-boot/board/gdsys/gdppc440etx/MAINTAINERS

@@ -0,0 +1,6 @@
+GDPPC440ETX BOARD
+M:	Dirk Eibach <eibach@gdsys.de>
+S:	Maintained
+F:	board/gdsys/gdppc440etx/
+F:	include/configs/gdppc440etx.h
+F:	configs/gdppc440etx_defconfig

u-boot/board/gdsys/gdppc440etx/Makefile

@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= gdppc440etx.o
+extra-y	+= init.o

u-boot/board/gdsys/gdppc440etx/config.mk

@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+#
+# G&D 440EP/GR ETX-Module
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif

u-boot/board/gdsys/gdppc440etx/gdppc440etx.c

@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/yosemite/yosemite.c
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/4xx_pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+int board_early_init_f(void)
+{
+	register uint reg;
+
+	/*
+	 * Setup the external bus controller/chip selects
+	 */
+	mfebc(EBC0_CFG, reg);
+	mtebc(EBC0_CFG, reg | 0x04000000);		/* Set ATC */
+
+	/*
+	 * Setup the GPIO pins
+	 */
+
+	/* setup Address lines for flash size 64Meg. */
+	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
+
+	/* setup emac */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+	/* UART0 and UART1*/
+	out32(GPIO1_TCR, in32(GPIO1_TCR)     | 0x16000000);
+	out32(GPIO1_OSRL, in32(GPIO1_OSRL)   | 0x02180000);
+	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
+	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
+
+	/* disable boot-eeprom WP */
+	out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
+
+	/* external interrupts IRQ0...3 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
+	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
+	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * Setup other serial configuration
+	 */
+	mfsdr(SDR0_PCI0, reg);
+	mtsdr(SDR0_PCI0, 0x80000000 | reg);	/* PCI arbiter enabled */
+	mtsdr(SDR0_PFC0, 0x00003e00);	/* Pin function */
+	mtsdr(SDR0_PFC1, 0x00048000);	/* Pin function: UART0 has 4 pins */
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	uint pbcr;
+	int size_val;
+	uint sz;
+
+	/* Re-do sizing to get full correct info */
+	mfebc(PB0CR, pbcr);
+
+	if (gd->bd->bi_flashsize > 0x08000000)
+		panic("Max. flash banksize is 128 MB!\n");
+
+	for (sz = gd->bd->bi_flashsize, size_val = 7;
+	    ((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
+		sz <<= 1;
+
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtebc(PB0CR, pbcr);
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char buf[64];
+	int i = getenv_f("serial#", buf, sizeof(buf));
+
+	printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
+
+	if (i > 0) {
+		puts(", serial# ");
+		puts(buf);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+/*
+ * Override weak pci_pre_init()
+ */
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller *hose)
+{
+	/* First call common code */
+	__pci_pre_init(hose);
+
+	/* enable 66 MHz ext. Clock */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
+	out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
+
+	return 1;
+}
+#endif	/* defined(CONFIG_PCI) */

u-boot/board/gdsys/gdppc440etx/init.S

@@ -0,0 +1,59 @@
+/*
+* (C) Copyright 2008
+* Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+*
+* based on board/amcc/yosemite/init.S
+* original Copyright not specified there
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+
+    /*
+     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use
+     * the speed up boot process. It is patched after relocation to enable SA_I
+     */
+    tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
+	0, AC_RWX | SA_G/*|SA_I*/)
+
+    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+    tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
+	0, AC_RWX | SA_G )
+
+    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
+	0, AC_RWX | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
+	0, AC_RW | SA_IG )
+
+    /* PCI */
+    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
+	0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
+	0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
+	0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
+	0, AC_RW | SA_IG )
+
+    tlbtab_end

u-boot/board/gdsys/intip/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_INTIP
+
+config SYS_BOARD
+	default "intip"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "intip"
+
+endif

u-boot/board/gdsys/intip/MAINTAINERS

@@ -0,0 +1,7 @@
+INTIP BOARD
+M:	Dirk Eibach <eibach@gdsys.de>
+S:	Maintained
+F:	board/gdsys/intip/
+F:	include/configs/intip.h
+F:	configs/devconcenter_defconfig
+F:	configs/intip_defconfig

u-boot/board/gdsys/intip/Makefile

@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2008
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= intip.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y	+= init.o

u-boot/board/gdsys/intip/chip_config.c

@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"800-nor", "NOR  CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1000-nor", "NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1066-nor", "NOR  CPU:1066 PLB: 266 OPB:  88 EBC:  88",
+		{
+			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1066-nand", "NAND CPU:1066 PLB: 266 OPB:  88 EBC:  88",
+		{
+			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);

u-boot/board/gdsys/intip/config.mk

@@ -0,0 +1,19 @@
+#
+# (C) Copyright 2008-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+#
+# G&D CompactCenter
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif

u-boot/board/gdsys/intip/init.S

@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/canyonlands/init.S
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+	 * use the speed up boot process. It is patched after relocation to
+	 * enable SA_I
+	 */
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
+		4, AC_RWX | SA_G) /* TLB 0 */
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
+		0, AC_RWX | SA_G)
+#endif
+
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
+		AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
+		AC_RW | SA_IG)
+
+	/* TLB-entry for NVRAM */
+	tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
+		AC_RW | SA_IG)
+
+	/* TLB-entry for UART */
+	tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
+		AC_RW | SA_IG)
+
+	/* TLB-entry for IO */
+	tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
+		AC_RW | SA_IG)
+
+	/* TLB-entry for OCM */
+	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
+		AC_RWX | SA_I)
+
+	/* TLB-entry for Local Configuration registers => peripherals */
+	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
+		4, AC_RWX | SA_IG)
+
+	/* AHB: Internal USB Peripherals (USB, SATA) */
+	tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
+		AC_RWX | SA_IG)
+
+	tlbtab_end

u-boot/board/gdsys/intip/intip.c

@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/canyonlands/canyonlands.c
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc440.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/4xx_pcie.h>
+#include <asm/ppc4xx-gpio.h>
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CONFIG_SYS_BCSR3_PCIE		0x10
+
+int board_early_init_f(void)
+{
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all */
+	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 * enable GPIO 49-63
+	 * UART0: 4 pins
+	 */
+	mtsdr(SDR0_PFC0, 0x00007fff);
+	mtsdr(SDR0_PFC1, 0x00040000);
+
+	/* Enable PCI host functionality in SDR0_PCI0 */
+	mtsdr(SDR0_PCI0, 0xe0000000);
+
+	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
+
+	/* Setup PLB4-AHB bridge based on the system address map */
+	mtdcr(AHB_TOP, 0x8000004B);
+	mtdcr(AHB_BOT, 0x8000004B);
+
+	/*
+	* Configure USB-STP pins as alternate and not GPIO
+	* It seems to be neccessary to configure the STP pins as GPIO
+	* input at powerup (perhaps while USB reset is asserted). So
+	* we configure those pins to their "real" function now.
+	*/
+	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
+	/* Trigger board component reset */
+	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
+	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
+	udelay(50);
+	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
+	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
+	udelay(50);
+	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
+	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
+
+	return 0;
+}
+
+int get_cpu_num(void)
+{
+	int cpu = NA_OR_UNKNOWN_CPU;
+
+	return cpu;
+}
+
+int checkboard(void)
+{
+	char buf[64];
+	int i = getenv_f("serial#", buf, sizeof(buf));
+
+#ifdef CONFIG_DEVCONCENTER
+	printf("Board: DevCon-Center");
+#else
+	printf("Board: Intip");
+#endif
+
+	if (i > 0) {
+		puts(", serial# ");
+		puts(buf);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	/*
+	 * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
+	 * (Spansion 29GL512), but the boot EBC mapping only supports a maximum
+	 * of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
+	 * To solve this problem, the FLASH has to get remapped to another
+	 * EBC address which accepts bigger regions:
+	 *
+	 * 0xfn00.0000 -> 4.cn00.0000
+	 */
+
+	u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?
+		EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
+
+	/* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
+	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L
+		| bxcr_bw
+		| EBC_BXCR_BU_RW
+		| EBC_BXCR_BW_16BIT);
+
+	/* Remove TLB entry of boot EBC mapping */
+	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+	/* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
+	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
+
+	/*
+	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
+	 * 0xfc00.0000 is possible
+	 */
+
+	/*
+	 * Clear potential errors resulting from auto-calibration.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u32 sdr0_srst1 = 0;
+	u32 eth_cfg;
+
+	/*
+	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+	 * This is board specific, so let's do it here.
+	 */
+	mfsdr(SDR0_ETH_CFG, eth_cfg);
+	/* disable SGMII mode */
+	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
+		     SDR0_ETH_CFG_SGMII1_ENABLE |
+		     SDR0_ETH_CFG_SGMII0_ENABLE);
+	/* Set the for 2 RGMII mode */
+	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
+	eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+	/*
+	 * The AHB Bridge core is held in reset after power-on or reset
+	 * so enable it now
+	 */
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~SDR0_SRST1_AHB;
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	__ft_board_setup(blob, bd);
+
+	fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
+			     "disabled", sizeof("disabled"), 1);
+
+	fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
+			     "disabled", sizeof("disabled"), 1);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */

u-boot/board/gdsys/mpc8308/Kconfig

@@ -0,0 +1,25 @@
+if TARGET_HRCON
+
+config SYS_BOARD
+	default "mpc8308"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "hrcon"
+
+endif
+
+if TARGET_STRIDER
+
+config SYS_BOARD
+	default "mpc8308"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "strider"
+
+endif

u-boot/board/gdsys/mpc8308/MAINTAINERS

@@ -0,0 +1,10 @@
+MPC8308 BOARD
+M:	Dirk Eibach <eibach@gdsys.de>
+S:	Maintained
+F:	board/gdsys/mpc8308/
+F:	include/configs/hrcon.h
+F:	configs/hrcon_defconfig
+F:	configs/hrcon_dh_defconfig
+F:	include/configs/strider.h
+F:	configs/strider_cpu_defconfig
+F:	configs/strider_con_defconfig

u-boot/board/gdsys/mpc8308/Makefile

@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2014
+# Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := mpc8308.o sdram.o
+obj-$(CONFIG_HRCON) += hrcon.o
+obj-$(CONFIG_STRIDER) += strider.o

u-boot/board/gdsys/mpc8308/hrcon.c

@@ -0,0 +1,482 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <spi.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+#include "mpc8308.h"
+
+#include <gdsys_fpga.h>
+
+#include "../common/ioep-fpga.h"
+#include "../common/osd.h"
+#include "../common/mclink.h"
+#include "../common/phy.h"
+#include "../common/fanctrl.h"
+
+#include <pca953x.h>
+#include <pca9698.h>
+
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_MUX_CHANNELS 2
+
+enum {
+	MCFPGA_DONE = 1 << 0,
+	MCFPGA_INIT_N = 1 << 1,
+	MCFPGA_PROGRAM_N = 1 << 2,
+	MCFPGA_UPDATE_ENABLE_N = 1 << 3,
+	MCFPGA_RESET_N = 1 << 4,
+};
+
+enum {
+	GPIO_MDC = 1 << 14,
+	GPIO_MDIO = 1 << 15,
+};
+
+unsigned int mclink_fpgacount;
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+struct {
+	u8 bus;
+	u8 addr;
+} hrcon_fans[] = CONFIG_HRCON_FANS;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+	int res;
+
+	switch (fpga) {
+	case 0:
+		out_le16(reg, data);
+		break;
+	default:
+		res = mclink_send(fpga - 1, regoff, data);
+		if (res < 0) {
+			printf("mclink_send reg %02lx data %04x returned %d\n",
+			       regoff, data, res);
+			return res;
+		}
+		break;
+	}
+
+	return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+	int res;
+
+	switch (fpga) {
+	case 0:
+		*data = in_le16(reg);
+		break;
+	default:
+		if (fpga > mclink_fpgacount)
+			return -EINVAL;
+		res = mclink_receive(fpga - 1, regoff, data);
+		if (res < 0) {
+			printf("mclink_receive reg %02lx returned %d\n",
+			       regoff, res);
+			return res;
+		}
+	}
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	bool hw_type_cat = pca9698_get_value(0x20, 20);
+
+	puts("Board: ");
+
+	printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	int slaves;
+	unsigned int k;
+	unsigned int mux_ch;
+	unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
+	u16 fpga_features;
+	bool hw_type_cat = pca9698_get_value(0x20, 20);
+	bool ch0_rgmii2_present = false;
+
+	FPGA_GET_REG(0, fpga_features, &fpga_features);
+
+	/* Turn on Parade DP501 */
+	pca9698_direction_output(0x20, 10, 1);
+	pca9698_direction_output(0x20, 11, 1);
+
+	ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+
+	/* wait for FPGA done, then reset FPGA */
+	for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
+		unsigned int ctr = 0;
+
+		if (i2c_probe(mclink_controllers[k]))
+			continue;
+
+		while (!(pca953x_get_val(mclink_controllers[k])
+		       & MCFPGA_DONE)) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				printf("no done for mclink_controller %d\n", k);
+				break;
+			}
+		}
+
+		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
+		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
+		udelay(10);
+		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
+				MCFPGA_RESET_N);
+	}
+
+	if (hw_type_cat) {
+		miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
+				bb_miiphy_write);
+		for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
+			if ((mux_ch == 1) && !ch0_rgmii2_present)
+				continue;
+
+			setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
+		}
+	}
+
+	/* give slave-PLLs and Parade DP501 some time to be up and running */
+	udelay(500000);
+
+	mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
+	slaves = mclink_probe();
+	mclink_fpgacount = 0;
+
+	ioep_fpga_print_info(0);
+	osd_probe(0);
+#ifdef CONFIG_SYS_OSD_DH
+	osd_probe(4);
+#endif
+
+	if (slaves <= 0)
+		return 0;
+
+	mclink_fpgacount = slaves;
+
+	for (k = 1; k <= slaves; ++k) {
+		FPGA_GET_REG(k, fpga_features, &fpga_features);
+
+		ioep_fpga_print_info(k);
+		osd_probe(k);
+#ifdef CONFIG_SYS_OSD_DH
+		osd_probe(k + 4);
+#endif
+		if (hw_type_cat) {
+			miiphy_register(bb_miiphy_buses[k].name,
+					bb_miiphy_read, bb_miiphy_write);
+			setup_88e1514(bb_miiphy_buses[k].name, 0);
+		}
+	}
+
+	for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
+		i2c_set_bus_num(hrcon_fans[k].bus);
+		init_fan_controller(hrcon_fans[k].addr);
+	}
+
+	return 0;
+}
+
+/*
+ * provide access to fpga gpios and controls (for I2C bitbang)
+ * (these may look all too simple but make iocon.h much more readable)
+ */
+void fpga_gpio_set(unsigned int bus, int pin)
+{
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
+}
+
+void fpga_gpio_clear(unsigned int bus, int pin)
+{
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
+}
+
+int fpga_gpio_get(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
+
+	return val & pin;
+}
+
+void fpga_control_set(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
+}
+
+void fpga_control_clear(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
+}
+
+void mpc8308_init(void)
+{
+	pca9698_direction_output(0x20, 4, 1);
+}
+
+void mpc8308_set_fpga_reset(unsigned state)
+{
+	pca9698_set_value(0x20, 4, state ? 0 : 1);
+}
+
+void mpc8308_setup_hw(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
+	setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
+}
+
+int mpc8308_get_fpga_done(unsigned fpga)
+{
+	return pca9698_get_value(0x20, 19);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+
+	/* Enable cache snooping in eSDHC system configuration register */
+	out_be32(&sysconf->sdhccr, 0x02000000);
+
+	return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+	law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+			 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(1, pcie_reg);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	info->portwidth = FLASH_CFI_16BIT;
+	info->chipwidth = FLASH_CFI_BY16;
+	info->interface = FLASH_CFI_X16;
+	return 1;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_dr_usb(blob, bd);
+	fdt_fixup_esdhc(blob, bd);
+
+	return 0;
+}
+#endif
+
+/*
+ * FPGA MII bitbang implementation
+ */
+
+struct fpga_mii {
+	unsigned fpga;
+	int mdio;
+} fpga_mii[] = {
+	{ 0, 1},
+	{ 1, 1},
+	{ 2, 1},
+	{ 3, 1},
+};
+
+static int mii_dummy_init(struct bb_miiphy_bus *bus)
+{
+	return 0;
+}
+
+static int mii_mdio_active(struct bb_miiphy_bus *bus)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	if (fpga_mii->mdio)
+		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+	else
+		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+	return 0;
+}
+
+static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+
+	return 0;
+}
+
+static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	if (v)
+		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+	else
+		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+	fpga_mii->mdio = v;
+
+	return 0;
+}
+
+static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+	u16 gpio;
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
+
+	*v = ((gpio & GPIO_MDIO) != 0);
+
+	return 0;
+}
+
+static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	if (v)
+		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
+	else
+		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
+
+	return 0;
+}
+
+static int mii_delay(struct bb_miiphy_bus *bus)
+{
+	udelay(1);
+
+	return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+	{
+		.name = "board0",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[0],
+	},
+	{
+		.name = "board1",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[1],
+	},
+	{
+		.name = "board2",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[2],
+	},
+	{
+		.name = "board3",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[3],
+	},
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+			  sizeof(bb_miiphy_buses[0]);

u-boot/board/gdsys/mpc8308/mpc8308.c

@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
+
+#include "mpc8308.h"
+#include <gdsys_fpga.h>
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+	return gd->arch.fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+	if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+		puts("       Waiting for FPGA-DONE timed out.\n");
+	if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+		puts("       FPGA reflection test failed.\n");
+}
+
+int board_early_init_f(void)
+{
+	unsigned k;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->arch.fpga_state[k] = 0;
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	unsigned k;
+	unsigned ctr;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->arch.fpga_state[k] = 0;
+
+	/*
+	 * reset FPGA
+	 */
+	mpc8308_init();
+
+	mpc8308_set_fpga_reset(1);
+
+	mpc8308_setup_hw();
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ctr = 0;
+		while (!mpc8308_get_fpga_done(k)) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_DONE_FAILED;
+				break;
+			}
+		}
+	}
+
+	udelay(10);
+
+	mpc8308_set_fpga_reset(0);
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		/*
+		 * wait for fpga out of reset
+		 */
+		ctr = 0;
+		while (1) {
+			u16 val;
+
+			FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
+
+			FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+			if (val == REFLECTION_TESTPATTERN_INV)
+				break;
+
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_REFLECTION_FAILED;
+				break;
+			}
+		}
+	}
+
+	return 0;
+}

u-boot/board/gdsys/mpc8308/mpc8308.h

@@ -0,0 +1,10 @@
+#ifndef __MPC8308_H_
+#define __MPC8308_H_
+
+/* functions to be provided by board implementation */
+void mpc8308_init(void);
+void mpc8308_set_fpga_reset(unsigned state);
+void mpc8308_setup_hw(void);
+int mpc8308_get_fpga_done(unsigned fpga);
+
+#endif /* __MPC8308_H_ */

u-boot/board/gdsys/mpc8308/sdram.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * Authors: Nick.Spence@freescale.com
+ *          Wilson.Lo@freescale.com
+ *          scottwood@freescale.com
+ *
+ * This files is  mostly identical to the original from
+ * board\freescale\mpc8315erdb\sdram.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+		 CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	sync();
+
+	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+}
+
+phys_size_t initdram(int board_type)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}

u-boot/board/gdsys/mpc8308/strider.c

@@ -0,0 +1,537 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <spi.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+#include "mpc8308.h"
+
+#include <gdsys_fpga.h>
+
+#include "../common/adv7611.h"
+#include "../common/ch7301.h"
+#include "../common/dp501.h"
+#include "../common/ioep-fpga.h"
+#include "../common/mclink.h"
+#include "../common/osd.h"
+#include "../common/phy.h"
+#include "../common/fanctrl.h"
+
+#include <pca953x.h>
+#include <pca9698.h>
+
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_MUX_CHANNELS 2
+
+enum {
+	MCFPGA_DONE = 1 << 0,
+	MCFPGA_INIT_N = 1 << 1,
+	MCFPGA_PROGRAM_N = 1 << 2,
+	MCFPGA_UPDATE_ENABLE_N = 1 << 3,
+	MCFPGA_RESET_N = 1 << 4,
+};
+
+enum {
+	GPIO_MDC = 1 << 14,
+	GPIO_MDIO = 1 << 15,
+};
+
+unsigned int mclink_fpgacount;
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+struct {
+	u8 bus;
+	u8 addr;
+} strider_fans[] = CONFIG_STRIDER_FANS;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+	int res;
+
+	switch (fpga) {
+	case 0:
+		out_le16(reg, data);
+		break;
+	default:
+		res = mclink_send(fpga - 1, regoff, data);
+		if (res < 0) {
+			printf("mclink_send reg %02lx data %04x returned %d\n",
+			       regoff, data, res);
+			return res;
+		}
+		break;
+	}
+
+	return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+	int res;
+
+	switch (fpga) {
+	case 0:
+		*data = in_le16(reg);
+		break;
+	default:
+		if (fpga > mclink_fpgacount)
+			return -EINVAL;
+		res = mclink_receive(fpga - 1, regoff, data);
+		if (res < 0) {
+			printf("mclink_receive reg %02lx returned %d\n",
+			       regoff, res);
+			return res;
+		}
+	}
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	bool hw_type_cat = pca9698_get_value(0x20, 18);
+
+	puts("Board: ");
+
+	printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	int slaves;
+	unsigned int k;
+	unsigned int mux_ch;
+	unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
+#ifdef CONFIG_STRIDER_CPU
+	unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
+#endif
+	bool hw_type_cat = pca9698_get_value(0x20, 18);
+#ifdef CONFIG_STRIDER_CON_DP
+	bool is_dh = pca9698_get_value(0x20, 25);
+#endif
+	bool ch0_sgmii2_present = false;
+
+	/* Turn on Analog Devices ADV7611 */
+	pca9698_direction_output(0x20, 8, 0);
+
+	/* Turn on Parade DP501 */
+	pca9698_direction_output(0x20, 10, 1);
+	pca9698_direction_output(0x20, 11, 1);
+
+	ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
+
+	/* wait for FPGA done, then reset FPGA */
+	for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
+		unsigned int ctr = 0;
+		unsigned char *mclink_controllers = mclink_controllers_dvi;
+
+#ifdef CONFIG_STRIDER_CPU
+		if (i2c_probe(mclink_controllers[k])) {
+			mclink_controllers = mclink_controllers_dp;
+			if (i2c_probe(mclink_controllers[k]))
+				continue;
+		}
+#else
+		if (i2c_probe(mclink_controllers[k]))
+			continue;
+#endif
+		while (!(pca953x_get_val(mclink_controllers[k])
+		       & MCFPGA_DONE)) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				printf("no done for mclink_controller %d\n", k);
+				break;
+			}
+		}
+
+		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
+		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
+		udelay(10);
+		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
+				MCFPGA_RESET_N);
+	}
+
+	if (hw_type_cat) {
+		miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
+				bb_miiphy_write);
+		for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
+			if ((mux_ch == 1) && !ch0_sgmii2_present)
+				continue;
+
+			setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
+		}
+	}
+
+	/* give slave-PLLs and Parade DP501 some time to be up and running */
+	udelay(500000);
+
+	mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
+	slaves = mclink_probe();
+	mclink_fpgacount = 0;
+
+	ioep_fpga_print_info(0);
+
+	if (!adv7611_probe(0))
+		printf("       Advantiv ADV7611 HDMI Receiver\n");
+
+#ifdef CONFIG_STRIDER_CON
+	if (ioep_fpga_has_osd(0))
+		osd_probe(0);
+#endif
+
+#ifdef CONFIG_STRIDER_CON_DP
+	if (ioep_fpga_has_osd(0)) {
+		osd_probe(0);
+		if (is_dh)
+			osd_probe(4);
+	}
+#endif
+
+#ifdef CONFIG_STRIDER_CPU
+	ch7301_probe(0, false);
+	dp501_probe(0, false);
+#endif
+
+	if (slaves <= 0)
+		return 0;
+
+	mclink_fpgacount = slaves;
+
+#ifdef CONFIG_STRIDER_CPU
+	/* get ADV7611 out of reset, power up DP501, give some time to wakeup */
+	for (k = 1; k <= slaves; ++k)
+		FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
+
+	udelay(500000);
+#endif
+
+	for (k = 1; k <= slaves; ++k) {
+		ioep_fpga_print_info(k);
+#ifdef CONFIG_STRIDER_CON
+		if (ioep_fpga_has_osd(k))
+			osd_probe(k);
+#endif
+#ifdef CONFIG_STRIDER_CON_DP
+		if (ioep_fpga_has_osd(k)) {
+			osd_probe(k);
+			if (is_dh)
+				osd_probe(k + 4);
+		}
+#endif
+#ifdef CONFIG_STRIDER_CPU
+		if (!adv7611_probe(k))
+			printf("       Advantiv ADV7611 HDMI Receiver\n");
+		ch7301_probe(k, false);
+		dp501_probe(k, false);
+#endif
+		if (hw_type_cat) {
+			miiphy_register(bb_miiphy_buses[k].name,
+					bb_miiphy_read, bb_miiphy_write);
+			setup_88e1514(bb_miiphy_buses[k].name, 0);
+		}
+	}
+
+	for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
+		i2c_set_bus_num(strider_fans[k].bus);
+		init_fan_controller(strider_fans[k].addr);
+	}
+
+	return 0;
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ * (these may look all too simple but make iocon.h much more readable)
+ */
+void fpga_gpio_set(unsigned int bus, int pin)
+{
+	FPGA_SET_REG(bus, gpio.set, pin);
+}
+
+void fpga_gpio_clear(unsigned int bus, int pin)
+{
+	FPGA_SET_REG(bus, gpio.clear, pin);
+}
+
+int fpga_gpio_get(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus, gpio.read, &val);
+
+	return val & pin;
+}
+
+#ifdef CONFIG_STRIDER_CON_DP
+void fpga_control_set(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus, control, &val);
+	FPGA_SET_REG(bus, control, val | pin);
+}
+
+void fpga_control_clear(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus, control, &val);
+	FPGA_SET_REG(bus, control, val & ~pin);
+}
+#endif
+
+void mpc8308_init(void)
+{
+	pca9698_direction_output(0x20, 26, 1);
+}
+
+void mpc8308_set_fpga_reset(unsigned state)
+{
+	pca9698_set_value(0x20, 26, state ? 0 : 1);
+}
+
+void mpc8308_setup_hw(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
+	setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
+}
+
+int mpc8308_get_fpga_done(unsigned fpga)
+{
+	return pca9698_get_value(0x20, 20);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+
+	/* Enable cache snooping in eSDHC system configuration register */
+	out_be32(&sysconf->sdhccr, 0x02000000);
+
+	return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+	law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+			 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(1, pcie_reg);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	info->portwidth = FLASH_CFI_16BIT;
+	info->chipwidth = FLASH_CFI_BY16;
+	info->interface = FLASH_CFI_X16;
+	return 1;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_dr_usb(blob, bd);
+	fdt_fixup_esdhc(blob, bd);
+
+	return 0;
+}
+#endif
+
+/*
+ * FPGA MII bitbang implementation
+ */
+
+struct fpga_mii {
+	unsigned fpga;
+	int mdio;
+} fpga_mii[] = {
+	{ 0, 1},
+	{ 1, 1},
+	{ 2, 1},
+	{ 3, 1},
+};
+
+static int mii_dummy_init(struct bb_miiphy_bus *bus)
+{
+	return 0;
+}
+
+static int mii_mdio_active(struct bb_miiphy_bus *bus)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	if (fpga_mii->mdio)
+		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+	else
+		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+	return 0;
+}
+
+static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+
+	return 0;
+}
+
+static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	if (v)
+		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+	else
+		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+	fpga_mii->mdio = v;
+
+	return 0;
+}
+
+static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+	u16 gpio;
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
+
+	*v = ((gpio & GPIO_MDIO) != 0);
+
+	return 0;
+}
+
+static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+	struct fpga_mii *fpga_mii = bus->priv;
+
+	if (v)
+		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
+	else
+		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
+
+	return 0;
+}
+
+static int mii_delay(struct bb_miiphy_bus *bus)
+{
+	udelay(1);
+
+	return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+	{
+		.name = "board0",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[0],
+	},
+	{
+		.name = "board1",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[1],
+	},
+	{
+		.name = "board2",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[2],
+	},
+	{
+		.name = "board3",
+		.init = mii_dummy_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &fpga_mii[3],
+	},
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+			  sizeof(bb_miiphy_buses[0]);

u-boot/board/gdsys/p1022/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_CONTROLCENTERD
+
+config SYS_BOARD
+	default "p1022"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "controlcenterd"
+
+endif

u-boot/board/gdsys/p1022/MAINTAINERS

@@ -0,0 +1,9 @@
+P1022 BOARD
+M:	Dirk Eibach <eibach@gdsys.de>
+S:	Maintained
+F:	board/gdsys/p1022/
+F:	include/configs/controlcenterd.h
+F:	configs/controlcenterd_36BIT_SDCARD_defconfig
+F:	configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+F:	configs/controlcenterd_TRAILBLAZER_defconfig
+F:	configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig

u-boot/board/gdsys/p1022/Makefile

@@ -0,0 +1,12 @@
+#
+# Copyright 2010 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= law.o
+obj-y	+= ddr.o
+obj-y	+= tlb.o
+obj-y	+= sdhc_boot.o
+obj-$(CONFIG_CONTROLCENTERD) += controlcenterd.o controlcenterd-id.o
+obj-$(CONFIG_FSL_DIU_FB) += diu.o

u-boot/board/gdsys/p1022/controlcenterd-id.h

@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013
+ * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONTROLCENTER_ID_H
+#define __CONTROLCENTER_ID_H
+
+int ccdm_compute_self_hash(void);
+int startup_ccdm_id_module(void);
+
+int show_self_hash(void);
+
+#endif /* __CONTROLCENTER_ID_H */

u-boot/board/gdsys/p1022/controlcenterd.c

@@ -0,0 +1,428 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <asm/fsl_law.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <pca9698.h>
+#include <watchdog.h>
+#include "../common/dp501.h"
+#include "controlcenterd-id.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	HWVER_100 = 0,
+	HWVER_110 = 1,
+	HWVER_120 = 2,
+};
+
+struct ihs_fpga {
+	u32 reflection_low;	/* 0x0000 */
+	u32 versions;		/* 0x0004 */
+	u32 fpga_version;	/* 0x0008 */
+	u32 fpga_features;	/* 0x000c */
+	u32 reserved[4];	/* 0x0010 */
+	u32 control;		/* 0x0020 */
+};
+
+#ifndef CONFIG_TRAILBLAZER
+static struct pci_device_id hydra_supported[] = {
+	{ 0x6d5e, 0xcdc0 },
+	{}
+};
+
+static void hydra_initialize(void);
+#endif
+
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
+
+	/* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */
+	clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000);
+
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, 0x00001000);
+
+	/* Set pmuxcr to enable GPIO 3_11-3_13 */
+	setbits_be32(&gur->pmuxcr, 0x00000010);
+
+	/* Set pmuxcr to enable GPIO 2_31,3_9+10 */
+	setbits_be32(&gur->pmuxcr, 0x00000020);
+
+	/* Set pmuxcr to enable GPIO 2_28-2_30 */
+	setbits_be32(&gur->pmuxcr, 0x000000c0);
+
+	/* Set pmuxcr to enable GPIO 3_20-3_22 */
+	setbits_be32(&gur->pmuxcr2, 0x03000000);
+
+	/* Set pmuxcr to enable IRQ0-2 */
+	clrbits_be32(&gur->pmuxcr, 0x00000300);
+
+	/* Set pmuxcr to disable IRQ3-11 */
+	setbits_be32(&gur->pmuxcr, 0x000000F0);
+
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+
+	/* Set the pin muxing to enable ETSEC2. */
+	clrbits_be32(&gur->pmuxcr2, 0x001F8000);
+
+#ifdef CONFIG_TRAILBLAZER
+	/*
+	 * GPIO3_10 SPERRTRIGGER
+	 */
+	setbits_be32(&pgpio->gpdir, 0x00200000);
+	clrbits_be32(&pgpio->gpdat, 0x00200000);
+	udelay(100);
+	setbits_be32(&pgpio->gpdat, 0x00200000);
+	udelay(100);
+	clrbits_be32(&pgpio->gpdat, 0x00200000);
+#endif
+
+	/*
+	 * GPIO3_11 CPU-TO-FPGA-RESET#
+	 */
+	setbits_be32(&pgpio->gpdir, 0x00100000);
+	clrbits_be32(&pgpio->gpdat, 0x00100000);
+
+	/*
+	 * GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER#
+	 */
+	setbits_be32(&pgpio->gpdir, 0x00000400);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: ControlCenter DIGITAL\n");
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+/*
+ * A list of PCI and SATA slots
+ */
+enum slot_id {
+	SLOT_PCIE1 = 1,
+	SLOT_PCIE2,
+	SLOT_PCIE3,
+	SLOT_PCIE4,
+	SLOT_PCIE5,
+	SLOT_SATA1,
+	SLOT_SATA2
+};
+
+/*
+ * This array maps the slot identifiers to their names on the P1022DS board.
+ */
+static const char * const slot_names[] = {
+	[SLOT_PCIE1] = "Slot 1",
+	[SLOT_PCIE2] = "Slot 2",
+	[SLOT_PCIE3] = "Slot 3",
+	[SLOT_PCIE4] = "Slot 4",
+	[SLOT_PCIE5] = "Mini-PCIe",
+	[SLOT_SATA1] = "SATA 1",
+	[SLOT_SATA2] = "SATA 2",
+};
+
+/*
+ * This array maps a given SERDES configuration and SERDES device to the PCI or
+ * SATA slot that it connects to.  This mapping is hard-coded in the FPGA.
+ */
+static u8 serdes_dev_slot[][SATA2 + 1] = {
+	[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
+	[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+	[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
+		   [PCIE2] = SLOT_PCIE5 },
+	[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
+		   [PCIE2] = SLOT_PCIE3,
+		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+	[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
+		   [PCIE2] = SLOT_PCIE3 },
+	[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
+		   [PCIE2] = SLOT_PCIE3,
+		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+	[0x1c] = { [PCIE1] = SLOT_PCIE1,
+		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+	[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
+	[0x1f] = { [PCIE1] = SLOT_PCIE1 },
+};
+
+
+/*
+ * Returns the name of the slot to which the PCIe or SATA controller is
+ * connected
+ */
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	enum slot_id slot = serdes_dev_slot[srds_cfg][device];
+	const char *name = slot_names[slot];
+
+	if (name)
+		return name;
+	else
+		return "Nothing";
+}
+
+void hw_watchdog_reset(void)
+{
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
+
+	clrbits_be32(&pgpio->gpdat, 0x00000400);
+	setbits_be32(&pgpio->gpdat, 0x00000400);
+}
+
+#ifdef CONFIG_TRAILBLAZER
+int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	return run_command(getenv("bootcmd"), flag);
+}
+
+int board_early_init_r(void)
+{
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
+
+	/*
+	 * GPIO3_12 PPC_SYSTEMREADY#
+	 */
+	setbits_be32(&pgpio->gpdir, 0x00080000);
+	setbits_be32(&pgpio->gpodr, 0x00080000);
+	clrbits_be32(&pgpio->gpdat, 0x00080000);
+
+	return ccdm_compute_self_hash();
+}
+
+int last_stage_init(void)
+{
+	startup_ccdm_id_module();
+	return 0;
+}
+
+#else
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+
+	hydra_initialize();
+}
+
+int board_early_init_r(void)
+{
+	unsigned int k = 0;
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
+
+	/* wait for FPGA configuration to finish */
+	while (!pca9698_get_value(0x22, 11) && (k++ < 30))
+		udelay(100000);
+
+	if (k > 30) {
+		puts("FPGA configuration timed out.\n");
+	} else {
+		/* clear FPGA reset */
+		udelay(1000);
+		setbits_be32(&pgpio->gpdat, 0x00100000);
+	}
+
+	/* give time for PCIe link training */
+	udelay(100000);
+
+	/*
+	 * GPIO3_12 PPC_SYSTEMREADY#
+	 */
+	setbits_be32(&pgpio->gpdir, 0x00080000);
+	setbits_be32(&pgpio->gpodr, 0x00080000);
+	clrbits_be32(&pgpio->gpdat, 0x00080000);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	/* Turn on Parade DP501 */
+	pca9698_direction_output(0x22, 7, 1);
+	udelay(500000);
+
+	dp501_powerup(0x08);
+
+	startup_ccdm_id_module();
+
+	return 0;
+}
+
+/*
+ * Initialize on-board and/or PCI Ethernet devices
+ *
+ * Returns:
+ *      <0, error
+ *       0, no ethernet devices found
+ *      >0, number of ethernet devices initialized
+ */
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[2];
+	unsigned int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+	fdt_fixup_dr_usb(blob, bd);
+#endif
+
+	FT_FSL_PCI_SETUP;
+
+	return 0;
+}
+#endif
+
+static void hydra_initialize(void)
+{
+	unsigned int i;
+	pci_dev_t devno;
+
+	/* Find and probe all the matching PCI devices */
+	for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
+		u32 val;
+		struct ihs_fpga *fpga;
+		u32 versions;
+		u32 fpga_version;
+		u32 fpga_features;
+
+		unsigned hardware_version;
+		unsigned feature_uart_channels;
+		unsigned feature_sb_channels;
+
+		/* Try to enable I/O accesses and bus-mastering */
+		val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+		pci_write_config_dword(devno, PCI_COMMAND, val);
+
+		/* Make sure it worked */
+		pci_read_config_dword(devno, PCI_COMMAND, &val);
+		if (!(val & PCI_COMMAND_MEMORY)) {
+			puts("Can't enable I/O memory\n");
+			continue;
+		}
+		if (!(val & PCI_COMMAND_MASTER)) {
+			puts("Can't enable bus-mastering\n");
+			continue;
+		}
+
+		/* read FPGA details */
+		fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
+			PCI_REGION_MEM);
+
+		/* disable sideband clocks */
+		writel(1, &fpga->control);
+
+		versions = readl(&fpga->versions);
+		fpga_version = readl(&fpga->fpga_version);
+		fpga_features = readl(&fpga->fpga_features);
+
+		hardware_version = versions & 0xf;
+		feature_uart_channels = (fpga_features >> 6) & 0x1f;
+		feature_sb_channels = fpga_features & 0x1f;
+
+		printf("FPGA%d: ", i);
+
+		switch (hardware_version) {
+		case HWVER_100:
+			printf("HW-Ver 1.00\n");
+			break;
+
+		case HWVER_110:
+			printf("HW-Ver 1.10\n");
+			break;
+
+		case HWVER_120:
+			printf("HW-Ver 1.20\n");
+			break;
+
+		default:
+			printf("HW-Ver %d(not supported)\n",
+			       hardware_version);
+			break;
+		}
+
+		printf("       FPGA V %d.%02d, features:",
+		       fpga_version / 100, fpga_version % 100);
+
+		printf(" %d uart channel(s)", feature_uart_channels);
+		printf(" %d sideband channel(s)\n", feature_sb_channels);
+	}
+}
+#endif

u-boot/board/gdsys/p1022/ddr.c

@@ -0,0 +1,68 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	unsigned int i;
+
+	if (ctrl_num) {
+		printf("Wrong parameter for controller number %d", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	/* set odt_rd_cfg and odt_wr_cfg. */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = 0;
+		popts->cs_local_opts[i].odt_wr_cfg = 1;
+	}
+
+	popts->clk_adjust = 5;
+	popts->cpo_override = 0x1f;
+	popts->write_data_delay = 2;
+	popts->half_strength_driver_enable = 1;
+
+	/* Per AN4039, enable ZQ calibration. */
+	popts->zq_en = 1;
+}
+
+#ifdef CONFIG_SPD_EEPROM
+/*
+ * we only have a "fake" SPD-EEPROM here, which has 16 bit addresses
+ */
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+	int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd,
+				sizeof(generic_spd_eeprom_t));
+
+	if (ret) {
+		if (i2c_address ==
+#ifdef SPD_EEPROM_ADDRESS
+				SPD_EEPROM_ADDRESS
+#elif defined(SPD_EEPROM_ADDRESS1)
+				SPD_EEPROM_ADDRESS1
+#endif
+				) {
+			printf("DDR: failed to read SPD from address %u\n",
+			       i2c_address);
+		} else {
+			debug("DDR: failed to read SPD from address %u\n",
+			      i2c_address);
+		}
+		memset(spd, 0, sizeof(generic_spd_eeprom_t));
+	}
+}
+#endif

u-boot/board/gdsys/p1022/diu.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Authors: Timur Tabi <timur@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <video_fb.h>
+#include <fsl_diu_fb.h>
+
+#define PMUXCR_ELBCDIU_MASK	0xc0000000
+#define PMUXCR_ELBCDIU_NOR16	0x80000000
+#define PMUXCR_ELBCDIU_DIU	0x40000000
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register.  So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F		0x10000000
+#define AD_ALPHA_C_SHIFT	25
+#define AD_BLUE_C_SHIFT		23
+#define AD_GREEN_C_SHIFT	21
+#define AD_RED_C_SHIFT		19
+#define AD_PIXEL_S_SHIFT	16
+#define AD_COMP_3_SHIFT		12
+#define AD_COMP_2_SHIFT		8
+#define AD_COMP_1_SHIFT		4
+#define AD_COMP_0_SHIFT		0
+
+/*
+ * Variables used by the DIU/LBC switching code.  It's safe to makes these
+ * global, because the DIU requires DDR, so we'll only run this code after
+ * relocation.
+ */
+static u32 pmuxcr;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	unsigned long speed_ccb, temp;
+	u32 pixval;
+
+	speed_ccb = get_bus_freq(0);
+	temp = 1000000000 / pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+	debug("DIU pixval = %u\n", pixval);
+
+	/* Modify PXCLK in GUTS CLKDVDR */
+	temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
+	out_be32(&gur->clkdvdr, temp);			/* turn off clock */
+	out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 pixel_format;
+
+	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+	printf("DIU:   Switching to %ux%u\n", xres, yres);
+
+	/* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
+	clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
+	pmuxcr = in_be32(&gur->pmuxcr);
+
+	return fsl_diu_init(xres, yres, pixel_format, 0);
+}

u-boot/board/gdsys/p1022/law.c

@@ -0,0 +1,17 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_ELBC_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

u-boot/board/gdsys/p1022/sdhc_boot.c

@@ -0,0 +1,63 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <malloc.h>
+
+/*
+ * The environment variables are written to just after the u-boot image
+ * on SDCard, so we must read the MBR to get the start address and code
+ * length of the u-boot image, then calculate the address of the env.
+ */
+#define ESDHC_BOOT_IMAGE_SIZE	0x48
+#define ESDHC_BOOT_IMAGE_ADDR	0x50
+
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
+{
+	u8 *tmp_buf;
+	u32 blklen, code_offset, code_len, n;
+
+	blklen = mmc->read_bl_len;
+	tmp_buf = malloc(blklen);
+	if (!tmp_buf)
+		return 1;
+
+	/* read out the first block, get the config data information */
+	n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf);
+	if (!n) {
+		free(tmp_buf);
+		return 1;
+	}
+
+	/* Get the Source Address, from offset 0x50 */
+	code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR);
+
+	/* Get the code size from offset 0x48 */
+	code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
+
+	*env_addr = code_offset + code_len;
+
+	free(tmp_buf);
+
+	return 0;
+}

u-boot/board/gdsys/p1022/tlb.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - eLBC */
+	SET_TLB_ENTRY(1, CONFIG_SYS_ELBC_BASE, CONFIG_SYS_ELBC_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_TRAILBLAZER)
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 9, BOOKE_PAGESZ_256K, 1),
+#else
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
+		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256K, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_1G, 1),
+#endif
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);