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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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12
u-boot/board/freescale/t4qds/Kconfig Normal file
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if TARGET_T4240QDS
config SYS_BOARD
default "t4qds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "T4240QDS"
endif

18
u-boot/board/freescale/t4qds/MAINTAINERS Normal file
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T4QDS BOARD
M: Shaohui Xie <Shaohui.Xie@freescale.com>
S: Maintained
F: board/freescale/t4qds/
F: include/configs/T4240QDS.h
F: configs/T4160QDS_defconfig
F: configs/T4160QDS_NAND_defconfig
F: configs/T4160QDS_SDCARD_defconfig
F: configs/T4240QDS_defconfig
F: configs/T4240QDS_NAND_defconfig
F: configs/T4240QDS_SDCARD_defconfig
F: configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
T4160QDS_SECURE_BOOT BOARD
M: Aneesh Bansal <aneesh.bansal@freescale.com>
S: Maintained
F: configs/T4160QDS_SECURE_BOOT_defconfig
F: configs/T4240QDS_SECURE_BOOT_defconfig

16
u-boot/board/freescale/t4qds/Makefile Normal file
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#
# Copyright 2012 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_T4240QDS) += t4240qds.o eth.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o

194
u-boot/board/freescale/t4qds/README Normal file
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Overview
--------
The T4240QDS is a high-performance computing evaluation, development and test
platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is
optimized to support the high-bandwidth DDR3 memory ports, as well as the
highly-configurable SerDes ports. The system is lead-free and RoHS-compliant.
Board Features
SERDES Connections
32 lanes grouped into four 8-lane banks
Two “front side” banks dedicated to Ethernet
- High-speed crosspoint switch fabric on selected lanes
- Two PCI Express slots with side-band connector supporting
- SGMII
- XAUI
- HiGig
- I-pass connectors allow board-to-board and loopback support
Two “back side” banks dedicated to other protocols
- High-speed crosspoint switch fabric on all lanes
- Four PCI Express slots with side-band connector supporting
- PCI Express 3.0
- SATA 2.0
- SRIO 2.0
- Supports 4X Aurora debug with two connectors
DDR Controllers
Three independant 64-bit DDR3 controllers
Supports rates of 1866 up to 2133 MHz data-rate
Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
DDR power supplies 1.5V to all devices with automatic tracking of VTT.
Power software-switchable to 1.35V if software detects all DDR3LP devices.
MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and
2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time
increases by 1 clock.
IFC/Local Bus
NAND flash: 8-bit, async or sync, up to 2GB.
NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB
NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- NOR devices support 16 virtual banks
GASIC: Minimal target within Qixis FPGA
PromJET rapid memory download support
Address demultiplexing handled within FPGA.
- Flexible demux allows 8 or 16 bit evaluation.
IFC Debug/Development card
- Support for 32-bit devices
Ethernet
Support two on-board RGMII 10/100/1G ethernet ports.
SGMII and XAUI support via SERDES block (see above).
1588 support via Symmetricom board.
QIXIS System Logic FPGA
Manages system power and reset sequencing
Manages DUT, board, clock, etc. configuration for dynamic shmoo
Collects V-I-T data in background for code/power profiling.
Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
General fault monitoring and logging
Runs from ATX “hot” power rails allowing operation while system is off.
Clocks
System and DDR clock (SYSCLK, “DDRCLK”)
- Switch selectable to one of 16 common settings in the interval 33MHz-166MHz.
- Software selectable in 1MHz increments from 1-200MHz.
SERDES clocks
- Provides clocks to all SerDes blocks and slots
- 100, 125 and 156.25 MHz
Power Supplies
Dedicated regulators for VDD
- Adjustable from (0.7V to 1.3V at 80A
- Regulators can be controlled by VID and/or software
Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A
- VTT/MVREF automatically track operating voltage
Dedicated regulators/filters for AVDD supplies
Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc.
USB
Supports two USB 2.0 ports with integrated PHYs
- One type A, one type micro-AB with 1.0A power per port.
Other IO
eSDHC/MMC
- SDHC card slot
eSPI port
- High-speed serial flash
Two Serial port
Four I2C ports
XFI
XFI is supported on T4QDS-XFI board which removed slot3 and routed
four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate
10GBASE-KR scenario.
So, for XFI usage, there are two scenarios, one will use fiber cable,
another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
introduced to indicate a XFI port will use copper cable, and U-Boot
will fixup the dtb accordingly.
It's used as: fsl_10gkr_copper:<10g_mac_name>
The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they
do not have to be coexist in hwconfig. If a MAC is listed in the env
"fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
will be used by default.
for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in
hwconfig, then both four XFI ports will use copper cable.
set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
XFI ports will use copper cable, the other two XFI ports will use fiber
cable.
Memory map
----------
The addresses in brackets are physical addresses.
0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB)
0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers)
0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan
0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan
0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash
0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR
0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS
0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores
The physical address of the last (boot page translation) varies with the actual DDR size.
Voltage ID and VDD override
--------------------
T4240 has a VID feature. U-Boot reads the VID efuses and adjust the voltage
accordingly. The voltage can also be override by command vdd_override. The
syntax is
vdd_override <voltage in mV>, eg. 1050 is for 1.050v.
Upon success, the actual voltage will be read back. The value is checked
for safety and any invalid value will not adjust the voltage.
Another way to override VDD is to use environmental variable, in case of using
command is too late for some debugging. The syntax is
setenv t4240qds_vdd_mv <voltage in mV>
saveenv
reset
The override voltage takes effect when booting.
Note: voltage adjustment needs to be done step by step. Changing voltage too
rapidly may cause current surge. The voltage stepping is done by software.
Users can set the final voltage directly.
2-stage NAND/SD boot loader
-------------------------------
PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
SPL further initialise DDR using SPD and environment variables
and copy U-Boot(768 KB) from NAND/SD device to DDR.
Finally SPL transers control to U-Boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework
-------------------------------------------------
|Area | Address |
-------------------------------------------------
|SecureBoot header | 0xFFFC0000 (32KB) |
-------------------------------------------------
|GD, BD | 0xFFFC8000 (4KB) |
-------------------------------------------------
|ENV | 0xFFFC9000 (8KB) |
-------------------------------------------------
|HEAP | 0xFFFCB000 (50KB) |
-------------------------------------------------
|STACK | 0xFFFD8000 (22KB) |
-------------------------------------------------
|U-Boot SPL | 0xFFFD8000 (160KB) |
-------------------------------------------------
NAND Flash memory Map on T4QDS
--------------------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF U-Boot img 1MB
0x140000 0x15FFFF U-Boot env 128KB
0x160000 0x17FFFF FMAN Ucode 128KB
Micro SD Card memory Map on T4QDS
----------------------------------------------------
Block #blocks Definition Size
0x008 2048 U-Boot img 1MB
0x800 0016 U-Boot env 8KB
0x820 0128 FMAN ucode 64KB
Switch Settings: (ON is 1, OFF is 0)
===============
NAND boot SW setting:
SW1[1:8] = 10000010
SW2[1.1] = 0
SW6[1:4] = 1001
SD boot SW setting:
SW1[1:8] = 00100000
SW2[1.1] = 0

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u-boot/board/freescale/t4qds/ddr.c Normal file
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/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
if (ctrl_num > 2) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
/*
* we use identical timing for all slots. If needed, change the code
* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
*/
if (popts->registered_dimm_en)
pbsp = rdimms[0];
else
pbsp = udimms[0];
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found "
"for data rate %lu MT/s\n"
"Trying to use the highest speed (%u) parameters\n",
ddr_freq, pbsp_highest->datarate_mhz_high);
popts->cpo_override = pbsp_highest->cpo;
popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
found:
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
"wrlvl_ctrl_3 0x%x\n",
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* Rtt and Rtt_WR override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
puts("Initializing....using SPD\n");
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
return dram_size;
}

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u-boot/board/freescale/t4qds/ddr.h Normal file
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/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DDR_H__
#define __DDR_H__
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
u32 cpo;
u32 write_data_delay;
u32 force_2t;
};
/*
* These tables contain all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
{2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
{2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
{2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
{2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
{1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
{1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{}
};
static const struct board_specific_parameters rdimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
{4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
{4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{}
};
/*
* The three slots have slightly different timing. The center values are good
* for all slots. We use identical speed tables for them. In future use, if
* DIMMs require separated tables, make more entries as needed.
*/
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
/*
* The three slots have slightly different timing. See comments above.
*/
static const struct board_specific_parameters *rdimms[] = {
rdimm0,
};
#endif

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u-boot/board/freescale/t4qds/eth.c Normal file
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/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include <hwconfig.h>
#include "../common/qixis.h"
#include "../common/fman.h"
#include "t4240qds_qixis.h"
#define EMI_NONE 0xFFFFFFFF
#define EMI1_RGMII 0
#define EMI1_SLOT1 1
#define EMI1_SLOT2 2
#define EMI1_SLOT3 3
#define EMI1_SLOT4 4
#define EMI1_SLOT5 5
#define EMI1_SLOT7 7
#define EMI2 8
/* Slot6 and Slot8 do not have EMI connections */
static int mdio_mux[NUM_FM_PORTS];
static const char *mdio_names[] = {
"T4240QDS_MDIO0",
"T4240QDS_MDIO1",
"T4240QDS_MDIO2",
"T4240QDS_MDIO3",
"T4240QDS_MDIO4",
"T4240QDS_MDIO5",
"NULL",
"T4240QDS_MDIO7",
"T4240QDS_10GC",
};
static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
static u8 slot_qsgmii_phyaddr[5][4] = {
{0, 0, 0, 0},/* not used, to make index match slot No. */
{0, 1, 2, 3},
{4, 5, 6, 7},
{8, 9, 0xa, 0xb},
{0xc, 0xd, 0xe, 0xf},
};
static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
const char *name = t4240qds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
return NULL;
}
bus = miiphy_get_dev_by_name(name);
if (!bus) {
printf("No bus by name %s\n", name);
return NULL;
}
return bus;
}
struct t4240qds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
static void t4240qds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
if ((muxval < 6) || (muxval == 7)) {
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
QIXIS_WRITE(brdcfg[4], brdcfg4);
}
}
static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
struct t4240qds_mdio *priv = bus->priv;
t4240qds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
struct t4240qds_mdio *priv = bus->priv;
t4240qds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
static int t4240qds_mdio_reset(struct mii_dev *bus)
{
struct t4240qds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
static int t4240qds_mdio_init(char *realbusname, u8 muxval)
{
struct t4240qds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate T4240QDS MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
printf("Failed to allocate T4240QDS private data\n");
free(bus);
return -1;
}
bus->read = t4240qds_mdio_read;
bus->write = t4240qds_mdio_write;
bus->reset = t4240qds_mdio_reset;
strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
if (!pmdio->realbus) {
printf("No bus with name %s\n", realbusname);
free(bus);
free(pmdio);
return -1;
}
pmdio->muxval = muxval;
bus->priv = pmdio;
return mdio_register(bus);
}
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
{
int interface = fm_info_get_enet_if(port);
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
if (interface == PHY_INTERFACE_MODE_SGMII ||
interface == PHY_INTERFACE_MODE_QSGMII) {
switch (port) {
case FM1_DTSEC1:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy21");
break;
case FM1_DTSEC2:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy22");
break;
case FM1_DTSEC3:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy23");
break;
case FM1_DTSEC4:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy24");
break;
case FM1_DTSEC6:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy12");
break;
case FM1_DTSEC9:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy14");
else
fdt_set_phy_handle(blob, prop, pa,
"phy_sgmii4");
break;
case FM1_DTSEC10:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy13");
else
fdt_set_phy_handle(blob, prop, pa,
"phy_sgmii3");
break;
case FM2_DTSEC1:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy41");
break;
case FM2_DTSEC2:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy42");
break;
case FM2_DTSEC3:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy43");
break;
case FM2_DTSEC4:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy44");
break;
case FM2_DTSEC6:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy32");
break;
case FM2_DTSEC9:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy34");
else
fdt_set_phy_handle(blob, prop, pa,
"phy_sgmii12");
break;
case FM2_DTSEC10:
if (qsgmiiphy_fix[port])
fdt_set_phy_handle(blob, prop, pa,
"sgmii_phy33");
else
fdt_set_phy_handle(blob, prop, pa,
"phy_sgmii11");
break;
default:
break;
}
} else if (interface == PHY_INTERFACE_MODE_XGMII &&
((prtcl2 == 55) || (prtcl2 == 57))) {
/*
* if the 10G is XFI, check hwconfig to see what is the
* media type, there are two types, fiber or copper,
* fix the dtb accordingly.
*/
int media_type = 0;
struct fixed_link f_link;
char lane_mode[20] = {"10GBASE-KR"};
char buf[32] = "serdes-2,";
int off;
switch (port) {
case FM1_10GEC1:
if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
media_type = 1;
fdt_set_phy_handle(blob, prop, pa,
"phy_xfi1");
sprintf(buf, "%s%s%s", buf, "lane-a,",
(char *)lane_mode);
}
break;
case FM1_10GEC2:
if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
media_type = 1;
fdt_set_phy_handle(blob, prop, pa,
"phy_xfi2");
sprintf(buf, "%s%s%s", buf, "lane-b,",
(char *)lane_mode);
}
break;
case FM2_10GEC1:
if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
media_type = 1;
fdt_set_phy_handle(blob, prop, pa,
"phy_xfi3");
sprintf(buf, "%s%s%s", buf, "lane-d,",
(char *)lane_mode);
}
break;
case FM2_10GEC2:
if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
media_type = 1;
fdt_set_phy_handle(blob, prop, pa,
"phy_xfi4");
sprintf(buf, "%s%s%s", buf, "lane-c,",
(char *)lane_mode);
}
break;
default:
return;
}
if (!media_type) {
/* fixed-link is used for XFI fiber cable */
fdt_delprop(blob, offset, "phy-handle");
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
f_link.pause = 0;
f_link.asym_pause = 0;
fdt_setprop(blob, offset, "fixed-link", &f_link,
sizeof(f_link));
} else {
/* set property for copper cable */
off = fdt_node_offset_by_compat_reg(blob,
"fsl,fman-memac-mdio", pa + 0x1000);
fdt_setprop_string(blob, off, "lane-instance", buf);
}
}
}
void fdt_fixup_board_enet(void *fdt)
{
int i;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_QSGMII:
switch (mdio_mux[i]) {
case EMI1_SLOT1:
fdt_status_okay_by_alias(fdt, "emi1_slot1");
break;
case EMI1_SLOT2:
fdt_status_okay_by_alias(fdt, "emi1_slot2");
break;
case EMI1_SLOT3:
fdt_status_okay_by_alias(fdt, "emi1_slot3");
break;
case EMI1_SLOT4:
fdt_status_okay_by_alias(fdt, "emi1_slot4");
break;
default:
break;
}
break;
case PHY_INTERFACE_MODE_XGMII:
/* check if it's XFI interface for 10g */
if ((prtcl2 == 55) || (prtcl2 == 57)) {
if (i == FM1_10GEC1 && hwconfig_sub(
"fsl_10gkr_copper", "fm1_10g1"))
fdt_status_okay_by_alias(
fdt, "xfi_pcs_mdio1");
if (i == FM1_10GEC2 && hwconfig_sub(
"fsl_10gkr_copper", "fm1_10g2"))
fdt_status_okay_by_alias(
fdt, "xfi_pcs_mdio2");
if (i == FM2_10GEC1 && hwconfig_sub(
"fsl_10gkr_copper", "fm2_10g1"))
fdt_status_okay_by_alias(
fdt, "xfi_pcs_mdio3");
if (i == FM2_10GEC2 && hwconfig_sub(
"fsl_10gkr_copper", "fm2_10g2"))
fdt_status_okay_by_alias(
fdt, "xfi_pcs_mdio4");
break;
}
switch (i) {
case FM1_10GEC1:
fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
break;
case FM1_10GEC2:
fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
break;
case FM2_10GEC1:
fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
break;
case FM2_10GEC2:
fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
break;
default:
break;
}
break;
default:
break;
}
}
}
static void initialize_qsgmiiphy_fix(void)
{
int i;
unsigned short reg;
for (i = 1; i <= 4; i++) {
/*
* Try to read if a SGMII card is used, we do it slot by slot.
* if a SGMII PHY address is valid on a slot, then we mark
* all ports on the slot, then fix the PHY address for the
* marked port when doing dtb fixup.
*/
if (miiphy_read(mdio_names[i],
SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
debug("Slot%d PHY ID register 2 read failed\n", i);
continue;
}
debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
if (reg == 0xFFFF) {
/* No physical device present at this address */
continue;
}
switch (i) {
case 1:
qsgmiiphy_fix[FM1_DTSEC5] = 1;
qsgmiiphy_fix[FM1_DTSEC6] = 1;
qsgmiiphy_fix[FM1_DTSEC9] = 1;
qsgmiiphy_fix[FM1_DTSEC10] = 1;
slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
break;
case 2:
qsgmiiphy_fix[FM1_DTSEC1] = 1;
qsgmiiphy_fix[FM1_DTSEC2] = 1;
qsgmiiphy_fix[FM1_DTSEC3] = 1;
qsgmiiphy_fix[FM1_DTSEC4] = 1;
slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
break;
case 3:
qsgmiiphy_fix[FM2_DTSEC5] = 1;
qsgmiiphy_fix[FM2_DTSEC6] = 1;
qsgmiiphy_fix[FM2_DTSEC9] = 1;
qsgmiiphy_fix[FM2_DTSEC10] = 1;
slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
break;
case 4:
qsgmiiphy_fix[FM2_DTSEC1] = 1;
qsgmiiphy_fix[FM2_DTSEC2] = 1;
qsgmiiphy_fix[FM2_DTSEC3] = 1;
qsgmiiphy_fix[FM2_DTSEC4] = 1;
slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
break;
default:
break;
}
}
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1, srds_prtcl_s2;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
initialize_qsgmiiphy_fix();
switch (srds_prtcl_s1) {
case 1:
case 2:
case 4:
/* XAUI/HiGig in Slot1 and Slot2 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
break;
case 27:
case 28:
case 35:
case 36:
/* SGMII in Slot1 and Slot2 */
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
slot_qsgmii_phyaddr[1][3]);
fm_info_set_phy_address(FM1_DTSEC10,
slot_qsgmii_phyaddr[1][2]);
}
break;
case 37:
case 38:
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
slot_qsgmii_phyaddr[1][2]);
fm_info_set_phy_address(FM1_DTSEC10,
slot_qsgmii_phyaddr[1][3]);
}
break;
case 39:
case 40:
case 45:
case 46:
case 47:
case 48:
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC10,
slot_qsgmii_phyaddr[1][2]);
fm_info_set_phy_address(FM1_DTSEC9,
slot_qsgmii_phyaddr[1][3]);
}
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
break;
default:
puts("Invalid SerDes1 protocol for T4240QDS\n");
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_QSGMII) {
if (idx <= 3)
lane = serdes_get_first_lane(FSL_SRDS_1,
QSGMII_FM1_A);
else
lane = serdes_get_first_lane(FSL_SRDS_1,
QSGMII_FM1_B);
if (lane < 0)
break;
slot = lane_to_slot_fsm1[lane];
debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
idx + 1, slot);
} else {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot_fsm1[lane];
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
}
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 1:
mdio_mux[i] = EMI1_SLOT1;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case 2:
mdio_mux[i] = EMI1_SLOT2;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
case PHY_INTERFACE_MODE_RGMII:
/* FM1 DTSEC5 routes to RGMII with EC2 */
debug("FM1@DTSEC%u is RGMII at address %u\n",
idx + 1, 2);
if (i == FM1_DTSEC5)
fm_info_set_phy_address(i, 2);
mdio_mux[i] = EMI1_RGMII;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
/* A fake PHY address to make U-Boot happy */
fm_info_set_phy_address(i, i);
} else {
lane = serdes_get_first_lane(FSL_SRDS_1,
XAUI_FM1_MAC9 + idx);
if (lane < 0)
break;
slot = lane_to_slot_fsm1[lane];
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
}
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
#if (CONFIG_SYS_NUM_FMAN == 2)
switch (srds_prtcl_s2) {
case 1:
case 2:
case 4:
/* XAUI/HiGig in Slot3 and Slot4 */
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
break;
case 6:
case 7:
case 12:
case 13:
case 14:
case 15:
case 16:
case 21:
case 22:
case 23:
case 24:
case 25:
case 26:
/* XAUI/HiGig in Slot3, SGMII in Slot4 */
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 27:
case 28:
case 35:
case 36:
/* SGMII in Slot3 and Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
break;
case 37:
case 38:
/* QSGMII in Slot3 and Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
break;
case 39:
case 40:
case 45:
case 46:
case 47:
case 48:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
/* QSGMII in Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 49:
case 50:
case 51:
case 52:
case 53:
case 54:
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 55:
case 57:
/* XFI in Slot3, SGMII in Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
default:
puts("Invalid SerDes2 protocol for T4240QDS\n");
break;
}
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
idx = i - FM2_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_QSGMII) {
if (idx <= 3)
lane = serdes_get_first_lane(FSL_SRDS_2,
QSGMII_FM2_A);
else
lane = serdes_get_first_lane(FSL_SRDS_2,
QSGMII_FM2_B);
if (lane < 0)
break;
slot = lane_to_slot_fsm2[lane];
debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
idx + 1, slot);
} else {
lane = serdes_get_first_lane(FSL_SRDS_2,
SGMII_FM2_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot_fsm2[lane];
debug("FM2@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
}
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
case PHY_INTERFACE_MODE_RGMII:
/*
* If DTSEC5 is RGMII, then it's routed via via EC1 to
* the first on-board RGMII port. If DTSEC6 is RGMII,
* then it's routed via via EC2 to the second on-board
* RGMII port.
*/
debug("FM2@DTSEC%u is RGMII at address %u\n",
idx + 1, i == FM2_DTSEC5 ? 1 : 2);
fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
mdio_mux[i] = EMI1_RGMII;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
idx = i - FM2_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
/* A fake PHY address to make U-Boot happy */
fm_info_set_phy_address(i, i);
} else {
lane = serdes_get_first_lane(FSL_SRDS_2,
XAUI_FM2_MAC9 + idx);
if (lane < 0)
break;
slot = lane_to_slot_fsm2[lane];
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
}
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
#endif /* CONFIG_SYS_NUM_FMAN */
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}

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u-boot/board/freescale/t4qds/law.c Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
#ifdef QIXIS_BASE_PHYS
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

23
u-boot/board/freescale/t4qds/pci.c Normal file
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/*
* Copyright 2007-2012 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}

143
u-boot/board/freescale/t4qds/spl.c Normal file
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/* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <console.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include "../common/qixis.h"
#include "t4240qds_qixis.h"
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
DECLARE_GLOBAL_DATA_PTR;
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x0F) {
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#ifdef CONFIG_SPL_NAND_BOOT
u32 porsr1, pinctl;
#endif
#ifdef CONFIG_SPL_NAND_BOOT
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
#endif
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("" : : : "memory");
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
ccb_clk / 16 / CONFIG_BAUDRATE);
#ifdef CONFIG_SPL_MMC_BOOT
puts("\nSD boot...\n");
#elif defined(CONFIG_SPL_NAND_BOOT)
puts("\nNAND boot...\n");
#endif
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
bd_t *bd;
bd = (bd_t *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
probecpu();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = 1;
i2c_init_all();
gd->ram_size = initdram(0);
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}

82
u-boot/board/freescale/t4qds/t4240emu.c Normal file
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/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_liodn.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
printf("Board: %sEMU\n", cpu->name);
return 0;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
return 0;
}
int misc_init_r(void)
{
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
fdt_fixup_liodn(blob);
fdt_fixup_dr_usb(blob, bd);
return 0;
}

888
u-boot/board/freescale/t4qds/t4240qds.c Normal file
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/*
* Copyright 2009-2012 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
#include "t4qds.h"
#include "t4240qds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
{8, 8}, {9, 9}, {14, 14}, {15, 15} };
static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
{10, 10}, {11, 11}, {12, 12}, {13, 13} };
static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
{10, 11}, {11, 10}, {12, 2}, {13, 3} };
static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
{8, 9}, {9, 8}, {14, 1}, {15, 0} };
int checkboard(void)
{
char buf[64];
u8 sw;
struct cpu_type *cpu = gd->arch.cpu;
unsigned int i;
printf("Board: %sQDS, ", cpu->name);
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
QIXIS_READ(id), QIXIS_READ(arch));
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
if (sw < 0x8)
printf("vBank: %d\n", sw);
else if (sw == 0x8)
puts("Promjet\n");
else if (sw == 0x9)
puts("NAND\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
printf("FPGA: v%d (%s), build %d",
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
/* the timestamp string contains "\n" at the end */
printf(" on %s", qixis_read_time(buf));
/*
* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
* technically be set to force the reference clocks to match the
* values that the SERDES expects (or vice versa). For now, however,
* we just display both values and hope the user notices when they
* don't match.
*/
puts("SERDES Reference Clocks: ");
sw = QIXIS_READ(brdcfg[2]);
for (i = 0; i < MAX_SERDES; i++) {
static const char * const freq[] = {
"100", "125", "156.25", "161.1328125"};
unsigned int clock = (sw >> (6 - 2 * i)) & 3;
printf("SERDES%u=%sMHz ", i+1, freq[clock]);
}
puts("\n");
return 0;
}
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
}
return 0;
}
/*
* read_voltage from sensor on I2C bus
* We use average of 4 readings, waiting for 532us befor another reading
*/
#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
static inline int read_voltage(void)
{
int i, ret, voltage_read = 0;
u16 vol_mon;
for (i = 0; i < NUM_READINGS; i++) {
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
if (ret) {
printf("VID: failed to read core voltage\n");
return ret;
}
if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
printf("VID: Core voltage sensor error\n");
return -1;
}
debug("VID: bus voltage reads 0x%04x\n", vol_mon);
/* LSB = 4mv */
voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
udelay(WAIT_FOR_ADC);
}
/* calculate the average */
voltage_read /= NUM_READINGS;
return voltage_read;
}
/*
* We need to calculate how long before the voltage starts to drop or increase
* It returns with the loop count. Each loop takes several readings (532us)
*/
static inline int wait_for_voltage_change(int vdd_last)
{
int timeout, vdd_current;
vdd_current = read_voltage();
/* wait until voltage starts to drop */
for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
timeout < 100; timeout++) {
vdd_current = read_voltage();
}
if (timeout >= 100) {
printf("VID: Voltage adjustment timeout\n");
return -1;
}
return timeout;
}
/*
* argument 'wait' is the time we know the voltage difference can be measured
* this function keeps reading the voltage until it is stable
*/
static inline int wait_for_voltage_stable(int wait)
{
int timeout, vdd_current, vdd_last;
vdd_last = read_voltage();
udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
/* wait until voltage is stable */
vdd_current = read_voltage();
for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
timeout < 100; timeout++) {
vdd_last = vdd_current;
udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
vdd_current = read_voltage();
}
if (timeout >= 100) {
printf("VID: Voltage adjustment timeout\n");
return -1;
}
return vdd_current;
}
static inline int set_voltage(u8 vid)
{
int wait, vdd_last;
vdd_last = read_voltage();
QIXIS_WRITE(brdcfg[6], vid);
wait = wait_for_voltage_change(vdd_last);
if (wait < 0)
return -1;
debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
wait = wait ? wait : 1;
vdd_last = wait_for_voltage_stable(wait);
if (vdd_last < 0)
return -1;
debug("VID: Current voltage is %d mV\n", vdd_last);
return vdd_last;
}
static int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
ccsr_gur_t __iomem *gur =
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 fusesr;
u8 vid, vid_current;
int vdd_target, vdd_current, vdd_last;
int ret;
unsigned long vdd_string_override;
char *vdd_string;
static const uint16_t vdd[32] = {
0, /* unused */
9875, /* 0.9875V */
9750,
9625,
9500,
9375,
9250,
9125,
9000,
8875,
8750,
8625,
8500,
8375,
8250,
8125,
10000, /* 1.0000V */
10125,
10250,
10375,
10500,
10625,
10750,
10875,
11000,
0, /* reserved */
};
struct vdd_drive {
u8 vid;
unsigned voltage;
};
ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
if (ret) {
debug("VID: I2c failed to switch channel\n");
ret = -1;
goto exit;
}
/* get the voltage ID from fuse status register */
fusesr = in_be32(&gur->dcfg_fusesr);
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_VID_MASK;
if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
}
vdd_target = vdd[vid];
/* check override variable for overriding VDD */
vdd_string = getenv("t4240qds_vdd_mv");
if (vdd_override == 0 && vdd_string &&
!strict_strtoul(vdd_string, 10, &vdd_string_override))
vdd_override = vdd_string_override;
if (vdd_override >= 819 && vdd_override <= 1212) {
vdd_target = vdd_override * 10; /* convert to 1/10 mV */
debug("VDD override is %lu\n", vdd_override);
} else if (vdd_override != 0) {
printf("Invalid value.\n");
}
if (vdd_target == 0) {
debug("VID: VID not used\n");
ret = 0;
goto exit;
} else {
/* round up and divice by 10 to get a value in mV */
vdd_target = DIV_ROUND_UP(vdd_target, 10);
debug("VID: vid = %d mV\n", vdd_target);
}
/*
* Check current board VID setting
* Voltage regulator support output to 6.250mv step
* The highes voltage allowed for this board is (vid=0x40) 1.21250V
* the lowest is (vid=0x7f) 0.81875V
*/
vid_current = QIXIS_READ(brdcfg[6]);
vdd_current = 121250 - (vid_current - 0x40) * 625;
debug("VID: Current vid setting is (0x%x) %d mV\n",
vid_current, vdd_current/100);
/*
* Read voltage monitor to check real voltage.
* Voltage monitor LSB is 4mv.
*/
vdd_last = read_voltage();
if (vdd_last < 0) {
printf("VID: Could not read voltage sensor abort VID adjustment\n");
ret = -1;
goto exit;
}
debug("VID: Core voltage is at %d mV\n", vdd_last);
/*
* Adjust voltage to at or 8mV above target.
* Each step of adjustment is 6.25mV.
* Stepping down too fast may cause over current.
*/
while (vdd_last > 0 && vid_current < 0x80 &&
vdd_last > (vdd_target + 8)) {
vid_current++;
vdd_last = set_voltage(vid_current);
}
/*
* Check if we need to step up
* This happens when board voltage switch was set too low
*/
while (vdd_last > 0 && vid_current >= 0x40 &&
vdd_last < vdd_target + 2) {
vid_current--;
vdd_last = set_voltage(vid_current);
}
if (vdd_last > 0)
printf("VID: Core voltage %d mV\n", vdd_last);
else
ret = -1;
exit:
if (re_enable)
enable_interrupts();
return ret;
}
/* Configure Crossbar switches for Front-Side SerDes Ports */
int config_frontside_crossbar_vsc3316(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1, srds_prtcl_s2;
int ret;
ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
if (ret)
return ret;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_prtcl_s1) {
case 37:
case 38:
/* swap first lane and third lane on slot1 */
vsc3316_fsm1_tx[0][1] = 14;
vsc3316_fsm1_tx[6][1] = 0;
vsc3316_fsm1_rx[1][1] = 2;
vsc3316_fsm1_rx[6][1] = 13;
case 39:
case 40:
case 45:
case 46:
case 47:
case 48:
/* swap first lane and third lane on slot2 */
vsc3316_fsm1_tx[2][1] = 8;
vsc3316_fsm1_tx[4][1] = 6;
vsc3316_fsm1_rx[2][1] = 10;
vsc3316_fsm1_rx[5][1] = 5;
default:
ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
if (ret)
return ret;
ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
if (ret)
return ret;
break;
}
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
switch (srds_prtcl_s2) {
case 37:
case 38:
/* swap first lane and third lane on slot3 */
vsc3316_fsm2_tx[2][1] = 11;
vsc3316_fsm2_tx[5][1] = 4;
vsc3316_fsm2_rx[2][1] = 9;
vsc3316_fsm2_rx[4][1] = 7;
case 39:
case 40:
case 45:
case 46:
case 47:
case 48:
case 49:
case 50:
case 51:
case 52:
case 53:
case 54:
/* swap first lane and third lane on slot4 */
vsc3316_fsm2_tx[6][1] = 3;
vsc3316_fsm2_tx[1][1] = 12;
vsc3316_fsm2_rx[0][1] = 1;
vsc3316_fsm2_rx[6][1] = 15;
default:
ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
if (ret)
return ret;
ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
if (ret)
return ret;
break;
}
return 0;
}
int config_backside_crossbar_mux(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s3, srds_prtcl_s4;
u8 brdcfg;
srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
switch (srds_prtcl_s3) {
case 0:
/* SerDes3 is not enabled */
break;
case 1:
case 2:
case 9:
case 10:
/* SD3(0:7) => SLOT5(0:7) */
brdcfg = QIXIS_READ(brdcfg[12]);
brdcfg &= ~BRDCFG12_SD3MX_MASK;
brdcfg |= BRDCFG12_SD3MX_SLOT5;
QIXIS_WRITE(brdcfg[12], brdcfg);
break;
case 3:
case 4:
case 5:
case 6:
case 7:
case 8:
case 11:
case 12:
case 13:
case 14:
case 15:
case 16:
case 17:
case 18:
case 19:
case 20:
/* SD3(4:7) => SLOT6(0:3) */
brdcfg = QIXIS_READ(brdcfg[12]);
brdcfg &= ~BRDCFG12_SD3MX_MASK;
brdcfg |= BRDCFG12_SD3MX_SLOT6;
QIXIS_WRITE(brdcfg[12], brdcfg);
break;
default:
printf("WARNING: unsupported for SerDes3 Protocol %d\n",
srds_prtcl_s3);
return -1;
}
srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
switch (srds_prtcl_s4) {
case 0:
/* SerDes4 is not enabled */
break;
case 1:
case 2:
/* 10b, SD4(0:7) => SLOT7(0:7) */
brdcfg = QIXIS_READ(brdcfg[12]);
brdcfg &= ~BRDCFG12_SD4MX_MASK;
brdcfg |= BRDCFG12_SD4MX_SLOT7;
QIXIS_WRITE(brdcfg[12], brdcfg);
break;
case 3:
case 4:
case 5:
case 6:
case 7:
case 8:
/* x1b, SD4(4:7) => SLOT8(0:3) */
brdcfg = QIXIS_READ(brdcfg[12]);
brdcfg &= ~BRDCFG12_SD4MX_MASK;
brdcfg |= BRDCFG12_SD4MX_SLOT8;
QIXIS_WRITE(brdcfg[12], brdcfg);
break;
case 9:
case 10:
case 11:
case 12:
case 13:
case 14:
case 15:
case 16:
case 18:
/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
brdcfg = QIXIS_READ(brdcfg[12]);
brdcfg &= ~BRDCFG12_SD4MX_MASK;
brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
QIXIS_WRITE(brdcfg[12], brdcfg);
break;
default:
printf("WARNING: unsupported for SerDes4 Protocol %d\n",
srds_prtcl_s4);
return -1;
}
return 0;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
*/
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
/* Configure board SERDES ports crossbar */
config_frontside_crossbar_vsc3316();
config_backside_crossbar_mux();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
return 0;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
/* use accurate clock measurement */
int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
u32 val;
val = freq * base;
if (val) {
debug("SYS Clock measurement is: %d\n", val);
return val;
} else {
printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
}
#endif
switch (sysclk_conf & 0x0F) {
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
/* use accurate clock measurement */
int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
u32 val;
val = freq * base;
if (val) {
debug("DDR Clock measurement is: %d\n", val);
return val;
} else {
printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
}
#endif
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
int misc_init_r(void)
{
u8 sw;
void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
serdes_corenet_t *srds_regs;
u32 actual[MAX_SERDES];
u32 pllcr0, expected;
unsigned int i;
sw = QIXIS_READ(brdcfg[2]);
for (i = 0; i < MAX_SERDES; i++) {
unsigned int clock = (sw >> (6 - 2 * i)) & 3;
switch (clock) {
case 0:
actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
break;
case 1:
actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
break;
case 2:
actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
break;
case 3:
actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
break;
}
}
for (i = 0; i < MAX_SERDES; i++) {
srds_regs = srds_base + i * 0x1000;
pllcr0 = srds_regs->bank[0].pllcr0;
expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
if (expected != actual[i]) {
printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
i + 1, serdes_clock_to_string(expected),
serdes_clock_to_string(actual[i]));
}
}
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_PCI
pci_of_setup(blob, bd);
#endif
fdt_fixup_liodn(blob);
fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
return 0;
}
/*
* This function is called by bdinfo to print detail board information.
* As an exmaple for future board, we organize the messages into
* several sections. If applicable, the message is in the format of
* <name> = <value>
* It should aligned with normal output of bdinfo command.
*
* Voltage: Core, DDR and another configurable voltages
* Clock : Critical clocks which are not printed already
* RCW : RCW source if not printed already
* Misc : Other important information not in above catagories
*/
void board_detail(void)
{
int i;
u8 brdcfg[16], dutcfg[16], rst_ctl;
int vdd, rcwsrc;
static const char * const clk[] = {"66.67", "100", "125", "133.33"};
for (i = 0; i < 16; i++) {
brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
}
/* Voltage secion */
if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
vdd = read_voltage();
if (vdd > 0)
printf("Core voltage= %d mV\n", vdd);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
}
printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
/* clock section */
printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
/* RCW section */
rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
puts("RCW source = ");
switch (rcwsrc) {
case 0x017:
case 0x01f:
puts("8-bit NOR\n");
break;
case 0x027:
case 0x02F:
puts("16-bit NOR\n");
break;
case 0x040:
puts("SDHC/eMMC\n");
break;
case 0x044:
puts("SPI 16-bit addressing\n");
break;
case 0x045:
puts("SPI 24-bit addressing\n");
break;
case 0x048:
puts("I2C normal addressing\n");
break;
case 0x049:
puts("I2C extended addressing\n");
break;
case 0x108:
case 0x109:
case 0x10a:
case 0x10b:
puts("8-bit NAND, 2KB\n");
break;
default:
if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
puts("Hard-coded RCW\n");
else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
puts("8-bit NAND, 4KB\n");
else
puts("unknown\n");
break;
}
/* Misc section */
rst_ctl = QIXIS_READ(rst_ctl);
puts("HRESET_REQ = ");
switch (rst_ctl & 0x30) {
case 0x00:
puts("Ignored\n");
break;
case 0x10:
puts("Assert HRESET\n");
break;
case 0x30:
puts("Reset system\n");
break;
default:
puts("N/A\n");
break;
}
}
/*
* Reverse engineering switch settings.
* Some bits cannot be figured out. They will be displayed as
* underscore in binary format. mask[] has those bits.
* Some bits are calculated differently than the actual switches
* if booting with overriding by FPGA.
*/
void qixis_dump_switch(void)
{
int i;
u8 sw[9];
/*
* Any bit with 1 means that bit cannot be reverse engineered.
* It will be displayed as _ in binary format.
*/
static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
char buf[10];
u8 brdcfg[16], dutcfg[16];
for (i = 0; i < 16; i++) {
brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
}
sw[0] = dutcfg[0];
sw[1] = (dutcfg[1] << 0x07) |
((dutcfg[12] & 0xC0) >> 1) |
((dutcfg[11] & 0xE0) >> 3) |
((dutcfg[6] & 0x80) >> 6) |
((dutcfg[1] & 0x80) >> 7);
sw[2] = ((brdcfg[1] & 0x0f) << 4) |
((brdcfg[1] & 0x30) >> 2) |
((brdcfg[1] & 0x40) >> 5) |
((brdcfg[1] & 0x80) >> 7);
sw[3] = brdcfg[2];
sw[4] = ((dutcfg[2] & 0x01) << 7) |
((dutcfg[2] & 0x06) << 4) |
((~QIXIS_READ(present)) & 0x10) |
((brdcfg[3] & 0x80) >> 4) |
((brdcfg[3] & 0x01) << 2) |
((brdcfg[6] == 0x62) ? 3 :
((brdcfg[6] == 0x5a) ? 2 :
((brdcfg[6] == 0x5e) ? 1 : 0)));
sw[5] = ((brdcfg[0] & 0x0f) << 4) |
((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
((brdcfg[0] & 0x40) >> 5);
sw[6] = (brdcfg[11] & 0x20) |
((brdcfg[5] & 0x02) << 3);
sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
((brdcfg[5] & 0x10) << 2);
sw[8] = ((brdcfg[12] & 0x08) << 4) |
((brdcfg[12] & 0x03) << 5);
puts("DIP switch (reverse-engineering)\n");
for (i = 0; i < 9; i++) {
printf("SW%d = 0b%s (0x%02x)\n",
i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
}
}
static int do_vdd_adjust(cmd_tbl_t *cmdtp,
int flag, int argc,
char * const argv[])
{
ulong override;
if (argc < 2)
return CMD_RET_USAGE;
if (!strict_strtoul(argv[1], 10, &override))
adjust_vdd(override); /* the value is checked by callee */
else
return CMD_RET_USAGE;
return 0;
}
U_BOOT_CMD(
vdd_override, 2, 0, do_vdd_adjust,
"Override VDD",
"- override with the voltage specified in mV, eg. 1050"
);

43
u-boot/board/freescale/t4qds/t4240qds_qixis.h Normal file
View File

@@ -0,0 +1,43 @@
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __T4020QDS_QIXIS_H__
#define __T4020QDS_QIXIS_H__
/* Definitions of QIXIS Registers for T4020QDS */
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xE0
#define BRDCFG4_EMISEL_SHIFT 5
/* SYSCLK */
#define QIXIS_SYSCLK_66 0x0
#define QIXIS_SYSCLK_83 0x1
#define QIXIS_SYSCLK_100 0x2
#define QIXIS_SYSCLK_125 0x3
#define QIXIS_SYSCLK_133 0x4
#define QIXIS_SYSCLK_150 0x5
#define QIXIS_SYSCLK_160 0x6
#define QIXIS_SYSCLK_166 0x7
/* DDRCLK */
#define QIXIS_DDRCLK_66 0x0
#define QIXIS_DDRCLK_100 0x1
#define QIXIS_DDRCLK_125 0x2
#define QIXIS_DDRCLK_133 0x3
#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
#define BRDCFG12_SD3EN_MASK 0x20
#define BRDCFG12_SD3MX_MASK 0x08
#define BRDCFG12_SD3MX_SLOT5 0x08
#define BRDCFG12_SD3MX_SLOT6 0x00
#define BRDCFG12_SD4EN_MASK 0x04
#define BRDCFG12_SD4MX_MASK 0x03
#define BRDCFG12_SD4MX_SLOT7 0x02
#define BRDCFG12_SD4MX_SLOT8 0x01
#define BRDCFG12_SD4MX_AURO_SATA 0x00
#endif

22
u-boot/board/freescale/t4qds/t4_pbi.cfg Normal file
View File

@@ -0,0 +1,22 @@
#PBI commands
#Initialize CPC1
09010000 00200400
09138000 00000000
091380c0 00000100
#512KB SRAM
09010100 00000000
09010104 fff80009
09010f00 08000000
#enable CPC1
09010000 80000000
#Configure LAW for CPC1
09000d00 00000000
09000d04 fff80000
09000d08 81000012
#Configure alternate space
09000010 00000000
09000014 ff000000
09000018 81000000
#Flush PBL data
09138000 00000000
091380c0 00000000

7
u-boot/board/freescale/t4qds/t4_rcw.cfg Normal file
View File

@@ -0,0 +1,7 @@
#PBL preamble and RCW header
aa55aa55 010e0100
#serdes protocol 1_27_5_11
1607001b 18101b16 00000000 00000000
04362858 30548c00 ec020000 f5000000
00000000 ee0000ee 00000000 000307fc
00000000 00000000 00000000 00000028

13
u-boot/board/freescale/t4qds/t4qds.h Normal file
View File

@@ -0,0 +1,13 @@
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CORENET_DS_H__
#define __CORENET_DS_H__
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
#endif

147
u-boot/board/freescale/t4qds/tlb.c Normal file
View File

@@ -0,0 +1,147 @@
/*
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff00000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
#endif
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_16M, 1),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 11, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif
#ifdef QIXIS_BASE_PHYS
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 17, BOOKE_PAGESZ_4K, 1),
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/*
* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
* fetching ucode and ENV from master
*/
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 19, BOOKE_PAGESZ_2G, 1)
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);