avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/board/freescale/p1_twr/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_P1_TWR
+
+config SYS_BOARD
+	default "p1_twr"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "p1_twr"
+
+endif

u-boot/board/freescale/p1_twr/MAINTAINERS

@@ -0,0 +1,6 @@
+P1_TWR BOARD
+#M:	-
+S:	Maintained
+F:	board/freescale/p1_twr/
+F:	include/configs/p1_twr.h
+F:	configs/TWR-P1025_defconfig

u-boot/board/freescale/p1_twr/Makefile

@@ -0,0 +1,9 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y        += p1_twr.o
+obj-y        += ddr.o
+obj-y        += law.o
+obj-y        += tlb.o

u-boot/board/freescale/p1_twr/ddr.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+	sys_info_t sysinfo;
+	char buf[32];
+	size_t ddr_size;
+	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
+		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+#endif
+		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
+		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
+		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
+		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
+		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
+		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
+		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
+		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+	};
+
+	get_sys_info(&sysinfo);
+	printf("Configuring DDR for %s MT/s data rate\n",
+			strmhz(buf, sysinfo.freq_ddrbus));
+
+	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
+		printf("ERROR setting Local Access Windows for DDR\n");
+		return 0;
+	};
+
+	return ddr_size;
+}

u-boot/board/freescale/p1_twr/law.c

@@ -0,0 +1,16 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_SSD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

u-boot/board/freescale/p1_twr/p1_twr.c

@@ -0,0 +1,289 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
+#include <asm/mp.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <ioports.h>
+#include <asm/fsl_serdes.h>
+#include <netdev.h>
+
+#define SYSCLK_64	64000000
+#define SYSCLK_66	66666666
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
+	unsigned int cpdat_val = 0;
+
+	/* Set-up up pin muxing based on board switch settings */
+	cpdat_val = par_io[1].cpdat;
+
+	/* Check switch setting for SYSCLK select (PB3)  */
+	if (cpdat_val & 0x10000000)
+		return SYSCLK_64;
+	else
+		return SYSCLK_66;
+
+	return 0;
+}
+
+#ifdef CONFIG_QE
+
+#define PCA_IOPORT_I2C_ADDR		0x23
+#define PCA_IOPORT_OUTPUT_CMD		0x2
+#define PCA_IOPORT_CFG_CMD		0x6
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+
+#ifdef CONFIG_TWR_P1025
+	/* GPIO */
+	{1,  0, 1, 0, 0},
+	{1,  18, 1, 0, 0},
+
+	/* GPIO for switch options */
+	{1,  2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
+	{1,  3, 2, 0, 0}, /* SYS_CLK_SELECT */
+	{1,  29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
+	{1,  30, 2, 0, 0}, /* ETH_TDM_SEL */
+
+	/* QE_MUX_MDC */
+	{1,  19, 1, 0, 1}, /* QE_MUX_MDC */
+
+	/* QE_MUX_MDIO */
+	{1,  20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+	/* UCC_1_MII */
+	{0, 23, 2, 0, 2}, /* CLK12 */
+	{0, 24, 2, 0, 1}, /* CLK9 */
+	{0,  7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+	{0,  9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+	{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+	{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+	{0,  6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+	{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+	{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+	{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+	{0,  5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+	{0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+	{0,  4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
+	{0,  8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
+	{0, 17, 2, 0, 2}, /* ENET1_CRS */
+	{0, 16, 2, 0, 2}, /* ENET1_COL */
+
+	/* UCC_5_RMII */
+	{1, 11, 2, 0, 1}, /* CLK13 */
+	{1, 7,  1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+	{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+	{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+	{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+	{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
+	{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
+	{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
+
+	/* TDMA - clock option is configured in OS based on board setting */
+	{1, 23, 2, 0, 2}, /* TDMA_TXD */
+	{1, 25, 2, 0, 2}, /* TDMA_RXD */
+	{1, 26, 1, 0, 2}, /* TDMA_SYNC */
+#endif
+
+	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->pmuxcr,
+			(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+
+	/* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u8 boot_status;
+
+	printf("Board: %s\n", CONFIG_BOARDNAME);
+
+	boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
+	puts("rom_loc: ");
+	if (boot_status == PORBMSR_ROMLOC_NOR)
+		puts("nor flash");
+	else if (boot_status == PORBMSR_ROMLOC_SDHC)
+		puts("sd");
+	else
+		puts("unknown");
+	puts("\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,           /* perms, wimge */
+		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	ccsr_gur_t *gur __attribute__((unused)) =
+		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		printf("eTSEC2 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+
+#if defined(CONFIG_UEC_ETH)
+	/* QE0 and QE3 need to be exposed for UCC1
+	 * and UCC5 Eth mode (in PMUXCR register).
+	 * Currently QE/LBC muxed pins assumed to be
+	 * LBC for U-Boot and PMUXCR updated by OS if required */
+
+	uec_standard_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_QE)
+static void fdt_board_fixup_qe_pins(void *blob)
+{
+	int node;
+
+	if (!hwconfig("qe")) {
+		/* For QE and eLBC pins multiplexing,
+		 * When don't use QE function, remove
+		 * qe node from dt blob.
+		 */
+		node = fdt_path_offset(blob, "/qe");
+		if (node >= 0)
+			fdt_del_node(blob, node);
+	} else {
+		/* For TWR Peripheral Modules - TWR-SER2
+		 * board only can support Signal Port MII,
+		 * so delete one UEC node when use MII port.
+		 */
+		if (hwconfig("mii"))
+			node = fdt_path_offset(blob, "/qe/ucc@2400");
+		else
+			node = fdt_path_offset(blob, "/qe/ucc@2000");
+		if (node >= 0)
+			fdt_del_node(blob, node);
+	}
+
+	return;
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_QE
+	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
+			sizeof("okay"), 0);
+#endif
+#if defined(CONFIG_TWR_P1025)
+	fdt_board_fixup_qe_pins(blob);
+#endif
+	fdt_fixup_dr_usb(blob, bd);
+
+	return 0;
+}
+#endif

u-boot/board/freescale/p1_twr/tlb.c

@@ -0,0 +1,76 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+			0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	/* W**G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+			0, 2, BOOKE_PAGESZ_64M, 1),
+
+	/* W**G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_PCI
+	/* *I*G* - PCI memory 1.5G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O effective: 192K  */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#endif
+
+#ifdef CONFIG_SYS_RAMBOOT
+	/* *I*G - eSDHC boot */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);