avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/board/freescale/c29xpcie/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_C29XPCIE
+
+config SYS_BOARD
+	default "c29xpcie"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "C29XPCIE"
+
+endif

u-boot/board/freescale/c29xpcie/MAINTAINERS

@@ -0,0 +1,10 @@
+C29XPCIE BOARD
+M:	Po Liu <po.liu@freescale.com>
+S:	Maintained
+F:	board/freescale/c29xpcie/
+F:	include/configs/C29XPCIE.h
+F:	configs/C29XPCIE_defconfig
+F:	configs/C29XPCIE_NAND_defconfig
+F:	configs/C29XPCIE_SPIFLASH_defconfig
+F:	configs/C29XPCIE_NOR_SECBOOT_defconfig
+F:	configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig

u-boot/board/freescale/c29xpcie/Makefile

@@ -0,0 +1,25 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+MINIMAL=
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y	+= spl_minimal.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+endif
+obj-y	+= c29xpcie.o
+obj-y	+= cpld.o
+obj-y	+= ddr.o
+endif
+
+obj-y	+= law.o
+obj-y	+= tlb.o

u-boot/board/freescale/c29xpcie/README

@@ -0,0 +1,100 @@
+Overview
+=========
+C29XPCIE board is a series of Freescale PCIe add-in cards to perform
+as public key crypto accelerator or secure key management module.
+It includes C293PCIE board, C293PCIE board and C291PCIE board.
+The Freescale C29x family is a high performance crypto co-processor.
+It combines a single e500v2 core with necessary SEC engines.
+(maximum core frequency 1000/1200 MHz).
+
+The C29xPCIE board features are as follows:
+Memory subsystem:
+	- 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+	- 64 Mbyte NOR flash single-chip memory
+	- 4 Gbyte NAND flash memory
+	- 1 Mbit AT24C1024 I2C EEPROM
+	- 16 Mbyte SPI memory
+
+Interfaces:
+	- 10/100/1000 BaseT Ethernet ports:
+		- eTSEC1, RGMII: one 10/100/1000 port
+		- eTSEC2, RGMII: one 10/100/1000 port
+	- DUART interface:
+		- DUART interface: supports two UARTs up to 115200 bps for
+		   console display
+
+Board connectors:
+	- Mini-ITX power supply connector
+	- JTAG/COP for debugging
+
+Physical Memory Map on C29xPCIE
+===============================
+Address Start   Address End   Memory type
+0x0_0000_0000 - 0x0_1fff_ffff   512MB DDR
+0xc_0000_0000 - 0xc_8fff_ffff   256MB PCIE memory
+0xf_ec00_0000 - 0xf_efff_ffff   64MB NOR flash
+0xf_ffb0_0000 - 0xf_ffb7_ffff   512KB SRAM
+0xf_ffc0_0000 - 0xf_ffc0_ffff   64KB PCIE IO
+0xf_ffdf_0000 - 0xf_ffdf_0fff   4KB CPLD
+0xf_ffe0_0000 - 0xf_ffef_ffff   1MB CCSR
+
+Serial Port Configuration on C29xPCIE
+=====================================
+Configure the serial port of the attached computer with the following values:
+	-Data rate: 115200 bps
+	-Number of data bits: 8
+	-Parity: None
+	-Number of Stop bits: 1
+	-Flow Control: Hardware/None
+
+Settings of DIP-switch
+======================
+  SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
+  SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
+Note: 1 stands for 'off', 0 stands for 'on'
+
+Build and program U-Boot to NOR flash
+==================================
+1. Build u-boot.bin image example:
+	export ARCH=powerpc
+	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+	make C293PCIE
+
+2. Program u-boot.bin into NOR flash
+	=> tftp $loadaddr $uboot
+	=> protect off eff40000 +$filesize
+	=> erase eff40000 +$filesize
+	=> cp.b $loadaddr eff40000 $filesize
+
+3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
+
+Alternate NOR bank
+==================
+There are four banks in C29XPCIE board, example to change bank booting:
+1. Program u-boot.bin into alternate NOR bank
+	=> tftp $loadaddr $uboot
+	=> protect off e9f40000 +$filesize
+	=> erase e9f40000 +$filesize
+	=> cp.b $loadaddr e9f40000 $filesize
+
+2. Switch to alternate NOR bank
+	=> cpld_cmd reset altbank [bank]
+	- [bank] bank value select 1-4
+	- bank 1 on the flash 0x0000000~0x0ffffff
+	- bank 2 on the flash 0x1000000~0x1ffffff
+	- bank 3 on the flash 0x2000000~0x2ffffff
+	- bank 4 on the flash 0x3000000~0x3ffffff
+	or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
+
+Build and program U-Boot to SPI flash
+==================================
+1. Build u-boot-spi.bin image
+	make C29xPCIE_SPIFLASH_config; make
+	Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
+
+2. Program u-boot-spi.bin into SPI flash
+	=> tftp $loadaddr $uboot-spi
+	=> sf erase 0 100000
+	=> sf write $loadaddr 0 $filesize
+
+3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.

u-boot/board/freescale/c29xpcie/c29xpcie.c

@@ -0,0 +1,156 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <pci.h>
+#include <fsl_ifc.h>
+#include <asm/fsl_pci.h>
+
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	struct cpu_type *cpu = gd->arch.cpu;
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	printf("Board: %sPCIe, ", cpu->name);
+	printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+
+	/* Clock configuration to access CPLD using IFC(GPCM) */
+	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 1;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_64M, 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif /* ifdef CONFIG_PCI */
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[2];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	/* Register 1G MDIO bus */
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+#endif
+
+	return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_del_sec(void *blob, int offset)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
+			CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
+			+ offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
+		fdt_del_node(blob, nodeoff);
+		offset++;
+	}
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+	struct cpu_type *cpu;
+
+	cpu = gd->arch.cpu;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+#if defined(CONFIG_PCI)
+	FT_FSL_PCI_SETUP;
+#endif
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+	if (cpu->soc_ver == SVR_C291)
+		fdt_del_sec(blob, 1);
+	else if (cpu->soc_ver == SVR_C292)
+		fdt_del_sec(blob, 2);
+
+	return 0;
+}
+#endif

u-boot/board/freescale/c29xpcie/cpld.c

@@ -0,0 +1,133 @@
+/**
+ * Copyright 2013 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ *         Po Liu <Po.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
+ * CPLD register map
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(u8 banksel)
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	u8 reg11;
+
+	reg11 = in_8(&cpld_data->flhcsr);
+
+	switch (banksel) {
+	case 1:
+		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
+		break;
+	case 2:
+		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
+		break;
+	case 3:
+		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
+		break;
+	case 4:
+		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
+		break;
+	default:
+		printf("Invalid value! [1-4]\n");
+		return;
+	}
+
+	udelay(100);
+	do_reset(NULL, 0, 0, NULL);
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+	cpld_set_altbank(4);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	printf("chipid1		= 0x%02x\n", in_8(&cpld_data->chipid1));
+	printf("chipid2		= 0x%02x\n", in_8(&cpld_data->chipid2));
+	printf("hwver		= 0x%02x\n", in_8(&cpld_data->hwver));
+	printf("cpldver		= 0x%02x\n", in_8(&cpld_data->cpldver));
+	printf("rstcon		= 0x%02x\n", in_8(&cpld_data->rstcon));
+	printf("flhcsr		= 0x%02x\n", in_8(&cpld_data->flhcsr));
+	printf("wdcsr		= 0x%02x\n", in_8(&cpld_data->wdcsr));
+	printf("wdkick		= 0x%02x\n", in_8(&cpld_data->wdkick));
+	printf("fancsr		= 0x%02x\n", in_8(&cpld_data->fancsr));
+	printf("ledcsr		= 0x%02x\n", in_8(&cpld_data->ledcsr));
+	printf("misc		= 0x%02x\n", in_8(&cpld_data->misccsr));
+	printf("bootor		= 0x%02x\n", in_8(&cpld_data->bootor));
+	printf("bootcfg1	= 0x%02x\n", in_8(&cpld_data->bootcfg1));
+	printf("bootcfg2	= 0x%02x\n", in_8(&cpld_data->bootcfg2));
+	printf("bootcfg3	= 0x%02x\n", in_8(&cpld_data->bootcfg3));
+	printf("bootcfg4	= 0x%02x\n", in_8(&cpld_data->bootcfg4));
+	putc('\n');
+}
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rc = 0;
+	unsigned char value;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (!strcmp(argv[2], "altbank") && argv[3]) {
+			value = (u8)simple_strtoul(argv[3], NULL, 16);
+			cpld_set_altbank(value);
+		} else if (!argv[2])
+			cpld_set_defbank();
+		else
+			cmd_usage(cmdtp);
+#ifdef DEBUG
+	} else if (strcmp(argv[1], "dump") == 0) {
+		cpld_dump_regs();
+#endif
+	} else
+		rc = cmd_usage(cmdtp);
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
+	"Reset the board using the CPLD sequencer",
+	"reset - hard reset to default bank 4\n"
+	"cpld_cmd reset altbank [bank]- reset to alternate bank\n"
+	"	- [bank] bank value select 1-4\n"
+	"	- bank 1 on the flash 0x0000000~0x0ffffff\n"
+	"	- bank 2 on the flash 0x1000000~0x1ffffff\n"
+	"	- bank 3 on the flash 0x2000000~0x2ffffff\n"
+	"	- bank 4 on the flash 0x3000000~0x3ffffff\n"
+#ifdef DEBUG
+	"cpld_cmd dump - display the CPLD registers\n"
+#endif
+	);
+#endif

u-boot/board/freescale/c29xpcie/cpld.h

@@ -0,0 +1,40 @@
+/**
+ * Copyright 2013 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.Hu@freescale.com>
+ *         Po Liu <Po.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+struct cpld_data {
+	u8 chipid1;	/* 0x0 - CPLD Chip ID1 Register */
+	u8 chipid2;	/* 0x1 - CPLD Chip ID2 Register */
+	u8 hwver;	/* 0x2 - Hardware Version Register */
+	u8 cpldver;	/* 0x3 - Software Version Register */
+	u8 res[12];
+	u8 rstcon;	/* 0x10 - Reset control register */
+	u8 flhcsr;	/* 0x11 - Flash control and status Register */
+	u8 wdcsr;	/* 0x12 - Watchdog control and status Register */
+	u8 wdkick;	/* 0x13 - Watchdog kick Register */
+	u8 fancsr;	/* 0x14 - Fan control and status Register */
+	u8 ledcsr;	/* 0x15 - LED control and status Register */
+	u8 misccsr;	/* 0x16 - Misc control and status Register */
+	u8 bootor;	/* 0x17 - Boot configure override Register */
+	u8 bootcfg1;	/* 0x18 - Boot configure 1 Register */
+	u8 bootcfg2;	/* 0x19 - Boot configure 2 Register */
+	u8 bootcfg3;	/* 0x1a - Boot configure 3 Register */
+	u8 bootcfg4;	/* 0x1b - Boot configure 4 Register */
+};
+
+#define CPLD_BANKSEL_EN		0x02
+#define CPLD_BANKSEL_MASK	0x3f
+#define CPLD_SELECT_BANK1	0xc0
+#define CPLD_SELECT_BANK2	0x80
+#define CPLD_SELECT_BANK3	0x40
+#define CPLD_SELECT_BANK4	0x00

u-boot/board/freescale/c29xpcie/ddr.c

@@ -0,0 +1,107 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+#include "cpld.h"
+
+#define C29XPCIE_HARDWARE_REVA	0x40
+/*
+ * Micron MT41J128M16HA-15E
+ * */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 536870912u,
+	.capacity = 536870912u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 14,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 2,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 1650,
+	.caslat_x = 0x7e << 4,	/* 5,6,7,8,9,10 */
+	.taa_ps = 14050,
+	.twr_ps = 15000,
+	.trcd_ps = 13500,
+	.trrd_ps = 75000,
+	.trp_ps = 13500,
+	.tras_ps = 40000,
+	.trc_ps = 49500,
+	.trfc_ps = 160000,
+	.twtr_ps = 75000,
+	.trtp_ps = 75000,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 30000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR on board";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	int i;
+
+	popts->clk_adjust = 4;
+	popts->cpo_override = 0x1f;
+	popts->write_data_delay = 4;
+	popts->half_strength_driver_enable = 1;
+	popts->bstopre = 0x3cf;
+	popts->quad_rank_present = 1;
+	popts->rtt_override = 1;
+	popts->rtt_override_value = 1;
+	popts->dynamic_power = 1;
+	/* Write leveling override */
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x4;
+	popts->trwt_override = 1;
+	popts->trwt = 0;
+
+	if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
+		popts->ecc_mode = 0;
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+	}
+}
+
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+	int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
+				sizeof(generic_spd_eeprom_t));
+
+	if (ret) {
+		printf("DDR: failed to read SPD from address %u\n",
+				i2c_address);
+		memset(spd, 0, sizeof(generic_spd_eeprom_t));
+	}
+}

u-boot/board/freescale/c29xpcie/law.c

@@ -0,0 +1,19 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
+					LAW_TRGT_IF_PLATFORM_SRAM),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

u-boot/board/freescale/c29xpcie/spl.c

@@ -0,0 +1,79 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <console.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+
+	/* relocate environment function pointers etc. */
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	i2c_init_all();
+
+	gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("TPL\n");
+#else
+	puts("SPL\n");
+#endif
+
+	nand_boot();
+}

u-boot/board/freescale/c29xpcie/spl_minimal.c

@@ -0,0 +1,63 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot...\n");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	puts("SPL\n");
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}

u-boot/board/freescale/c29xpcie/tlb.c

@@ -0,0 +1,85 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+			0, 1, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 2, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 3, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 4, BOOKE_PAGESZ_64K, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_64K, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
+			CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 6, BOOKE_PAGESZ_256K, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
+			CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 7, BOOKE_PAGESZ_256K, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+		(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
+			CONFIG_SYS_DDR_SDRAM_BASE,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 8, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+			CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 9, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);