avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
15
u-boot/board/denx/m53evk/Kconfig
Normal file
15
u-boot/board/denx/m53evk/Kconfig
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@@ -0,0 +1,15 @@
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if TARGET_M53EVK
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config SYS_BOARD
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default "m53evk"
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config SYS_VENDOR
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default "denx"
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config SYS_SOC
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default "mx5"
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config SYS_CONFIG_NAME
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default "m53evk"
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endif
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6
u-boot/board/denx/m53evk/MAINTAINERS
Normal file
6
u-boot/board/denx/m53evk/MAINTAINERS
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@@ -0,0 +1,6 @@
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M53EVK BOARD
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M: Marek Vasut <marek.vasut@gmail.com>
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S: Maintained
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F: board/denx/m53evk/
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F: include/configs/m53evk.h
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F: configs/m53evk_defconfig
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8
u-boot/board/denx/m53evk/Makefile
Normal file
8
u-boot/board/denx/m53evk/Makefile
Normal file
@@ -0,0 +1,8 @@
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#
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# DENX M53EVK
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# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := m53evk.o
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92
u-boot/board/denx/m53evk/imximage.cfg
Normal file
92
u-boot/board/denx/m53evk/imximage.cfg
Normal file
@@ -0,0 +1,92 @@
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/*
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* DENX M53 DRAM init values
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* Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#include <asm/imx-common/imximage.cfg>
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/* image version */
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IMAGE_VERSION 2
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/* Boot Offset 0x400, valid for both SD and NAND boot. */
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BOOT_OFFSET FLASH_OFFSET_STANDARD
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
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DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
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DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
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DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
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DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
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DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
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DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
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DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
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DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
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DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
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DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */
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DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */
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DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
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DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */
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DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */
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DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
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DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */
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DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */
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DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */
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DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */
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DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */
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DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
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DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
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DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
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/* ESDCTL */
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DATA 4 0x63fd9088 0x32383535
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DATA 4 0x63fd9090 0x40383538
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DATA 4 0x63fd907c 0x0136014d
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DATA 4 0x63fd9080 0x01510141
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DATA 4 0x63fd9018 0x00011740
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DATA 4 0x63fd9000 0xc3190000
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DATA 4 0x63fd900c 0x555952e3
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DATA 4 0x63fd9010 0xb68e8b63
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DATA 4 0x63fd9014 0x01ff00db
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DATA 4 0x63fd902c 0x000026d2
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DATA 4 0x63fd9030 0x009f0e21
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DATA 4 0x63fd9008 0x12273030
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DATA 4 0x63fd9004 0x0002002d
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DATA 4 0x63fd901c 0x00008032
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DATA 4 0x63fd901c 0x00008033
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DATA 4 0x63fd901c 0x00028031
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DATA 4 0x63fd901c 0x092080b0
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DATA 4 0x63fd901c 0x04008040
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DATA 4 0x63fd901c 0x0000803a
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DATA 4 0x63fd901c 0x0000803b
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DATA 4 0x63fd901c 0x00028039
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DATA 4 0x63fd901c 0x09208138
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DATA 4 0x63fd901c 0x04008048
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DATA 4 0x63fd9020 0x00001800
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DATA 4 0x63fd9040 0x04b80003
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DATA 4 0x63fd9058 0x00022227
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DATA 4 0x63fd901c 0x00000000
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402
u-boot/board/denx/m53evk/m53evk.c
Normal file
402
u-boot/board/denx/m53evk/m53evk.c
Normal file
@@ -0,0 +1,402 @@
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/*
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* DENX M53 module
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*
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* Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux-mx53.h>
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#include <asm/imx-common/mx5_video.h>
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#include <asm/spl.h>
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#include <asm/errno.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <spl.h>
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#include <fsl_esdhc.h>
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#include <asm/gpio.h>
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#include <usb/ehci-ci.h>
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#include <linux/fb.h>
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#include <ipu_pixfmt.h>
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/* Special MXCFB sync flags are here. */
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#include "../drivers/video/mxcfb.h"
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DECLARE_GLOBAL_DATA_PTR;
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static uint32_t mx53_dram_size[2];
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phys_size_t get_effective_memsize(void)
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{
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/*
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* WARNING: We must override get_effective_memsize() function here
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* to report only the size of the first DRAM bank. This is to make
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* U-Boot relocator place U-Boot into valid memory, that is, at the
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* end of the first DRAM bank. If we did not override this function
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* like so, U-Boot would be placed at the address of the first DRAM
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* bank + total DRAM size - sizeof(uboot), which in the setup where
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* each DRAM bank contains 512MiB of DRAM would result in placing
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* U-Boot into invalid memory area close to the end of the first
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* DRAM bank.
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*/
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return mx53_dram_size[0];
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}
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int dram_init(void)
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{
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mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
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mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
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gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = mx53_dram_size[0];
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = mx53_dram_size[1];
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}
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static void setup_iomux_uart(void)
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{
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static const iomux_v3_cfg_t uart_pads[] = {
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MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
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MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
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};
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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#ifdef CONFIG_USB_EHCI_MX5
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int board_ehci_hcd_init(int port)
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{
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if (port == 0) {
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/* USB OTG PWRON */
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
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gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
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/* USB OTG Over Current */
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imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
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} else if (port == 1) {
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/* USB Host PWRON */
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
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gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
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/* USB Host Over Current */
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imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
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}
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return 0;
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}
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#endif
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static void setup_iomux_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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/* MDIO pads */
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NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
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PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
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NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
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/* FEC 0 pads */
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NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
|
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|
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/* FEC 1 pads */
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NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
|
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
|
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PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
|
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PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
struct fsl_esdhc_cfg esdhc_cfg = {
|
||||
MMC_SDHC1_BASE_ADDR,
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
|
||||
gpio_direction_input(IMX_GPIO_NR(1, 1));
|
||||
|
||||
return !gpio_get_value(IMX_GPIO_NR(1, 1));
|
||||
}
|
||||
|
||||
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_PUS_100K_UP)
|
||||
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
|
||||
PAD_CTL_DSE_HIGH)
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
static const iomux_v3_cfg_t sd1_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
|
||||
MX53_PAD_EIM_DA13__GPIO3_13,
|
||||
|
||||
MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
|
||||
};
|
||||
|
||||
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
|
||||
|
||||
/* GPIO 2_31 is SD power */
|
||||
gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
|
||||
|
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
static struct fb_videomode const ampire_wvga = {
|
||||
.name = "Ampire",
|
||||
.refresh = 60,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 29851, /* picosecond (33.5 MHz) */
|
||||
.left_margin = 89,
|
||||
.right_margin = 164,
|
||||
.upper_margin = 23,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 10,
|
||||
.vsync_len = 10,
|
||||
.sync = FB_SYNC_CLK_LAT_FALL,
|
||||
};
|
||||
|
||||
int board_video_skip(void)
|
||||
{
|
||||
int ret;
|
||||
ret = ipuv3_fb_init(&ire_wvga, 1, IPU_PIX_FMT_RGB666);
|
||||
if (ret)
|
||||
printf("Ampire LCD cannot be configured: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
|
||||
|
||||
static void setup_iomux_i2c(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t i2c_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
|
||||
}
|
||||
|
||||
static void setup_iomux_video(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t lcd_pads[] = {
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
|
||||
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
|
||||
MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
|
||||
MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
|
||||
MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
|
||||
MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
|
||||
MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
|
||||
MX53_PAD_EIM_A25__IPU_DI1_PIN12,
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
}
|
||||
|
||||
static void setup_iomux_nand(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t nand_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
|
||||
PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
|
||||
PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
|
||||
PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
|
||||
PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
|
||||
PAD_CTL_PUS_100K_UP),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
|
||||
PAD_CTL_PUS_100K_UP),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
|
||||
PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
|
||||
}
|
||||
|
||||
static void m53_set_clock(void)
|
||||
{
|
||||
int ret;
|
||||
const uint32_t ref_clk = MXC_HCLK;
|
||||
const uint32_t dramclk = 400;
|
||||
uint32_t cpuclk;
|
||||
|
||||
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
|
||||
gpio_direction_input(IMX_GPIO_NR(4, 0));
|
||||
|
||||
/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
|
||||
cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
|
||||
|
||||
ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
|
||||
if (ret)
|
||||
printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
|
||||
|
||||
ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
|
||||
if (ret) {
|
||||
printf("CPU: Switch peripheral clock to %dMHz failed\n",
|
||||
dramclk);
|
||||
}
|
||||
|
||||
ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
|
||||
if (ret)
|
||||
printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
|
||||
}
|
||||
|
||||
static void m53_set_nand(void)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
/* NAND flash is muxed on ATA pins */
|
||||
setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
|
||||
|
||||
/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
|
||||
for (i = 0x4; i < 0x94; i += 0x18) {
|
||||
clrbits_le32(WEIM_BASE_ADDR + i,
|
||||
WEIM_GCR2_MUX16_BYP_GRANT_MASK);
|
||||
}
|
||||
|
||||
mxc_set_clock(0, 33, MXC_NFC_CLK);
|
||||
enable_nfc_clk(1);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
setup_iomux_fec();
|
||||
setup_iomux_i2c();
|
||||
setup_iomux_nand();
|
||||
setup_iomux_video();
|
||||
|
||||
m53_set_clock();
|
||||
|
||||
mxc_set_sata_internal_clock();
|
||||
|
||||
/* NAND clock @ 33MHz */
|
||||
m53_set_nand();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: DENX M53EVK\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* NAND SPL
|
||||
*/
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void spl_board_init(void)
|
||||
{
|
||||
setup_iomux_nand();
|
||||
m53_set_clock();
|
||||
m53_set_nand();
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
return BOOT_DEVICE_NAND;
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user