avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
15
u-boot/board/denx/m28evk/Kconfig
Normal file
15
u-boot/board/denx/m28evk/Kconfig
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@@ -0,0 +1,15 @@
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if TARGET_M28EVK
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config SYS_BOARD
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default "m28evk"
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config SYS_VENDOR
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default "denx"
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config SYS_SOC
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default "mxs"
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config SYS_CONFIG_NAME
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default "m28evk"
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endif
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6
u-boot/board/denx/m28evk/MAINTAINERS
Normal file
6
u-boot/board/denx/m28evk/MAINTAINERS
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@@ -0,0 +1,6 @@
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M28EVK BOARD
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M: Marek Vasut <marek.vasut@gmail.com>
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S: Maintained
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F: board/denx/m28evk/
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F: include/configs/m28evk.h
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F: configs/m28evk_defconfig
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12
u-boot/board/denx/m28evk/Makefile
Normal file
12
u-boot/board/denx/m28evk/Makefile
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@@ -0,0 +1,12 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifndef CONFIG_SPL_BUILD
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obj-y := m28evk.o
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else
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obj-y := spl_boot.o
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endif
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13
u-boot/board/denx/m28evk/README
Normal file
13
u-boot/board/denx/m28evk/README
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@@ -0,0 +1,13 @@
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DENX M28EVK
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===========
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Files of the M28/M28EVK port
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----------------------------
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arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28
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arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28
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board/denx/m28evk/ - M28EVK board specific files
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include/configs/m28evk.h - M28EVK configuration file
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Follow the instructions from doc/README.mxs to generate a bootable SD card or to
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boot from NAND flash.
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173
u-boot/board/denx/m28evk/m28evk.c
Normal file
173
u-boot/board/denx/m28evk/m28evk.c
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@@ -0,0 +1,173 @@
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/*
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* DENX M28 module
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/mii.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Functions
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*/
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int board_early_init_f(void)
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{
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/* IO0 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP0 clock at 96MHz */
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mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
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/* SSP2 clock at 160MHz */
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mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
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#ifdef CONFIG_CMD_USB
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mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
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mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
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MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
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gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
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mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 |
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MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
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gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0);
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#endif
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return 0;
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}
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int board_init(void)
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{
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/* Adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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return mxs_dram_init();
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}
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#ifdef CONFIG_CMD_MMC
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static int m28_mmc_wp(int id)
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{
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if (id != 0) {
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printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
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return 1;
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}
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return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
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}
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int board_mmc_init(bd_t *bis)
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{
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/* Configure WP as input. */
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gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
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/* Turn on the power to the card. */
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gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
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return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL);
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}
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#endif
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#ifdef CONFIG_CMD_NET
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#define MII_OPMODE_STRAP_OVERRIDE 0x16
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#define MII_PHY_CTRL1 0x1e
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#define MII_PHY_CTRL2 0x1f
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int fecmxc_mii_postcall(int phy)
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{
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#if defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10)
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/* KZ8031 PHY on old boards. */
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const uint32_t freq = 0x0080;
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#else
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/* KZ8021 PHY on new boards. */
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const uint32_t freq = 0x0000;
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#endif
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miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
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miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
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if (phy == 3)
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miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct eth_device *dev;
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int ret;
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ret = cpu_eth_init(bis);
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if (ret)
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return ret;
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clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
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CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
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CLKCTRL_ENET_TIME_SEL_RMII_CLK);
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#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
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/* Reset the new PHY */
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gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
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udelay(10000);
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gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
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udelay(10000);
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#endif
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ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
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if (ret) {
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printf("FEC MXS: Unable to init FEC0\n");
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return ret;
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}
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ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
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if (ret) {
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printf("FEC MXS: Unable to init FEC1\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC0");
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if (!dev) {
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printf("FEC MXS: Unable to get FEC0 device entry\n");
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return -EINVAL;
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}
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ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
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if (ret) {
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printf("FEC MXS: Unable to register FEC0 mii postcall\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC1");
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if (!dev) {
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printf("FEC MXS: Unable to get FEC1 device entry\n");
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return -EINVAL;
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}
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ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
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if (ret) {
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printf("FEC MXS: Unable to register FEC1 mii postcall\n");
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return ret;
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}
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return ret;
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}
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#endif
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206
u-boot/board/denx/m28evk/spl_boot.c
Normal file
206
u-boot/board/denx/m28evk/spl_boot.c
Normal file
@@ -0,0 +1,206 @@
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/*
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* DENX M28 Boot setup
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_GPMI (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
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const iomux_cfg_t iomux_setup[] = {
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/* LED */
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MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
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/* framebuffer */
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MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
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MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
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||||
|
||||
/* UART1 */
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#ifdef CONFIG_DENX_M28_V10
|
||||
MX28_PAD_AUART0_CTS__DUART_RX,
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MX28_PAD_AUART0_RTS__DUART_TX,
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#else
|
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MX28_PAD_PWM0__DUART_RX,
|
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MX28_PAD_PWM1__DUART_TX,
|
||||
#endif
|
||||
MX28_PAD_AUART0_TX__DUART_RTS,
|
||||
MX28_PAD_AUART0_RX__DUART_CTS,
|
||||
|
||||
/* UART2 */
|
||||
MX28_PAD_AUART1_RX__AUART1_RX,
|
||||
MX28_PAD_AUART1_TX__AUART1_TX,
|
||||
MX28_PAD_AUART1_RTS__AUART1_RTS,
|
||||
MX28_PAD_AUART1_CTS__AUART1_CTS,
|
||||
|
||||
/* CAN */
|
||||
MX28_PAD_GPMI_RDY2__CAN0_TX,
|
||||
MX28_PAD_GPMI_RDY3__CAN0_RX,
|
||||
|
||||
/* TSC2007 */
|
||||
MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
|
||||
|
||||
/* MMC0 */
|
||||
MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
|
||||
MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
|
||||
MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
|
||||
MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
|
||||
MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
|
||||
MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
|
||||
MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
|
||||
MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
|
||||
MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
|
||||
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
|
||||
(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
|
||||
MX28_PAD_SSP0_SCK__SSP0_SCK |
|
||||
(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
|
||||
MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 |
|
||||
(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), /* Power */
|
||||
MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP */
|
||||
|
||||
/* GPMI NAND */
|
||||
MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_RDN__GPMI_RDN |
|
||||
(MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
|
||||
MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
|
||||
|
||||
/* FEC Ethernet */
|
||||
MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
|
||||
|
||||
MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
|
||||
#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
|
||||
MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
MX28_PAD_I2C0_SCL__I2C0_SCL,
|
||||
MX28_PAD_I2C0_SDA__I2C0_SDA,
|
||||
|
||||
/* EMI */
|
||||
MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
|
||||
|
||||
MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
|
||||
|
||||
/* SPI2 (for flash) */
|
||||
MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
|
||||
MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
|
||||
MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
|
||||
MX28_PAD_SSP2_SS0__SSP2_D3 |
|
||||
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
|
||||
};
|
||||
|
||||
void board_init_ll(const uint32_t arg, const uint32_t *resptr)
|
||||
{
|
||||
mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
|
||||
}
|
||||
15
u-boot/board/denx/m53evk/Kconfig
Normal file
15
u-boot/board/denx/m53evk/Kconfig
Normal file
@@ -0,0 +1,15 @@
|
||||
if TARGET_M53EVK
|
||||
|
||||
config SYS_BOARD
|
||||
default "m53evk"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "denx"
|
||||
|
||||
config SYS_SOC
|
||||
default "mx5"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "m53evk"
|
||||
|
||||
endif
|
||||
6
u-boot/board/denx/m53evk/MAINTAINERS
Normal file
6
u-boot/board/denx/m53evk/MAINTAINERS
Normal file
@@ -0,0 +1,6 @@
|
||||
M53EVK BOARD
|
||||
M: Marek Vasut <marek.vasut@gmail.com>
|
||||
S: Maintained
|
||||
F: board/denx/m53evk/
|
||||
F: include/configs/m53evk.h
|
||||
F: configs/m53evk_defconfig
|
||||
8
u-boot/board/denx/m53evk/Makefile
Normal file
8
u-boot/board/denx/m53evk/Makefile
Normal file
@@ -0,0 +1,8 @@
|
||||
#
|
||||
# DENX M53EVK
|
||||
# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := m53evk.o
|
||||
92
u-boot/board/denx/m53evk/imximage.cfg
Normal file
92
u-boot/board/denx/m53evk/imximage.cfg
Normal file
@@ -0,0 +1,92 @@
|
||||
/*
|
||||
* DENX M53 DRAM init values
|
||||
* Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
#include <asm/imx-common/imximage.cfg>
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
|
||||
/* Boot Offset 0x400, valid for both SD and NAND boot. */
|
||||
BOOT_OFFSET FLASH_OFFSET_STANDARD
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
|
||||
DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
|
||||
DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
|
||||
DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
|
||||
|
||||
DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
|
||||
DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
|
||||
DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
|
||||
|
||||
DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
|
||||
DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
|
||||
DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
|
||||
|
||||
DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */
|
||||
DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */
|
||||
DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
|
||||
|
||||
DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */
|
||||
DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */
|
||||
DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
|
||||
|
||||
DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */
|
||||
DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */
|
||||
|
||||
DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */
|
||||
DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */
|
||||
DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */
|
||||
DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
|
||||
|
||||
DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
|
||||
DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
|
||||
|
||||
/* ESDCTL */
|
||||
DATA 4 0x63fd9088 0x32383535
|
||||
DATA 4 0x63fd9090 0x40383538
|
||||
DATA 4 0x63fd907c 0x0136014d
|
||||
DATA 4 0x63fd9080 0x01510141
|
||||
|
||||
DATA 4 0x63fd9018 0x00011740
|
||||
DATA 4 0x63fd9000 0xc3190000
|
||||
DATA 4 0x63fd900c 0x555952e3
|
||||
DATA 4 0x63fd9010 0xb68e8b63
|
||||
DATA 4 0x63fd9014 0x01ff00db
|
||||
DATA 4 0x63fd902c 0x000026d2
|
||||
DATA 4 0x63fd9030 0x009f0e21
|
||||
DATA 4 0x63fd9008 0x12273030
|
||||
DATA 4 0x63fd9004 0x0002002d
|
||||
DATA 4 0x63fd901c 0x00008032
|
||||
DATA 4 0x63fd901c 0x00008033
|
||||
DATA 4 0x63fd901c 0x00028031
|
||||
DATA 4 0x63fd901c 0x092080b0
|
||||
DATA 4 0x63fd901c 0x04008040
|
||||
DATA 4 0x63fd901c 0x0000803a
|
||||
DATA 4 0x63fd901c 0x0000803b
|
||||
DATA 4 0x63fd901c 0x00028039
|
||||
DATA 4 0x63fd901c 0x09208138
|
||||
DATA 4 0x63fd901c 0x04008048
|
||||
DATA 4 0x63fd9020 0x00001800
|
||||
DATA 4 0x63fd9040 0x04b80003
|
||||
DATA 4 0x63fd9058 0x00022227
|
||||
DATA 4 0x63fd901c 0x00000000
|
||||
402
u-boot/board/denx/m53evk/m53evk.c
Normal file
402
u-boot/board/denx/m53evk/m53evk.c
Normal file
@@ -0,0 +1,402 @@
|
||||
/*
|
||||
* DENX M53 module
|
||||
*
|
||||
* Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux-mx53.h>
|
||||
#include <asm/imx-common/mx5_video.h>
|
||||
#include <asm/spl.h>
|
||||
#include <asm/errno.h>
|
||||
#include <netdev.h>
|
||||
#include <i2c.h>
|
||||
#include <mmc.h>
|
||||
#include <spl.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <usb/ehci-ci.h>
|
||||
#include <linux/fb.h>
|
||||
#include <ipu_pixfmt.h>
|
||||
|
||||
/* Special MXCFB sync flags are here. */
|
||||
#include "../drivers/video/mxcfb.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static uint32_t mx53_dram_size[2];
|
||||
|
||||
phys_size_t get_effective_memsize(void)
|
||||
{
|
||||
/*
|
||||
* WARNING: We must override get_effective_memsize() function here
|
||||
* to report only the size of the first DRAM bank. This is to make
|
||||
* U-Boot relocator place U-Boot into valid memory, that is, at the
|
||||
* end of the first DRAM bank. If we did not override this function
|
||||
* like so, U-Boot would be placed at the address of the first DRAM
|
||||
* bank + total DRAM size - sizeof(uboot), which in the setup where
|
||||
* each DRAM bank contains 512MiB of DRAM would result in placing
|
||||
* U-Boot into invalid memory area close to the end of the first
|
||||
* DRAM bank.
|
||||
*/
|
||||
return mx53_dram_size[0];
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
|
||||
mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
|
||||
|
||||
gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = mx53_dram_size[0];
|
||||
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = mx53_dram_size[1];
|
||||
}
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t uart_pads[] = {
|
||||
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
|
||||
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX5
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
if (port == 0) {
|
||||
/* USB OTG PWRON */
|
||||
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
|
||||
|
||||
/* USB OTG Over Current */
|
||||
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
|
||||
} else if (port == 1) {
|
||||
/* USB Host PWRON */
|
||||
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
|
||||
|
||||
/* USB Host Over Current */
|
||||
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t fec_pads[] = {
|
||||
/* MDIO pads */
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
|
||||
|
||||
/* FEC 0 pads */
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
|
||||
|
||||
/* FEC 1 pads */
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
struct fsl_esdhc_cfg esdhc_cfg = {
|
||||
MMC_SDHC1_BASE_ADDR,
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
|
||||
gpio_direction_input(IMX_GPIO_NR(1, 1));
|
||||
|
||||
return !gpio_get_value(IMX_GPIO_NR(1, 1));
|
||||
}
|
||||
|
||||
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_PUS_100K_UP)
|
||||
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
|
||||
PAD_CTL_DSE_HIGH)
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
static const iomux_v3_cfg_t sd1_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
|
||||
MX53_PAD_EIM_DA13__GPIO3_13,
|
||||
|
||||
MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
|
||||
};
|
||||
|
||||
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
|
||||
|
||||
/* GPIO 2_31 is SD power */
|
||||
gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
|
||||
|
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
static struct fb_videomode const ampire_wvga = {
|
||||
.name = "Ampire",
|
||||
.refresh = 60,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 29851, /* picosecond (33.5 MHz) */
|
||||
.left_margin = 89,
|
||||
.right_margin = 164,
|
||||
.upper_margin = 23,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 10,
|
||||
.vsync_len = 10,
|
||||
.sync = FB_SYNC_CLK_LAT_FALL,
|
||||
};
|
||||
|
||||
int board_video_skip(void)
|
||||
{
|
||||
int ret;
|
||||
ret = ipuv3_fb_init(&ire_wvga, 1, IPU_PIX_FMT_RGB666);
|
||||
if (ret)
|
||||
printf("Ampire LCD cannot be configured: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
|
||||
|
||||
static void setup_iomux_i2c(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t i2c_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
|
||||
}
|
||||
|
||||
static void setup_iomux_video(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t lcd_pads[] = {
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
|
||||
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
|
||||
MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
|
||||
MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
|
||||
MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
|
||||
MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
|
||||
MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
|
||||
MX53_PAD_EIM_A25__IPU_DI1_PIN12,
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
}
|
||||
|
||||
static void setup_iomux_nand(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t nand_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
|
||||
PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
|
||||
PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
|
||||
PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
|
||||
PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
|
||||
PAD_CTL_PUS_100K_UP),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
|
||||
PAD_CTL_PUS_100K_UP),
|
||||
NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
|
||||
PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
|
||||
}
|
||||
|
||||
static void m53_set_clock(void)
|
||||
{
|
||||
int ret;
|
||||
const uint32_t ref_clk = MXC_HCLK;
|
||||
const uint32_t dramclk = 400;
|
||||
uint32_t cpuclk;
|
||||
|
||||
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
|
||||
gpio_direction_input(IMX_GPIO_NR(4, 0));
|
||||
|
||||
/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
|
||||
cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
|
||||
|
||||
ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
|
||||
if (ret)
|
||||
printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
|
||||
|
||||
ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
|
||||
if (ret) {
|
||||
printf("CPU: Switch peripheral clock to %dMHz failed\n",
|
||||
dramclk);
|
||||
}
|
||||
|
||||
ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
|
||||
if (ret)
|
||||
printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
|
||||
}
|
||||
|
||||
static void m53_set_nand(void)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
/* NAND flash is muxed on ATA pins */
|
||||
setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
|
||||
|
||||
/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
|
||||
for (i = 0x4; i < 0x94; i += 0x18) {
|
||||
clrbits_le32(WEIM_BASE_ADDR + i,
|
||||
WEIM_GCR2_MUX16_BYP_GRANT_MASK);
|
||||
}
|
||||
|
||||
mxc_set_clock(0, 33, MXC_NFC_CLK);
|
||||
enable_nfc_clk(1);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
setup_iomux_fec();
|
||||
setup_iomux_i2c();
|
||||
setup_iomux_nand();
|
||||
setup_iomux_video();
|
||||
|
||||
m53_set_clock();
|
||||
|
||||
mxc_set_sata_internal_clock();
|
||||
|
||||
/* NAND clock @ 33MHz */
|
||||
m53_set_nand();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: DENX M53EVK\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* NAND SPL
|
||||
*/
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void spl_board_init(void)
|
||||
{
|
||||
setup_iomux_nand();
|
||||
m53_set_clock();
|
||||
m53_set_nand();
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
return BOOT_DEVICE_NAND;
|
||||
}
|
||||
#endif
|
||||
12
u-boot/board/denx/ma5d4evk/Kconfig
Normal file
12
u-boot/board/denx/ma5d4evk/Kconfig
Normal file
@@ -0,0 +1,12 @@
|
||||
if TARGET_MA5D4EVK
|
||||
|
||||
config SYS_BOARD
|
||||
default "ma5d4evk"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "denx"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "ma5d4evk"
|
||||
|
||||
endif
|
||||
6
u-boot/board/denx/ma5d4evk/MAINTAINERS
Normal file
6
u-boot/board/denx/ma5d4evk/MAINTAINERS
Normal file
@@ -0,0 +1,6 @@
|
||||
DENX MA5D4EVK BOARD
|
||||
M: Marek Vasut <marek.vasut@gmail.com>
|
||||
S: Maintained
|
||||
F: board/denx/ma5d4evk/
|
||||
F: include/configs/ma5d4evk.h
|
||||
F: configs/ma5d4evk_defconfig
|
||||
7
u-boot/board/denx/ma5d4evk/Makefile
Normal file
7
u-boot/board/denx/ma5d4evk/Makefile
Normal file
@@ -0,0 +1,7 @@
|
||||
#
|
||||
# Copyright (C) 2015 Marek Vasut <marex@denx.de>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += ma5d4evk.o
|
||||
412
u-boot/board/denx/ma5d4evk/ma5d4evk.c
Normal file
412
u-boot/board/denx/ma5d4evk/ma5d4evk.c
Normal file
@@ -0,0 +1,412 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/atmel_mpddrc.h>
|
||||
#include <asm/arch/atmel_usba_udc.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/sama5d3_smc.h>
|
||||
#include <asm/arch/sama5d4.h>
|
||||
#include <atmel_hlcdc.h>
|
||||
#include <atmel_mci.h>
|
||||
#include <lcd.h>
|
||||
#include <mmc.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <spi.h>
|
||||
#include <version.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_ATMEL_SPI
|
||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
||||
{
|
||||
return bus == 0 && cs == 0;
|
||||
}
|
||||
|
||||
void spi_cs_activate(struct spi_slave *slave)
|
||||
{
|
||||
at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
|
||||
}
|
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave)
|
||||
{
|
||||
at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
|
||||
}
|
||||
|
||||
static void ma5d4evk_spi0_hw_init(void)
|
||||
{
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
|
||||
|
||||
at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
|
||||
|
||||
/* Enable clock */
|
||||
at91_periph_clk_enable(ATMEL_ID_SPI0);
|
||||
}
|
||||
#endif /* CONFIG_ATMEL_SPI */
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
static void ma5d4evk_usb_hw_init(void)
|
||||
{
|
||||
at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
|
||||
at91_set_pio_output(AT91_PIO_PORTE, 14, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LCD
|
||||
vidinfo_t panel_info = {
|
||||
.vl_col = 800,
|
||||
.vl_row = 480,
|
||||
.vl_clk = 33500000,
|
||||
.vl_bpix = LCD_BPP,
|
||||
.vl_tft = 1,
|
||||
.vl_hsync_len = 10,
|
||||
.vl_left_margin = 89,
|
||||
.vl_right_margin = 164,
|
||||
.vl_vsync_len = 10,
|
||||
.vl_upper_margin = 23,
|
||||
.vl_lower_margin = 10,
|
||||
.mmio = ATMEL_BASE_LCDC,
|
||||
};
|
||||
|
||||
/* No power up/down pin for the LCD pannel */
|
||||
void lcd_enable(void) { /* Empty! */ }
|
||||
void lcd_disable(void) { /* Empty! */ }
|
||||
|
||||
unsigned int has_lcdc(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void ma5d4evk_lcd_hw_init(void)
|
||||
{
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */
|
||||
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
|
||||
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
|
||||
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
|
||||
|
||||
/* Enable clock */
|
||||
at91_periph_clk_enable(ATMEL_ID_LCDC);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_LCD */
|
||||
|
||||
#ifdef CONFIG_GENERIC_ATMEL_MCI
|
||||
/* On-SoM eMMC */
|
||||
void ma5d4evk_mci0_hw_init(void)
|
||||
{
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */
|
||||
|
||||
/*
|
||||
* As the mci io internal pull down is too strong, so if the io needs
|
||||
* external pull up, the pull up resistor will be very small, if so
|
||||
* the power consumption will increase, so disable the internal pull
|
||||
* down to save the power.
|
||||
*/
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
|
||||
|
||||
/* Enable clock */
|
||||
at91_periph_clk_enable(ATMEL_ID_MCI0);
|
||||
}
|
||||
|
||||
/* On-board MicroSD slot */
|
||||
void ma5d4evk_mci1_hw_init(void)
|
||||
{
|
||||
at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
|
||||
at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
|
||||
at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
|
||||
at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
|
||||
at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
|
||||
at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
|
||||
|
||||
/*
|
||||
* As the mci io internal pull down is too strong, so if the io needs
|
||||
* external pull up, the pull up resistor will be very small, if so
|
||||
* the power consumption will increase, so disable the internal pull
|
||||
* down to save the power.
|
||||
*/
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
|
||||
|
||||
/* Deal with WP pin on the microSD slot. */
|
||||
at91_set_pio_output(AT91_PIO_PORTE, 16, 0);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
|
||||
|
||||
/* Enable clock */
|
||||
at91_periph_clk_enable(ATMEL_ID_MCI1);
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* De-assert reset on On-SoM eMMC */
|
||||
at91_set_pio_output(AT91_PIO_PORTE, 15, 1);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
|
||||
|
||||
ret = atmel_mci_init((void *)ATMEL_BASE_MCI0);
|
||||
if (ret) /* eMMC init failed, skip it. */
|
||||
at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
|
||||
|
||||
/* Enable the power supply to On-board MicroSD */
|
||||
at91_set_pio_output(AT91_PIO_PORTE, 17, 0);
|
||||
|
||||
ret = atmel_mci_init((void *)ATMEL_BASE_MCI1);
|
||||
if (ret) /* uSD init failed, power it down. */
|
||||
at91_set_pio_output(AT91_PIO_PORTE, 17, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_GENERIC_ATMEL_MCI */
|
||||
|
||||
#ifdef CONFIG_MACB
|
||||
void ma5d4evk_macb0_hw_init(void)
|
||||
{
|
||||
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
|
||||
at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
|
||||
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
|
||||
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
|
||||
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
|
||||
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
|
||||
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
|
||||
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
|
||||
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
|
||||
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
|
||||
|
||||
/* Enable clock */
|
||||
at91_periph_clk_enable(ATMEL_ID_GMAC0);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void ma5d4evk_serial_hw_init(void)
|
||||
{
|
||||
/* USART0 */
|
||||
at91_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */
|
||||
at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */
|
||||
at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */
|
||||
at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */
|
||||
at91_periph_clk_enable(ATMEL_ID_USART0);
|
||||
|
||||
/* USART1 */
|
||||
at91_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */
|
||||
at91_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */
|
||||
at91_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */
|
||||
at91_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */
|
||||
at91_periph_clk_enable(ATMEL_ID_USART1);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOA);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOB);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOC);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOD);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOE);
|
||||
|
||||
/* Configure LEDs as OFF */
|
||||
at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
|
||||
at91_set_pio_output(AT91_PIO_PORTD, 29, 0);
|
||||
at91_set_pio_output(AT91_PIO_PORTD, 30, 0);
|
||||
|
||||
/* Reset CAN controllers */
|
||||
at91_set_pio_output(AT91_PIO_PORTB, 21, 0);
|
||||
udelay(100);
|
||||
at91_set_pio_output(AT91_PIO_PORTB, 21, 1);
|
||||
at91_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
|
||||
|
||||
ma5d4evk_serial_hw_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
#ifdef CONFIG_ATMEL_SPI
|
||||
ma5d4evk_spi0_hw_init();
|
||||
#endif
|
||||
#ifdef CONFIG_GENERIC_ATMEL_MCI
|
||||
ma5d4evk_mci0_hw_init();
|
||||
ma5d4evk_mci1_hw_init();
|
||||
#endif
|
||||
#ifdef CONFIG_MACB
|
||||
ma5d4evk_macb0_hw_init();
|
||||
#endif
|
||||
#ifdef CONFIG_LCD
|
||||
ma5d4evk_lcd_hw_init();
|
||||
#endif
|
||||
#ifdef CONFIG_CMD_USB
|
||||
ma5d4evk_usb_hw_init();
|
||||
#endif
|
||||
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
|
||||
at91_udp_hw_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
|
||||
CONFIG_SYS_SDRAM_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
#ifdef CONFIG_MACB
|
||||
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
|
||||
usba_udc_probe(&pdata);
|
||||
#ifdef CONFIG_USB_ETH_RNDIS
|
||||
usb_eth_initialize(bis);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* SPL */
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void spl_board_init(void)
|
||||
{
|
||||
ma5d4evk_spi0_hw_init();
|
||||
}
|
||||
|
||||
static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
|
||||
{
|
||||
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
|
||||
|
||||
ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
|
||||
ATMEL_MPDDRC_CR_NR_ROW_13 |
|
||||
ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
|
||||
ATMEL_MPDDRC_CR_NB_8BANKS |
|
||||
ATMEL_MPDDRC_CR_NDQS_DISABLED |
|
||||
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
|
||||
ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
|
||||
|
||||
ddr2->rtr = 0x2b0;
|
||||
|
||||
ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
|
||||
3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
|
||||
3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
|
||||
10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
|
||||
3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
|
||||
|
||||
ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
|
||||
200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
|
||||
25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
|
||||
23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
|
||||
|
||||
ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
|
||||
3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
|
||||
8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
|
||||
}
|
||||
|
||||
void mem_init(void)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
struct atmel_mpddrc_config ddr2;
|
||||
|
||||
ddr2_conf(&ddr2);
|
||||
|
||||
/* enable MPDDR clock */
|
||||
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
|
||||
writel(AT91_PMC_DDR, &pmc->scer);
|
||||
|
||||
/* DDRAM2 Controller initialize */
|
||||
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
|
||||
}
|
||||
|
||||
void at91_pmc_init(void)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
u32 tmp;
|
||||
|
||||
tmp = AT91_PMC_PLLAR_29 |
|
||||
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
|
||||
AT91_PMC_PLLXR_MUL(87) |
|
||||
AT91_PMC_PLLXR_DIV(1);
|
||||
at91_plla_init(tmp);
|
||||
|
||||
writel(0x0 << 8, &pmc->pllicpr);
|
||||
|
||||
tmp = AT91_PMC_MCKR_H32MXDIV |
|
||||
AT91_PMC_MCKR_PLLADIV_2 |
|
||||
AT91_PMC_MCKR_MDIV_3 |
|
||||
AT91_PMC_MCKR_CSS_PLLA;
|
||||
at91_mck_init(tmp);
|
||||
}
|
||||
#endif
|
||||
5
u-boot/board/denx/mcvevk/MAINTAINERS
Normal file
5
u-boot/board/denx/mcvevk/MAINTAINERS
Normal file
@@ -0,0 +1,5 @@
|
||||
SOCKIT BOARD
|
||||
M: Marek Vasut <marex@denx.de>
|
||||
S: Maintained
|
||||
F: include/configs/socfpga_mcvevk.h
|
||||
F: configs/socfpga_mcvevk_defconfig
|
||||
9
u-boot/board/denx/mcvevk/Makefile
Normal file
9
u-boot/board/denx/mcvevk/Makefile
Normal file
@@ -0,0 +1,9 @@
|
||||
#
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := socfpga.o
|
||||
660
u-boot/board/denx/mcvevk/qts/iocsr_config.h
Normal file
660
u-boot/board/denx/mcvevk/qts/iocsr_config.h
Normal file
@@ -0,0 +1,660 @@
|
||||
/*
|
||||
* Altera SoCFPGA IOCSR configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
|
||||
#define __SOCFPGA_IOCSR_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
|
||||
const unsigned long iocsr_scan_chain0_table[] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0xC0000000,
|
||||
0x0000003F,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x18060000,
|
||||
0x00000060,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x0C0300C0,
|
||||
0x00000000,
|
||||
0x0C000000,
|
||||
0x0000C030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x06018060,
|
||||
0x06018000,
|
||||
0x06000018,
|
||||
0x00006018,
|
||||
0x01806018,
|
||||
0x00001000,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain1_table[] = {
|
||||
0x000C0300,
|
||||
0x300C0000,
|
||||
0x300000C0,
|
||||
0x000000C0,
|
||||
0x000300C0,
|
||||
0x00008000,
|
||||
0x00060180,
|
||||
0x18060000,
|
||||
0x18000000,
|
||||
0x00000060,
|
||||
0x00018060,
|
||||
0x00004000,
|
||||
0x000300C0,
|
||||
0x0C030000,
|
||||
0x0C000000,
|
||||
0x00000030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x00018060,
|
||||
0x06018000,
|
||||
0x01FE0000,
|
||||
0xF8000000,
|
||||
0x00000007,
|
||||
0x00001000,
|
||||
0x0300C030,
|
||||
0x00000000,
|
||||
0x03000000,
|
||||
0x0000000C,
|
||||
0x00000000,
|
||||
0x00000800,
|
||||
0x00006018,
|
||||
0x01806000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001806,
|
||||
0x00000400,
|
||||
0x0000300C,
|
||||
0x00C03000,
|
||||
0x00C00000,
|
||||
0x00000003,
|
||||
0x00000C03,
|
||||
0x00000200,
|
||||
0x00001806,
|
||||
0x00601800,
|
||||
0x80600000,
|
||||
0x80000001,
|
||||
0x00000601,
|
||||
0x00000100,
|
||||
0x00001000,
|
||||
0x00300C00,
|
||||
0xC0300000,
|
||||
0xC0000000,
|
||||
0x00000300,
|
||||
0x00000080,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain2_table[] = {
|
||||
0x300C0300,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0x00000000,
|
||||
0x0C0300C0,
|
||||
0x00008000,
|
||||
0x00060180,
|
||||
0x00000000,
|
||||
0x18000000,
|
||||
0x00018060,
|
||||
0x06018060,
|
||||
0x00004000,
|
||||
0x200300C0,
|
||||
0x0C030000,
|
||||
0x0C000000,
|
||||
0x00000030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x00018060,
|
||||
0x00000000,
|
||||
0x06000000,
|
||||
0x00010018,
|
||||
0x01806018,
|
||||
0x00001000,
|
||||
0x0000C030,
|
||||
0x00000000,
|
||||
0x03000000,
|
||||
0x0000000C,
|
||||
0x00C0300C,
|
||||
0x00000800,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain3_table[] = {
|
||||
0x0C420D80,
|
||||
0x0C3000FF,
|
||||
0x0A804001,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x20430000,
|
||||
0x0C003001,
|
||||
0x00C00481,
|
||||
0x00000000,
|
||||
0x00000021,
|
||||
0x82000004,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x04010000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x90218000,
|
||||
0x86001800,
|
||||
0x00600240,
|
||||
0x80090218,
|
||||
0x00000001,
|
||||
0x40000002,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x4810C000,
|
||||
0x43000C00,
|
||||
0x00300120,
|
||||
0xC004810C,
|
||||
0x12043000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0xC0680A28,
|
||||
0x45034030,
|
||||
0x12481A01,
|
||||
0x80A280D0,
|
||||
0x34030C06,
|
||||
0x01A01450,
|
||||
0x280D0000,
|
||||
0x30C0680A,
|
||||
0x02490340,
|
||||
0xD000001A,
|
||||
0x0680A280,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x18000000,
|
||||
0x01800902,
|
||||
0x00240860,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x0A800001,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x20430000,
|
||||
0x0C003001,
|
||||
0x00C00481,
|
||||
0x00000FF0,
|
||||
0x4810C000,
|
||||
0x80000C00,
|
||||
0x05400000,
|
||||
0x02480000,
|
||||
0x04000000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x90218000,
|
||||
0x86001800,
|
||||
0x00600240,
|
||||
0x80090218,
|
||||
0x24086001,
|
||||
0x40000600,
|
||||
0x02A00040,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x4810C000,
|
||||
0x43000C00,
|
||||
0x00300120,
|
||||
0xC004810C,
|
||||
0x12043000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0xC0680A28,
|
||||
0x49034030,
|
||||
0x12481A02,
|
||||
0x80A280D0,
|
||||
0x34030C06,
|
||||
0x01A00040,
|
||||
0x280D0002,
|
||||
0x30C0680A,
|
||||
0x02490340,
|
||||
0xD00A281A,
|
||||
0x0680A280,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x18000000,
|
||||
0x01800902,
|
||||
0x00240860,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x99300001,
|
||||
0x34343400,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A890,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x01000000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x2043090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA24,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x18864000,
|
||||
0x49247A06,
|
||||
0x9A28A3D7,
|
||||
0xF511451E,
|
||||
0x0356E388,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x05140680,
|
||||
0xD749247A,
|
||||
0x1E9A28A3,
|
||||
0x88F51145,
|
||||
0x00034EE3,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x00000000,
|
||||
0x00000010,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00003FC2,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A890,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040000,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00800000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA24,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00015000,
|
||||
0x0000F200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x86120800,
|
||||
0x00600240,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x18864000,
|
||||
0x49247A06,
|
||||
0xEBCF23D7,
|
||||
0xF611451E,
|
||||
0x034E9248,
|
||||
0x821A038E,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD749247A,
|
||||
0x1E9BCF23,
|
||||
0x88F61145,
|
||||
0x00034EE3,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x00000000,
|
||||
0x00000010,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00000002,
|
||||
0x00820004,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A890,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040000,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00800000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x2043090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010000,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00200000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x18864000,
|
||||
0x49247A06,
|
||||
0x9A28A3D7,
|
||||
0xF431451E,
|
||||
0x034E9248,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD749247A,
|
||||
0x1E9A28A3,
|
||||
0x88F61145,
|
||||
0x000356E3,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x00000000,
|
||||
0x00000010,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00000002,
|
||||
0x00820004,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040000,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00800000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00001000,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00400000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F1690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x08864000,
|
||||
0x49247A02,
|
||||
0xEBCF23DB,
|
||||
0xF431451E,
|
||||
0x0356E388,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD749247A,
|
||||
0x1EEBCF23,
|
||||
0x88F43E79,
|
||||
0x000356A2,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x00000000,
|
||||
0x00000010,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00000002,
|
||||
0x00820004,
|
||||
0x00489800,
|
||||
0x801A1A1A,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x00000004,
|
||||
0x00000200,
|
||||
0x00000004,
|
||||
0x00040000,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x00010000,
|
||||
0x40002080,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x00000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x00000002,
|
||||
0x00020000,
|
||||
0x00000000,
|
||||
0x00000008,
|
||||
0x00000020,
|
||||
0x00008000,
|
||||
0x20001040,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x00000001,
|
||||
0x00010000,
|
||||
0x04000000,
|
||||
0x00FF0000,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x00000800,
|
||||
0xC0000001,
|
||||
0x00041419,
|
||||
0x40000000,
|
||||
0x04000816,
|
||||
0x000D0000,
|
||||
0x00006800,
|
||||
0x00000340,
|
||||
0xD000001A,
|
||||
0x06800000,
|
||||
0x00340000,
|
||||
0x0001A000,
|
||||
0x00000D00,
|
||||
0x40000068,
|
||||
0x1A000003,
|
||||
0x00D00000,
|
||||
0x00068000,
|
||||
0x00003400,
|
||||
0x000001A0,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x80000008,
|
||||
0x0000007F,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0xE0000080,
|
||||
0x0000001F,
|
||||
0x00004000,
|
||||
};
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
|
||||
219
u-boot/board/denx/mcvevk/qts/pinmux_config.h
Normal file
219
u-boot/board/denx/mcvevk/qts/pinmux_config.h
Normal file
@@ -0,0 +1,219 @@
|
||||
/*
|
||||
* Altera SoCFPGA PinMux configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_PINMUX_CONFIG_H__
|
||||
#define __SOCFPGA_PINMUX_CONFIG_H__
|
||||
|
||||
const u8 sys_mgr_init_table[] = {
|
||||
3, /* EMACIO0 */
|
||||
3, /* EMACIO1 */
|
||||
3, /* EMACIO2 */
|
||||
3, /* EMACIO3 */
|
||||
3, /* EMACIO4 */
|
||||
3, /* EMACIO5 */
|
||||
3, /* EMACIO6 */
|
||||
3, /* EMACIO7 */
|
||||
3, /* EMACIO8 */
|
||||
3, /* EMACIO9 */
|
||||
3, /* EMACIO10 */
|
||||
3, /* EMACIO11 */
|
||||
3, /* EMACIO12 */
|
||||
3, /* EMACIO13 */
|
||||
0, /* EMACIO14 */
|
||||
0, /* EMACIO15 */
|
||||
0, /* EMACIO16 */
|
||||
0, /* EMACIO17 */
|
||||
0, /* EMACIO18 */
|
||||
0, /* EMACIO19 */
|
||||
3, /* FLASHIO0 */
|
||||
0, /* FLASHIO1 */
|
||||
3, /* FLASHIO2 */
|
||||
3, /* FLASHIO3 */
|
||||
3, /* FLASHIO4 */
|
||||
3, /* FLASHIO5 */
|
||||
3, /* FLASHIO6 */
|
||||
3, /* FLASHIO7 */
|
||||
0, /* FLASHIO8 */
|
||||
3, /* FLASHIO9 */
|
||||
3, /* FLASHIO10 */
|
||||
3, /* FLASHIO11 */
|
||||
0, /* GENERALIO0 */
|
||||
1, /* GENERALIO1 */
|
||||
1, /* GENERALIO2 */
|
||||
0, /* GENERALIO3 */
|
||||
0, /* GENERALIO4 */
|
||||
1, /* GENERALIO5 */
|
||||
1, /* GENERALIO6 */
|
||||
1, /* GENERALIO7 */
|
||||
1, /* GENERALIO8 */
|
||||
0, /* GENERALIO9 */
|
||||
0, /* GENERALIO10 */
|
||||
0, /* GENERALIO11 */
|
||||
0, /* GENERALIO12 */
|
||||
2, /* GENERALIO13 */
|
||||
2, /* GENERALIO14 */
|
||||
1, /* GENERALIO15 */
|
||||
1, /* GENERALIO16 */
|
||||
1, /* GENERALIO17 */
|
||||
1, /* GENERALIO18 */
|
||||
0, /* GENERALIO19 */
|
||||
0, /* GENERALIO20 */
|
||||
0, /* GENERALIO21 */
|
||||
0, /* GENERALIO22 */
|
||||
0, /* GENERALIO23 */
|
||||
0, /* GENERALIO24 */
|
||||
0, /* GENERALIO25 */
|
||||
0, /* GENERALIO26 */
|
||||
0, /* GENERALIO27 */
|
||||
0, /* GENERALIO28 */
|
||||
0, /* GENERALIO29 */
|
||||
0, /* GENERALIO30 */
|
||||
0, /* GENERALIO31 */
|
||||
0, /* MIXED1IO0 */
|
||||
1, /* MIXED1IO1 */
|
||||
1, /* MIXED1IO2 */
|
||||
1, /* MIXED1IO3 */
|
||||
1, /* MIXED1IO4 */
|
||||
0, /* MIXED1IO5 */
|
||||
0, /* MIXED1IO6 */
|
||||
0, /* MIXED1IO7 */
|
||||
1, /* MIXED1IO8 */
|
||||
1, /* MIXED1IO9 */
|
||||
1, /* MIXED1IO10 */
|
||||
1, /* MIXED1IO11 */
|
||||
0, /* MIXED1IO12 */
|
||||
0, /* MIXED1IO13 */
|
||||
0, /* MIXED1IO14 */
|
||||
1, /* MIXED1IO15 */
|
||||
1, /* MIXED1IO16 */
|
||||
1, /* MIXED1IO17 */
|
||||
1, /* MIXED1IO18 */
|
||||
0, /* MIXED1IO19 */
|
||||
0, /* MIXED1IO20 */
|
||||
0, /* MIXED1IO21 */
|
||||
0, /* MIXED2IO0 */
|
||||
0, /* MIXED2IO1 */
|
||||
0, /* MIXED2IO2 */
|
||||
0, /* MIXED2IO3 */
|
||||
0, /* MIXED2IO4 */
|
||||
0, /* MIXED2IO5 */
|
||||
0, /* MIXED2IO6 */
|
||||
0, /* MIXED2IO7 */
|
||||
0, /* GPLINMUX48 */
|
||||
0, /* GPLINMUX49 */
|
||||
0, /* GPLINMUX50 */
|
||||
0, /* GPLINMUX51 */
|
||||
0, /* GPLINMUX52 */
|
||||
0, /* GPLINMUX53 */
|
||||
0, /* GPLINMUX54 */
|
||||
0, /* GPLINMUX55 */
|
||||
0, /* GPLINMUX56 */
|
||||
0, /* GPLINMUX57 */
|
||||
0, /* GPLINMUX58 */
|
||||
0, /* GPLINMUX59 */
|
||||
0, /* GPLINMUX60 */
|
||||
0, /* GPLINMUX61 */
|
||||
0, /* GPLINMUX62 */
|
||||
0, /* GPLINMUX63 */
|
||||
0, /* GPLINMUX64 */
|
||||
0, /* GPLINMUX65 */
|
||||
0, /* GPLINMUX66 */
|
||||
0, /* GPLINMUX67 */
|
||||
0, /* GPLINMUX68 */
|
||||
0, /* GPLINMUX69 */
|
||||
0, /* GPLINMUX70 */
|
||||
1, /* GPLMUX0 */
|
||||
1, /* GPLMUX1 */
|
||||
1, /* GPLMUX2 */
|
||||
1, /* GPLMUX3 */
|
||||
1, /* GPLMUX4 */
|
||||
1, /* GPLMUX5 */
|
||||
1, /* GPLMUX6 */
|
||||
1, /* GPLMUX7 */
|
||||
1, /* GPLMUX8 */
|
||||
1, /* GPLMUX9 */
|
||||
1, /* GPLMUX10 */
|
||||
1, /* GPLMUX11 */
|
||||
1, /* GPLMUX12 */
|
||||
1, /* GPLMUX13 */
|
||||
1, /* GPLMUX14 */
|
||||
1, /* GPLMUX15 */
|
||||
1, /* GPLMUX16 */
|
||||
1, /* GPLMUX17 */
|
||||
1, /* GPLMUX18 */
|
||||
1, /* GPLMUX19 */
|
||||
1, /* GPLMUX20 */
|
||||
1, /* GPLMUX21 */
|
||||
1, /* GPLMUX22 */
|
||||
1, /* GPLMUX23 */
|
||||
1, /* GPLMUX24 */
|
||||
1, /* GPLMUX25 */
|
||||
1, /* GPLMUX26 */
|
||||
1, /* GPLMUX27 */
|
||||
1, /* GPLMUX28 */
|
||||
1, /* GPLMUX29 */
|
||||
1, /* GPLMUX30 */
|
||||
1, /* GPLMUX31 */
|
||||
1, /* GPLMUX32 */
|
||||
1, /* GPLMUX33 */
|
||||
1, /* GPLMUX34 */
|
||||
1, /* GPLMUX35 */
|
||||
1, /* GPLMUX36 */
|
||||
1, /* GPLMUX37 */
|
||||
1, /* GPLMUX38 */
|
||||
1, /* GPLMUX39 */
|
||||
1, /* GPLMUX40 */
|
||||
1, /* GPLMUX41 */
|
||||
1, /* GPLMUX42 */
|
||||
1, /* GPLMUX43 */
|
||||
1, /* GPLMUX44 */
|
||||
1, /* GPLMUX45 */
|
||||
1, /* GPLMUX46 */
|
||||
1, /* GPLMUX47 */
|
||||
1, /* GPLMUX48 */
|
||||
1, /* GPLMUX49 */
|
||||
1, /* GPLMUX50 */
|
||||
1, /* GPLMUX51 */
|
||||
1, /* GPLMUX52 */
|
||||
1, /* GPLMUX53 */
|
||||
1, /* GPLMUX54 */
|
||||
1, /* GPLMUX55 */
|
||||
1, /* GPLMUX56 */
|
||||
1, /* GPLMUX57 */
|
||||
1, /* GPLMUX58 */
|
||||
1, /* GPLMUX59 */
|
||||
1, /* GPLMUX60 */
|
||||
1, /* GPLMUX61 */
|
||||
1, /* GPLMUX62 */
|
||||
1, /* GPLMUX63 */
|
||||
1, /* GPLMUX64 */
|
||||
1, /* GPLMUX65 */
|
||||
1, /* GPLMUX66 */
|
||||
1, /* GPLMUX67 */
|
||||
1, /* GPLMUX68 */
|
||||
1, /* GPLMUX69 */
|
||||
1, /* GPLMUX70 */
|
||||
0, /* NANDUSEFPGA */
|
||||
0, /* UART0USEFPGA */
|
||||
0, /* RGMII1USEFPGA */
|
||||
0, /* SPIS0USEFPGA */
|
||||
0, /* CAN0USEFPGA */
|
||||
0, /* I2C0USEFPGA */
|
||||
0, /* SDMMCUSEFPGA */
|
||||
0, /* QSPIUSEFPGA */
|
||||
0, /* SPIS1USEFPGA */
|
||||
0, /* RGMII0USEFPGA */
|
||||
1, /* UART1USEFPGA */
|
||||
0, /* CAN1USEFPGA */
|
||||
0, /* USB1USEFPGA */
|
||||
0, /* I2C3USEFPGA */
|
||||
0, /* I2C2USEFPGA */
|
||||
0, /* I2C1USEFPGA */
|
||||
0, /* SPIM1USEFPGA */
|
||||
0, /* USB0USEFPGA */
|
||||
0 /* SPIM0USEFPGA */
|
||||
};
|
||||
#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
|
||||
85
u-boot/board/denx/mcvevk/qts/pll_config.h
Normal file
85
u-boot/board/denx/mcvevk/qts/pll_config.h
Normal file
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Altera SoCFPGA Clock and PLL configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_PLL_CONFIG_H__
|
||||
#define __SOCFPGA_PLL_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
||||
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
|
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
|
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ 3125000
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
||||
|
||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
|
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
|
||||
341
u-boot/board/denx/mcvevk/qts/sdram_config.h
Normal file
341
u-boot/board/denx/mcvevk/qts/sdram_config.h
Normal file
@@ -0,0 +1,341 @@
|
||||
/*
|
||||
* Altera SoCFPGA SDRAM configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_SDRAM_CONFIG_H__
|
||||
#define __SOCFPGA_SDRAM_CONFIG_H__
|
||||
|
||||
/* SDRAM configuration */
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
|
||||
/* Sequencer auto configuration */
|
||||
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
|
||||
#define RW_MGR_ACTIVATE_1 0x0F
|
||||
#define RW_MGR_CLEAR_DQS_ENABLE 0x49
|
||||
#define RW_MGR_GUARANTEED_READ 0x4C
|
||||
#define RW_MGR_GUARANTEED_READ_CONT 0x54
|
||||
#define RW_MGR_GUARANTEED_WRITE 0x18
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
|
||||
#define RW_MGR_IDLE 0x00
|
||||
#define RW_MGR_IDLE_LOOP1 0x7B
|
||||
#define RW_MGR_IDLE_LOOP2 0x7A
|
||||
#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
|
||||
#define RW_MGR_INIT_RESET_1_CKE_0 0x74
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
|
||||
#define RW_MGR_MRS0_DLL_RESET 0x02
|
||||
#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
|
||||
#define RW_MGR_MRS0_USER 0x07
|
||||
#define RW_MGR_MRS0_USER_MIRR 0x0C
|
||||
#define RW_MGR_MRS1 0x03
|
||||
#define RW_MGR_MRS1_MIRR 0x09
|
||||
#define RW_MGR_MRS2 0x04
|
||||
#define RW_MGR_MRS2_MIRR 0x0A
|
||||
#define RW_MGR_MRS3 0x05
|
||||
#define RW_MGR_MRS3_MIRR 0x0B
|
||||
#define RW_MGR_PRECHARGE_ALL 0x12
|
||||
#define RW_MGR_READ_B2B 0x59
|
||||
#define RW_MGR_READ_B2B_WAIT1 0x61
|
||||
#define RW_MGR_READ_B2B_WAIT2 0x6B
|
||||
#define RW_MGR_REFRESH_ALL 0x14
|
||||
#define RW_MGR_RETURN 0x01
|
||||
#define RW_MGR_SGLE_READ 0x7D
|
||||
#define RW_MGR_ZQCL 0x06
|
||||
|
||||
/* Sequencer defines configuration */
|
||||
#define AFI_RATE_RATIO 1
|
||||
#define CALIB_LFIFO_OFFSET 7
|
||||
#define CALIB_VFIFO_OFFSET 5
|
||||
#define ENABLE_SUPER_QUICK_CALIBRATION 0
|
||||
#define IO_DELAY_PER_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_OPA_TAP 312
|
||||
#define IO_DLL_CHAIN_LENGTH 8
|
||||
#define IO_DQDQS_OUT_PHASE_MAX 0
|
||||
#define IO_DQS_EN_DELAY_MAX 31
|
||||
#define IO_DQS_EN_DELAY_OFFSET 0
|
||||
#define IO_DQS_EN_PHASE_MAX 7
|
||||
#define IO_DQS_IN_DELAY_MAX 31
|
||||
#define IO_DQS_IN_RESERVE 4
|
||||
#define IO_DQS_OUT_RESERVE 4
|
||||
#define IO_IO_IN_DELAY_MAX 31
|
||||
#define IO_IO_OUT1_DELAY_MAX 31
|
||||
#define IO_IO_OUT2_DELAY_MAX 0
|
||||
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
|
||||
#define MAX_LATENCY_COUNT_WIDTH 5
|
||||
#define READ_VALID_FIFO_SIZE 16
|
||||
#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496
|
||||
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
|
||||
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
|
||||
#define RW_MGR_MEM_DATA_WIDTH 32
|
||||
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
|
||||
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
|
||||
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
|
||||
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
|
||||
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
|
||||
#define TINIT_CNTR0_VAL 99
|
||||
#define TINIT_CNTR1_VAL 32
|
||||
#define TINIT_CNTR2_VAL 32
|
||||
#define TRESET_CNTR0_VAL 99
|
||||
#define TRESET_CNTR1_VAL 99
|
||||
#define TRESET_CNTR2_VAL 10
|
||||
|
||||
/* Sequencer ac_rom_init configuration */
|
||||
const u32 ac_rom_init[] = {
|
||||
0x20700000,
|
||||
0x20780000,
|
||||
0x10080421,
|
||||
0x10080520,
|
||||
0x10090044,
|
||||
0x100a0008,
|
||||
0x100b0000,
|
||||
0x10380400,
|
||||
0x10080441,
|
||||
0x100804c0,
|
||||
0x100a0024,
|
||||
0x10090010,
|
||||
0x100b0000,
|
||||
0x30780000,
|
||||
0x38780000,
|
||||
0x30780000,
|
||||
0x10680000,
|
||||
0x106b0000,
|
||||
0x10280400,
|
||||
0x10480000,
|
||||
0x1c980000,
|
||||
0x1c9b0000,
|
||||
0x1c980008,
|
||||
0x1c9b0008,
|
||||
0x38f80000,
|
||||
0x3cf80000,
|
||||
0x38780000,
|
||||
0x18180000,
|
||||
0x18980000,
|
||||
0x13580000,
|
||||
0x135b0000,
|
||||
0x13580008,
|
||||
0x135b0008,
|
||||
0x33780000,
|
||||
0x10580008,
|
||||
0x10780000
|
||||
};
|
||||
|
||||
/* Sequencer inst_rom_init configuration */
|
||||
const u32 inst_rom_init[] = {
|
||||
0x80000,
|
||||
0x80680,
|
||||
0x8180,
|
||||
0x8200,
|
||||
0x8280,
|
||||
0x8300,
|
||||
0x8380,
|
||||
0x8100,
|
||||
0x8480,
|
||||
0x8500,
|
||||
0x8580,
|
||||
0x8600,
|
||||
0x8400,
|
||||
0x800,
|
||||
0x8680,
|
||||
0x880,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x900,
|
||||
0x80680,
|
||||
0x980,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xb68,
|
||||
0xcce8,
|
||||
0xae8,
|
||||
0x8ce8,
|
||||
0xb88,
|
||||
0xec88,
|
||||
0xa08,
|
||||
0xac88,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x60e80,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x70e80,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0x1158,
|
||||
0x6d8,
|
||||
0x80680,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0x87e8,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0xa7e8,
|
||||
0x80680,
|
||||
0x40e88,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x40f68,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0xa680,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x41008,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x1100,
|
||||
0xc680,
|
||||
0x8680,
|
||||
0xe680,
|
||||
0x80680,
|
||||
0x0,
|
||||
0x8000,
|
||||
0xa000,
|
||||
0xc000,
|
||||
0x80000,
|
||||
0x80,
|
||||
0x8080,
|
||||
0xa080,
|
||||
0xc080,
|
||||
0x80080,
|
||||
0x9180,
|
||||
0x8680,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x40f08,
|
||||
0x80680
|
||||
};
|
||||
|
||||
#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
|
||||
6
u-boot/board/denx/mcvevk/socfpga.c
Normal file
6
u-boot/board/denx/mcvevk/socfpga.c
Normal file
@@ -0,0 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
Reference in New Issue
Block a user