avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
46
u-boot/board/dbau1x00/Kconfig
Normal file
46
u-boot/board/dbau1x00/Kconfig
Normal file
@@ -0,0 +1,46 @@
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if TARGET_DBAU1X00
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config SYS_BOARD
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default "dbau1x00"
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config SYS_SOC
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default "au1x00"
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config SYS_CONFIG_NAME
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default "dbau1x00"
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config SYS_TEXT_BASE
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default 0xbfc00000
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config SYS_DCACHE_SIZE
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default 16384
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config SYS_DCACHE_LINE_SIZE
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default 32
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config SYS_ICACHE_SIZE
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default 16384
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config SYS_ICACHE_LINE_SIZE
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default 32
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menu "dbau1x00 board options"
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choice
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prompt "Select au1x00 SoC type"
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optional
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config DBAU1100
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bool "Select AU1100"
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config DBAU1500
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bool "Select AU1500"
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config DBAU1550
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bool "Select AU1550"
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endchoice
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endmenu
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endif
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10
u-boot/board/dbau1x00/MAINTAINERS
Normal file
10
u-boot/board/dbau1x00/MAINTAINERS
Normal file
@@ -0,0 +1,10 @@
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DBAU1X00 BOARD
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#M: -
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S: Orphan (since 2016-06)
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F: board/dbau1x00/
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F: include/configs/dbau1x00.h
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F: configs/dbau1000_defconfig
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F: configs/dbau1100_defconfig
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F: configs/dbau1500_defconfig
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F: configs/dbau1550_defconfig
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F: configs/dbau1550_el_defconfig
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9
u-boot/board/dbau1x00/Makefile
Normal file
9
u-boot/board/dbau1x00/Makefile
Normal file
@@ -0,0 +1,9 @@
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = dbau1x00.o
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obj-y += lowlevel_init.o
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63
u-boot/board/dbau1x00/README
Normal file
63
u-boot/board/dbau1x00/README
Normal file
@@ -0,0 +1,63 @@
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By Thomas.Lange@corelatus.se 2004-Oct-05
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----------------------------------------
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DbAu1xx0 are development boards from AMD containing
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an Alchemy AU1xx0 series cpu with mips32 core.
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Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
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Limitations & comments
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----------------------
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Support was originally big endian only.
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I have not tested, but several u-boot users report working
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configurations in little endian mode.
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I named the board dbau1x00, to allow
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support for all three development boards
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( dbau1000, dbau1100 and dbau1500 ).
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Now there is a new board called dbau1550 also, which
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should be supported RSN.
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I only have a dbau1000, so my testing is limited
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to this board.
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The board has two different flash banks, that can
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be selected via dip switch. This makes it possible
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to test new bootloaders without thrashing the YAMON
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boot loader delivered with board.
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NOTE! When you switch between the two boot flashes, the
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base addresses will be swapped.
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Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has
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to match the address where u-boot is located when you
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actually launch.
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Ethernet only supported for mac0.
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PCMCIA only supported for slot 0, only 3.3V.
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PCMCIA IDE tested with Sandisk Compact Flash and
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IBM microdrive.
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###################################
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######## NOTE!!!!!! #########
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###################################
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If you partition a disk on another system (e.g. laptop),
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all bytes will be swapped on 16bit level when using
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PCMCIA and running cpu in big endian mode!!!!
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This is probably due to an error in Au1000 chip.
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Solution:
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a) Boot via network and partition disk directly from
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dbau1x00. The endian will then be correct.
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b) Partition disk on "laptop" and fill it with all files
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you need. Then write a simple program that endian swaps
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whole disk,
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Example:
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Original "laptop" byte order:
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B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
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Dbau1000 byte order will then be:
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B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
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115
u-boot/board/dbau1x00/dbau1x00.c
Normal file
115
u-boot/board/dbau1x00/dbau1x00.c
Normal file
@@ -0,0 +1,115 @@
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/*
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* (C) Copyright 2003
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* Thomas.Lange@corelatus.se
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <mach/au1x00.h>
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#include <asm/mipsregs.h>
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#include <asm/io.h>
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phys_size_t initdram(int board_type)
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{
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/* Sdram is setup by assembler code */
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/* If memory could be changed, we should return the true value here */
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return MEM_SIZE*1024*1024;
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}
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#define BCSR_PCMCIA_PC0DRVEN 0x0010
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#define BCSR_PCMCIA_PC0RST 0x0080
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/* In arch/mips/cpu/cpu.c */
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void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
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int checkboard (void)
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{
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#ifdef CONFIG_IDE_PCMCIA
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u16 status;
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volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
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#endif /* CONFIG_IDE_PCMCIA */
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volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
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volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
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u32 proc_id;
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*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
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proc_id = read_c0_prid();
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switch (proc_id >> 24) {
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case 0:
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puts ("Board: Merlot (DbAu1000)\n");
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printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
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(proc_id >> 8) & 0xFF, proc_id & 0xFF);
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break;
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case 1:
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puts ("Board: DbAu1500\n");
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printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
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(proc_id >> 8) & 0xFF, proc_id & 0xFF);
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break;
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case 2:
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puts ("Board: DbAu1100\n");
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printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
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(proc_id >> 8) & 0xFF, proc_id & 0xFF);
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break;
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case 3:
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puts ("Board: DbAu1550\n");
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printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
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(proc_id >> 8) & 0xFF, proc_id & 0xFF);
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break;
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default:
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printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
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}
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set_io_port_base(0);
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#ifdef CONFIG_IDE_PCMCIA
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/* Enable 3.3 V on slot 0 ( VCC )
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No 5V */
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status = 4;
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*pcmcia_bcsr = status;
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status |= BCSR_PCMCIA_PC0DRVEN;
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*pcmcia_bcsr = status;
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au_sync();
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udelay(300*1000);
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status |= BCSR_PCMCIA_PC0RST;
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*pcmcia_bcsr = status;
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au_sync();
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udelay(100*1000);
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/* PCMCIA is on a 36 bit physical address.
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We need to map it into a 32 bit addresses */
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#if 0
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/* We dont need theese unless we run whole pcmcia package */
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write_one_tlb(20, /* index */
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0x01ffe000, /* Pagemask, 16 MB pages */
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CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
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0x3C000017, /* Lo0 */
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0x3C200017); /* Lo1 */
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write_one_tlb(21, /* index */
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0x01ffe000, /* Pagemask, 16 MB pages */
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CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
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0x3D000017, /* Lo0 */
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0x3D200017); /* Lo1 */
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#endif /* 0 */
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write_one_tlb(22, /* index */
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0x01ffe000, /* Pagemask, 16 MB pages */
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CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
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0x3E000017, /* Lo0 */
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0x3E200017); /* Lo1 */
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#endif /* CONFIG_IDE_PCMCIA */
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|
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/* Release reset of ethernet PHY chips */
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/* Always do this, because linux does not know about it */
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*phy = 3;
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|
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return 0;
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}
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589
u-boot/board/dbau1x00/lowlevel_init.S
Normal file
589
u-boot/board/dbau1x00/lowlevel_init.S
Normal file
@@ -0,0 +1,589 @@
|
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/* Memory sub-system initialization code */
|
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|
||||
#include <config.h>
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#include <mach/au1x00.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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|
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#define AU1500_SYS_ADDR 0xB1900000
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#define sys_endian 0x0038
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#define CP0_Config0 $16
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#define CPU_SCALE ((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
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#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000)
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.text
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.set noreorder
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.set mips32
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|
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.globl lowlevel_init
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lowlevel_init:
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/*
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* Step 1) Establish CPU endian mode.
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* Db1500-specific:
|
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* Switch S1.1 Off(bit7 reads 1) is Little Endian
|
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* Switch S1.1 On (bit7 reads 0) is Big Endian
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||||
*/
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#ifdef CONFIG_DBAU1550
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li t0, MEM_STCFG2
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li t1, 0x00000040
|
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sw t1, 0(t0)
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|
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li t0, MEM_STTIME2
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li t1, 0x22080a20
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sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STADDR2
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li t1, 0x10c03f00
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sw t1, 0(t0)
|
||||
#else
|
||||
li t0, MEM_STCFG1
|
||||
li t1, 0x00000080
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STTIME1
|
||||
li t1, 0x22080a20
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STADDR1
|
||||
li t1, 0x10c03f00
|
||||
sw t1, 0(t0)
|
||||
#endif
|
||||
|
||||
li t0, DB1XX0_BCSR_ADDR
|
||||
lw t1,8(t0)
|
||||
andi t1,t1,0x80
|
||||
beq zero,t1,big_endian
|
||||
nop
|
||||
little_endian:
|
||||
|
||||
/* Change Au1 core to little endian */
|
||||
li t0, AU1500_SYS_ADDR
|
||||
li t1, 1
|
||||
sw t1, sys_endian(t0)
|
||||
mfc0 t2, CP0_CONFIG
|
||||
mtc0 t2, CP0_CONFIG
|
||||
nop
|
||||
nop
|
||||
|
||||
/* Big Endian is default so nothing to do but fall through */
|
||||
|
||||
big_endian:
|
||||
|
||||
/*
|
||||
* Step 2) Establish Status Register
|
||||
* (set BEV, clear ERL, clear EXL, clear IE)
|
||||
*/
|
||||
li t1, 0x00400000
|
||||
mtc0 t1, CP0_STATUS
|
||||
|
||||
/*
|
||||
* Step 3) Establish CP0 Config0
|
||||
* (set OD, set K0=3)
|
||||
*/
|
||||
li t1, 0x00080003
|
||||
mtc0 t1, CP0_CONFIG
|
||||
|
||||
/*
|
||||
* Step 4) Disable Watchpoint facilities
|
||||
*/
|
||||
li t1, 0x00000000
|
||||
mtc0 t1, CP0_WATCHLO
|
||||
mtc0 t1, CP0_IWATCHLO
|
||||
/*
|
||||
* Step 5) Disable the performance counters
|
||||
*/
|
||||
mtc0 zero, CP0_PERFORMANCE
|
||||
nop
|
||||
|
||||
/*
|
||||
* Step 6) Establish EJTAG Debug register
|
||||
*/
|
||||
mtc0 zero, CP0_DEBUG
|
||||
nop
|
||||
|
||||
/*
|
||||
* Step 7) Establish Cause
|
||||
* (set IV bit)
|
||||
*/
|
||||
li t1, 0x00800000
|
||||
mtc0 t1, CP0_CAUSE
|
||||
|
||||
/* Establish Wired (and Random) */
|
||||
mtc0 zero, CP0_WIRED
|
||||
nop
|
||||
|
||||
#ifdef CONFIG_DBAU1550
|
||||
/* No workaround if running from ram */
|
||||
lui t0, 0xffc0
|
||||
lui t3, 0xbfc0
|
||||
and t1, ra, t0
|
||||
bne t1, t3, noCacheJump
|
||||
nop
|
||||
|
||||
/*** From AMD YAMON ***/
|
||||
/*
|
||||
* Step 8) Initialize the caches
|
||||
*/
|
||||
li t0, (16*1024)
|
||||
li t1, 32
|
||||
li t2, 0x80000000
|
||||
addu t3, t0, t2
|
||||
cacheloop:
|
||||
cache 0, 0(t2)
|
||||
cache 1, 0(t2)
|
||||
addu t2, t1
|
||||
bne t2, t3, cacheloop
|
||||
nop
|
||||
|
||||
/* Save return address */
|
||||
move t3, ra
|
||||
|
||||
/* Run from cacheable space now */
|
||||
bal cachehere
|
||||
nop
|
||||
cachehere:
|
||||
li t1, ~0x20000000 /* convert to KSEG0 */
|
||||
and t0, ra, t1
|
||||
addi t0, 5*4 /* 5 insns beyond cachehere */
|
||||
jr t0
|
||||
nop
|
||||
|
||||
/* Restore return address */
|
||||
move ra, t3
|
||||
|
||||
/*
|
||||
* Step 9) Initialize the TLB
|
||||
*/
|
||||
li t0, 0 # index value
|
||||
li t1, 0x00000000 # entryhi value
|
||||
li t2, 32 # 32 entries
|
||||
|
||||
tlbloop:
|
||||
/* Probe TLB for matching EntryHi */
|
||||
mtc0 t1, CP0_ENTRYHI
|
||||
tlbp
|
||||
nop
|
||||
|
||||
/* Examine Index[P], 1=no matching entry */
|
||||
mfc0 t3, CP0_INDEX
|
||||
li t4, 0x80000000
|
||||
and t3, t4, t3
|
||||
addiu t1, t1, 1 # increment t1 (asid)
|
||||
beq zero, t3, tlbloop
|
||||
nop
|
||||
|
||||
/* Initialize the TLB entry */
|
||||
mtc0 t0, CP0_INDEX
|
||||
mtc0 zero, CP0_ENTRYLO0
|
||||
mtc0 zero, CP0_ENTRYLO1
|
||||
mtc0 zero, CP0_PAGEMASK
|
||||
tlbwi
|
||||
|
||||
/* Do it again */
|
||||
addiu t0, t0, 1
|
||||
bne t0, t2, tlbloop
|
||||
nop
|
||||
|
||||
#endif /* CONFIG_DBAU1550 */
|
||||
|
||||
/* First setup pll:s to make serial work ok */
|
||||
/* We have a 12 MHz crystal */
|
||||
li t0, SYS_CPUPLL
|
||||
li t1, CPU_SCALE /* CPU clock */
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
nop
|
||||
nop
|
||||
|
||||
/* wait 1mS for clocks to settle */
|
||||
li t1, MEM_1MS
|
||||
1: add t1, -1
|
||||
bne t1, zero, 1b
|
||||
nop
|
||||
/* Setup AUX PLL */
|
||||
li t0, SYS_AUXPLL
|
||||
li t1, 0x20 /* 96 MHz */
|
||||
sw t1, 0(t0) /* aux pll */
|
||||
sync
|
||||
|
||||
#ifdef CONFIG_DBAU1550
|
||||
/* Static memory controller */
|
||||
/* RCE0 - can not change while fetching, do so from icache */
|
||||
move t2, ra /* Store return address */
|
||||
bal getAddr
|
||||
nop
|
||||
|
||||
getAddr:
|
||||
move t1, ra
|
||||
move ra, t2 /* Move return addess back */
|
||||
|
||||
cache 0x14,0(t1)
|
||||
cache 0x14,32(t1)
|
||||
/*** /From YAMON ***/
|
||||
|
||||
noCacheJump:
|
||||
#endif /* CONFIG_DBAU1550 */
|
||||
|
||||
#ifdef CONFIG_DBAU1550
|
||||
li t0, MEM_STTIME0
|
||||
li t1, 0x040181D7
|
||||
sw t1, 0(t0)
|
||||
|
||||
/* RCE0 AMD MirrorBit Flash (?) */
|
||||
li t0, MEM_STCFG0
|
||||
li t1, 0x00000003
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STADDR0
|
||||
li t1, 0x11803E00
|
||||
sw t1, 0(t0)
|
||||
#else /* CONFIG_DBAU1550 */
|
||||
li t0, MEM_STTIME0
|
||||
li t1, 0x040181D7
|
||||
sw t1, 0(t0)
|
||||
|
||||
/* RCE0 AMD 29LV640M MirrorBit Flash */
|
||||
li t0, MEM_STCFG0
|
||||
li t1, 0x00000013
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STADDR0
|
||||
li t1, 0x11E03F80
|
||||
sw t1, 0(t0)
|
||||
#endif /* CONFIG_DBAU1550 */
|
||||
|
||||
/* RCE1 CPLD Board Logic */
|
||||
li t0, MEM_STCFG1
|
||||
li t1, 0x00000080
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STTIME1
|
||||
li t1, 0x22080a20
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STADDR1
|
||||
li t1, 0x10c03f00
|
||||
sw t1, 0(t0)
|
||||
|
||||
#ifdef CONFIG_DBAU1550
|
||||
/* RCE2 CPLD Board Logic */
|
||||
li t0, MEM_STCFG2
|
||||
li t1, 0x00000040
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STTIME2
|
||||
li t1, 0x22080a20
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STADDR2
|
||||
li t1, 0x10c03f00
|
||||
sw t1, 0(t0)
|
||||
#else
|
||||
li t0, MEM_STCFG2
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STTIME2
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STADDR2
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
#endif
|
||||
|
||||
/* RCE3 PCMCIA 250ns */
|
||||
li t0, MEM_STCFG3
|
||||
li t1, 0x00000002
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STTIME3
|
||||
li t1, 0x280E3E07
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_STADDR3
|
||||
li t1, 0x10000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
sync
|
||||
|
||||
/* Set peripherals to a known state */
|
||||
li t0, IC0_CFG0CLR
|
||||
li t1, 0xFFFFFFFF
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC0_CFG0CLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC0_CFG1CLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC0_CFG2CLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC0_SRCSET
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC0_ASSIGNSET
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC0_WAKECLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC0_RISINGCLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC0_FALLINGCLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC0_TESTBIT
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, IC1_CFG0CLR
|
||||
li t1, 0xFFFFFFFF
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC1_CFG0CLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC1_CFG1CLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC1_CFG2CLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC1_SRCSET
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC1_ASSIGNSET
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC1_WAKECLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC1_RISINGCLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC1_FALLINGCLR
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, IC1_TESTBIT
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, SYS_FREQCTRL0
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, SYS_FREQCTRL1
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, SYS_CLKSRC
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, SYS_PININPUTEN
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, 0xB1100100
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, 0xB1400100
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
|
||||
li t0, SYS_WAKEMSK
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, SYS_WAKESRC
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
/* wait 1mS before setup */
|
||||
li t1, MEM_1MS
|
||||
1: add t1, -1
|
||||
bne t1, zero, 1b
|
||||
nop
|
||||
|
||||
#ifdef CONFIG_DBAU1550
|
||||
/* SDCS 0,1,2 DDR SDRAM */
|
||||
li t0, MEM_SDMODE0
|
||||
li t1, 0x04276221
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_SDMODE1
|
||||
li t1, 0x04276221
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_SDMODE2
|
||||
li t1, 0x04276221
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_SDADDR0
|
||||
li t1, 0xe21003f0
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_SDADDR1
|
||||
li t1, 0xe21043f0
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_SDADDR2
|
||||
li t1, 0xe21083f0
|
||||
sw t1, 0(t0)
|
||||
|
||||
sync
|
||||
|
||||
li t0, MEM_SDCONFIGA
|
||||
li t1, 0x9030060a /* Program refresh - disabled */
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDCONFIGB
|
||||
li t1, 0x00028000
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDPRECMD /* Precharge all */
|
||||
li t1, 0
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDWRMD0
|
||||
li t1, 0x40000000
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDWRMD1
|
||||
li t1, 0x40000000
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDWRMD2
|
||||
li t1, 0x40000000
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDWRMD0
|
||||
li t1, 0x00000063
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDWRMD1
|
||||
li t1, 0x00000063
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDWRMD2
|
||||
li t1, 0x00000063
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDPRECMD /* Precharge all */
|
||||
sw zero, 0(t0)
|
||||
sync
|
||||
|
||||
/* Issue 2 autoref */
|
||||
li t0, MEM_SDAUTOREF
|
||||
sw zero, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDAUTOREF
|
||||
sw zero, 0(t0)
|
||||
sync
|
||||
|
||||
/* Enable refresh */
|
||||
li t0, MEM_SDCONFIGA
|
||||
li t1, 0x9830060a /* Program refresh - enabled */
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
#else /* CONFIG_DBAU1550 */
|
||||
/* SDCS 0,1 SDRAM */
|
||||
li t0, MEM_SDMODE0
|
||||
li t1, 0x005522AA
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_SDMODE1
|
||||
li t1, 0x005522AA
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_SDMODE2
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_SDADDR0
|
||||
li t1, 0x001003F8
|
||||
sw t1, 0(t0)
|
||||
|
||||
|
||||
li t0, MEM_SDADDR1
|
||||
li t1, 0x001023F8
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, MEM_SDADDR2
|
||||
li t1, 0x00000000
|
||||
sw t1, 0(t0)
|
||||
|
||||
sync
|
||||
|
||||
li t0, MEM_SDREFCFG
|
||||
li t1, 0x64000C24 /* Disable */
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDPRECMD
|
||||
sw zero, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDAUTOREF
|
||||
sw zero, 0(t0)
|
||||
sync
|
||||
sw zero, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDREFCFG
|
||||
li t1, 0x66000C24 /* Enable */
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDWRMD0
|
||||
li t1, 0x00000033
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
li t0, MEM_SDWRMD1
|
||||
li t1, 0x00000033
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
#endif /* CONFIG_DBAU1550 */
|
||||
/* wait 1mS after setup */
|
||||
li t1, MEM_1MS
|
||||
1: add t1, -1
|
||||
bne t1, zero, 1b
|
||||
nop
|
||||
|
||||
li t0, SYS_PINFUNC
|
||||
li t1, 0x00008080
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, SYS_TRIOUTCLR
|
||||
li t1, 0x00001FFF
|
||||
sw t1, 0(t0)
|
||||
|
||||
li t0, SYS_OUTPUTCLR
|
||||
li t1, 0x00008000
|
||||
sw t1, 0(t0)
|
||||
sync
|
||||
|
||||
jr ra
|
||||
nop
|
||||
Reference in New Issue
Block a user