Kevin/Jibo-Platform-Tools-OLD
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

avionic design with actual uboot and tooling

Browse Source 
submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
u-boot/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg Normal file
View File

@@ -0,0 +1,42 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7974
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42720306
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026F0266
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4273030A
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02740240
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45393B3E
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x403A3747
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40434541
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x473E4A3B
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0011000E
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E001B
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00190015
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00070018
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006

42
u-boot/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg Normal file
View File

@@ -0,0 +1,42 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42740304
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026e0265
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x02750306
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02720244
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x463d4041
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c47
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x37414441
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4633473b
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0025001f
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00290027
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f002b
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000f0029
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006

63
u-boot/board/boundary/nitrogen6x/6x_bootscript.txt Normal file
View File

@@ -0,0 +1,63 @@
setenv bootargs enable_wait_mode=off
setenv nextcon 0;
if hdmidet ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
setenv fbmem "fbmem=28M";
setexpr nextcon $nextcon + 1
else
echo "------ no HDMI monitor";
fi
i2c dev 2
if i2c probe 0x04 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
if test "0" -eq $nextcon; then
setenv fbmem "fbmem=10M";
else
setenv fbmem ${fbmem},10M
fi
setexpr nextcon $nextcon + 1
else
echo "------ no Freescale display";
fi
if i2c probe 0x38 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
if test "0" -eq $nextcon; then
setenv fbmem "fbmem=10M";
else
setenv fbmem ${fbmem},10M
fi
setexpr nextcon $nextcon + 1
else
echo "------ no 1024x600 display";
fi
if i2c probe 0x48 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666
if test "0" -eq $nextcon; then
setenv fbmem "fbmem=10M";
else
setenv fbmem ${fbmem},10M
fi
setexpr nextcon $nextcon + 1
else
echo "------ no 800x480 display";
fi
while test "3" -ne $nextcon ; do
setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
setexpr nextcon $nextcon + 1 ;
done
setenv bootargs $bootargs $fbmem
setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait"
if test "sata" = "${dtype}" ; then
setenv bootargs "$bootargs root=/dev/sda1" ;
else
setenv "bootargs $bootargs root=/dev/mmcblk0p1" ;
fi
${fs}load ${dtype} ${disk}:1 10800000 /boot/uImage && bootm 10800000 ;
echo "Error loading kernel image"

64
u-boot/board/boundary/nitrogen6x/6x_bootscript_android.txt Normal file
View File

@@ -0,0 +1,64 @@
${dtype} dev ${disk}
setenv bootargs enable_wait_mode=off
setenv nextcon 0;
setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
i2c dev 2
if i2c probe 0x04 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
if test "0" -eq $nextcon; then
setenv fbcon "fbcon=10M";
else
setenv fbcon ${fbcon},10M
fi
setexpr nextcon $nextcon + 1
else
echo "------ no Freescale display";
fi
if i2c probe 0x38 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
if test "0" -eq $nextcon; then
setenv fbcon "fbcon=10M";
else
setenv fbcon ${fbcon},10M
fi
setexpr nextcon $nextcon + 1
else
echo "------ no 1024x600 display";
fi
if i2c probe 0x48 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
if test "0" -eq $nextcon; then
setenv fbcon "fbcon=10M";
else
setenv fbcon ${fbcon},10M
fi
setexpr nextcon $nextcon + 1
else
echo "------ no 800x480 display";
fi
if hdmidet ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
if test "0" -eq $nextcon; then
setenv fbcon "fbcon=28M";
else
setenv fbcon ${fbcon},28M
fi
setexpr nextcon $nextcon + 1
else
echo "------ no HDMI monitor";
fi
while test "3" -ne $nextcon ; do
setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
setexpr nextcon $nextcon + 1 ;
done
setenv bootargs $bootargs fbcon=$fbcon
${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000
echo "Error loading kernel image"

64
u-boot/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt Normal file
View File

@@ -0,0 +1,64 @@
${dtype} dev ${disk}
setenv bootargs enable_wait_mode=off
setenv nextcon 0;
setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
i2c dev 2
if i2c probe 0x04 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
if test "0" -eq $nextcon; then
setenv fbcon "fbcon=10M";
else
setenv fbcon ${fbcon},10M
fi
setexpr nextcon $nextcon + 1
else
echo "------ no Freescale display";
fi
if i2c probe 0x38 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
if test "0" -eq $nextcon; then
setenv fbcon "fbcon=10M";
else
setenv fbcon ${fbcon},10M
fi
setexpr nextcon $nextcon + 1
else
echo "------ no 1024x600 display";
fi
if i2c probe 0x48 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
if test "0" -eq $nextcon; then
setenv fbcon "fbcon=10M";
else
setenv fbcon ${fbcon},10M
fi
setexpr nextcon $nextcon + 1
else
echo "------ no 800x480 display";
fi
if hdmidet ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
if test "0" -eq $nextcon; then
setenv fbcon "fbcon=28M";
else
setenv fbcon ${fbcon},28M
fi
setexpr nextcon $nextcon + 1
else
echo "------ no HDMI monitor";
fi
while test "3" -ne $nextcon ; do
setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
setexpr nextcon $nextcon + 1 ;
done
setenv bootargs $bootargs fbcon=$fbcon
${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000
echo "Error loading kernel image"

45
u-boot/board/boundary/nitrogen6x/6x_upgrade.txt Normal file
View File

@@ -0,0 +1,45 @@
setenv stdout serial,vga
echo "check U-Boot" ;
setenv offset 0x400
if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then
echo "read $filesize bytes from SD card" ;
if sf probe || sf probe || \
sf probe 1 27000000 || sf probe 1 27000000 ; then
echo "probed SPI ROM" ;
if sf read 0x12400000 $offset $filesize ; then
if cmp.b 0x12000000 0x12400000 $filesize ; then
echo "------- U-Boot versions match" ;
else
echo "Need U-Boot upgrade" ;
echo "Program in 5 seconds" ;
for n in 5 4 3 2 1 ; do
echo $n ;
sleep 1 ;
done
echo "erasing" ;
sf erase 0 0xC0000 ;
# two steps to prevent bricking
echo "programming" ;
sf write 0x12000000 $offset $filesize ;
echo "verifying" ;
if sf read 0x12400000 $offset $filesize ; then
if cmp.b 0x12000000 0x12400000 $filesize ; then
while echo "---- U-Boot upgraded. reset" ; do
sleep 120
done
else
echo "Read verification error" ;
fi
else
echo "Error re-reading EEPROM" ;
fi
fi
else
echo "Error reading boot loader from EEPROM" ;
fi
else
echo "Error initializing EEPROM" ;
fi ;
else
echo "No U-Boot image found on SD card" ;
fi

42
u-boot/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg Normal file
View File

@@ -0,0 +1,42 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006

42
u-boot/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg Normal file
View File

@@ -0,0 +1,42 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006

42
u-boot/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg Normal file
View File

@@ -0,0 +1,42 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006

42
u-boot/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg Normal file
View File

@@ -0,0 +1,42 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006

12
u-boot/board/boundary/nitrogen6x/Kconfig Normal file
View File

@@ -0,0 +1,12 @@
if TARGET_NITROGEN6X
config SYS_BOARD
default "nitrogen6x"
config SYS_VENDOR
default "boundary"
config SYS_CONFIG_NAME
default "nitrogen6x"
endif

12
u-boot/board/boundary/nitrogen6x/MAINTAINERS Normal file
View File

@@ -0,0 +1,12 @@
NITROGEN6X BOARD
M: Troy Kisky <troy.kisky@boundarydevices.com>
S: Maintained
F: board/boundary/nitrogen6x/
F: include/configs/nitrogen6x.h
F: configs/mx6qsabrelite_defconfig
F: configs/nitrogen6dl_defconfig
F: configs/nitrogen6dl2g_defconfig
F: configs/nitrogen6q_defconfig
F: configs/nitrogen6q2g_defconfig
F: configs/nitrogen6s_defconfig
F: configs/nitrogen6s1g_defconfig

9
u-boot/board/boundary/nitrogen6x/Makefile Normal file
View File

@@ -0,0 +1,9 @@
#
# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := nitrogen6x.o

92
u-boot/board/boundary/nitrogen6x/README Normal file
View File

@@ -0,0 +1,92 @@
U-Boot for the Boundary Devices Nitrogen6X and
Freescale i.MX6Q SabreLite boards
This file contains information for the port of
U-Boot to the Boundary Devices Nitrogen6X and
Freescale i.MX6Q SabreLite boards.
1. Boot source, boot from SPI NOR
---------------------------------
The configuration in this directory supports both the
Nitrogen6X and Freescale SabreLite board, but in a
different fashion from Freescale's implementation in
board/freescale/mx6qsabrelite.
In particular, this image supports booting from SPI NOR
and saving the environment to SPI NOR.
It does not support 'boot from SD' at offset 0x400
except through the 'bmode' command.
http://lists.denx.de/pipermail/u-boot/2012-August/131151.html
2. Boots using 6x_bootscript on SATA or SD card
-----------------------------------------------
The default bootcmd for these boards is configured
to look for and source a boot script named '6x_bootscript'
in the root of the first partition of the following
devices:
sata 0
mmc 0
mmc 1
They're searched in the order listed above, trying both the
ext2 and fat filesystems.
2. Maintaining the SPI NOR
--------------------------
A couple of convenience commands
clearenv - clear environment to factory default
upgradeu - look and source a boot script named
'6x_upgrade' to upgrade the U-Boot version
in SPI NOR. The search is the same as for
6x_bootscript described above.
3. Display support
------------------
U-Boot support for the following displays is configured by
default:
HDMI - 1024 x 768 for maximum compatibility
Hannstar-XGA - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1)
wsvga-lvds - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600)
wvga-rgb - 800 x 480 RGB (Boundary p/n Nit6X_800x480)
Since the ipuv3_fb display driver currently supports only a single display,
this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect
or the I2C touch controller of the LVDS and RGB displays in the priority
listed above.
Setting 'panel' environment variable to one of the names above will
override auto-detection and force activation of the specified panel.
4. Building
------------
To build U-Boot for one of the Nitrogen6x or SabreLite board:
make nitrogen6x_config
make
Note that 'nitrogen6x' is a placeholder. The complete list of supported
board configurations is shown in the boards.cfg file:
nitrogen6q i.MX6Q/6D 1GB
nitrogen6dl i.MX6DL 1GB
nitrogen6s i.MX6S 512MB
nitrogen6q2g i.MX6Q/6D 2GB
nitrogen6dl2g i.MX6DL 2GB
nitrogen6s1g i.MX6S 1GB
The -6q variants support either the i.MX6Quad or i.MX6Dual processors
and are configured for a 64-bit memory bus at 1066 MHz.
The -6dl variants also use a 64-bit memory bus, operated at 800MHz.
The -6s variants use a 32-bit memory bus at 800MHz.
If you place the u-boot.imx into a single-partition SD card
along with a binary version of the boot script 6x_upgrade.txt,
you can program it using 'upgradeu':
U-Boot> run upgradeu

72
u-boot/board/boundary/nitrogen6x/README.mx6qsabrelite Normal file
View File

@@ -0,0 +1,72 @@
U-Boot for the Freescale i.MX6q SabreLite board
This file contains information for the port of U-Boot to the Freescale
i.MX6q SabreLite board.
1. Boot source, boot from SD card
---------------------------------
The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports
boot from SD card only. However, by default, the SabreLite
boards boot from the SPI NOR flash. These boards need to be reflashed with
a small SD card loader to support boot from SD card. This small SD card loader
will be flashed into the SPI NOR. The board will still boot from SPI NOR, but
the loader will in turn request the BootROM to load the U-Boot from SD card.
The SD card loader is available from
https://wiki.linaro.org/Boards/MX6QSabreLite
under a open-source 3-clause BSD license.
To update the SPI-NOR on the SabreLite board without the Freescale
manufacturing tool use the following procedure:
1. Write this SD card loader onto a large SD card using:
sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx
Note: Replace sXx with the device representing the SD card in your system.
Note: This writes SD card loader at address 0
2. Put this SD card into the slot for the large SD card (SD3 on the bottom of
the board). Make sure SW1 switch is at position "00", so that it can boot
from the fuses.
3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot
(the default one the board is shipped with, starting from the SPI NOR) and
enter the following commands:
MX6Q SABRELITE U-Boot > mmc dev 0
MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200
MX6Q SABRELITE U-Boot > sf probe
MX6Q SABRELITE U-Boot > sf erase 0 0x40000
MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000
4. done.
In case you somehow do not succeed with this procedure you will have to use
the Freescale manufacturing tool in order to reflash the SPI-NOR.
Note: The board now boots from full size SD3 on the bottom of the board. NOT
the micro SD4/BOOT slot on the top of the board. I.e. you have to use
full size SD cards.
This information is taken from
https://wiki.linaro.org/Boards/MX6QSabreLite
2. Build
--------
To build U-Boot for the SabreLite board:
make mx6qsabrelite_config
make
To copy the resulting u-boot.imx to the SD card:
sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2&&sudo sync
Note: Replace sXx with the device representing the SD card in your system.

41
u-boot/board/boundary/nitrogen6x/clocks.cfg Normal file
View File

@@ -0,0 +1,41 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0x00FFF300
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
DATA 4, CCM_CCOSR, 0x000000fb

96
u-boot/board/boundary/nitrogen6x/ddr-setup.cfg Normal file
View File

@@ -0,0 +1,96 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/*
* DDR3 settings
* MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
* memory bus width: 64 bits x16/x32/x64
* MX6DL ddr is limited to 800 MHz(400 MHz clock)
* memory bus width: 64 bits x16/x32/x64
* MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
* memory bus width: 32 bits x16/x32
*/
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
/* (differential input) */
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
/* (differential input) */
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
/* disable ddr pullups */
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
/* Read data DQ Byte0-3 delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
/*
* MDMISC mirroring interleaved (row/bank/col)
*/
DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
/*
* MDSCR con_req
*/
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000

29
u-boot/board/boundary/nitrogen6x/nitrogen6dl.cfg Normal file
View File

@@ -0,0 +1,29 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "800mhz_4x128mx16.cfg"
#include "clocks.cfg"

29
u-boot/board/boundary/nitrogen6x/nitrogen6dl2g.cfg Normal file
View File

@@ -0,0 +1,29 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "800mhz_4x256mx16.cfg"
#include "clocks.cfg"

29
u-boot/board/boundary/nitrogen6x/nitrogen6q.cfg Normal file
View File

@@ -0,0 +1,29 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "1066mhz_4x128mx16.cfg"
#include "clocks.cfg"

29
u-boot/board/boundary/nitrogen6x/nitrogen6q2g.cfg Normal file
View File

@@ -0,0 +1,29 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "1066mhz_4x256mx16.cfg"
#include "clocks.cfg"

29
u-boot/board/boundary/nitrogen6x/nitrogen6s.cfg Normal file
View File

@@ -0,0 +1,29 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "800mhz_2x128mx16.cfg"
#include "clocks.cfg"

29
u-boot/board/boundary/nitrogen6x/nitrogen6s1g.cfg Normal file
View File

@@ -0,0 +1,29 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "800mhz_2x256mx16.cfg"
#include "clocks.cfg"

1026
u-boot/board/boundary/nitrogen6x/nitrogen6x.c Normal file
View File

File diff suppressed because it is too large Load Diff