avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/board/atmel/at91rm9200ek/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_AT91RM9200EK
+
+config SYS_BOARD
+	default "at91rm9200ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91rm9200ek"
+
+endif

u-boot/board/atmel/at91rm9200ek/MAINTAINERS

@@ -0,0 +1,7 @@
+AT91RM9200EK BOARD
+M:	Andreas Bießmann <andreas@biessmann.org>
+S:	Maintained
+F:	board/atmel/at91rm9200ek/
+F:	include/configs/at91rm9200ek.h
+F:	configs/at91rm9200ek_defconfig
+F:	configs/at91rm9200ek_ram_defconfig

u-boot/board/atmel/at91rm9200ek/Makefile

@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += at91rm9200ek.o
+obj-y += led.o

u-boot/board/atmel/at91rm9200ek/at91rm9200ek.c

@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2010 Andreas Bießmann <andreas@biessmann.org>
+ *
+ * derived from previous work
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+int board_init(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+
+	/*
+	 * Correct IRDA resistor problem
+	 * Set PA23_TXD in Output
+	 */
+	writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
+
+	/* arch number of AT91RM9200EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int dram_init (void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	return at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
+}
+#endif

u-boot/board/atmel/at91rm9200ek/led.c

@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2006
+ * Atmel Nordic AB <www.atmel.com>
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * (C) Copyright 2010
+ * Andreas Bießmann <andreas@biessmann.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/at91_pio.h>
+#include <status_led.h>
+
+/* bit mask in PIO port B */
+#define	GREEN_LED	(1<<0)
+#define	YELLOW_LED	(1<<1)
+#define	RED_LED		(1<<2)
+
+void	green_led_on(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(GREEN_LED, &pio->piob.codr);
+}
+
+void	 yellow_led_on(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(YELLOW_LED, &pio->piob.codr);
+}
+
+void	 red_led_on(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(RED_LED, &pio->piob.codr);
+}
+
+void	green_led_off(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(GREEN_LED, &pio->piob.sodr);
+}
+
+void	yellow_led_off(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(YELLOW_LED, &pio->piob.sodr);
+}
+
+void	red_led_off(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(RED_LED, &pio->piob.sodr);
+}
+
+void coloured_LED_init (void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+
+	/* Disable peripherals on LEDs */
+	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
+	/* Enable pins as outputs */
+	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
+	/* Turn all LEDs OFF */
+	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
+}

u-boot/board/atmel/at91sam9260ek/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9260EK
+
+config SYS_BOARD
+	default "at91sam9260ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9260ek"
+
+endif

u-boot/board/atmel/at91sam9260ek/MAINTAINERS

@@ -0,0 +1,17 @@
+AT91SAM9260EK BOARD
+M:	Stelian Pop <stelian@popies.net>
+S:	Maintained
+F:	board/atmel/at91sam9260ek/
+F:	include/configs/at91sam9260ek.h
+F:	configs/at91sam9260ek_dataflash_cs0_defconfig
+F:	configs/at91sam9260ek_dataflash_cs1_defconfig
+F:	configs/at91sam9260ek_nandflash_defconfig
+F:	configs/at91sam9g20ek_2mmc_nandflash_defconfig
+F:	configs/at91sam9g20ek_dataflash_cs0_defconfig
+F:	configs/at91sam9g20ek_dataflash_cs1_defconfig
+F:	configs/at91sam9g20ek_mmc_defconfig
+F:	configs/at91sam9g20ek_2mmc_defconfig
+F:	configs/at91sam9g20ek_nandflash_defconfig
+F:	configs/at91sam9xeek_dataflash_cs0_defconfig
+F:	configs/at91sam9xeek_dataflash_cs1_defconfig
+F:	configs/at91sam9xeek_nandflash_defconfig

u-boot/board/atmel/at91sam9260ek/Makefile

@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= at91sam9260ek.o
+obj-y	+= led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o

u-boot/board/atmel/at91sam9260ek/at91sam9260ek.c

@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <atmel_mci.h>
+
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+# include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9260ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9260ek_macb_hw_init(void)
+{
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+	at91_periph_clk_enable(ATMEL_ID_EMAC0);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+		pin_to_mask(AT91_PIN_PA15) |
+		pin_to_mask(AT91_PIN_PA17) |
+		pin_to_mask(AT91_PIN_PA25) |
+		pin_to_mask(AT91_PIN_PA26) |
+		pin_to_mask(AT91_PIN_PA28),
+		&pioa->pudr);
+
+	at91_phy_reset();
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+		pin_to_mask(AT91_PIN_PA15) |
+		pin_to_mask(AT91_PIN_PA17) |
+		pin_to_mask(AT91_PIN_PA25) |
+		pin_to_mask(AT91_PIN_PA26) |
+		pin_to_mask(AT91_PIN_PA28),
+		&pioa->puer);
+
+	/* Initialize EMAC=MACB hardware */
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	at91_seriald_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91sam9260ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init((1 << 0) | (1 << 1));
+#endif
+#ifdef CONFIG_MACB
+	at91sam9260ek_macb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+#endif
+	return rc;
+}

u-boot/board/atmel/at91sam9260ek/led.c

@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <status_led.h>
+
+void coloured_LED_init(void)
+{
+	/* Clock is enabled in board_early_init_f() */
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}

u-boot/board/atmel/at91sam9260ek/partition.c

@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00083FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};

u-boot/board/atmel/at91sam9261ek/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9261EK
+
+config SYS_BOARD
+	default "at91sam9261ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9261ek"
+
+endif

u-boot/board/atmel/at91sam9261ek/MAINTAINERS

@@ -0,0 +1,11 @@
+AT91SAM9261EK BOARD
+M:	Stelian Pop <stelian@popies.net>
+S:	Maintained
+F:	board/atmel/at91sam9261ek/
+F:	include/configs/at91sam9261ek.h
+F:	configs/at91sam9261ek_dataflash_cs0_defconfig
+F:	configs/at91sam9261ek_dataflash_cs3_defconfig
+F:	configs/at91sam9261ek_nandflash_defconfig
+F:	configs/at91sam9g10ek_dataflash_cs0_defconfig
+F:	configs/at91sam9g10ek_dataflash_cs3_defconfig
+F:	configs/at91sam9g10ek_nandflash_defconfig

u-boot/board/atmel/at91sam9261ek/Makefile

@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += at91sam9261ek.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o

u-boot/board/atmel/at91sam9261ek/at91sam9261ek.c

@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91sam9261_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
+#include <net.h>
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9261ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+#ifdef CONFIG_AT91SAM9G10EK
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+		&smc->cs[3].cycle);
+#else
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+#endif
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_MODE_DBW_8 |
+#endif
+		       AT91_SMC_MODE_TDF_CYCLE(2),
+		       &smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
+	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+static void at91sam9261ek_dm9000_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	/* Configure SMC CS2 for DM9000 */
+#ifdef CONFIG_AT91SAM9G10EK
+	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[2].setup);
+	writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
+		AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
+		&smc->cs[2].pulse);
+	writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
+		&smc->cs[2].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		       AT91_SMC_MODE_EXNW_DISABLE |
+		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+		       AT91_SMC_MODE_TDF_CYCLE(1),
+		       &smc->cs[2].mode);
+#else
+	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[2].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
+		&smc->cs[2].pulse);
+	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
+		&smc->cs[2].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		       AT91_SMC_MODE_EXNW_DISABLE |
+		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+		       AT91_SMC_MODE_TDF_CYCLE(1),
+		       &smc->cs[2].mode);
+#endif
+
+	/* Configure Reset signal as output */
+	at91_set_gpio_output(AT91_PIN_PC10, 0);
+
+	/* Configure Interrupt pin as input, no pull-up */
+	at91_set_gpio_input(AT91_PIN_PC11, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
+}
+
+static void at91sam9261ek_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
+	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
+	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
+	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
+	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
+	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
+	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
+	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
+
+	at91_system_clk_enable(AT91_PMC_HCK1);
+
+	/* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
+#ifdef CONFIG_AT91SAM9261EK
+	gd->fb_base = ATMEL_BASE_SRAM;
+#endif
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		ATMEL_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i]->size;
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_AT91SAM9G10EK
+	/* arch number of AT91SAM9G10EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
+#else
+	/* arch number of AT91SAM9261EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
+#endif
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	at91_seriald_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91sam9261ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+	at91sam9261ek_dm9000_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	at91sam9261ek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_DRIVER_DM9000
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init();
+#endif
+}
+#endif

u-boot/board/atmel/at91sam9261ek/led.c

@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/io.h>
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}

u-boot/board/atmel/at91sam9261ek/partition.c

@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00083FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};

u-boot/board/atmel/at91sam9263ek/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9263EK
+
+config SYS_BOARD
+	default "at91sam9263ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9263ek"
+
+endif

u-boot/board/atmel/at91sam9263ek/MAINTAINERS

@@ -0,0 +1,10 @@
+AT91SAM9263EK BOARD
+M:	Stelian Pop <stelian@popies.net>
+S:	Maintained
+F:	board/atmel/at91sam9263ek/
+F:	include/configs/at91sam9263ek.h
+F:	configs/at91sam9263ek_dataflash_defconfig
+F:	configs/at91sam9263ek_dataflash_cs0_defconfig
+F:	configs/at91sam9263ek_nandflash_defconfig
+F:	configs/at91sam9263ek_norflash_defconfig
+F:	configs/at91sam9263ek_norflash_boot_defconfig

u-boot/board/atmel/at91sam9263ek/Makefile

@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += at91sam9263ek.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o

u-boot/board/atmel/at91sam9263ek/at91sam9263ek.c

@@ -0,0 +1,278 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+#include <atmel_mci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9263ek_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
+	at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Enable CS3 */
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_MODE_DBW_8 |
+#endif
+		       AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9263ek_macb_hw_init(void)
+{
+	at91_pio_t	*pio	= (at91_pio_t *) ATMEL_BASE_PIO;
+
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PC25) => PHY normal mode (not Test mode)
+	 * 	ERX0 (PE25) => PHY ADDR0
+	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(1 << 25, &pio->pioc.pudr);
+	writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
+
+	at91_phy_reset();
+
+	/* Re-enable pull-up */
+	writel(1 << 25, &pio->pioc.puer);
+	writel((1 << 25) | (1 <<26), &pio->pioe.puer);
+
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
+}
+
+static void at91sam9263ek_lcd_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
+	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
+
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+	gd->fb_base = ATMEL_BASE_SRAM0;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+#ifndef CONFIG_SYS_NO_FLASH
+extern flash_info_t flash_info[];
+#endif
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+#ifndef CONFIG_SYS_NO_FLASH
+	ulong flash_size;
+#endif
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		ATMEL_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i]->size;
+#ifndef CONFIG_SYS_NO_FLASH
+	flash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+		flash_size += flash_info[i].size;
+#endif
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
+		dram_size >> 20,
+		nand_size >> 20 );
+#ifndef CONFIG_SYS_NO_FLASH
+	lcd_printf (",\n  %ld MB NOR",
+		flash_size >> 20);
+#endif
+	lcd_puts ("\n");
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
+
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of AT91SAM9263EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	at91sam9263ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_set_pio_output(AT91_PIO_PORTE, 20, 1);	/* select spi0 clock */
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	at91sam9263ek_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	at91sam9263ek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}

u-boot/board/atmel/at91sam9263ek/led.c

@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/clk.h>
+
+void coloured_LED_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}

u-boot/board/atmel/at91sam9263ek/partition.c

@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00083FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};

u-boot/board/atmel/at91sam9m10g45ek/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9M10G45EK
+
+config SYS_BOARD
+	default "at91sam9m10g45ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9m10g45ek"
+
+endif

u-boot/board/atmel/at91sam9m10g45ek/MAINTAINERS

@@ -0,0 +1,7 @@
+AT91SAM9M10G45EK BOARD
+M:	Bo Shen <voice.shen@atmel.com>
+S:	Maintained
+F:	board/atmel/at91sam9m10g45ek/
+F:	include/configs/at91sam9m10g45ek.h
+F:	configs/at91sam9m10g45ek_mmc_defconfig
+F:	configs/at91sam9m10g45ek_nandflash_defconfig

u-boot/board/atmel/at91sam9m10g45ek/Makefile

@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += at91sam9m10g45ek.o
+obj-y += led.o

u-boot/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c

@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <linux/mtd/nand.h>
+#include <atmel_lcdc.h>
+#include <atmel_mci.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+void at91sam9m10g45ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+	/*
+	 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
+	 * test mode, so it needs do some action to exit test mode.
+	 */
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+	at91_set_gpio_output(AT91_PIN_PD7, 0);
+	at91_set_gpio_output(AT91_PIN_PD8, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+
+#ifdef CONFIG_SYS_USE_MMC
+	at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	at91sam9m10g45ek_nand_hw_init();
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_DQMS_SHARED |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+
+	ddr2->rtr = 0x24b;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void at91sam9m10g45ek_usb_hw_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+
+	at91_set_gpio_output(AT91_PIN_PD1, 0);
+	at91_set_gpio_output(AT91_PIN_PD3, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9m10g45ek_macb_hw_init(void)
+{
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *      RXDV (PA15) => PHY normal mode (not Test mode)
+	 *      ERX0 (PA12) => PHY ADDR0
+	 *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       &pioa->pudr);
+
+	at91_phy_reset();
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       &pioa->puer);
+
+	/* And the pins. */
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+
+vidinfo_t panel_info = {
+	.vl_col =		480,
+	.vl_row =		272,
+	.vl_clk =		9000000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_NORMAL |
+				ATMEL_LCDC_INVFRAME_NORMAL,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		45,
+	.vl_left_margin =	1,
+	.vl_right_margin =	1,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	40,
+	.vl_lower_margin =	1,
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+
+void lcd_enable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 0);	/* power down */
+}
+
+static void at91sam9m10g45ek_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
+	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
+
+	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
+	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
+	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
+	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
+	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
+	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
+	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
+
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+
+	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		ATMEL_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i]->size;
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of AT91SAM9M10G45EK-Board */
+#ifdef CONFIG_AT91SAM9M10G45EK
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
+#elif defined CONFIG_AT91SAM9G45EKES
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	at91sam9m10g45ek_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	at91sam9m10g45ek_usb_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4);
+#endif
+#ifdef CONFIG_MACB
+	at91sam9m10g45ek_macb_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	at91sam9m10g45ek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch(slave->cs) {
+		case 1:
+			at91_set_gpio_output(AT91_PIN_PB18, 0);
+			break;
+		case 0:
+		default:
+			at91_set_gpio_output(AT91_PIN_PB3, 0);
+			break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch(slave->cs) {
+		case 1:
+			at91_set_gpio_output(AT91_PIN_PB18, 1);
+			break;
+		case 0:
+		default:
+			at91_set_gpio_output(AT91_PIN_PB3, 1);
+		break;
+	}
+}
+#endif /* CONFIG_ATMEL_SPI */

u-boot/board/atmel/at91sam9m10g45ek/led.c

@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+void coloured_LED_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}

u-boot/board/atmel/at91sam9n12ek/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9N12EK
+
+config SYS_BOARD
+	default "at91sam9n12ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9n12ek"
+
+endif

u-boot/board/atmel/at91sam9n12ek/MAINTAINERS

@@ -0,0 +1,8 @@
+AT91SAM9N12EK BOARD
+M:	Josh Wu <josh.wu@atmel.com>
+S:	Maintained
+F:	board/atmel/at91sam9n12ek/
+F:	include/configs/at91sam9n12ek.h
+F:	configs/at91sam9n12ek_mmc_defconfig
+F:	configs/at91sam9n12ek_nandflash_defconfig
+F:	configs/at91sam9n12ek_spiflash_defconfig

u-boot/board/atmel/at91sam9n12ek/Makefile

@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Josh Wu <josh.wu@atmel.com>
+# Atmel corporation <www.atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= at91sam9n12ek.o

u-boot/board/atmel/at91sam9n12ek/at91sam9n12ek.c

@@ -0,0 +1,330 @@
+/*
+ * (C) Copyright 2013 Atmel Corporation
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <netdev.h>
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+#ifdef CONFIG_NAND_ATMEL
+static void at91sam9n12ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+	/* Configure databus */
+	csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
+	/* Configure IO drive */
+	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(1),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY pin */
+	at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
+
+	/* Configure ENABLE pin for NandFlash */
+	at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
+
+	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);    /* NAND OE */
+	at91_set_a_periph(AT91_PIO_PORTD, 1, 1);    /* NAND WE */
+	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);    /* ALE */
+	at91_set_a_periph(AT91_PIO_PORTD, 3, 1);    /* CLE */
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col = 480,
+	.vl_row = 272,
+	.vl_clk = 9000000,
+	.vl_bpix = LCD_BPP,
+	.vl_sync = 0,
+	.vl_tft = 1,
+	.vl_hsync_len = 5,
+	.vl_left_margin = 8,
+	.vl_right_margin = 43,
+	.vl_vsync_len = 10,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 12,
+	.mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 25, 0);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 25, 1);	/* power down */
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_printf("ATMEL Corp\n");
+	lcd_printf("at91@atmel.com\n");
+	lcd_printf("%s CPU at %s MHz\n",
+		ATMEL_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i]->size;
+	lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 0:
+		at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
+		break;
+	case 1:
+		at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
+		break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 0:
+		at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
+		break;
+	case 1:
+		at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
+		break;
+	}
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
+}
+#endif
+
+#ifdef CONFIG_KS8851_MLL
+void at91sam9n12ek_ks8851_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[2].setup);
+	writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
+	       AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
+	       &smc->cs[2].pulse);
+	writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
+	       &smc->cs[2].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+	       AT91_SMC_MODE_TDF_CYCLE(1),
+	       &smc->cs[2].mode);
+
+	/* Configure NCS2 PIN */
+	at91_set_b_periph(AT91_PIO_PORTD, 19, 0);
+}
+#endif
+
+#ifdef CONFIG_USB_ATMEL
+void at91sam9n12ek_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOAB);
+	at91_periph_clk_enable(ATMEL_ID_PIOCD);
+
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	at91sam9n12ek_nand_hw_init();
+#endif
+
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 0);
+#endif
+
+#ifdef CONFIG_LCD
+	at91_lcd_hw_init();
+#endif
+
+#ifdef CONFIG_KS8851_MLL
+	at91sam9n12ek_ks8851_hw_init();
+#endif
+
+#ifdef CONFIG_USB_ATMEL
+	at91sam9n12ek_usb_hw_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_KS8851_MLL
+int board_eth_init(bd_t *bis)
+{
+	return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+					CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	at91sam9n12ek_nand_hw_init();
+#elif CONFIG_SYS_USE_SPIFLASH
+	at91_spi0_hw_init(1 << 4);
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_13 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddrc_config ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+	csa |= AT91_MATRIX_EBI_DBPD_OFF;
+	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+	writel(csa, &matrix->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
+}
+#endif

u-boot/board/atmel/at91sam9rlek/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9RLEK
+
+config SYS_BOARD
+	default "at91sam9rlek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9rlek"
+
+endif

u-boot/board/atmel/at91sam9rlek/MAINTAINERS

@@ -0,0 +1,8 @@
+AT91SAM9RLEK BOARD
+M:	Stelian Pop <stelian@popies.net>
+S:	Maintained
+F:	board/atmel/at91sam9rlek/
+F:	include/configs/at91sam9rlek.h
+F:	configs/at91sam9rlek_dataflash_defconfig
+F:	configs/at91sam9rlek_nandflash_defconfig
+F:	configs/at91sam9rlek_mmc_defconfig

u-boot/board/atmel/at91sam9rlek/Makefile

@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += at91sam9rlek.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o

u-boot/board/atmel/at91sam9rlek/at91sam9rlek.c

@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9rl.h>
+#include <asm/arch/at91sam9rl_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#include <atmel_mci.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9rlek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	at91_set_A_periph(AT91_PIN_PB4, 0);		/* NANDOE */
+	at91_set_A_periph(AT91_PIN_PB5, 0);		/* NANDWE */
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
+}
+static void at91sam9rlek_lcd_hw_init(void)
+{
+	at91_set_B_periph(AT91_PIN_PC1, 0);	/* LCDPWR */
+	at91_set_A_periph(AT91_PIN_PC5, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDDEN */
+	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDCC */
+	at91_set_B_periph(AT91_PIN_PC9, 0);	/* LCDD3 */
+	at91_set_B_periph(AT91_PIN_PC10, 0);	/* LCDD4 */
+	at91_set_B_periph(AT91_PIN_PC11, 0);	/* LCDD5 */
+	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD6 */
+	at91_set_B_periph(AT91_PIN_PC13, 0);	/* LCDD7 */
+	at91_set_B_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
+	at91_set_B_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD13 */
+	at91_set_B_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
+	at91_set_B_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
+	at91_set_B_periph(AT91_PIN_PC20, 0);	/* LCDD18 */
+	at91_set_B_periph(AT91_PIN_PC21, 0);	/* LCDD19 */
+	at91_set_B_periph(AT91_PIN_PC22, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PC23, 0);	/* LCDD21 */
+	at91_set_B_periph(AT91_PIN_PC24, 0);	/* LCDD22 */
+	at91_set_B_periph(AT91_PIN_PC25, 0);	/* LCDD23 */
+
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		ATMEL_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i]->size;
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of AT91SAM9RLEK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	at91_seriald_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91sam9rlek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_LCD
+	at91sam9rlek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}

u-boot/board/atmel/at91sam9rlek/led.c

@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9rl.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+void coloured_LED_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}

u-boot/board/atmel/at91sam9rlek/partition.c

@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00083FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};

u-boot/board/atmel/at91sam9x5ek/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9X5EK
+
+config SYS_BOARD
+	default "at91sam9x5ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9x5ek"
+
+endif

u-boot/board/atmel/at91sam9x5ek/MAINTAINERS

@@ -0,0 +1,9 @@
+AT91SAM9X5EK BOARD
+M:	Bo Shen <voice.shen@atmel.com>
+S:	Maintained
+F:	board/atmel/at91sam9x5ek/
+F:	include/configs/at91sam9x5ek.h
+F:	configs/at91sam9x5ek_dataflash_defconfig
+F:	configs/at91sam9x5ek_mmc_defconfig
+F:	configs/at91sam9x5ek_nandflash_defconfig
+F:	configs/at91sam9x5ek_spiflash_defconfig

u-boot/board/atmel/at91sam9x5ek/Makefile

@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2012
+# Bo Shen <voice.shen@atmel.com>
+# Atmel corporation <www.atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += at91sam9x5ek.o

u-boot/board/atmel/at91sam9x5ek/at91sam9x5ek.c

@@ -0,0 +1,365 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <lcd.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#ifdef CONFIG_MACB
+#include <net.h>
+#endif
+#include <netdev.h>
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+#ifdef CONFIG_CMD_NAND
+static void at91sam9x5ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+	/* NAND flash on D16 */
+	csa |= AT91_MATRIX_NFD0_ON_D16;
+
+	/* Configure IO drive */
+	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(1),
+		&smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOCD);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
+	at91_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
+	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* NAND ALE */
+	at91_set_a_periph(AT91_PIO_PORTD, 3, 1);	/* NAND CLE */
+	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);
+	at91_set_a_periph(AT91_PIO_PORTD, 7, 1);
+	at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
+	at91_set_a_periph(AT91_PIO_PORTD, 9, 1);
+	at91_set_a_periph(AT91_PIO_PORTD, 10, 1);
+	at91_set_a_periph(AT91_PIO_PORTD, 11, 1);
+	at91_set_a_periph(AT91_PIO_PORTD, 12, 1);
+	at91_set_a_periph(AT91_PIO_PORTD, 13, 1);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	if (has_emac0())
+		rc = macb_eth_initialize(0,
+			(void *)ATMEL_BASE_EMAC0, 0x00);
+	if (has_emac1())
+		rc = macb_eth_initialize(1,
+			(void *)ATMEL_BASE_EMAC1, 0x00);
+#endif
+	return rc;
+}
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col	= 800,
+	.vl_row = 480,
+	.vl_clk = 24000000,
+	.vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL,
+	.vl_bpix = LCD_BPP,
+	.vl_tft = 1,
+	.vl_clk_pol = 1,
+	.vl_hsync_len = 128,
+	.vl_left_margin = 64,
+	.vl_right_margin = 64,
+	.vl_vsync_len = 2,
+	.vl_upper_margin = 22,
+	.vl_lower_margin = 21,
+	.mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+	if (has_lcdc())
+		at91_set_a_periph(AT91_PIO_PORTC, 29, 1);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	if (has_lcdc())
+		at91_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* power down */
+}
+
+static void at91sam9x5ek_lcd_hw_init(void)
+{
+	if (has_lcdc()) {
+		at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDPWM */
+		at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDVSYNC */
+		at91_set_a_periph(AT91_PIO_PORTC, 28, 0);	/* LCDHSYNC */
+		at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDISP */
+		at91_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* LCDDEN */
+		at91_set_a_periph(AT91_PIO_PORTC, 30, 0);	/* LCDPCK */
+
+		at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDD0 */
+		at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDD1 */
+		at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDD2 */
+		at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDD3 */
+		at91_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* LCDD4 */
+		at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* LCDD5 */
+		at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD6 */
+		at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD7 */
+		at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD8 */
+		at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD9 */
+		at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD10 */
+		at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD11 */
+		at91_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD12 */
+		at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD13 */
+		at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD14 */
+		at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD15 */
+		at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD16 */
+		at91_set_a_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD17 */
+		at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD18 */
+		at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD19 */
+		at91_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDD20 */
+		at91_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDD21 */
+		at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD22 */
+		at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD23 */
+
+		at91_periph_clk_enable(ATMEL_ID_LCDC);
+	}
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	if (has_lcdc()) {
+		lcd_printf("%s\n", U_BOOT_VERSION);
+		lcd_printf("(C) 2012 ATMEL Corp\n");
+		lcd_printf("at91support@atmel.com\n");
+		lcd_printf("%s CPU at %s MHz\n",
+			get_cpu_name(),
+			strmhz(temp, get_cpu_clk_rate()));
+
+		dram_size = 0;
+		for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+			dram_size += gd->bd->bi_dram[i].size;
+		nand_size = 0;
+		for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+			nand_size += nand_info[i]->size;
+		lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
+			dram_size >> 20,
+			nand_size >> 20);
+	}
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+		at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
+		break;
+	case 0:
+	default:
+		at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
+		break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+		at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
+		break;
+	case 0:
+	default:
+		at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
+		break;
+	}
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of AT91SAM9X5EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	at91sam9x5ek_nand_hw_init();
+#endif
+
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+	at91_macb_hw_init();
+#endif
+
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	at91sam9x5ek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+					CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	at91sam9x5ek_nand_hw_init();
+#elif CONFIG_SYS_USE_SPIFLASH
+	at91_spi0_hw_init(1 << 4);
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_13 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddrc_config ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+	csa |= AT91_MATRIX_EBI_DBPD_OFF;
+	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+	writel(csa, &matrix->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
+}
+#endif

u-boot/board/atmel/atngw100/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_ATNGW100
+
+config SYS_BOARD
+	default "atngw100"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at32ap700x"
+
+config SYS_CONFIG_NAME
+	default "atngw100"
+
+endif

u-boot/board/atmel/atngw100/MAINTAINERS

@@ -0,0 +1,6 @@
+ATNGW100 BOARD
+#M:	Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+S:	Orphan (since 2014-06)
+F:	board/atmel/atngw100/
+F:	include/configs/atngw100.h
+F:	configs/atngw100_defconfig

u-boot/board/atmel/atngw100/Makefile

@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	:= atngw100.o

u-boot/board/atmel/atngw100/atngw100.c

@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+	{
+		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
+					| MMU_VMR_CACHE_NONE,
+	}, {
+		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
+					| MMU_VMR_CACHE_WRBACK,
+	},
+};
+
+static const struct sdram_config sdram_config = {
+	.data_bits	= SDRAM_DATA_16BIT,
+	.row_bits	= 13,
+	.col_bits	= 9,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 5,
+	.txsr		= 5,
+	/* 7.81 us */
+	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+int board_early_init_f(void)
+{
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+	portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
+	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
+
+	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+#if defined(CONFIG_MACB)
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_ATMEL_SPI)
+	portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
+#endif
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	gd->bd->bi_phy_id[0] = 0x01;
+	gd->bd->bi_phy_id[1] = 0x03;
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+	return 0;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+#define ATNGW100_DATAFLASH_CS_PIN	GPIO_PIN_PA(3)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
+}
+#endif /* CONFIG_ATMEL_SPI */

u-boot/board/atmel/atngw100mkii/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_ATNGW100MKII
+
+config SYS_BOARD
+	default "atngw100mkii"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at32ap700x"
+
+config SYS_CONFIG_NAME
+	default "atngw100mkii"
+
+endif

u-boot/board/atmel/atngw100mkii/MAINTAINERS

@@ -0,0 +1,6 @@
+ATNGW100MKII BOARD
+M:	Andreas Bießmann <andreas@biessmann.org>
+S:	Maintained
+F:	board/atmel/atngw100mkii/
+F:	include/configs/atngw100mkii.h
+F:	configs/atngw100mkii_defconfig

u-boot/board/atmel/atngw100mkii/Makefile

@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	:= atngw100mkii.o

u-boot/board/atmel/atngw100mkii/atngw100mkii.c

@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2010 Atmel Corporation
+ *
+ * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+
+#include <spi.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+	{
+		/* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
+		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
+					| MMU_VMR_CACHE_NONE,
+	}, {
+		/* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
+		.virt_pgno	= EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT,
+		.nr_pages	= EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT,
+		.phys		= (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT)
+					| MMU_VMR_CACHE_NONE,
+	}, {
+		/* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
+		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
+					| MMU_VMR_CACHE_WRBACK,
+	},
+};
+
+static const struct sdram_config sdram_config = {
+	.data_bits	= SDRAM_DATA_32BIT,
+	.row_bits	= 13,
+	.col_bits	= 10,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 5,
+	.txsr		= 6,
+	/* 7.81 us */
+	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+int board_early_init_f(void)
+{
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
+			| HMATRIX_BIT(EBI_NAND_ENABLE));
+
+	portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
+			PORTMUX_DRIVE_HIGH);
+	portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
+			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
+			| PORTMUX_DRIVE_MIN);
+
+	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
+
+	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+#if defined(CONFIG_MACB)
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_ATMEL_SPI)
+	portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
+#endif
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	gd->bd->bi_phy_id[0] = 0x01;
+	gd->bd->bi_phy_id[1] = 0x03;
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+	return 0;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#define ATNGW100_DATAFLASH_CS_PIN	GPIO_PIN_PA(3)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
+}
+#endif /* CONFIG_ATMEL_SPI */

u-boot/board/atmel/atstk1000/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_ATSTK1002
+
+config SYS_BOARD
+	default "atstk1000"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at32ap700x"
+
+config SYS_CONFIG_NAME
+	default "atstk1002"
+
+endif

u-boot/board/atmel/atstk1000/MAINTAINERS

@@ -0,0 +1,6 @@
+ATSTK1000 BOARD
+M:	Andreas Bießmann <andreas.biessmann@corscience.de>
+S:	Maintained
+F:	board/atmel/atstk1000/
+F:	include/configs/atstk1002.h
+F:	configs/atstk1002_defconfig

u-boot/board/atmel/atstk1000/Makefile

@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y			+= atstk1000.o

u-boot/board/atmel/atstk1000/atstk1000.c

@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+	{
+		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
+					| MMU_VMR_CACHE_NONE,
+	}, {
+		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
+					| MMU_VMR_CACHE_WRBACK,
+	},
+};
+
+static const struct sdram_config sdram_config = {
+	.data_bits	= SDRAM_DATA_32BIT,
+#ifdef CONFIG_ATSTK1000_16MB_SDRAM
+	/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
+	.row_bits	= 12,
+#else
+	/* MT48LC2M32B2P-5 (8 MB) on motherboard */
+	.row_bits	= 11,
+#endif
+	.col_bits	= 8,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 5,
+	.txsr		= 5,
+	/* 15.6 us */
+	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
+};
+
+int board_early_init_f(void)
+{
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+	portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH);
+	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
+
+	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+#if defined(CONFIG_MACB)
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
+	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_MMC)
+	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	gd->bd->bi_phy_id[0] = 0x10;
+	gd->bd->bi_phy_id[1] = 0x11;
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+	return 0;
+}
+#endif

u-boot/board/atmel/sama5d2_ptc/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_SAMA5D2_PTC
+
+config SYS_BOARD
+	default "sama5d2_ptc"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama5d2_ptc"
+
+endif

u-boot/board/atmel/sama5d2_ptc/MAINTAINERS

@@ -0,0 +1,7 @@
+SAMA5D2 PTC Engineering BOARD
+M:	Wenyou Yang <wenyou.yang@atmel.com>
+S:	Maintained
+F:	board/atmel/sama5d2_ptc/
+F:	include/configs/sama5d2_ptc.h
+F:	configs/sama5d2_ptc_spiflash_defconfig
+F:	configs/sama5d2_ptc_nandflash_defconfig

u-boot/board/atmel/sama5d2_ptc/Makefile

@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Atmel
+#		     Wenyou Yang <wenyou.yang@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sama5d2_ptc.o

u-boot/board/atmel/sama5d2_ptc/sama5d2_ptc.c

@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2016 Atmel
+ *		      Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_hlcdc.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/sama5d2.h>
+#include <asm/arch/sama5d3_smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+}
+
+static void board_spi0_hw_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
+
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+
+static void board_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+
+	at91_periph_clk_enable(ATMEL_ID_HSMC);
+
+	writel(AT91_SFR_EBICFG_DRIVE0_HIGH |
+	       AT91_SFR_EBICFG_PULL0_NONE |
+	       AT91_SFR_EBICFG_DRIVE1_HIGH |
+	       AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);
+
+	/* Configure SMC CS3 for NAND */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+	       AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
+	       AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3) |
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0);	/* D0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0);	/* D1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0);	/* D2 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0);	/* D3 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0);	/* D4 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0);	/* D5 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0);	/* D6 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0);	/* D7 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0);	/* RE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0);	/* WE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1);	/* NCS */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1);	/* RDY */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1);	/* ALE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1);	/* CLE */
+}
+
+static void board_usb_hw_init(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
+}
+
+static void board_gmac_hw_init(void)
+{
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0);	/* GTXCK */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0);	/* GTXEN */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0);	/* GRXDV */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0);	/* GRXER */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0);	/* GRX0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0);	/* GRX1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0);	/* GTX0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0);	/* GTX1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0);	/* GMDC */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0);	/* GMDIO */
+
+	at91_periph_clk_enable(ATMEL_ID_GMAC);
+}
+
+static void board_uart0_hw_init(void)
+{
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1);	/* URXD0 */
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0);	/* UTXD0 */
+
+	at91_periph_clk_enable(CONFIG_USART_ID);
+}
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+	board_uart0_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+	board_spi0_hw_init();
+#endif
+#ifdef CONFIG_NAND_ATMEL
+	board_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	board_gmac_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	board_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+	if (rc)
+		printf("GMAC register failed\n");
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+	board_spi0_hw_init();
+#endif
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+	board_nand_hw_init();
+#endif
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
+
+	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
+		    ATMEL_MPDDRC_CR_DIC_DS |
+		    ATMEL_MPDDRC_CR_DIS_DLL |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddrc->rtr = 0x511;
+
+	ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+		      (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+	ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+		      (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+	ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+		      (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	struct atmel_mpddrc_config ddrc_config;
+	u32 reg;
+
+	ddrc_conf(&ddrc_config);
+
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	reg = readl(&mpddrc->io_calibr);
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+	writel(reg, &mpddrc->io_calibr);
+
+	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
+	       &mpddrc->rd_data_path);
+
+	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+	writel(0x3, &mpddrc->cal_mr4);
+	writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+	at91_plla_init(AT91_PMC_PLLAR_29 |
+		       AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+		       AT91_PMC_PLLXR_MUL(82) |
+		       AT91_PMC_PLLXR_DIV(1));
+
+	at91_pllicpr_init(0);
+
+	at91_mck_init(AT91_PMC_MCKR_H32MXDIV |
+		      AT91_PMC_MCKR_PLLADIV_2 |
+		      AT91_PMC_MCKR_MDIV_3 |
+		      AT91_PMC_MCKR_CSS_PLLA);
+}
+#endif

u-boot/board/atmel/sama5d2_xplained/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_SAMA5D2_XPLAINED
+
+config SYS_BOARD
+	default "sama5d2_xplained"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama5d2_xplained"
+
+endif

u-boot/board/atmel/sama5d2_xplained/MAINTAINERS

@@ -0,0 +1,7 @@
+SAMA5D2 XPLAINED BOARD
+M:	Wenyou Yang <wenyou.yang@atmel.com>
+S:	Maintained
+F:	board/atmel/sama5d2_xplained/
+F:	include/configs/sama5d2_xplained.h
+F:	configs/sama5d2_xplained_mmc_defconfig
+F:	configs/sama5d2_xplained_spiflash_defconfig

u-boot/board/atmel/sama5d2_xplained/Makefile

@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2015 Atmel Corporation
+#		     Wenyou Yang <wenyou.yang@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sama5d2_xplained.o

u-boot/board/atmel/sama5d2_xplained/sama5d2_xplained.c

@@ -0,0 +1,386 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ *		      Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_hlcdc.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+}
+
+static void board_spi0_hw_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
+
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+
+static void board_usb_hw_init(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
+}
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col = 480,
+	.vl_row = 272,
+	.vl_clk = 9000000,
+	.vl_bpix = LCD_BPP,
+	.vl_tft = 1,
+	.vl_hsync_len = 41,
+	.vl_left_margin = 2,
+	.vl_right_margin = 2,
+	.vl_vsync_len = 11,
+	.vl_upper_margin = 2,
+	.vl_lower_margin = 2,
+	.mmio = ATMEL_BASE_LCDC,
+};
+
+/* No power up/down pin for the LCD pannel */
+void lcd_enable(void)	{ /* Empty! */ }
+void lcd_disable(void)	{ /* Empty! */ }
+
+unsigned int has_lcdc(void)
+{
+	return 1;
+}
+
+static void board_lcd_hw_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0);	/* LCDPWM */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* LCDDISP */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0);	/* LCDVSYNC */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0);	/* LCDHSYNC */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTD,  0, 0);	/* LCDPCK */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTD,  1, 0);	/* LCDDEN */
+
+	/* LCDDAT0 */
+	/* LCDDAT1 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDDAT2 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDDAT3 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* LCDDAT4 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDDAT5 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDDAT6 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDDAT7 */
+
+	/* LCDDAT8 */
+	/* LCDDAT9 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDDAT10 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0);	/* LCDDAT11 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDDAT12 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDDAT13 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDDAT14 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDDAT15 */
+
+	/* LCDD16 */
+	/* LCDD17 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDDAT18 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDDAT19 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDAT20 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0);	/* LCDDAT21 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDDAT22 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDDAT23 */
+
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+	ulong dram_size;
+	int i;
+	char temp[32];
+
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_printf("2015 ATMEL Corp\n");
+	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
+		   strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+
+	lcd_printf("%ld MB SDRAM\n", dram_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+static void board_gmac_hw_init(void)
+{
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0);	/* GTXCK */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0);	/* GTXEN */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0);	/* GRXDV */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0);	/* GRXER */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0);	/* GRX0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0);	/* GRX1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0);	/* GTX0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0);	/* GTX1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0);	/* GMDC */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0);	/* GMDIO */
+
+	at91_periph_clk_enable(ATMEL_ID_GMAC);
+}
+
+static void board_sdhci0_hw_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* SDMMC0_CK */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* SDMMC0_CMD */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* SDMMC0_DAT0 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0);	/* SDMMC0_DAT1 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0);	/* SDMMC0_DAT2 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0);	/* SDMMC0_DAT3 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0);	/* SDMMC0_DAT4 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0);	/* SDMMC0_DAT5 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0);	/* SDMMC0_DAT6 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0);	/* SDMMC0_DAT7 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* SDMMC0_RSTN */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SDMMC0_VDDSEL */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SDMMC0_CD */
+
+	at91_periph_clk_enable(ATMEL_ID_SDMMC0);
+	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
+					 GCK_CSS_UPLL_CLK, 1);
+}
+
+static void board_sdhci1_hw_init(void)
+{
+	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0);	/* SDMMC1_DAT0 */
+	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0);	/* SDMMC1_DAT1 */
+	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0);	/* SDMMC1_DAT2 */
+	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0);	/* SDMMC1_DAT3 */
+	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0);	/* SDMMC1_CK */
+	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0);	/* SDMMC1_RSTN */
+	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0);	/* SDMMC1_CMD */
+	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0);	/* SDMMC1_CD */
+
+	at91_periph_clk_enable(ATMEL_ID_SDMMC1);
+	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
+					 GCK_CSS_UPLL_CLK, 1);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_ATMEL_SDHCI0
+	atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0);
+#endif
+#ifdef CONFIG_ATMEL_SDHCI1
+	atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1);
+#endif
+
+	return 0;
+}
+
+static void board_uart1_hw_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* URXD1 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);	/* UTXD1 */
+
+	at91_periph_clk_enable(ATMEL_ID_UART1);
+}
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+	board_uart1_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+	board_spi0_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SDHCI
+#ifdef CONFIG_ATMEL_SDHCI0
+	board_sdhci0_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SDHCI1
+	board_sdhci1_hw_init();
+#endif
+#endif
+#ifdef CONFIG_MACB
+	board_gmac_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	board_lcd_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	board_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+	board_spi0_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SDHCI
+#ifdef CONFIG_ATMEL_SDHCI0
+	board_sdhci0_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SDHCI1
+	board_sdhci1_hw_init();
+#endif
+#endif
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
+
+	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
+		    ATMEL_MPDDRC_CR_DIC_DS |
+		    ATMEL_MPDDRC_CR_DIS_DLL |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddrc->rtr = 0x511;
+
+	ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
+		      29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);
+
+	ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	struct atmel_mpddrc_config ddrc_config;
+	u32 reg;
+
+	ddrc_conf(&ddrc_config);
+
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	reg = readl(&mpddrc->io_calibr);
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+	writel(reg, &mpddrc->io_calibr);
+
+	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
+	       &mpddrc->rd_data_path);
+
+	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+	writel(0x3, &mpddrc->cal_mr4);
+	writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(82) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	writel(0x0 << 8, &pmc->pllicpr);
+
+	tmp = AT91_PMC_MCKR_H32MXDIV |
+	      AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif

u-boot/board/atmel/sama5d3_xplained/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_SAMA5D3_XPLAINED
+
+config SYS_BOARD
+	default "sama5d3_xplained"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "sama5d3_xplained"
+
+endif

u-boot/board/atmel/sama5d3_xplained/MAINTAINERS

@@ -0,0 +1,7 @@
+SAMA5D3_XPLAINED BOARD
+M:	Bo Shen <voice.shen@atmel.com>
+S:	Maintained
+F:	board/atmel/sama5d3_xplained/
+F:	include/configs/sama5d3_xplained.h
+F:	configs/sama5d3_xplained_mmc_defconfig
+F:	configs/sama5d3_xplained_nandflash_defconfig

u-boot/board/atmel/sama5d3_xplained/Makefile

@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2014
+# Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sama5d3_xplained.o

u-boot/board/atmel/sama5d3_xplained/sama5d3_xplained.c

@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2014 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <atmel_mci.h>
+#include <net.h>
+#include <netdev.h>
+#include <spl.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/at91_wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_ATMEL
+void sama5d3_xplained_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
+	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d3_xplained_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+static void sama5d3_xplained_mci0_hw_init(void)
+{
+	at91_mci_hw_init();
+
+	at91_set_pio_output(AT91_PIO_PORTE, 2, 0);	/* MCI0 Power */
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+	at91_seriald_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	sama5d3_xplained_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	sama5d3_xplained_usb_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	sama5d3_xplained_mci0_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	at91_gmac_hw_init();
+	at91_macb_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_MACB
+	macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+	macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+	atmel_mci_init((void *)ATMEL_BASE_MCI0);
+
+	return 0;
+}
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	sama5d3_xplained_mci0_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	sama5d3_xplained_nand_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_ENRDM_ON |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+	/*
+	 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
+	 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
+	 */
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	/* Enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(43) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
+
+	tmp = AT91_PMC_MCKR_MDIV_4 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif

u-boot/board/atmel/sama5d3xek/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_SAMA5D3XEK
+
+config SYS_BOARD
+	default "sama5d3xek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "sama5d3xek"
+
+endif

u-boot/board/atmel/sama5d3xek/MAINTAINERS

@@ -0,0 +1,8 @@
+SAMA5D3XEK BOARD
+M:	Bo Shen <voice.shen@atmel.com>
+S:	Maintained
+F:	board/atmel/sama5d3xek/
+F:	include/configs/sama5d3xek.h
+F:	configs/sama5d3xek_mmc_defconfig
+F:	configs/sama5d3xek_nandflash_defconfig
+F:	configs/sama5d3xek_spiflash_defconfig

u-boot/board/atmel/sama5d3xek/Makefile

@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sama5d3xek.o

u-boot/board/atmel/sama5d3xek/sama5d3xek.c

@@ -0,0 +1,473 @@
+/*
+ * Copyright (C) 2012 - 2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <linux/ctype.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <phy.h>
+#include <micrel.h>
+#include <net.h>
+#include <netdev.h>
+#include <spl.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/at91_wdt.h>
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+#include <asm/arch/atmel_usba_udc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_NAND_ATMEL
+void sama5d3xek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
+	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+}
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void sama5d3xek_nor_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS0 for NOR flash */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
+	       AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
+	       &smc->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
+	       &smc->cs[0].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0)  |
+	       AT91_SMC_TIMINGS_TAR(0)  | AT91_SMC_TIMINGS_TRR(0)   |
+	       AT91_SMC_TIMINGS_TWB(0)  | AT91_SMC_TIMINGS_RBNSEL(0)|
+	       AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_16 |
+	       AT91_SMC_MODE_TDF_CYCLE(1),
+	       &smc->cs[0].mode);
+
+	/* Address pin (A1 ~ A23) configuration */
+	at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 12, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 13, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 14, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 15, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 16, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 17, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 18, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 19, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 20, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 21, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 22, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 23, 0);
+	/* CS0 pin configuration */
+	at91_set_a_periph(AT91_PIO_PORTE, 26, 0);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d3xek_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
+	at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
+	at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+static void sama5d3xek_mci_hw_init(void)
+{
+	at91_mci_hw_init();
+
+	at91_set_pio_output(AT91_PIO_PORTB, 10, 0);	/* MCI0 Power */
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col = 800,
+	.vl_row = 480,
+	.vl_clk = 24000000,
+	.vl_bpix = LCD_BPP,
+	.vl_tft = 1,
+	.vl_hsync_len = 128,
+	.vl_left_margin = 64,
+	.vl_right_margin = 64,
+	.vl_vsync_len = 2,
+	.vl_upper_margin = 22,
+	.vl_lower_margin = 21,
+	.mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+static void sama5d3xek_lcd_hw_init(void)
+{
+	gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
+
+	/* The higher 8 bit of LCD is board related */
+	at91_set_c_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD16 */
+	at91_set_c_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD17 */
+	at91_set_c_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD18 */
+	at91_set_c_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD19 */
+	at91_set_c_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD20 */
+	at91_set_c_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD21 */
+	at91_set_c_periph(AT91_PIO_PORTE, 27, 0);	/* LCDD22 */
+	at91_set_c_periph(AT91_PIO_PORTE, 28, 0);	/* LCDD23 */
+
+	/* Configure lower 16 bit of LCD and enable clock */
+	at91_lcd_hw_init();
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size;
+	uint64_t nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_printf("(C) 2013 ATMEL Corp\n");
+	lcd_printf("at91@atmel.com\n");
+	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
+		   strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+
+	nand_size = 0;
+#ifdef CONFIG_NAND_ATMEL
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i]->size;
+#endif
+	lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
+		   dram_size >> 20, nand_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+	at91_seriald_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	sama5d3xek_nand_hw_init();
+#endif
+#ifndef CONFIG_SYS_NO_FLASH
+	sama5d3xek_nor_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	sama5d3xek_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	sama5d3xek_mci_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	if (has_emac())
+		at91_macb_hw_init();
+	if (has_gmac())
+		at91_gmac_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	if (has_lcdc())
+		sama5d3xek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* board specific timings for GMAC */
+	if (has_gmac()) {
+		/* rx data delay */
+		ksz9021_phy_extended_write(phydev,
+					   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+					   0x2222);
+		/* tx data delay */
+		ksz9021_phy_extended_write(phydev,
+					   MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+					   0x2222);
+		/* rx/tx clock delay */
+		ksz9021_phy_extended_write(phydev,
+					   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+					   0xf2f4);
+	}
+
+	/* always run the PHY's config routine */
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	if (has_emac())
+		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+	if (has_gmac())
+		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+	int rc = 0;
+
+	rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
+
+	return rc;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 4;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 0:
+		at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
+	case 1:
+		at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
+	case 2:
+		at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
+	case 3:
+		at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
+	default:
+		break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 0:
+		at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
+	case 1:
+		at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
+	case 2:
+		at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
+	case 3:
+		at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
+	default:
+		break;
+	}
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	const int MAX_STR_LEN = 32;
+	char name[MAX_STR_LEN], *p;
+	int i;
+
+	strncpy(name, get_cpu_name(), MAX_STR_LEN);
+	for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++)
+		*p = tolower(*p);
+
+	strcat(name, "ek.dtb");
+	setenv("dtb_name", name);
+#endif
+	return 0;
+}
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	sama5d3xek_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	sama5d3xek_nand_hw_init();
+#elif CONFIG_SYS_USE_SERIALFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_ENRDM_ON |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+	/*
+	 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
+	 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
+	 */
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	/* Enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(43) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
+
+	tmp = AT91_PMC_MCKR_MDIV_4 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif

u-boot/board/atmel/sama5d4_xplained/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_SAMA5D4_XPLAINED
+
+config SYS_BOARD
+	default "sama5d4_xplained"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "sama5d4_xplained"
+
+endif

u-boot/board/atmel/sama5d4_xplained/MAINTAINERS

@@ -0,0 +1,8 @@
+SAMA5D4 XPLAINED ULTRA BOARD
+M:	Bo Shen <voice.shen@atmel.com>
+S:	Maintained
+F:	board/atmel/sama5d4_xplained/
+F:	include/configs/sama5d4_xplained.h
+F:	configs/sama5d4_xplained_mmc_defconfig
+F:	configs/sama5d4_xplained_nandflash_defconfig
+F:	configs/sama5d4_xplained_spiflash_defconfig

u-boot/board/atmel/sama5d4_xplained/Makefile

@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2014 Atmel
+#		     Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sama5d4_xplained.o

u-boot/board/atmel/sama5d4_xplained/sama5d4_xplained.c

@@ -0,0 +1,415 @@
+/*
+ * Copyright (C) 2014 Atmel
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/sama5d4.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+#include <spi.h>
+#include <version.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+}
+
+static void sama5d4_xplained_spi0_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
+
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_NAND_ATMEL
+static void sama5d4_xplained_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS3 for NAND */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+	       AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
+	       AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3)|
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* D0 */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* D1 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* D2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* D3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* D4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* D5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* D6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* D7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* RE */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* WE */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 1);	/* NCS */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 1);	/* RDY */
+	at91_set_a_periph(AT91_PIO_PORTC, 17, 1);	/* ALE */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 1);	/* CLE */
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d4_xplained_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
+	at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col = 480,
+	.vl_row = 272,
+	.vl_clk = 9000000,
+	.vl_bpix = LCD_BPP,
+	.vl_tft = 1,
+	.vl_hsync_len = 41,
+	.vl_left_margin = 2,
+	.vl_right_margin = 2,
+	.vl_vsync_len = 11,
+	.vl_upper_margin = 2,
+	.vl_lower_margin = 2,
+	.mmio = ATMEL_BASE_LCDC,
+};
+
+/* No power up/down pin for the LCD pannel */
+void lcd_enable(void)	{ /* Empty! */ }
+void lcd_disable(void)	{ /* Empty! */ }
+
+unsigned int has_lcdc(void)
+{
+	return 1;
+}
+
+static void sama5d4_xplained_lcd_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTA, 24, 0);	/* LCDPWM */
+	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
+	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 29, 0);	/* LCDDEN */
+
+	at91_set_a_periph(AT91_PIO_PORTA,  0, 0);	/* LCDD0 */
+	at91_set_a_periph(AT91_PIO_PORTA,  1, 0);	/* LCDD1 */
+	at91_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
+
+	at91_set_a_periph(AT91_PIO_PORTA,  8, 0);	/* LCDD9 */
+	at91_set_a_periph(AT91_PIO_PORTA,  9, 0);	/* LCDD8 */
+	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
+
+	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* LCDD16 */
+	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* LCDD17 */
+	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* LCDD20 */
+	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTA, 22, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTA, 23, 0);	/* LCDD23 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_printf("2014 ATMEL Corp\n");
+	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
+		   strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+
+	nand_size = 0;
+#ifdef CONFIG_NAND_ATMEL
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i]->size;
+#endif
+	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
+		   dram_size >> 20, nand_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+
+#endif /* CONFIG_LCD */
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void sama5d4_xplained_mci1_hw_init(void)
+{
+	at91_set_c_periph(AT91_PIO_PORTE, 19, 1);	/* MCI1 CDA */
+	at91_set_c_periph(AT91_PIO_PORTE, 20, 1);	/* MCI1 DA0 */
+	at91_set_c_periph(AT91_PIO_PORTE, 21, 1);	/* MCI1 DA1 */
+	at91_set_c_periph(AT91_PIO_PORTE, 22, 1);	/* MCI1 DA2 */
+	at91_set_c_periph(AT91_PIO_PORTE, 23, 1);	/* MCI1 DA3 */
+	at91_set_c_periph(AT91_PIO_PORTE, 18, 0);	/* MCI1 CLK */
+
+	/*
+	 * As the mci io internal pull down is too strong, so if the io needs
+	 * external pull up, the pull up resistor will be very small, if so
+	 * the power consumption will increase, so disable the interanl pull
+	 * down to save the power.
+	 */
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI1);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	/* Enable the power supply */
+	at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+}
+#endif /* CONFIG_GENERIC_ATMEL_MCI */
+
+#ifdef CONFIG_MACB
+void sama5d4_xplained_macb0_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
+	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
+	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
+	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
+	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_GMAC0);
+}
+#endif
+
+static void sama5d4_xplained_serial3_hw_init(void)
+{
+	at91_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
+	at91_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART3);
+}
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+	sama5d4_xplained_serial3_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+	sama5d4_xplained_spi0_hw_init();
+#endif
+#ifdef CONFIG_NAND_ATMEL
+	sama5d4_xplained_nand_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	sama5d4_xplained_mci1_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	sama5d4_xplained_macb0_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	sama5d4_xplained_lcd_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	sama5d4_xplained_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	sama5d4_xplained_mci1_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	sama5d4_xplained_nand_hw_init();
+#elif CONFIG_SYS_USE_SERIALFLASH
+	sama5d4_xplained_spi0_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddr2->rtr = 0x2b0;
+
+	ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	/* Enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(87) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
+
+	tmp = AT91_PMC_MCKR_H32MXDIV |
+	      AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif

u-boot/board/atmel/sama5d4ek/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_SAMA5D4EK
+
+config SYS_BOARD
+	default "sama5d4ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "sama5d4ek"
+
+endif

u-boot/board/atmel/sama5d4ek/MAINTAINERS

@@ -0,0 +1,8 @@
+SAMA5D4EK BOARD
+M:	Bo Shen <voice.shen@atmel.com>
+S:	Maintained
+F:	board/atmel/sama5d4ek/
+F:	include/configs/sama5d4ek.h
+F:	configs/sama5d4ek_mmc_defconfig
+F:	configs/sama5d4ek_nandflash_defconfig
+F:	configs/sama5d4ek_spiflash_defconfig

u-boot/board/atmel/sama5d4ek/Makefile

@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2014 Atmel
+#		     Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sama5d4ek.o

u-boot/board/atmel/sama5d4ek/sama5d4ek.c

@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) 2014 Atmel
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/sama5d4.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+#include <spi.h>
+#include <version.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+}
+
+static void sama5d4ek_spi0_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
+
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_NAND_ATMEL
+static void sama5d4ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS3 for NAND */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+	       AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
+	       AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3)|
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* D0 */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* D1 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* D2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* D3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* D4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* D5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* D6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* D7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* RE */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* WE */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 1);	/* NCS */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 1);	/* RDY */
+	at91_set_a_periph(AT91_PIO_PORTC, 17, 1);	/* ALE */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 1);	/* CLE */
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d4ek_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col = 800,
+	.vl_row = 480,
+	.vl_clk = 33260000,
+	.vl_bpix = LCD_BPP,
+	.vl_tft = 1,
+	.vl_hsync_len = 5,
+	.vl_left_margin = 128,
+	.vl_right_margin = 0,
+	.vl_vsync_len = 5,
+	.vl_upper_margin = 23,
+	.vl_lower_margin = 22,
+	.mmio = ATMEL_BASE_LCDC,
+};
+
+/* No power up/down pin for the LCD pannel */
+void lcd_enable(void)	{ /* Empty! */ }
+void lcd_disable(void)	{ /* Empty! */ }
+
+unsigned int has_lcdc(void)
+{
+	return 1;
+}
+
+static void sama5d4ek_lcd_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTA, 24, 0);	/* LCDPWM */
+	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
+	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 29, 0);	/* LCDDEN */
+
+	at91_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
+
+	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
+
+	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* LCDD20 */
+	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTA, 22, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTA, 23, 0);	/* LCDD23 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_printf("2014 ATMEL Corp\n");
+	lcd_printf("at91@atmel.com\n");
+	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
+		   strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+
+	nand_size = 0;
+#ifdef CONFIG_NAND_ATMEL
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i]->size;
+#endif
+	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
+		   dram_size >> 20, nand_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+
+#endif /* CONFIG_LCD */
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void sama5d4ek_mci1_hw_init(void)
+{
+	at91_set_c_periph(AT91_PIO_PORTE, 19, 1);	/* MCI1 CDA */
+	at91_set_c_periph(AT91_PIO_PORTE, 20, 1);	/* MCI1 DA0 */
+	at91_set_c_periph(AT91_PIO_PORTE, 21, 1);	/* MCI1 DA1 */
+	at91_set_c_periph(AT91_PIO_PORTE, 22, 1);	/* MCI1 DA2 */
+	at91_set_c_periph(AT91_PIO_PORTE, 23, 1);	/* MCI1 DA3 */
+	at91_set_c_periph(AT91_PIO_PORTE, 18, 0);	/* MCI1 CLK */
+
+	/*
+	 * As the mci io internal pull down is too strong, so if the io needs
+	 * external pull up, the pull up resistor will be very small, if so
+	 * the power consumption will increase, so disable the interanl pull
+	 * down to save the power.
+	 */
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI1);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	/* Enable power for MCI1 interface */
+	at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+}
+#endif /* CONFIG_GENERIC_ATMEL_MCI */
+
+#ifdef CONFIG_MACB
+void sama5d4ek_macb0_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
+	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
+	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
+	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
+	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_GMAC0);
+}
+#endif
+
+static void sama5d4ek_serial3_hw_init(void)
+{
+	at91_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
+	at91_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART3);
+}
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+	sama5d4ek_serial3_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+	sama5d4ek_spi0_hw_init();
+#endif
+#ifdef CONFIG_NAND_ATMEL
+	sama5d4ek_nand_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	sama5d4ek_mci1_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	sama5d4ek_macb0_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	sama5d4ek_lcd_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	sama5d4ek_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	sama5d4ek_mci1_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	sama5d4ek_nand_hw_init();
+#elif CONFIG_SYS_USE_SERIALFLASH
+	sama5d4ek_spi0_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddr2->rtr = 0x2b0;
+
+	ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	/* Enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(87) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
+
+	tmp = AT91_PMC_MCKR_H32MXDIV |
+	      AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif