avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions

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if TARGET_ODROID_C2
config SYS_BOARD
default "odroid-c2"
config SYS_VENDOR
default "amlogic"
config SYS_CONFIG_NAME
default "odroid-c2"
endif

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ODROID-C2
M: Beniamino Galvani <b.galvani@gmail.com>
S: Maintained
F: board/amlogic/odroid-c2/
F: include/configs/odroid-c2.h
F: configs/odroid-c2_defconfig

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#
# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := odroid-c2.o

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U-Boot for ODROID-C2
====================
ODROID-C2 is a single board computer manufactured by Hardkernel
Co. Ltd with the following specifications:
- Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
- Gigabit Ethernet
- HDMI 2.0 4K/60Hz display
- 40-pin GPIO header
- 4 x USB 2.0 Host, 1 x USB OTG
- eMMC, microSD
- Infrared receiver
Schematics are available on the manufacturer website.
Currently the u-boot port supports the following devices:
- serial
- Ethernet
u-boot compilation
==================
> export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make odroid-c2_defconfig
> make
Image creation
==============
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
> DIR=odroid-c2
> git clone --depth 1 \
https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
$DIR
> $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \
--bl301 $DIR/fip/gxb/bl301.bin \
--bl31 $DIR/fip/gxb/bl31.bin \
--bl33 u-boot.bin \
$DIR/fip.bin
> $DIR/fip/fip_create --dump $DIR/fip.bin
> cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin
> $DIR/fip/gxb/aml_encrypt_gxb --bootsig \
--input $DIR/boot_new.bin \
--output $DIR/u-boot.img
> dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96
and then write the image to SD with:
> DEV=/dev/your_sd_device
> BL1=$DIR/sd_fuse/bl1.bin.hardkernel
> dd if=$BL1 of=$DEV conv=fsync bs=1 count=442
> dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1
> dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97

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/*
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gxbb.h>
#include <asm/arch/sm.h>
#include <dm/platdata.h>
#include <phy.h>
#define EFUSE_SN_OFFSET 20
#define EFUSE_SN_SIZE 16
#define EFUSE_MAC_OFFSET 52
#define EFUSE_MAC_SIZE 6
int board_init(void)
{
return 0;
}
static const struct eth_pdata gxbb_eth_pdata = {
.iobase = GXBB_ETH_BASE,
.phy_interface = PHY_INTERFACE_MODE_RGMII,
};
U_BOOT_DEVICE(meson_eth) = {
.name = "eth_designware",
.platdata = &gxbb_eth_pdata,
};
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
ssize_t len;
/* Select Ethernet function */
setbits_le32(GXBB_PINMUX(6), 0x3fff);
/* Set RGMII mode */
setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
GXBB_ETH_REG_0_TX_PHASE(1) |
GXBB_ETH_REG_0_TX_RATIO(4) |
GXBB_ETH_REG_0_PHY_CLK_EN |
GXBB_ETH_REG_0_CLK_EN);
/* Enable power and clock gate */
setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
/* Reset PHY on GPIOZ_14 */
clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
mdelay(10);
setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
return 0;
}