Kevin/Jibo-Platform-Tools-OLD
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

avionic design with actual uboot and tooling

Browse Source 
submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

136
u-boot/arch/x86/include/asm/acpi/debug.asl Normal file
View File

@@ -0,0 +1,136 @@
/*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/arch/x86/acpi/debug.asl
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* POST register region */
OperationRegion(X80, SystemIO, 0x80, 1)
Field(X80, ByteAcc, NoLock, Preserve)
{
P80, 8
}
/* Legacy serial port register region */
OperationRegion(CREG, SystemIO, 0x3F8, 8)
Field(CREG, ByteAcc, NoLock, Preserve)
{
CDAT, 8,
CDLM, 8,
, 8,
CLCR, 8,
CMCR, 8,
CLSR, 8
}
/* DINI - Initialize the serial port to 115200 8-N-1 */
Method(DINI)
{
Store(0x83, CLCR)
Store(0x01, CDAT) /* 115200 baud (low) */
Store(0x00, CDLM) /* 115200 baud (high) */
Store(0x03, CLCR) /* word=8 stop=1 parity=none */
Store(0x03, CMCR) /* DTR=1 RTS=1 out1/2=Off loop=Off */
Store(0x00, CDLM) /* turn off interrupts */
}
/* THRE - Wait for serial port transmitter holding register to go empty */
Method(THRE)
{
And(CLSR, 0x20, Local0)
While (LEqual(Local0, Zero)) {
And(CLSR, 0x20, Local0)
}
}
/* OUTX - Send a single raw character */
Method(OUTX, 1)
{
THRE()
Store(Arg0, CDAT)
}
/* OUTC - Send a single character, expanding LF into CR/LF */
Method(OUTC, 1)
{
If (LEqual(Arg0, 0x0a)) {
OUTX(0x0d)
}
OUTX(Arg0)
}
/* DBGN - Send a single hex nibble */
Method(DBGN, 1)
{
And(Arg0, 0x0f, Local0)
If (LLess(Local0, 10)) {
Add(Local0, 0x30, Local0)
} Else {
Add(Local0, 0x37, Local0)
}
OUTC(Local0)
}
/* DBGB - Send a hex byte */
Method(DBGB, 1)
{
ShiftRight(Arg0, 4, Local0)
DBGN(Local0)
DBGN(Arg0)
}
/* DBGW - Send a hex word */
Method(DBGW, 1)
{
ShiftRight(Arg0, 8, Local0)
DBGB(Local0)
DBGB(Arg0)
}
/* DBGD - Send a hex dword */
Method(DBGD, 1)
{
ShiftRight(Arg0, 16, Local0)
DBGW(Local0)
DBGW(Arg0)
}
/* Get a char from a string */
Method(GETC, 2)
{
CreateByteField(Arg0, Arg1, DBGC)
Return (DBGC)
}
/* DBGO - Send either a string or an integer */
Method(DBGO, 1, Serialized)
{
If (LEqual(ObjectType(Arg0), 1)) {
If (LGreater(Arg0, 0xffff)) {
DBGD(Arg0)
} Else {
If (LGreater(Arg0, 0xff)) {
DBGW(Arg0)
} Else {
DBGB(Arg0)
}
}
} Else {
Name(BDBG, Buffer(80) {})
Store(Arg0, BDBG)
Store(0, Local1)
While (One) {
Store(GETC(BDBG, Local1), Local0)
If (LEqual(Local0, 0)) {
Return (Zero)
}
OUTC(Local0)
Increment(Local1)
}
}
Return (Zero)
}

113
u-boot/arch/x86/include/asm/acpi/globutil.asl Normal file
View File

@@ -0,0 +1,113 @@
/*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/arch/x86/acpi/globutil.asl
*
* SPDX-License-Identifier: GPL-2.0+
*/
Method(MIN, 2)
{
If (LLess(Arg0, Arg1)) {
Return (Arg0)
} Else {
Return (Arg1)
}
}
Method(SLEN, 1)
{
Store(Arg0, Local0)
Return (Sizeof(Local0))
}
Method(S2BF, 1, Serialized)
{
Add(SLEN(Arg0), One, Local0)
Name(BUFF, Buffer(Local0) {})
Store(Arg0, BUFF)
Return (BUFF)
}
/*
* SCMP - Strong string compare
*
* Checks both length and content
*/
Method(SCMP, 2)
{
Store(S2BF(Arg0), Local0)
Store(S2BF(Arg1), Local1)
Store(Zero, Local4)
Store(SLEN(Arg0), Local5)
Store(SLEN(Arg1), Local6)
Store(MIN(Local5, Local6), Local7)
While (LLess(Local4, Local7)) {
Store(Derefof(Index(Local0, Local4)), Local2)
Store(Derefof(Index(Local1, Local4)), Local3)
If (LGreater(Local2, Local3)) {
Return (One)
} Else {
If (LLess(Local2, Local3)) {
Return (Ones)
}
}
Increment(Local4)
}
If (LLess(Local4, Local5)) {
Return (One)
} Else {
If (LLess(Local4, Local6)) {
Return (Ones)
} Else {
Return (Zero)
}
}
}
/*
* WCMP - Weak string compare
*
* Checks to find Arg1 at beginning of Arg0.
* Fails if length(Arg0) < length(Arg1).
* Returns 0 on fail, 1 on pass.
*/
Method(WCMP, 2)
{
Store(S2BF(Arg0), Local0)
Store(S2BF(Arg1), Local1)
If (LLess(SLEN(Arg0), SLEN(Arg1))) {
Return (Zero)
}
Store(Zero, Local2)
Store(SLEN(Arg1), Local3)
While (LLess(Local2, Local3)) {
If (LNotEqual(Derefof(Index(Local0, Local2)),
Derefof(Index(Local1, Local2)))) {
Return (Zero)
}
Increment(Local2)
}
Return (One)
}
/*
* I2BM - Returns Bit Map
*
* Arg0 = IRQ Number (0-15)
*/
Method(I2BM, 1)
{
Store(0, Local0)
If (LNotEqual(Arg0, 0)) {
Store(1, Local1)
ShiftLeft(Local1, Arg0, Local0)
}
Return (Local0)
}

111
u-boot/arch/x86/include/asm/acpi/irq_helper.h Normal file
View File

@@ -0,0 +1,111 @@
/*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2014 Sage Electronics Engineering, LLC.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* This file intentionally gets included multiple times, to set pic and apic
* modes, so should not have guard statements added.
*/
/*
* This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
* routing for the platform being compiled.
*
* This method uses #defines in irqroute.h along with the macros contained
* in this file to generate an IRQ routing for each PCI device in the system.
*/
#undef PCI_DEV_PIRQ_ROUTES
#undef PCI_DEV_PIRQ_ROUTE
#undef ACPI_DEV_IRQ
#undef PCIE_BRIDGE_DEV
#undef RP_IRQ_ROUTES
#undef ROOTPORT_METHODS
#undef ROOTPORT_IRQ_ROUTES
#undef RP_METHOD
#if defined(PIC_MODE)
#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
Name(prefix_ ## func_ ## P, Package() \
{ \
ACPI_DEV_IRQ(0x0000, 0, a_), \
ACPI_DEV_IRQ(0x0000, 1, b_), \
ACPI_DEV_IRQ(0x0000, 2, c_), \
ACPI_DEV_IRQ(0x0000, 3, d_), \
})
/* define as blank so ROOTPORT_METHODS only gets inserted once */
#define ROOTPORT_METHODS(prefix_, dev_)
#else /* defined(PIC_MODE) */
#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
Name(prefix_ ## func_ ## A, Package() \
{ \
ACPI_DEV_IRQ(0x0000, 0, a_), \
ACPI_DEV_IRQ(0x0000, 1, b_), \
ACPI_DEV_IRQ(0x0000, 2, c_), \
ACPI_DEV_IRQ(0x0000, 3, d_), \
})
#define ROOTPORT_METHODS(prefix_, dev_) \
RP_METHOD(prefix_, dev_, 0) \
RP_METHOD(prefix_, dev_, 1) \
RP_METHOD(prefix_, dev_, 2) \
RP_METHOD(prefix_, dev_, 3) \
RP_METHOD(prefix_, dev_, 4) \
RP_METHOD(prefix_, dev_, 5) \
RP_METHOD(prefix_, dev_, 6) \
RP_METHOD(prefix_, dev_, 7)
#endif /* defined(PIC_MODE) */
#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
ACPI_DEV_IRQ(dev_, 0, a_), \
ACPI_DEV_IRQ(dev_, 1, b_), \
ACPI_DEV_IRQ(dev_, 2, c_), \
ACPI_DEV_IRQ(dev_, 3, d_)
#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
ROOTPORT_METHODS(prefix_, dev_)
#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
#define RP_METHOD(prefix_, dev_, func_)\
Device (prefix_ ## 0 ## func_) \
{ \
Name(_ADR, dev_ ## 000 ## func_) \
Name(_PRW, Package() { 0, 0 }) \
Method(_PRT) { \
If (PICM) { \
Return (prefix_ ## func_ ## A) \
} Else { \
Return (prefix_ ## func_ ## P) \
} \
} \
}
/* SoC specific PIRQ route configuration */
#include <asm/arch/acpi/irqroute.h>

486
u-boot/arch/x86/include/asm/acpi/irqlinks.asl Normal file
View File

@@ -0,0 +1,486 @@
/*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Intel chipset PIRQ routing control ASL description
*
* The programming interface is common to most Intel chipsets. But the PRTx
* registers may be mapped to different blocks. Some chipsets map them to LPC
* device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while
* some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy
* Block (ILB) memory space.
*
* This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines
* PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be
* defined somewhere else in the platform's ASL files.
*/
Device (LNKA)
{
Name(_HID, EISAID("PNP0C0F"))
Name(_UID, 1)
/* Disable method */
Method(_DIS, 0, Serialized)
{
Store(0x80, PRTA)
}
/* Possible Resource Settings for this Link */
Name(_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
})
/* Current Resource Settings for this link */
Method(_CRS, 0, Serialized)
{
Name(RTLA, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLA, 1, IRQ0)
/* Clear the WordField */
Store(Zero, IRQ0)
/* Set the bit from PRTA */
ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
Return (RTLA)
}
/* Set Resource Setting for this IRQ link */
Method(_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
/* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTA)
}
/* Status */
Method(_STA, 0, Serialized)
{
If (And(PRTA, 0x80)) {
Return (STA_DISABLED)
} Else {
Return (STA_INVISIBLE)
}
}
}
Device (LNKB)
{
Name(_HID, EISAID("PNP0C0F"))
Name(_UID, 2)
/* Disable method */
Method(_DIS, 0, Serialized)
{
Store(0x80, PRTB)
}
/* Possible Resource Settings for this Link */
Name(_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
})
/* Current Resource Settings for this link */
Method(_CRS, 0, Serialized)
{
Name(RTLB, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLB, 1, IRQ0)
/* Clear the WordField */
Store(Zero, IRQ0)
/* Set the bit from PRTB */
ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
Return (RTLB)
}
/* Set Resource Setting for this IRQ link */
Method(_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
/* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTB)
}
/* Status */
Method(_STA, 0, Serialized)
{
If (And(PRTB, 0x80)) {
Return (STA_DISABLED)
} Else {
Return (STA_INVISIBLE)
}
}
}
Device (LNKC)
{
Name(_HID, EISAID("PNP0C0F"))
Name(_UID, 3)
/* Disable method */
Method(_DIS, 0, Serialized)
{
Store(0x80, PRTC)
}
/* Possible Resource Settings for this Link */
Name(_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
})
/* Current Resource Settings for this link */
Method(_CRS, 0, Serialized)
{
Name(RTLC, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLC, 1, IRQ0)
/* Clear the WordField */
Store(Zero, IRQ0)
/* Set the bit from PRTC */
ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
Return (RTLC)
}
/* Set Resource Setting for this IRQ link */
Method(_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
/* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTC)
}
/* Status */
Method(_STA, 0, Serialized)
{
If (And(PRTC, 0x80)) {
Return (STA_DISABLED)
} Else {
Return (STA_INVISIBLE)
}
}
}
Device (LNKD)
{
Name(_HID, EISAID("PNP0C0F"))
Name(_UID, 4)
/* Disable method */
Method(_DIS, 0, Serialized)
{
Store(0x80, PRTD)
}
/* Possible Resource Settings for this Link */
Name(_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
})
/* Current Resource Settings for this link */
Method(_CRS, 0, Serialized)
{
Name(RTLD, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLD, 1, IRQ0)
/* Clear the WordField */
Store(Zero, IRQ0)
/* Set the bit from PRTD */
ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
Return (RTLD)
}
/* Set Resource Setting for this IRQ link */
Method(_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
/* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTD)
}
/* Status */
Method(_STA, 0, Serialized)
{
If (And(PRTD, 0x80)) {
Return (STA_DISABLED)
} Else {
Return (STA_INVISIBLE)
}
}
}
Device (LNKE)
{
Name(_HID, EISAID("PNP0C0F"))
Name(_UID, 5)
/* Disable method */
Method(_DIS, 0, Serialized)
{
Store(0x80, PRTE)
}
/* Possible Resource Settings for this Link */
Name(_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
})
/* Current Resource Settings for this link */
Method(_CRS, 0, Serialized)
{
Name(RTLE, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLE, 1, IRQ0)
/* Clear the WordField */
Store(Zero, IRQ0)
/* Set the bit from PRTE */
ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
Return (RTLE)
}
/* Set Resource Setting for this IRQ link */
Method(_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
/* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTE)
}
/* Status */
Method(_STA, 0, Serialized)
{
If (And(PRTE, 0x80)) {
Return (STA_DISABLED)
} Else {
Return (STA_INVISIBLE)
}
}
}
Device (LNKF)
{
Name(_HID, EISAID("PNP0C0F"))
Name(_UID, 6)
/* Disable method */
Method(_DIS, 0, Serialized)
{
Store(0x80, PRTF)
}
/* Possible Resource Settings for this Link */
Name(_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
})
/* Current Resource Settings for this link */
Method(_CRS, 0, Serialized)
{
Name(RTLF, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLF, 1, IRQ0)
/* Clear the WordField */
Store(Zero, IRQ0)
/* Set the bit from PRTF */
ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
Return (RTLF)
}
/* Set Resource Setting for this IRQ link */
Method(_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
/* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTF)
}
/* Status */
Method(_STA, 0, Serialized)
{
If (And(PRTF, 0x80)) {
Return (STA_DISABLED)
} Else {
Return (STA_INVISIBLE)
}
}
}
Device (LNKG)
{
Name(_HID, EISAID("PNP0C0F"))
Name(_UID, 7)
/* Disable method */
Method(_DIS, 0, Serialized)
{
Store(0x80, PRTG)
}
/* Possible Resource Settings for this Link */
Name(_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
})
/* Current Resource Settings for this link */
Method(_CRS, 0, Serialized)
{
Name(RTLG, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLG, 1, IRQ0)
/* Clear the WordField */
Store(Zero, IRQ0)
/* Set the bit from PRTG */
ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
Return (RTLG)
}
/* Set Resource Setting for this IRQ link */
Method(_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
/* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTG)
}
/* Status */
Method(_STA, 0, Serialized)
{
If (And(PRTG, 0x80)) {
Return (STA_DISABLED)
} Else {
Return (STA_INVISIBLE)
}
}
}
Device (LNKH)
{
Name(_HID, EISAID("PNP0C0F"))
Name(_UID, 8)
/* Disable method */
Method(_DIS, 0, Serialized)
{
Store(0x80, PRTH)
}
/* Possible Resource Settings for this Link */
Name(_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
})
/* Current Resource Settings for this link */
Method(_CRS, 0, Serialized)
{
Name(RTLH, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLH, 1, IRQ0)
/* Clear the WordField */
Store(Zero, IRQ0)
/* Set the bit from PRTH */
ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
Return (RTLH)
}
/* Set Resource Setting for this IRQ link */
Method(_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
/* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTH)
}
/* Status */
Method(_STA, 0, Serialized)
{
If (And(PRTH, 0x80)) {
Return (STA_DISABLED)
} Else {
Return (STA_INVISIBLE)
}
}
}

48
u-boot/arch/x86/include/asm/acpi/irqroute.asl Normal file
View File

@@ -0,0 +1,48 @@
/*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
*
* SPDX-License-Identifier: GPL-2.0+
*/
Name(\PICM, 0)
/*
* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local APIC/IOAPIC configuration.
*/
Method(\_PIC, 1)
{
/* Remember the OS' IRQ routing choice */
Store(Arg0, PICM)
}
/* PCI interrupt routing */
Method(_PRT) {
If (PICM) {
Return (Package() {
#undef PIC_MODE
#include "irq_helper.h"
PCI_DEV_PIRQ_ROUTES
})
} Else {
Return (Package() {
#define PIC_MODE
#include "irq_helper.h"
PCI_DEV_PIRQ_ROUTES
})
}
}
/* PCIe downstream ports interrupt routing */
PCIE_BRIDGE_IRQ_ROUTES
#undef PIC_MODE
#include "irq_helper.h"
PCIE_BRIDGE_IRQ_ROUTES

82
u-boot/arch/x86/include/asm/acpi/statdef.asl Normal file
View File

@@ -0,0 +1,82 @@
/*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/arch/x86/acpi/statdef.asl
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Status and notification definitions */
#define STA_MISSING 0x00
#define STA_PRESENT 0x01
#define STA_ENABLED 0x03
#define STA_DISABLED 0x09
#define STA_INVISIBLE 0x0b
#define STA_UNAVAILABLE 0x0d
#define STA_VISIBLE 0x0f
/* SMBus status codes */
#define SMB_OK 0x00
#define SMB_UNKNOWN_FAIL 0x07
#define SMB_DEV_ADDR_NAK 0x10
#define SMB_DEVICE_ERROR 0x11
#define SMB_DEV_CMD_DENIED 0x12
#define SMB_UNKNOWN_ERR 0x13
#define SMB_DEV_ACC_DENIED 0x17
#define SMB_TIMEOUT 0x18
#define SMB_HST_UNSUPP_PROTOCOL 0x19
#define SMB_BUSY 0x1a
#define SMB_PKT_CHK_ERROR 0x1f
/* Device Object Notification Values */
#define NOTIFY_BUS_CHECK 0x00
#define NOTIFY_DEVICE_CHECK 0x01
#define NOTIFY_DEVICE_WAKE 0x02
#define NOTIFY_EJECT_REQUEST 0x03
#define NOTIFY_DEVICE_CHECK_JR 0x04
#define NOTIFY_FREQUENCY_ERROR 0x05
#define NOTIFY_BUS_MODE 0x06
#define NOTIFY_POWER_FAULT 0x07
#define NOTIFY_CAPABILITIES 0x08
#define NOTIFY_PLD_CHECK 0x09
#define NOTIFY_SLIT_UPDATE 0x0b
#define NOTIFY_SRA_UPDATE 0x0d
/* Battery Device Notification Values */
#define NOTIFY_BAT_STATUSCHG 0x80
#define NOTIFY_BAT_INFOCHG 0x81
#define NOTIFY_BAT_MAINTDATA 0x82
/* Power Source Object Notification Values */
#define NOTIFY_PWR_STATUSCHG 0x80
#define NOTIFY_PWR_INFOCHG 0x81
/* Thermal Zone Object Notification Values */
#define NOTIFY_TZ_STATUSCHG 0x80
#define NOTIFY_TZ_TRIPPTCHG 0x81
#define NOTIFY_TZ_DEVLISTCHG 0x82
#define NOTIFY_TZ_RELTBLCHG 0x83
/* Power Button Notification Values */
#define NOTIFY_POWER_BUTTON 0x80
/* Sleep Button Notification Values */
#define NOTIFY_SLEEP_BUTTON 0x80
/* Lid Notification Values */
#define NOTIFY_LID_STATUSCHG 0x80
/* Processor Device Notification Values */
#define NOTIFY_CPU_PPCCHG 0x80
#define NOTIFY_CPU_CSTATECHG 0x81
#define NOTIFY_CPU_THROTLCHG 0x82
/* User Presence Device Notification Values */
#define NOTIFY_USR_PRESNCECHG 0x80
/* Ambient Light Sensor Notification Values */
#define NOTIFY_ALS_ILLUMCHG 0x80
#define NOTIFY_ALS_COLORTMPCHG 0x81
#define NOTIFY_ALS_RESPCHG 0x82

315
u-boot/arch/x86/include/asm/acpi_table.h Normal file
View File

@@ -0,0 +1,315 @@
/*
* Based on acpi.c from coreboot
*
* Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */
#define OEM_ID "U-BOOT" /* U-Boot */
#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */
#define ASLC_ID "INTL" /* Intel ASL Compiler */
#define ACPI_RSDP_REV_ACPI_1_0 0
#define ACPI_RSDP_REV_ACPI_2_0 2
/*
* RSDP (Root System Description Pointer)
* Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
*/
struct acpi_rsdp {
char signature[8]; /* RSDP signature */
u8 checksum; /* Checksum of the first 20 bytes */
char oem_id[6]; /* OEM ID */
u8 revision; /* 0 for ACPI 1.0, others 2 */
u32 rsdt_address; /* Physical address of RSDT (32 bits) */
u32 length; /* Total RSDP length (incl. extended part) */
u64 xsdt_address; /* Physical address of XSDT (64 bits) */
u8 ext_checksum; /* Checksum of the whole table */
u8 reserved[3];
};
/* Generic ACPI header, provided by (almost) all tables */
struct acpi_table_header {
char signature[4]; /* ACPI signature (4 ASCII characters) */
u32 length; /* Table length in bytes (incl. header) */
u8 revision; /* Table version (not ACPI version!) */
volatile u8 checksum; /* To make sum of entire table == 0 */
char oem_id[6]; /* OEM identification */
char oem_table_id[8]; /* OEM table identification */
u32 oem_revision; /* OEM revision number */
char aslc_id[4]; /* ASL compiler vendor ID */
u32 aslc_revision; /* ASL compiler revision number */
};
/* A maximum number of 32 ACPI tables ought to be enough for now */
#define MAX_ACPI_TABLES 32
/* RSDT (Root System Description Table) */
struct acpi_rsdt {
struct acpi_table_header header;
u32 entry[MAX_ACPI_TABLES];
};
/* XSDT (Extended System Description Table) */
struct acpi_xsdt {
struct acpi_table_header header;
u64 entry[MAX_ACPI_TABLES];
};
/* FADT Preferred Power Management Profile */
enum acpi_pm_profile {
ACPI_PM_UNSPECIFIED = 0,
ACPI_PM_DESKTOP,
ACPI_PM_MOBILE,
ACPI_PM_WORKSTATION,
ACPI_PM_ENTERPRISE_SERVER,
ACPI_PM_SOHO_SERVER,
ACPI_PM_APPLIANCE_PC,
ACPI_PM_PERFORMANCE_SERVER,
ACPI_PM_TABLET
};
/* FADT flags for p_lvl2_lat and p_lvl3_lat */
#define ACPI_FADT_C2_NOT_SUPPORTED 101
#define ACPI_FADT_C3_NOT_SUPPORTED 1001
/* FADT Boot Architecture Flags */
#define ACPI_FADT_LEGACY_FREE 0x00
#define ACPI_FADT_LEGACY_DEVICES (1 << 0)
#define ACPI_FADT_8042 (1 << 1)
#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2)
#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3)
#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4)
/* FADT Feature Flags */
#define ACPI_FADT_WBINVD (1 << 0)
#define ACPI_FADT_WBINVD_FLUSH (1 << 1)
#define ACPI_FADT_C1_SUPPORTED (1 << 2)
#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3)
#define ACPI_FADT_POWER_BUTTON (1 << 4)
#define ACPI_FADT_SLEEP_BUTTON (1 << 5)
#define ACPI_FADT_FIXED_RTC (1 << 6)
#define ACPI_FADT_S4_RTC_WAKE (1 << 7)
#define ACPI_FADT_32BIT_TIMER (1 << 8)
#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9)
#define ACPI_FADT_RESET_REGISTER (1 << 10)
#define ACPI_FADT_SEALED_CASE (1 << 11)
#define ACPI_FADT_HEADLESS (1 << 12)
#define ACPI_FADT_SLEEP_TYPE (1 << 13)
#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14)
#define ACPI_FADT_PLATFORM_CLOCK (1 << 15)
#define ACPI_FADT_S4_RTC_VALID (1 << 16)
#define ACPI_FADT_REMOTE_POWER_ON (1 << 17)
#define ACPI_FADT_APIC_CLUSTER (1 << 18)
#define ACPI_FADT_APIC_PHYSICAL (1 << 19)
#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20)
#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21)
enum acpi_address_space_type {
ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */
ACPI_ADDRESS_SPACE_IO, /* System I/O */
ACPI_ADDRESS_SPACE_PCI, /* PCI config space */
ACPI_ADDRESS_SPACE_EC, /* Embedded controller */
ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */
ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */
ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */
};
enum acpi_address_space_size {
ACPI_ACCESS_SIZE_UNDEFINED = 0,
ACPI_ACCESS_SIZE_BYTE_ACCESS,
ACPI_ACCESS_SIZE_WORD_ACCESS,
ACPI_ACCESS_SIZE_DWORD_ACCESS,
ACPI_ACCESS_SIZE_QWORD_ACCESS
};
struct acpi_gen_regaddr {
u8 space_id; /* Address space ID */
u8 bit_width; /* Register size in bits */
u8 bit_offset; /* Register bit offset */
u8 access_size; /* Access size */
u32 addrl; /* Register address, low 32 bits */
u32 addrh; /* Register address, high 32 bits */
};
/* FADT (Fixed ACPI Description Table) */
struct __packed acpi_fadt {
struct acpi_table_header header;
u32 firmware_ctrl;
u32 dsdt;
u8 res1;
u8 preferred_pm_profile;
u16 sci_int;
u32 smi_cmd;
u8 acpi_enable;
u8 acpi_disable;
u8 s4bios_req;
u8 pstate_cnt;
u32 pm1a_evt_blk;
u32 pm1b_evt_blk;
u32 pm1a_cnt_blk;
u32 pm1b_cnt_blk;
u32 pm2_cnt_blk;
u32 pm_tmr_blk;
u32 gpe0_blk;
u32 gpe1_blk;
u8 pm1_evt_len;
u8 pm1_cnt_len;
u8 pm2_cnt_len;
u8 pm_tmr_len;
u8 gpe0_blk_len;
u8 gpe1_blk_len;
u8 gpe1_base;
u8 cst_cnt;
u16 p_lvl2_lat;
u16 p_lvl3_lat;
u16 flush_size;
u16 flush_stride;
u8 duty_offset;
u8 duty_width;
u8 day_alrm;
u8 mon_alrm;
u8 century;
u16 iapc_boot_arch;
u8 res2;
u32 flags;
struct acpi_gen_regaddr reset_reg;
u8 reset_value;
u8 res3;
u8 res4;
u8 res5;
u32 x_firmware_ctl_l;
u32 x_firmware_ctl_h;
u32 x_dsdt_l;
u32 x_dsdt_h;
struct acpi_gen_regaddr x_pm1a_evt_blk;
struct acpi_gen_regaddr x_pm1b_evt_blk;
struct acpi_gen_regaddr x_pm1a_cnt_blk;
struct acpi_gen_regaddr x_pm1b_cnt_blk;
struct acpi_gen_regaddr x_pm2_cnt_blk;
struct acpi_gen_regaddr x_pm_tmr_blk;
struct acpi_gen_regaddr x_gpe0_blk;
struct acpi_gen_regaddr x_gpe1_blk;
};
/* FACS flags */
#define ACPI_FACS_S4BIOS_F (1 << 0)
#define ACPI_FACS_64BIT_WAKE_F (1 << 1)
/* FACS (Firmware ACPI Control Structure) */
struct acpi_facs {
char signature[4]; /* "FACS" */
u32 length; /* Length in bytes (>= 64) */
u32 hardware_signature; /* Hardware signature */
u32 firmware_waking_vector; /* Firmware waking vector */
u32 global_lock; /* Global lock */
u32 flags; /* FACS flags */
u32 x_firmware_waking_vector_l; /* X FW waking vector, low */
u32 x_firmware_waking_vector_h; /* X FW waking vector, high */
u8 version; /* Version 2 */
u8 res1[3];
u32 ospm_flags; /* OSPM enabled flags */
u8 res2[24];
};
/* MADT flags */
#define ACPI_MADT_PCAT_COMPAT (1 << 0)
/* MADT (Multiple APIC Description Table) */
struct acpi_madt {
struct acpi_table_header header;
u32 lapic_addr; /* Local APIC address */
u32 flags; /* Multiple APIC flags */
};
/* MADT: APIC Structure Type*/
enum acpi_apic_types {
ACPI_APIC_LAPIC = 0, /* Processor local APIC */
ACPI_APIC_IOAPIC, /* I/O APIC */
ACPI_APIC_IRQ_SRC_OVERRIDE, /* Interrupt source override */
ACPI_APIC_NMI_SRC, /* NMI source */
ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */
ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */
ACPI_APIC_IOSAPIC, /* I/O SAPIC */
ACPI_APIC_LSAPIC, /* Local SAPIC */
ACPI_APIC_PLATFORM_IRQ_SRC, /* Platform interrupt sources */
ACPI_APIC_LX2APIC, /* Processor local x2APIC */
ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */
};
/* MADT: Processor Local APIC Structure */
#define LOCAL_APIC_FLAG_ENABLED (1 << 0)
struct acpi_madt_lapic {
u8 type; /* Type (0) */
u8 length; /* Length in bytes (8) */
u8 processor_id; /* ACPI processor ID */
u8 apic_id; /* Local APIC ID */
u32 flags; /* Local APIC flags */
};
/* MADT: I/O APIC Structure */
struct acpi_madt_ioapic {
u8 type; /* Type (1) */
u8 length; /* Length in bytes (12) */
u8 ioapic_id; /* I/O APIC ID */
u8 reserved;
u32 ioapic_addr; /* I/O APIC address */
u32 gsi_base; /* Global system interrupt base */
};
/* MADT: Interrupt Source Override Structure */
struct __packed acpi_madt_irqoverride {
u8 type; /* Type (2) */
u8 length; /* Length in bytes (10) */
u8 bus; /* ISA (0) */
u8 source; /* Bus-relative int. source (IRQ) */
u32 gsirq; /* Global system interrupt */
u16 flags; /* MPS INTI flags */
};
/* MADT: Local APIC NMI Structure */
struct __packed acpi_madt_lapic_nmi {
u8 type; /* Type (4) */
u8 length; /* Length in bytes (6) */
u8 processor_id; /* ACPI processor ID */
u16 flags; /* MPS INTI flags */
u8 lint; /* Local APIC LINT# */
};
/* MCFG (PCI Express MMIO config space BAR description table) */
struct acpi_mcfg {
struct acpi_table_header header;
u8 reserved[8];
};
struct acpi_mcfg_mmconfig {
u32 base_address_l;
u32 base_address_h;
u16 pci_segment_group_number;
u8 start_bus_number;
u8 end_bus_number;
u8 reserved[4];
};
/* PM1_CNT bit defines */
#define PM1_CNT_SCI_EN (1 << 0)
/* These can be used by the target port */
void acpi_fill_header(struct acpi_table_header *header, char *signature);
void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
void *dsdt);
int acpi_create_madt_lapics(u32 current);
int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
u32 addr, u32 gsi_base);
int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
u8 bus, u8 source, u32 gsirq, u16 flags);
int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
u8 cpu, u16 flags, u8 lint);
u32 acpi_fill_madt(u32 current);
u32 write_acpi_tables(u32 start);

95
u-boot/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl Normal file
View File

@@ -0,0 +1,95 @@
/*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* SouthCluster GPIO */
Device (GPSC)
{
Name(_HID, "INT33FC")
Name(_CID, "INT33FC")
Name(_UID, 1)
Name(RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
{
GPIO_SC_IRQ
}
})
Method(_CRS)
{
CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
Return (^RBUF)
}
Method(_STA)
{
Return (STA_VISIBLE)
}
}
/* NorthCluster GPIO */
Device (GPNC)
{
Name(_HID, "INT33FC")
Name(_CID, "INT33FC")
Name(_UID, 2)
Name(RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
{
GPIO_NC_IRQ
}
})
Method(_CRS)
{
CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
Return (^RBUF)
}
Method(_STA)
{
Return (STA_VISIBLE)
}
}
/* SUS GPIO */
Device (GPSS)
{
Name(_HID, "INT33FC")
Name(_CID, "INT33FC")
Name(_UID, 3)
Name(RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
{
GPIO_SUS_IRQ
}
})
Method(_CRS)
{
CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
Return (^RBUF)
}
Method(_STA)
{
Return (STA_VISIBLE)
}
}

27
u-boot/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h Normal file
View File

@@ -0,0 +1,27 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/device.h>
#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(EMMC_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SD_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(MMC45_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
#define PCIE_BRIDGE_IRQ_ROUTES \
PCIE_BRIDGE_DEV(RP, PCIE_DEV, A, B, C, D)

202
u-boot/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl Normal file
View File

@@ -0,0 +1,202 @@
/*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Intel LPC Bus Device - 0:1f.0 */
Scope (\)
{
/* Intel Legacy Block */
OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Field(ILBS, AnyAcc, NoLock, Preserve) {
Offset (0x8),
PRTA, 8,
PRTB, 8,
PRTC, 8,
PRTD, 8,
PRTE, 8,
PRTF, 8,
PRTG, 8,
PRTH, 8,
Offset (0x88),
, 3,
UI3E, 1,
UI4E, 1
}
}
Device (LPCB)
{
Name(_ADR, 0x001f0000)
OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
Field(LPC0, AnyAcc, NoLock, Preserve) {
Offset(0x08),
SRID, 8,
Offset(0x80),
C1EN, 1,
Offset(0x84)
}
#include <asm/acpi/irqlinks.asl>
/* Firmware Hub */
Device (FWH)
{
Name(_HID, EISAID("INT0800"))
Name(_CRS, ResourceTemplate()
{
Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
})
}
/* 8259 Interrupt Controller */
Device (PIC)
{
Name(_HID, EISAID("PNP0000"))
Name(_CRS, ResourceTemplate()
{
IO(Decode16, 0x20, 0x20, 0x01, 0x02)
IO(Decode16, 0x24, 0x24, 0x01, 0x02)
IO(Decode16, 0x28, 0x28, 0x01, 0x02)
IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
IO(Decode16, 0x30, 0x30, 0x01, 0x02)
IO(Decode16, 0x34, 0x34, 0x01, 0x02)
IO(Decode16, 0x38, 0x38, 0x01, 0x02)
IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
IO(Decode16, 0xac, 0xac, 0x01, 0x02)
IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
IRQNoFlags () { 2 }
})
}
/* 8254 timer */
Device (TIMR)
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
{
IO(Decode16, 0x40, 0x40, 0x01, 0x04)
IO(Decode16, 0x50, 0x50, 0x10, 0x04)
IRQNoFlags() { 0 }
})
}
/* HPET */
Device (HPET)
{
Name(_HID, EISAID("PNP0103"))
Name(_CID, 0x010CD041)
Name(_CRS, ResourceTemplate()
{
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
})
Method(_STA)
{
Return (STA_VISIBLE)
}
}
/* Internal UART */
Device (IURT)
{
Name(_HID, EISAID("PNP0501"))
Name(_UID, 1)
Method(_STA, 0, Serialized)
{
/*
* TODO:
*
* Need to hide the internal UART depending on whether
* internal UART is enabled or not so that external
* SuperIO UART can be exposed to system.
*/
Store(1, UI3E)
Store(1, UI4E)
Store(1, C1EN)
Return (STA_VISIBLE)
}
Method(_DIS, 0, Serialized)
{
Store(0, UI3E)
Store(0, UI4E)
Store(0, C1EN)
}
Method(_CRS, 0, Serialized)
{
Name(BUF0, ResourceTemplate()
{
IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
IRQNoFlags() { 3 }
})
Name(BUF1, ResourceTemplate()
{
IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
IRQNoFlags() { 4 }
})
If (LLessEqual(SRID, 0x04)) {
Return (BUF0)
} Else {
Return (BUF1)
}
}
}
/* Real Time Clock */
Device (RTC)
{
Name(_HID, EISAID("PNP0B00"))
Name(_CRS, ResourceTemplate()
{
IO(Decode16, 0x70, 0x70, 1, 8)
/*
* Disable as Windows doesn't like it, and systems
* don't seem to use it
*/
/* IRQNoFlags() { 8 } */
})
}
/* LPC device: Resource consumption */
Device (LDRC)
{
Name(_HID, EISAID("PNP0C02"))
Name(_UID, 2)
Name(RBUF, ResourceTemplate()
{
IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
})
Method(_CRS, 0, NotSerialized)
{
Return (RBUF)
}
}
}

36
u-boot/arch/x86/include/asm/arch-baytrail/acpi/platform.asl Normal file
View File

@@ -0,0 +1,36 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/acpi/statdef.asl>
#include <asm/arch/iomap.h>
#include <asm/arch/irq.h>
/*
* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0.
*/
Method(_PTS, 1)
{
}
/* The _WAK method is called on system wakeup */
Method(_WAK, 1)
{
Return (Package() {0, 0})
}
/* TODO: add CPU ASL support */
Scope (\_SB)
{
#include "southcluster.asl"
/* ACPI devices */
#include "gpio.asl"
}
/* Chipset specific sleep states */
#include "sleepstates.asl"

13
u-boot/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl Normal file
View File

@@ -0,0 +1,13 @@
/*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
*
* SPDX-License-Identifier: GPL-2.0+
*/
Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})

211
u-boot/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl Normal file
View File

@@ -0,0 +1,211 @@
/*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
*
* SPDX-License-Identifier: GPL-2.0+
*/
Device (PCI0)
{
Name(_HID, EISAID("PNP0A08")) /* PCIe */
Name(_CID, EISAID("PNP0A03")) /* PCI */
Name(_ADR, 0)
Name(_BBN, 0)
Name(MCRS, ResourceTemplate()
{
/* Bus Numbers */
WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
/* IO Region 0 */
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
/* PCI Config Space */
IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
/* IO Region 1 */
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
/* VGA memory (0xa0000-0xbffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
0x00020000, , , ASEG)
/* OPROM reserved (0xc0000-0xc3fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
0x00004000, , , OPR0)
/* OPROM reserved (0xc4000-0xc7fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
0x00004000, , , OPR1)
/* OPROM reserved (0xc8000-0xcbfff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
0x00004000, , , OPR2)
/* OPROM reserved (0xcc000-0xcffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
0x00004000, , , OPR3)
/* OPROM reserved (0xd0000-0xd3fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
0x00004000, , , OPR4)
/* OPROM reserved (0xd4000-0xd7fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
0x00004000, , , OPR5)
/* OPROM reserved (0xd8000-0xdbfff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
0x00004000, , , OPR6)
/* OPROM reserved (0xdc000-0xdffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
0x00004000, , , OPR7)
/* BIOS Extension (0xe0000-0xe3fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
0x00004000, , , ESG0)
/* BIOS Extension (0xe4000-0xe7fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
0x00004000, , , ESG1)
/* BIOS Extension (0xe8000-0xebfff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
0x00004000, , , ESG2)
/* BIOS Extension (0xec000-0xeffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000ec000, 0x000effff, 0x00000000,
0x00004000, , , ESG3)
/* System BIOS (0xf0000-0xfffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000, , , FSEG)
/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, , , PMEM)
/* High PCI Memory Region */
QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, , , UMEM)
})
Method(_CRS, 0, Serialized)
{
/* Update PCI resource area */
CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
/*
* Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
*
* TODO: for generic usage, read TOLM value from register, or
* from global NVS (not implemented by U-Boot yet).
*/
Store(0x80000000, PMIN)
Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
Add(Subtract(PMAX, PMIN), 1, PLEN)
/* Update High PCI resource area */
CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
/* Set base address to 48GB and allocate 16GB for PCI space */
Store(0xc00000000, UMIN)
Store(0x400000000, ULEN)
Add(UMIN, Subtract(ULEN, 1), UMAX)
Return (MCRS)
}
/* Device Resource Consumption */
Device (PDRC)
{
Name(_HID, EISAID("PNP0C02"))
Name(_UID, 1)
Name(PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
})
/* Current Resource Settings */
Method(_CRS, 0, Serialized)
{
Return (PDRS)
}
}
Method(_OSC, 4)
{
/* Check for proper GUID */
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
/* Let OS control everything */
Return (Arg3)
} Else {
/* Unrecognized UUID */
CreateDWordField(Arg3, 0, CDW1)
Or(CDW1, 4, CDW1)
Return (Arg3)
}
}
/* LPC Bridge 0:1f.0 */
#include "lpc.asl"
/* USB EHCI 0:1d.0 */
#include "usb.asl"
/* USB XHCI 0:14.0 */
#include "xhci.asl"
/* IRQ routing for each PCI device */
#include <asm/acpi/irqroute.asl>
}

34
u-boot/arch/x86/include/asm/arch-baytrail/acpi/usb.asl Normal file
View File

@@ -0,0 +1,34 @@
/*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* EHCI Controller 0:1d.0 */
Device (EHC1)
{
Name(_ADR, 0x001d0000)
/* Power Resources for Wake */
Name(_PRW, Package() { 13, 4 })
/* Highest D state in S3 state */
Name(_S3D, 2)
/* Highest D state in S4 state */
Name(_S4D, 2)
Device (HUB7)
{
Name(_ADR, 0x00000000)
Device(PRT1) { Name(_ADR, 1) } /* USB Port 0 */
Device(PRT2) { Name(_ADR, 2) } /* USB Port 1 */
Device(PRT3) { Name(_ADR, 3) } /* USB Port 2 */
Device(PRT4) { Name(_ADR, 4) } /* USB Port 3 */
}
}

31
u-boot/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl Normal file
View File

@@ -0,0 +1,31 @@
/*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* XHCI Controller 0:14.0 */
Device (XHCI)
{
Name(_ADR, 0x00140000)
/* Power Resources for Wake */
Name(_PRW, Package() { 13, 3 })
/* Highest D state in S3 state */
Name(_S3D, 3)
Device (RHUB)
{
Name(_ADR, 0x00000000)
Device (PRT1) { Name(_ADR, 1) } /* USB Port 0 */
Device (PRT2) { Name(_ADR, 2) } /* USB Port 1 */
Device (PRT3) { Name(_ADR, 3) } /* USB Port 2 */
Device (PRT4) { Name(_ADR, 4) } /* USB Port 3 */
}
}

74
u-boot/arch/x86/include/asm/arch-baytrail/device.h Normal file
View File

@@ -0,0 +1,74 @@
/*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DEVICE_H_
#define _DEVICE_H_
/*
* Internal PCI device numbers within the SoC.
*
* Note it must start with 0x_ prefix, as the device number macro will be
* included in the ACPI ASL files (see irq_helper.h and irq_route.h).
*/
/* SoC transaction router */
#define SOC_DEV 0x00
/* Graphics and Display */
#define GFX_DEV 0x02
/* MIPI */
#define MIPI_DEV 0x03
/* EMMC Port */
#define EMMC_DEV 0x10
/* SDIO Port */
#define SDIO_DEV 0x11
/* SD Port */
#define SD_DEV 0x12
/* SATA */
#define SATA_DEV 0x13
/* xHCI */
#define XHCI_DEV 0x14
/* LPE Audio */
#define LPE_DEV 0x15
/* OTG */
#define OTG_DEV 0x16
/* MMC45 Port */
#define MMC45_DEV 0x17
/* Serial IO 1 */
#define SIO1_DEV 0x18
/* Trusted Execution Engine */
#define TXE_DEV 0x1a
/* HD Audio */
#define HDA_DEV 0x1b
/* PCIe Ports */
#define PCIE_DEV 0x1c
/* EHCI */
#define EHCI_DEV 0x1d
/* Serial IO 2 */
#define SIO2_DEV 0x1e
/* Platform Controller Unit */
#define PCU_DEV 0x1f
#endif /* _DEVICE_H_ */

39
u-boot/arch/x86/include/asm/arch-baytrail/fsp/azalia.h Normal file
View File

@@ -0,0 +1,39 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2015 Google, Inc
*
* SPDX-License-Identifier: Intel
*/
#ifndef _FSP_AZALIA_H_
#define _FSP_AZALIA_H_
struct __packed pch_azalia_verb_table_header {
uint32_t vendor_device_id;
uint16_t sub_system_id;
uint8_t revision_id; /* 0xff applies to all steppings */
uint8_t front_panel_support;
uint16_t number_of_rear_jacks;
uint16_t number_of_front_jacks;
};
struct __packed pch_azalia_verb_table {
struct pch_azalia_verb_table_header verb_table_header;
const uint32_t *verb_table_data;
};
struct __packed pch_azalia_config {
uint8_t pme_enable:1;
uint8_t docking_supported:1;
uint8_t docking_attached:1;
uint8_t hdmi_codec_enable:1;
uint8_t azalia_v_ci_enable:1;
uint8_t rsvdbits:3;
/* number of verb tables provided by platform */
uint8_t azalia_verb_table_num;
const struct pch_azalia_verb_table *azalia_verb_table;
/* delay timer after azalia reset */
uint16_t reset_wait_timer_us;
};
#endif

19
u-boot/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h Normal file
View File

@@ -0,0 +1,19 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: Intel
*/
#ifndef __FSP_CONFIGS_H__
#define __FSP_CONFIGS_H__
struct fsp_config_data {
struct fsp_cfg_common common;
struct upd_region fsp_upd;
};
struct fspinit_rtbuf {
struct common_buf common; /* FSP common runtime data structure */
};
#endif /* __FSP_CONFIGS_H__ */

95
u-boot/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h Normal file
View File

@@ -0,0 +1,95 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2015 Google, Inc
*
* SPDX-License-Identifier: Intel
*/
#ifndef __FSP_VPD_H
#define __FSP_VPD_H
struct memory_down_data {
uint8_t enable_memory_down;
uint8_t dram_speed;
uint8_t dram_type;
uint8_t dimm_0_enable;
uint8_t dimm_1_enable;
uint8_t dimm_width;
uint8_t dimm_density;
uint8_t dimm_bus_width;
uint8_t dimm_sides; /* Ranks Per dimm_ */
uint8_t dimm_tcl; /* tCL */
/* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
uint8_t dimm_trpt_rcd;
uint8_t dimm_twr; /* tWR in DRAM clk */
uint8_t dimm_twtr; /* tWTR in DRAM clk */
uint8_t dimm_trrd; /* tRRD in DRAM clk */
uint8_t dimm_trtp; /* tRTP in DRAM clk */
uint8_t dimm_tfaw; /* tFAW in DRAM clk */
};
struct __packed upd_region {
uint64_t signature; /* Offset 0x0000 */
uint8_t reserved0[24]; /* Offset 0x0008 */
uint16_t mrc_init_tseg_size; /* Offset 0x0020 */
uint16_t mrc_init_mmio_size; /* Offset 0x0022 */
uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */
uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */
uint8_t emmc_boot_mode; /* Offset 0x0026 */
uint8_t enable_sdio; /* Offset 0x0027 */
uint8_t enable_sdcard; /* Offset 0x0028 */
uint8_t enable_hsuart0; /* Offset 0x0029 */
uint8_t enable_hsuart1; /* Offset 0x002a */
uint8_t enable_spi; /* Offset 0x002b */
uint8_t reserved1; /* Offset 0x002c */
uint8_t enable_sata; /* Offset 0x002d */
uint8_t sata_mode; /* Offset 0x002e */
uint8_t enable_azalia; /* Offset 0x002f */
uint32_t azalia_config_ptr; /* Offset 0x0030 */
uint8_t enable_xhci; /* Offset 0x0034 */
uint8_t enable_lpe; /* Offset 0x0035 */
uint8_t lpss_sio_enable_pci_mode; /* Offset 0x0036 */
uint8_t enable_dma0; /* Offset 0x0037 */
uint8_t enable_dma1; /* Offset 0x0038 */
uint8_t enable_i2_c0; /* Offset 0x0039 */
uint8_t enable_i2_c1; /* Offset 0x003a */
uint8_t enable_i2_c2; /* Offset 0x003b */
uint8_t enable_i2_c3; /* Offset 0x003c */
uint8_t enable_i2_c4; /* Offset 0x003d */
uint8_t enable_i2_c5; /* Offset 0x003e */
uint8_t enable_i2_c6; /* Offset 0x003f */
uint8_t enable_pwm0; /* Offset 0x0040 */
uint8_t enable_pwm1; /* Offset 0x0041 */
uint8_t enable_hsi; /* Offset 0x0042 */
uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */
uint8_t aperture_size; /* Offset 0x0044 */
uint8_t gtt_size; /* Offset 0x0045 */
uint32_t serial_debug_port_address; /* Offset 0x0046 */
uint8_t serial_debug_port_type; /* Offset 0x004a */
uint8_t mrc_debug_msg; /* Offset 0x004b */
uint8_t isp_enable; /* Offset 0x004c */
uint8_t scc_enable_pci_mode; /* Offset 0x004d */
uint8_t igd_render_standby; /* Offset 0x004e */
uint8_t txe_uma_enable; /* Offset 0x004f */
uint8_t os_selection; /* Offset 0x0050 */
uint8_t emmc45_ddr50_enabled; /* Offset 0x0051 */
uint8_t emmc45_hs200_enabled; /* Offset 0x0052 */
uint8_t emmc45_retune_timer_value; /* Offset 0x0053 */
uint8_t enable_igd; /* Offset 0x0054 */
uint8_t unused_upd_space1[155]; /* Offset 0x0055 */
struct memory_down_data memory_params; /* Offset 0x00f0 */
uint16_t terminator; /* Offset 0x0100 */
};
#define VPD_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */
struct __packed vpd_region {
uint64_t sign; /* Offset 0x0000 */
uint32_t img_rev; /* Offset 0x0008 */
uint32_t upd_offset; /* Offset 0x000c */
uint8_t unused[16]; /* Offset 0x0010 */
uint32_t fsp_res_memlen; /* Offset 0x0020 */
uint8_t platform_type; /* Offset 0x0024 */
uint8_t enable_secure_boot; /* Offset 0x0025 */
};
#endif

70
u-boot/arch/x86/include/asm/arch-baytrail/iomap.h Normal file
View File

@@ -0,0 +1,70 @@
/*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BAYTRAIL_IOMAP_H_
#define _BAYTRAIL_IOMAP_H_
/* Memory Mapped IO bases */
/* PCI Configuration Space */
#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
#define MCFG_BASE_SIZE 0x10000000
/* Temporary Base Address */
#define TEMP_BASE_ADDRESS 0xfd000000
/* Transactions in this range will abort */
#define ABORT_BASE_ADDRESS 0xfeb00000
#define ABORT_BASE_SIZE 0x00100000
/* High Performance Event Timer */
#define HPET_BASE_ADDRESS 0xfed00000
#define HPET_BASE_SIZE 0x400
/* SPI Bus */
#define SPI_BASE_ADDRESS 0xfed01000
#define SPI_BASE_SIZE 0x400
/* Power Management Controller */
#define PMC_BASE_ADDRESS 0xfed03000
#define PMC_BASE_SIZE 0x400
/* Power Management Unit */
#define PUNIT_BASE_ADDRESS 0xfed05000
#define PUNIT_BASE_SIZE 0x800
/* Intel Legacy Block */
#define ILB_BASE_ADDRESS 0xfed08000
#define ILB_BASE_SIZE 0x400
/* IO Memory */
#define IO_BASE_ADDRESS 0xfed0c000
#define IO_BASE_OFFSET_GPSCORE 0x0000
#define IO_BASE_OFFSET_GPNCORE 0x1000
#define IO_BASE_OFFSET_GPSSUS 0x2000
#define IO_BASE_SIZE 0x4000
/* Root Complex Base Address */
#define RCBA_BASE_ADDRESS 0xfed1c000
#define RCBA_BASE_SIZE 0x400
/* MODPHY */
#define MPHY_BASE_ADDRESS 0xfef00000
#define MPHY_BASE_SIZE 0x100000
/* IO Port bases */
#define ACPI_BASE_ADDRESS 0x0400
#define ACPI_BASE_SIZE 0x80
#define GPIO_BASE_ADDRESS 0x0500
#define GPIO_BASE_SIZE 0x100
#define SMBUS_BASE_ADDRESS 0xefa0
#endif /* _BAYTRAIL_IOMAP_H_ */

86
u-boot/arch/x86/include/asm/arch-baytrail/irq.h Normal file
View File

@@ -0,0 +1,86 @@
/*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BAYTRAIL_IRQ_H_
#define _BAYTRAIL_IRQ_H_
#define PIRQA_APIC_IRQ 16
#define PIRQB_APIC_IRQ 17
#define PIRQC_APIC_IRQ 18
#define PIRQD_APIC_IRQ 19
#define PIRQE_APIC_IRQ 20
#define PIRQF_APIC_IRQ 21
#define PIRQG_APIC_IRQ 22
#define PIRQH_APIC_IRQ 23
/* The below IRQs are for when devices are in ACPI mode */
#define LPE_DMA0_IRQ 24
#define LPE_DMA1_IRQ 25
#define LPE_SSP0_IRQ 26
#define LPE_SSP1_IRQ 27
#define LPE_SSP2_IRQ 28
#define LPE_IPC2HOST_IRQ 29
#define LPSS_I2C1_IRQ 32
#define LPSS_I2C2_IRQ 33
#define LPSS_I2C3_IRQ 34
#define LPSS_I2C4_IRQ 35
#define LPSS_I2C5_IRQ 36
#define LPSS_I2C6_IRQ 37
#define LPSS_I2C7_IRQ 38
#define LPSS_HSUART1_IRQ 39
#define LPSS_HSUART2_IRQ 40
#define LPSS_SPI_IRQ 41
#define LPSS_DMA1_IRQ 42
#define LPSS_DMA2_IRQ 43
#define SCC_EMMC_IRQ 44
#define SCC_SDIO_IRQ 46
#define SCC_SD_IRQ 47
#define GPIO_NC_IRQ 48
#define GPIO_SC_IRQ 49
#define GPIO_SUS_IRQ 50
/* GPIO direct / dedicated IRQs */
#define GPIO_S0_DED_IRQ_0 51
#define GPIO_S0_DED_IRQ_1 52
#define GPIO_S0_DED_IRQ_2 53
#define GPIO_S0_DED_IRQ_3 54
#define GPIO_S0_DED_IRQ_4 55
#define GPIO_S0_DED_IRQ_5 56
#define GPIO_S0_DED_IRQ_6 57
#define GPIO_S0_DED_IRQ_7 58
#define GPIO_S0_DED_IRQ_8 59
#define GPIO_S0_DED_IRQ_9 60
#define GPIO_S0_DED_IRQ_10 61
#define GPIO_S0_DED_IRQ_11 62
#define GPIO_S0_DED_IRQ_12 63
#define GPIO_S0_DED_IRQ_13 64
#define GPIO_S0_DED_IRQ_14 65
#define GPIO_S0_DED_IRQ_15 66
#define GPIO_S5_DED_IRQ_0 67
#define GPIO_S5_DED_IRQ_1 68
#define GPIO_S5_DED_IRQ_2 69
#define GPIO_S5_DED_IRQ_3 70
#define GPIO_S5_DED_IRQ_4 71
#define GPIO_S5_DED_IRQ_5 72
#define GPIO_S5_DED_IRQ_6 73
#define GPIO_S5_DED_IRQ_7 74
#define GPIO_S5_DED_IRQ_8 75
#define GPIO_S5_DED_IRQ_9 76
#define GPIO_S5_DED_IRQ_10 77
#define GPIO_S5_DED_IRQ_11 78
#define GPIO_S5_DED_IRQ_12 79
#define GPIO_S5_DED_IRQ_13 80
#define GPIO_S5_DED_IRQ_14 81
#define GPIO_S5_DED_IRQ_15 82
/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot
#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot
#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot)
#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot)
#endif /* _BAYTRAIL_IRQ_H_ */

48
u-boot/arch/x86/include/asm/arch-broadwell/cpu.h Normal file
View File

@@ -0,0 +1,48 @@
/*
* Copyright (c) 2016 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __asm_arch_cpu_h
#define __asm_arch_cpu_h
/* CPU types */
#define HASWELL_FAMILY_ULT 0x40650
#define BROADWELL_FAMILY_ULT 0x306d0
/* Supported CPUIDs */
#define CPUID_HASWELL_A0 0x306c1
#define CPUID_HASWELL_B0 0x306c2
#define CPUID_HASWELL_C0 0x306c3
#define CPUID_HASWELL_ULT_B0 0x40650
#define CPUID_HASWELL_ULT 0x40651
#define CPUID_HASWELL_HALO 0x40661
#define CPUID_BROADWELL_C0 0x306d2
#define CPUID_BROADWELL_D0 0x306d3
#define CPUID_BROADWELL_E0 0x306d4
/* Broadwell bus clock is fixed at 100MHz */
#define BROADWELL_BCLK 100
#define BROADWELL_FAMILY_ULT 0x306d0
#define CORE_THREAD_COUNT_MSR 0x35
#define MSR_VR_CURRENT_CONFIG 0x601
#define MSR_VR_MISC_CONFIG 0x603
#define MSR_PKG_POWER_SKU 0x614
#define MSR_DDR_RAPL_LIMIT 0x618
#define MSR_VR_MISC_CONFIG2 0x636
/* Latency times in units of 1024ns. */
#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
void cpu_set_power_limits(int power_limit_1_time);
#endif

91
u-boot/arch/x86/include/asm/arch-broadwell/gpio.h Normal file
View File

@@ -0,0 +1,91 @@
/*
* Copyright (c) 2016 Google, Inc
*
* From Coreboot src/soc/intel/broadwell/include/soc/gpio.h
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_GPIO
#define __ASM_ARCH_GPIO
#define GPIO_PER_BANK 32
#define GPIO_BANKS 3
struct broadwell_bank_platdata {
uint16_t base_addr;
const char *bank_name;
int bank;
};
/* PCH-LP GPIOBASE Registers */
struct pch_lp_gpio_regs {
u32 own[GPIO_BANKS];
u32 reserved0;
u16 pirq_to_ioxapic;
u16 reserved1[3];
u32 blink;
u32 ser_blink;
u32 ser_blink_cmdsts;
u32 ser_blink_data;
u16 gpi_nmi_en;
u16 gpi_nmi_sts;
u32 reserved2;
u32 gpi_route[GPIO_BANKS];
u32 reserved3;
u32 reserved4[4];
u32 alt_gpi_smi_sts;
u32 alt_gpi_smi_en;
u32 reserved5[2];
u32 rst_sel[GPIO_BANKS];
u32 reserved6;
u32 reserved9[3];
u32 gpio_gc;
u32 gpi_is[GPIO_BANKS];
u32 reserved10;
u32 gpi_ie[GPIO_BANKS];
u32 reserved11;
u32 reserved12[24];
struct {
u32 conf_a;
u32 conf_b;
} config[GPIO_BANKS * GPIO_PER_BANK];
};
check_member(pch_lp_gpio_regs, gpi_ie[0], 0x90);
check_member(pch_lp_gpio_regs, config[0], 0x100);
enum {
CONFA_MODE_SHIFT = 0,
CONFA_MODE_GPIO = 1 << CONFA_MODE_SHIFT,
CONFA_DIR_SHIFT = 2,
CONFA_DIR_INPUT = 1 << CONFA_DIR_SHIFT,
CONFA_INVERT_SHIFT = 3,
CONFA_INVERT = 1 << CONFA_INVERT_SHIFT,
CONFA_TRIGGER_SHIFT = 4,
CONFA_TRIGGER_LEVEL = 1 << CONFA_TRIGGER_SHIFT,
CONFA_LEVEL_SHIFT = 30,
CONFA_LEVEL_HIGH = 1UL << CONFA_LEVEL_SHIFT,
CONFA_OUTPUT_SHIFT = 31,
CONFA_OUTPUT_HIGH = 1UL << CONFA_OUTPUT_SHIFT,
CONFB_SENSE_SHIFT = 2,
CONFB_SENSE_DISABLE = 1 << CONFB_SENSE_SHIFT,
};
#endif

53
u-boot/arch/x86/include/asm/arch-broadwell/iomap.h Normal file
View File

@@ -0,0 +1,53 @@
/*
* From Coreboot soc/intel/broadwell/include/soc/iomap.h
*
* Copyright (C) 2016 Google Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __asm_arch_iomap_h
#define __asm_arch_iomap_h
#define MCFG_BASE_ADDRESS 0xf0000000
#define MCFG_BASE_SIZE 0x4000000
#define HPET_BASE_ADDRESS 0xfed00000
#define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE 0x8000
#define DMI_BASE_ADDRESS 0xfed18000
#define DMI_BASE_SIZE 0x1000
#define EP_BASE_ADDRESS 0xfed19000
#define EP_BASE_SIZE 0x1000
#define EDRAM_BASE_ADDRESS 0xfed80000
#define EDRAM_BASE_SIZE 0x4000
#define GDXC_BASE_ADDRESS 0xfed84000
#define GDXC_BASE_SIZE 0x1000
#define RCBA_BASE_ADDRESS 0xfed1c000
#define RCBA_BASE_SIZE 0x4000
#define HPET_BASE_ADDRESS 0xfed00000
#define ACPI_BASE_ADDRESS 0x1000
#define ACPI_BASE_SIZE 0x100
#define GPIO_BASE_ADDRESS 0x1400
#define GPIO_BASE_SIZE 0x400
#define SMBUS_BASE_ADDRESS 0x0400
#define SMBUS_BASE_SIZE 0x10
/* Temporary addresses used before relocation */
#define EARLY_GTT_BAR 0xe0000000
#define EARLY_XHCI_BAR 0xd7000000
#define EARLY_EHCI_BAR 0xd8000000
#define EARLY_UART_BAR 0x3f8
#define EARLY_TEMP_MMIO 0xfed08000
#endif

32
u-boot/arch/x86/include/asm/arch-broadwell/lpc.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* From coreboot soc/intel/broadwell/include/soc/lpc.h
*
* Copyright (C) 2016 Google Inc.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_ARCH_LPC_H
#define _ASM_ARCH_LPC_H
#define GEN_PMCON_1 0xa0
#define SMI_LOCK (1 << 4)
#define GEN_PMCON_2 0xa2
#define SYSTEM_RESET_STS (1 << 4)
#define THERMTRIP_STS (1 << 3)
#define SYSPWR_FLR (1 << 1)
#define PWROK_FLR (1 << 0)
#define GEN_PMCON_3 0xa4
#define SUS_PWR_FLR (1 << 14)
#define GEN_RST_STS (1 << 9)
#define RTC_BATTERY_DEAD (1 << 2)
#define PWR_FLR (1 << 1)
#define SLEEP_AFTER_POWER_FAIL (1 << 0)
#define GEN_PMCON_LOCK 0xa6
#define SLP_STR_POL_LOCK (1 << 2)
#define ACPI_BASE_LOCK (1 << 1)
#define PMIR 0xac
#define PMIR_CF9LOCK (1 << 31)
#define PMIR_CF9GR (1 << 20)
#endif

200
u-boot/arch/x86/include/asm/arch-broadwell/me.h Normal file
View File

@@ -0,0 +1,200 @@
/*
* From coreboot soc/intel/broadwell/include/soc/me.h
*
* Copyright (C) 2014 Google Inc.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _asm_arch_me_h
#define _asm_arch_me_h
#include <asm/me_common.h>
#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
#define ME_HSIO_MESSAGE (7 << 28)
#define ME_HSIO_CMD_GETHSIOVER 1
#define ME_HSIO_CMD_CLOSE 0
/*
* Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
* to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature.
*/
#define PCI_ME_HFS2 0x48
/* Infrastructure Progress Values */
#define ME_HFS2_PHASE_ROM 0
#define ME_HFS2_PHASE_BUP 1
#define ME_HFS2_PHASE_UKERNEL 2
#define ME_HFS2_PHASE_POLICY 3
#define ME_HFS2_PHASE_MODULE_LOAD 4
#define ME_HFS2_PHASE_UNKNOWN 5
#define ME_HFS2_PHASE_HOST_COMM 6
/* Current State - Based on Infra Progress values. */
/* ROM State */
#define ME_HFS2_STATE_ROM_BEGIN 0
#define ME_HFS2_STATE_ROM_DISABLE 6
/* BUP State */
#define ME_HFS2_STATE_BUP_INIT 0
#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
#define ME_HFS2_STATE_BUP_FLOW_DET 4
#define ME_HFS2_STATE_BUP_VSCC_ERR 8
#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
#define ME_HFS2_STATE_BUP_M3 0x11
#define ME_HFS2_STATE_BUP_M0 0x12
#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c
#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f
#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
#define ME_HFS2_STATE_BUP_M0_CLK 0x26
#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28
#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
/* Policy Module State */
#define ME_HFS2_STATE_POLICY_ENTRY 0
#define ME_HFS2_STATE_POLICY_RCVD_S3 3
#define ME_HFS2_STATE_POLICY_RCVD_S4 4
#define ME_HFS2_STATE_POLICY_RCVD_S5 5
#define ME_HFS2_STATE_POLICY_RCVD_UPD 6
#define ME_HFS2_STATE_POLICY_RCVD_PCR 7
#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8
#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb
#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe
#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
/* Current PM Event Values */
#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
#define ME_HFS2_PMEVENT_S0MO_SXM3 7
#define ME_HFS2_PMEVENT_SXM3_S0M0 8
#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
struct me_hfs2 {
u32 bist_in_progress:1;
u32 reserved1:2;
u32 invoke_mebx:1;
u32 cpu_replaced_sts:1;
u32 mbp_rdy:1;
u32 mfs_failure:1;
u32 warm_reset_request:1;
u32 cpu_replaced_valid:1;
u32 reserved2:4;
u32 mbp_cleared:1;
u32 reserved3:2;
u32 current_state:8;
u32 current_pmevent:4;
u32 progress_code:4;
} __packed;
#define PCI_ME_HFS5 0x68
#define PCI_ME_H_GS2 0x70
#define PCI_ME_MBP_GIVE_UP 0x01
/* ICC Messages */
#define ICC_SET_CLOCK_ENABLES 0x3
#define ICC_API_VERSION_LYNXPOINT 0x00030000
struct icc_header {
u32 api_version;
u32 icc_command;
u32 icc_status;
u32 length;
u32 reserved;
} __packed;
struct icc_clock_enables_msg {
u32 clock_enables;
u32 clock_mask;
u32 no_response:1;
u32 reserved:31;
} __packed;
/*
* ME to BIOS Payload Datastructures and definitions. The ordering of the
* structures follows the ordering in the ME9 BWG.
*/
#define MBP_APPID_KERNEL 1
#define MBP_APPID_INTEL_AT 3
#define MBP_APPID_HWA 4
#define MBP_APPID_ICC 5
#define MBP_APPID_NFC 6
/* Kernel items: */
#define MBP_KERNEL_FW_VER_ITEM 1
#define MBP_KERNEL_FW_CAP_ITEM 2
#define MBP_KERNEL_ROM_BIST_ITEM 3
#define MBP_KERNEL_PLAT_KEY_ITEM 4
#define MBP_KERNEL_FW_TYPE_ITEM 5
#define MBP_KERNEL_MFS_FAILURE_ITEM 6
#define MBP_KERNEL_PLAT_TIME_ITEM 7
/* Intel AT items: */
#define MBP_INTEL_AT_STATE_ITEM 1
/* ICC Items: */
#define MBP_ICC_PROFILE_ITEM 1
/* HWA Items: */
#define MBP_HWA_REQUEST_ITEM 1
/* NFC Items: */
#define MBP_NFC_SUPPORT_DATA_ITEM 1
#define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item)
#define MBP_IDENT(appid, item) \
MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM)
struct mbp_fw_version_name {
u32 major_version:16;
u32 minor_version:16;
u32 hotfix_version:16;
u32 build_version:16;
} __packed;
struct icc_address_mask {
u16 icc_start_address;
u16 mask;
} __packed;
struct mbp_icc_profile {
u8 num_icc_profiles;
u8 icc_profile_soft_strap;
u8 icc_profile_index;
u8 reserved;
u32 icc_reg_bundles;
struct icc_address_mask icc_address_mask[0];
} __packed;
struct me_bios_payload {
struct mbp_fw_version_name *fw_version_name;
struct mbp_mefwcaps *fw_capabilities;
struct mbp_rom_bist_data *rom_bist_data;
struct mbp_platform_key *platform_key;
struct mbp_plat_type *fw_plat_type;
struct mbp_icc_profile *icc_profile;
struct mbp_at_state *at_state;
u32 *mfsintegrity;
struct mbp_plat_time *plat_time;
struct mbp_nfc_data *nfc_data;
};
#endif

153
u-boot/arch/x86/include/asm/arch-broadwell/pch.h Normal file
View File

@@ -0,0 +1,153 @@
/*
* Copyright (c) 2016 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_PCH_H
#define __ASM_ARCH_PCH_H
/* CPU bus clock is fixed at 100MHz */
#define CPU_BCLK 100
#define PMBASE 0x40
#define ACPI_CNTL 0x44
#define ACPI_EN (1 << 7)
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
#define GPIO_EN (1 << 4)
#define PCIEXBAR 0x60
#define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0)
/* RCB registers */
#define OIC 0x31fe /* 16bit */
#define HPTC 0x3404 /* 32bit */
#define FD 0x3418 /* 32bit */
/* Function Disable 1 RCBA 0x3418 */
#define PCH_DISABLE_ALWAYS (1 << 0)
/* PM registers */
#define TCO1_CNT 0x60
#define TCO_TMR_HLT (1 << 11)
/* Device 0:0.0 PCI configuration space */
#define EPBAR 0x40
#define MCHBAR 0x48
#define PCIEXBAR 0x60
#define DMIBAR 0x68
#define GGC 0x50 /* GMCH Graphics Control */
#define DEVEN 0x54 /* Device Enable */
#define DEVEN_D7EN (1 << 14)
#define DEVEN_D4EN (1 << 7)
#define DEVEN_D3EN (1 << 5)
#define DEVEN_D2EN (1 << 4)
#define DEVEN_D1F0EN (1 << 3)
#define DEVEN_D1F1EN (1 << 2)
#define DEVEN_D1F2EN (1 << 1)
#define DEVEN_D0EN (1 << 0)
#define DPR 0x5c
#define DPR_EPM (1 << 2)
#define DPR_PRS (1 << 1)
#define DPR_SIZE_MASK 0xff0
#define MCHBAR_PEI_VERSION 0x5034
#define BIOS_RESET_CPL 0x5da8
#define EDRAMBAR 0x5408
#define MCH_PAIR 0x5418
#define GDXCBAR 0x5420
#define PAM0 0x80
#define PAM1 0x81
#define PAM2 0x82
#define PAM3 0x83
#define PAM4 0x84
#define PAM5 0x85
#define PAM6 0x86
/* PCODE MMIO communications live in the MCHBAR. */
#define BIOS_MAILBOX_INTERFACE 0x5da4
#define MAILBOX_RUN_BUSY (1 << 31)
#define MAILBOX_BIOS_CMD_READ_PCS 1
#define MAILBOX_BIOS_CMD_WRITE_PCS 2
#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509
#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909
#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa
#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb
#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26
#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27
/* Errors are returned back in bits 7:0. */
#define MAILBOX_BIOS_ERROR_NONE 0
#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
#define MAILBOX_BIOS_ERROR_TIMEOUT 2
#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3
#define MAILBOX_BIOS_ERROR_RESERVED 4
#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5
#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
#define MAILBOX_BIOS_ERROR_VR_ERROR 7
/* Data is passed through bits 31:0 of the data register. */
#define BIOS_MAILBOX_DATA 0x5da0
/* SATA IOBP Registers */
#define SATA_IOBP_SP0_SECRT88 0xea002688
#define SATA_IOBP_SP1_SECRT88 0xea002488
#define SATA_SECRT88_VADJ_MASK 0xff
#define SATA_SECRT88_VADJ_SHIFT 16
#define SATA_IOBP_SP0DTLE_DATA 0xea002550
#define SATA_IOBP_SP0DTLE_EDGE 0xea002554
#define SATA_IOBP_SP1DTLE_DATA 0xea002750
#define SATA_IOBP_SP1DTLE_EDGE 0xea002754
#define SATA_DTLE_MASK 0xF
#define SATA_DTLE_DATA_SHIFT 24
#define SATA_DTLE_EDGE_SHIFT 16
/* Power Management */
#define GEN_PMCON_1 0xa0
#define SMI_LOCK (1 << 4)
#define GEN_PMCON_2 0xa2
#define SYSTEM_RESET_STS (1 << 4)
#define THERMTRIP_STS (1 << 3)
#define SYSPWR_FLR (1 << 1)
#define PWROK_FLR (1 << 0)
#define GEN_PMCON_3 0xa4
#define SUS_PWR_FLR (1 << 14)
#define GEN_RST_STS (1 << 9)
#define RTC_BATTERY_DEAD (1 << 2)
#define PWR_FLR (1 << 1)
#define SLEEP_AFTER_POWER_FAIL (1 << 0)
#define GEN_PMCON_LOCK 0xa6
#define SLP_STR_POL_LOCK (1 << 2)
#define ACPI_BASE_LOCK (1 << 1)
#define PMIR 0xac
#define PMIR_CF9LOCK (1 << 31)
#define PMIR_CF9GR (1 << 20)
/* Broadwell PCH (Wildcat Point) */
#define PCH_WPT_HSW_U_SAMPLE 0x9cc1
#define PCH_WPT_BDW_U_SAMPLE 0x9cc2
#define PCH_WPT_BDW_U_PREMIUM 0x9cc3
#define PCH_WPT_BDW_U_BASE 0x9cc5
#define PCH_WPT_BDW_Y_SAMPLE 0x9cc6
#define PCH_WPT_BDW_Y_PREMIUM 0x9cc7
#define PCH_WPT_BDW_Y_BASE 0x9cc9
#define PCH_WPT_BDW_H 0x9ccb
#define SA_IGD_OPROM_VENDEV 0x80860406
/* Dynamically determine if the part is ULT */
bool cpu_is_ult(void);
u32 pch_iobp_read(u32 address);
int pch_iobp_write(u32 address, u32 data);
int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
int pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp);
#endif

177
u-boot/arch/x86/include/asm/arch-broadwell/pei_data.h Normal file
View File

@@ -0,0 +1,177 @@
/*
* From Coreboot soc/intel/broadwell/include/soc/pei_data.h
*
* Copyright (C) 2014 Google Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef ASM_ARCH_PEI_DATA_H
#define ASM_ARCH_PEI_DATA_H
#include <linux/linkage.h>
#define PEI_VERSION 22
typedef void asmlinkage (*tx_byte_func)(unsigned char byte);
enum board_type {
BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */
BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */
BOARD_TYPE_USER1, /* SV mobile */
BOARD_TYPE_USER2, /* SV desktop */
BOARD_TYPE_USER3, /* SV server */
BOARD_TYPE_ULT, /* ULT */
BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */
BOARD_TYPE_UNKNOWN,
};
#define MAX_USB2_PORTS 14
#define MAX_USB3_PORTS 6
#define USB_OC_PIN_SKIP 8
enum usb2_port_location {
USB_PORT_BACK_PANEL = 0,
USB_PORT_FRONT_PANEL,
USB_PORT_DOCK,
USB_PORT_MINI_PCIE,
USB_PORT_FLEX,
USB_PORT_INTERNAL,
USB_PORT_SKIP,
USB_PORT_NGFF_DEVICE_DOWN,
};
struct usb2_port_setting {
/*
* Usb Port Length:
* [16:4] = length in inches in octal format
* [3:0] = decimal point
*/
uint16_t length;
uint8_t enable;
uint8_t oc_pin;
uint8_t location;
} __packed;
struct usb3_port_setting {
uint8_t enable;
uint8_t oc_pin;
/*
* Set to 0 if trace length is > 5 inches
* Set to 1 if trace length is <= 5 inches
*/
uint8_t fixed_eq;
} __packed;
struct pei_data {
uint32_t pei_version;
enum board_type board_type;
int boot_mode;
int ec_present;
int usbdebug;
/* Base addresses */
uint32_t pciexbar;
uint16_t smbusbar;
uint32_t xhcibar;
uint32_t ehcibar;
uint32_t gttbar;
uint32_t rcba;
uint32_t pmbase;
uint32_t gpiobase;
uint32_t temp_mmio_base;
uint32_t tseg_size;
/*
* 0 = leave channel enabled
* 1 = disable dimm 0 on channel
* 2 = disable dimm 1 on channel
* 3 = disable dimm 0+1 on channel
*/
int dimm_channel0_disabled;
int dimm_channel1_disabled;
/* Set to 0 for memory down */
uint8_t spd_addresses[4];
/* Enable 2x Refresh Mode */
int ddr_refresh_2x;
/* DQ pins are interleaved on board */
int dq_pins_interleaved;
/* Limit DDR3 frequency */
int max_ddr3_freq;
/* Disable self refresh */
int disable_self_refresh;
/* Disable cmd power/CKEPD */
int disable_cmd_pwr;
/* USB port configuration */
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
/*
* USB3 board specific PHY tuning
*/
/* Valid range: 0x69 - 0x80 */
uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS];
/* Valid range: 0x80 - 0x9c */
uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS];
/* Valid range: 0x39 - 0x80 */
uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS];
/* Valid range: 0x3d - 0x4a */
uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS];
/* Console output function */
tx_byte_func tx_byte;
/*
* DIMM SPD data for memory down configurations
* [CHANNEL][SLOT][SPD]
*/
uint8_t spd_data[2][2][512];
/*
* LPDDR3 DQ byte map
* [CHANNEL][ITERATION][2]
*
* Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
* DQByteMap[0] - ClkDQByteMap:
* - If clock is per rank, program to [0xFF, 0xFF]
* - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
* - If clock is shared by 2 ranks but does not go to all bytes,
* Entry[i] defines which DQ bytes Group i services
* DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
* DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
* DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
* For DDR, DQByteMap[3:1] = [0xFF, 0]
* DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
* since we have 1 CTL / rank
* DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
* since we have 1 CA Vref
*/
uint8_t dq_map[2][6][2];
/*
* LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
* [CHANNEL][MAX_BYTES]
*/
uint8_t dqs_map[2][8];
/* Data read from flash and passed into MRC */
const void *saved_data;
int saved_data_size;
/* Disable use of saved data (can be set by mainboard) */
int disable_saved_data;
/* Data from MRC that should be saved to flash */
void *data_to_save;
int data_to_save_size;
struct pei_memory_info meminfo;
} __packed;
void mainboard_fill_pei_data(struct pei_data *pei_data);
void broadwell_fill_pei_data(struct pei_data *pei_data);
#endif

129
u-boot/arch/x86/include/asm/arch-broadwell/pm.h Normal file
View File

@@ -0,0 +1,129 @@
/*
* From coreboot src/soc/intel/broadwell/include/soc/pm.h
*
* Copyright (C) 2016 Google, Inc.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_PM_H
#define __ASM_ARCH_PM_H
#define PM1_STS 0x00
#define WAK_STS (1 << 15)
#define PCIEXPWAK_STS (1 << 14)
#define PRBTNOR_STS (1 << 11)
#define RTC_STS (1 << 10)
#define PWRBTN_STS (1 << 8)
#define GBL_STS (1 << 5)
#define BM_STS (1 << 4)
#define TMROF_STS (1 << 0)
#define PM1_EN 0x02
#define PCIEXPWAK_DIS (1 << 14)
#define RTC_EN (1 << 10)
#define PWRBTN_EN (1 << 8)
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
#define SLP_EN (1 << 13)
#define SLP_TYP (7 << 10)
#define SLP_TYP_SHIFT 10
#define SLP_TYP_S0 0
#define SLP_TYP_S1 1
#define SLP_TYP_S3 5
#define SLP_TYP_S4 6
#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)
#define PM1_TMR 0x08
#define SMI_EN 0x30
#define XHCI_SMI_EN (1 << 31)
#define ME_SMI_EN (1 << 30)
#define GPIO_UNLOCK_SMI_EN (1 << 27)
#define INTEL_USB2_EN (1 << 18)
#define LEGACY_USB2_EN (1 << 17)
#define PERIODIC_EN (1 << 14)
#define TCO_EN (1 << 13)
#define MCSMI_EN (1 << 11)
#define BIOS_RLS (1 << 7)
#define SWSMI_TMR_EN (1 << 6)
#define APMC_EN (1 << 5)
#define SLP_SMI_EN (1 << 4)
#define LEGACY_USB_EN (1 << 3)
#define BIOS_EN (1 << 2)
#define EOS (1 << 1)
#define GBL_SMI_EN (1 << 0)
#define SMI_STS 0x34
#define UPWRC 0x3c
#define UPWRC_WS (1 << 8)
#define UPWRC_WE (1 << 1)
#define UPWRC_SMI (1 << 0)
#define GPE_CNTL 0x42
#define SWGPE_CTRL (1 << 1)
#define DEVACT_STS 0x44
#define PM2_CNT 0x50
#define TCO1_CNT 0x60
#define TCO_TMR_HLT (1 << 11)
#define TCO1_STS 0x64
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
#define TCO2_STS_SECOND_TO (1 << 1)
#define GPE0_REG_MAX 4
#define GPE0_REG_SIZE 32
#define GPE0_STS(x) (0x80 + (x * 4))
#define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */
#define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */
#define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */
#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */
#define WADT_STS (1 << 18)
#define GP27_STS (1 << 16)
#define PME_B0_STS (1 << 13)
#define ME_SCI_STS (1 << 12)
#define PME_STS (1 << 11)
#define BATLOW_STS (1 << 10)
#define PCI_EXP_STS (1 << 9)
#define SMB_WAK_STS (1 << 7)
#define TCOSCI_STS (1 << 6)
#define SWGPE_STS (1 << 2)
#define HOT_PLUG_STS (1 << 1)
#define GPE0_EN(x) (0x90 + (x * 4))
#define WADT_en (1 << 18)
#define GP27_EN (1 << 16)
#define PME_B0_EN (1 << 13)
#define ME_SCI_EN (1 << 12)
#define PME_EN (1 << 11)
#define BATLOW_EN (1 << 10)
#define PCI_EXP_EN (1 << 9)
#define TCOSCI_EN (1 << 6)
#define SWGPE_EN (1 << 2)
#define HOT_PLUG_EN (1 << 1)
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
#define SLEEP_STATE_S0 0
#define SLEEP_STATE_S3 3
#define SLEEP_STATE_S5 5
struct chipset_power_state {
uint16_t pm1_sts;
uint16_t pm1_en;
uint32_t pm1_cnt;
uint16_t tco1_sts;
uint16_t tco2_sts;
uint32_t gpe0_sts[4];
uint32_t gpe0_en[4];
uint16_t gen_pmcon1;
uint16_t gen_pmcon2;
uint16_t gen_pmcon3;
int prev_sleep_state;
uint16_t hsio_version;
uint16_t hsio_checksum;
};
void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps);
#endif

58
u-boot/arch/x86/include/asm/arch-broadwell/rcb.h Normal file
View File

@@ -0,0 +1,58 @@
/*
* Copyright (c) 2016 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __asm_arch_rcba_h
#define __asm_arch_rcba_h
#define PMSYNC_CONFIG 0x33c4 /* 32bit */
#define PMSYNC_CONFIG2 0x33cc /* 32bit */
#define DEEP_S3_POL 0x3328 /* 32bit */
#define DEEP_S3_EN_AC (1 << 0)
#define DEEP_S3_EN_DC (1 << 1)
#define DEEP_S5_POL 0x3330 /* 32bit */
#define DEEP_S5_EN_AC (1 << 14)
#define DEEP_S5_EN_DC (1 << 15)
#define DEEP_SX_CONFIG 0x3334 /* 32bit */
#define DEEP_SX_WAKE_PIN_EN (1 << 2)
#define DEEP_SX_ACPRESENT_PD (1 << 1)
#define DEEP_SX_GP27_PIN_EN (1 << 0)
#define PMSYNC_CONFIG 0x33c4 /* 32bit */
#define PMSYNC_CONFIG2 0x33cc /* 32bit */
#define RC 0x3400 /* 32bit */
#define HPTC 0x3404 /* 32bit */
#define GCS 0x3410 /* 32bit */
#define BUC 0x3414 /* 32bit */
#define PCH_DISABLE_GBE (1 << 5)
#define FD 0x3418 /* 32bit */
#define FDSW 0x3420 /* 8bit */
#define DISPBDF 0x3424 /* 16bit */
#define FD2 0x3428 /* 32bit */
#define CG 0x341c /* 32bit */
/* Function Disable 1 RCBA 0x3418 */
#define PCH_DISABLE_ALWAYS (1 << 0)
#define PCH_DISABLE_ADSPD (1 << 1)
#define PCH_DISABLE_SATA1 (1 << 2)
#define PCH_DISABLE_SMBUS (1 << 3)
#define PCH_DISABLE_HD_AUDIO (1 << 4)
#define PCH_DISABLE_EHCI2 (1 << 13)
#define PCH_DISABLE_LPC (1 << 14)
#define PCH_DISABLE_EHCI1 (1 << 15)
#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
#define PCH_DISABLE_THERMAL (1 << 24)
#define PCH_DISABLE_SATA2 (1 << 25)
#define PCH_DISABLE_XHCI (1 << 27)
/* Function Disable 2 RCBA 0x3428 */
#define PCH_DISABLE_KT (1 << 4)
#define PCH_DISABLE_IDER (1 << 3)
#define PCH_DISABLE_MEI2 (1 << 2)
#define PCH_DISABLE_MEI1 (1 << 1)
#define PCH_ENABLE_DBDF (1 << 0)
#endif

87
u-boot/arch/x86/include/asm/arch-broadwell/spi.h Normal file
View File

@@ -0,0 +1,87 @@
/*
* Copyright (C) 2014 Google Inc.
*
* This file is from coreboot soc/intel/broadwell/include/soc/spi.h
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _BROADWELL_SPI_H_
#define _BROADWELL_SPI_H_
/*
* SPI Opcode Menu setup for SPIBAR lockdown
* should support most common flash chips.
*/
#define SPIBAR_OFFSET 0x3800
#define SPI_REG(x) (RCB_REG(SPIBAR_OFFSET + (x)))
/* Reigsters within the SPIBAR */
#define SPIBAR_SSFC 0x91
#define SPIBAR_FDOC 0xb0
#define SPIBAR_FDOD 0xb4
#define SPIBAR_PREOP 0x94
#define SPIBAR_OPTYPE 0x96
#define SPIBAR_OPMENU_LOWER 0x98
#define SPIBAR_OPMENU_UPPER 0x9c
#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
#define SPI_OPTYPE_0 0x01 /* Write, no address */
#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
#define SPI_OPTYPE_1 0x03 /* Write, address required */
#define SPI_OPMENU_2 0x03 /* READ: Read Data */
#define SPI_OPTYPE_2 0x02 /* Read, address required */
#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
#define SPI_OPTYPE_3 0x00 /* Read, no address */
#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
#define SPI_OPTYPE_4 0x03 /* Write, address required */
#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
#define SPI_OPTYPE_5 0x00 /* Read, no address */
#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
#define SPI_OPTYPE_6 0x03 /* Write, address required */
#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
#define SPI_OPTYPE_7 0x02 /* Read, address required */
#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
(SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
#define SPIBAR_FADDR 0x08 /* SPI flash address */
#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */
#define SPIBAR_SSFS 0x90
#define SPIBAR_SSFS_ERROR (1 << 3)
#define SPIBAR_SSFS_DONE (1 << 2)
#define SPIBAR_SSFC 0x91
#define SPIBAR_SSFC_DATA (1 << 14)
#define SPIBAR_SSFC_GO (1 << 1)
#endif

61
u-boot/arch/x86/include/asm/arch-coreboot/sysinfo.h Normal file
View File

@@ -0,0 +1,61 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _COREBOOT_SYSINFO_H
#define _COREBOOT_SYSINFO_H
#include <asm/coreboot_tables.h>
/* Maximum number of memory range definitions */
#define SYSINFO_MAX_MEM_RANGES 32
/* Allow a maximum of 8 GPIOs */
#define SYSINFO_MAX_GPIOS 8
struct sysinfo_t {
int n_memranges;
struct memrange {
unsigned long long base;
unsigned long long size;
unsigned int type;
} memrange[SYSINFO_MAX_MEM_RANGES];
u32 cmos_range_start;
u32 cmos_range_end;
u32 cmos_checksum_location;
u32 vbnv_start;
u32 vbnv_size;
char *version;
char *extra_version;
char *build;
char *compile_time;
char *compile_by;
char *compile_host;
char *compile_domain;
char *compiler;
char *linker;
char *assembler;
struct cb_framebuffer *framebuffer;
int num_gpios;
struct cb_gpio gpios[SYSINFO_MAX_GPIOS];
void *vdat_addr;
u32 vdat_size;
void *tstamp_table;
void *cbmem_cons;
struct cb_serial *serial;
};
extern struct sysinfo_t lib_sysinfo;
int get_coreboot_info(struct sysinfo_t *info);
#endif

48
u-boot/arch/x86/include/asm/arch-coreboot/timestamp.h Normal file
View File

@@ -0,0 +1,48 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __COREBOOT_TIMESTAMP_H__
#define __COREBOOT_TIMESTAMP_H__
enum timestamp_id {
/* coreboot specific timestamp IDs */
TS_START_ROMSTAGE = 1,
TS_BEFORE_INITRAM = 2,
TS_AFTER_INITRAM = 3,
TS_END_ROMSTAGE = 4,
TS_START_COPYRAM = 8,
TS_END_COPYRAM = 9,
TS_START_RAMSTAGE = 10,
TS_DEVICE_ENUMERATE = 30,
TS_DEVICE_CONFIGURE = 40,
TS_DEVICE_ENABLE = 50,
TS_DEVICE_INITIALIZE = 60,
TS_DEVICE_DONE = 70,
TS_CBMEM_POST = 75,
TS_WRITE_TABLES = 80,
TS_LOAD_PAYLOAD = 90,
TS_ACPI_WAKE_JUMP = 98,
TS_SELFBOOT_JUMP = 99,
/* U-Boot entry IDs start at 1000 */
TS_U_BOOT_INITTED = 1000, /* This is where u-boot starts */
TS_U_BOOT_START_KERNEL = 1100, /* Right before jumping to kernel. */
};
void timestamp_init(void);
void timestamp_add(enum timestamp_id id, uint64_t ts_time);
void timestamp_add_now(enum timestamp_id id);
/**
* timestamp_add_to_bootstage - Add important coreboot timestamps to bootstage
*
* @return 0 if ok, -1 if no timestamps were found
*/
int timestamp_add_to_bootstage(void);
#endif

12
u-boot/arch/x86/include/asm/arch-ivybridge/bd82x6x.h Normal file
View File

@@ -0,0 +1,12 @@
/*
* Copyright (C) 2014 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_BD82X6X_H
#define _ASM_ARCH_BD82X6X_H
int gma_func0_init(struct udevice *dev);
#endif

40
u-boot/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FSP_CONFIGS_H__
#define __FSP_CONFIGS_H__
struct platform_config {
u8 enable_ht;
u8 enable_turbo;
u8 enable_memory_down;
u8 enable_fast_boot;
};
/*
* Dummy structure for now as currently only SPD is verified in U-Boot.
*
* We can add the missing parameters when adding support on a board with
* memory down configuration.
*/
struct memory_config {
u8 dummy;
};
struct fsp_config_data {
struct fsp_cfg_common common;
struct platform_config plat_config;
struct memory_config mem_config;
};
struct fspinit_rtbuf {
u32 stack_top;
u32 boot_mode;
struct platform_config *plat_config;
struct memory_config *mem_config;
};
#endif /* __FSP_CONFIGS_H__ */

12
u-boot/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h Normal file
View File

@@ -0,0 +1,12 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FSP_VPD_H__
#define __FSP_VPD_H__
/* IvyBridge FSP does not support VPD/UPD */
#endif

60
u-boot/arch/x86/include/asm/arch-ivybridge/me.h Normal file
View File

@@ -0,0 +1,60 @@
/*
* From Coreboot src/southbridge/intel/bd82x6x/me.h
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_INTEL_ME_H
#define _ASM_INTEL_ME_H
#include <asm/me_common.h>
struct __packed mbp_fw_version_name {
u32 major_version:16;
u32 minor_version:16;
u32 hotfix_version:16;
u32 build_version:16;
};
struct __packed mbp_icc_profile {
u8 num_icc_profiles;
u8 icc_profile_soft_strap;
u8 icc_profile_index;
u8 reserved;
u32 register_lock_mask[3];
};
struct __packed platform_type_rule_data {
u32 platform_target_usage_type:4;
u32 platform_target_market_type:2;
u32 super_sku:1;
u32 reserved:1;
u32 intel_me_fw_image_type:4;
u32 platform_brand:4;
u32 reserved_1:16;
};
struct __packed mbp_fw_caps {
struct mefwcaps_sku fw_capabilities;
u8 available;
};
struct __packed mbp_plat_type {
struct platform_type_rule_data rule_data;
u8 available;
};
struct __packed me_bios_payload {
struct mbp_fw_version_name fw_version_name;
struct mbp_fw_caps fw_caps_sku;
struct mbp_rom_bist_data rom_bist_data;
struct mbp_platform_key platform_key;
struct mbp_plat_type fw_plat_type;
struct mbp_icc_profile icc_profile;
struct tdt_state_info at_state;
u32 mfsintegrity;
};
#endif

67
u-boot/arch/x86/include/asm/arch-ivybridge/model_206ax.h Normal file
View File

@@ -0,0 +1,67 @@
/*
* From Coreboot file of the same name
*
* Copyright (C) 2011 The ChromiumOS Authors.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_ARCH_MODEL_206AX_H
#define _ASM_ARCH_MODEL_206AX_H
/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
#define SANDYBRIDGE_BCLK 100
#define CPUID_VMX (1 << 5)
#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
#define IA32_MC0_STATUS 0x401
#define MSR_MISC_PWR_MGMT 0x1aa
#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
#define MSR_PKGC3_IRTL 0x60a
#define MSR_PKGC6_IRTL 0x60b
#define MSR_PKGC7_IRTL 0x60c
#define IRTL_VALID (1 << 15)
#define IRTL_1_NS (0 << 10)
#define IRTL_32_NS (1 << 10)
#define IRTL_1024_NS (2 << 10)
#define IRTL_32768_NS (3 << 10)
#define IRTL_1048576_NS (4 << 10)
#define IRTL_33554432_NS (5 << 10)
#define IRTL_RESPONSE_MASK (0x3ff)
#define MSR_PP0_CURRENT_CONFIG 0x601
#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
#define MSR_PP1_CURRENT_CONFIG 0x602
#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
#define MSR_PKG_POWER_SKU 0x614
#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
#define MSR_CONFIG_TDP_LEVEL1 0x649
#define MSR_CONFIG_TDP_LEVEL2 0x64a
#define MSR_CONFIG_TDP_CONTROL 0x64b
/* P-state configuration */
#define PSS_MAX_ENTRIES 8
#define PSS_RATIO_STEP 2
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
#endif

425
u-boot/arch/x86/include/asm/arch-ivybridge/pch.h Normal file
View File

@@ -0,0 +1,425 @@
/*
* Copyright (c) 2014 Google, Inc
*
* From Coreboot src/southbridge/intel/bd82x6x/pch.h
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_ARCH_PCH_H
#define _ASM_ARCH_PCH_H
#include <pci.h>
/* PCH types */
#define PCH_TYPE_CPT 0x1c /* CougarPoint */
#define PCH_TYPE_PPT 0x1e /* IvyBridge */
/* PCH stepping values for LPC device */
#define PCH_STEP_A0 0
#define PCH_STEP_A1 1
#define PCH_STEP_B0 2
#define PCH_STEP_B1 3
#define PCH_STEP_B2 4
#define PCH_STEP_B3 5
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
#define SMBUS_IO_BASE 0x0400
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS 0x06
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
#define BCTRL 0x3e
#define SBR (1 << 6)
#define SEE (1 << 1)
#define PERE (1 << 0)
#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
#define PCH_ME_DEV PCI_BDF(0, 0x16, 0)
#define PCH_PCIE_DEV_SLOT 28
#define PCH_DEV PCI_BDF(0, 0, 0)
#define PCH_VIDEO_DEV PCI_BDF(0, 2, 0)
/* PCI Configuration Space (D31:F0): LPC */
#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
#define SERIRQ_CNTL 0x64
#define GEN_PMCON_1 0xa0
#define GEN_PMCON_2 0xa2
#define GEN_PMCON_3 0xa4
#define ETR3 0xac
#define ETR3_CWORWRE (1 << 18)
#define ETR3_CF9GR (1 << 20)
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)
#define RTC_POWER_FAILED (1 << 1)
#define SLEEP_AFTER_POWER_FAIL (1 << 0)
#define BIOS_CNTL 0xDC
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
#define GPIO_ROUT 0xb8
#define PIRQA_ROUT 0x60
#define PIRQB_ROUT 0x61
#define PIRQC_ROUT 0x62
#define PIRQD_ROUT 0x63
#define PIRQE_ROUT 0x68
#define PIRQF_ROUT 0x69
#define PIRQG_ROUT 0x6A
#define PIRQH_ROUT 0x6B
#define GEN_PMCON_1 0xa0
#define GEN_PMCON_2 0xa2
#define GEN_PMCON_3 0xa4
#define ETR3 0xac
#define ETR3_CWORWRE (1 << 18)
#define ETR3_CF9GR (1 << 20)
#define PMBASE 0x40
#define ACPI_CNTL 0x44
#define BIOS_CNTL 0xDC
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
#define GPIO_ROUT 0xb8
/* PCI Configuration Space (D31:F1): IDE */
#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
#define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2)
#define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5)
#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
#define IDE_SSDE1 (1 << 3)
#define IDE_SSDE0 (1 << 2)
#define IDE_PSDE1 (1 << 1)
#define IDE_PSDE0 (1 << 0)
#define IDE_SDMA_TIM 0x4a
#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
#define SIG_MODE_SEC_NORMAL (0 << 18)
#define SIG_MODE_SEC_TRISTATE (1 << 18)
#define SIG_MODE_SEC_DRIVELOW (2 << 18)
#define SIG_MODE_PRI_NORMAL (0 << 16)
#define SIG_MODE_PRI_TRISTATE (1 << 16)
#define SIG_MODE_PRI_DRIVELOW (2 << 16)
#define FAST_SCB1 (1 << 15)
#define FAST_SCB0 (1 << 14)
#define FAST_PCB1 (1 << 13)
#define FAST_PCB0 (1 << 12)
#define SCB1 (1 << 3)
#define SCB0 (1 << 2)
#define PCB1 (1 << 1)
#define PCB0 (1 << 0)
#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
#define SATA_SP 0xd0 /* Scratchpad */
/* SATA IOBP Registers */
#define SATA_IOBP_SP0G3IR 0xea000151
#define SATA_IOBP_SP1G3IR 0xea000051
/* PCI Configuration Space (D31:F3): SMBus */
#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3)
#define SMB_BASE 0x20
#define HOSTC 0x40
#define SMB_RCV_SLVA 0x09
/* HOSTC bits */
#define I2C_EN (1 << 2)
#define SMB_SMI_EN (1 << 1)
#define HST_EN (1 << 0)
/* SMBus I/O bits. */
#define SMBHSTSTAT 0x0
#define SMBHSTCTL 0x2
#define SMBHSTCMD 0x3
#define SMBXMITADD 0x4
#define SMBHSTDAT0 0x5
#define SMBHSTDAT1 0x6
#define SMBBLKDAT 0x7
#define SMBTRNSADD 0x9
#define SMBSLVDATA 0xa
#define SMLINK_PIN_CTL 0xe
#define SMBUS_PIN_CTL 0xf
#define SMBUS_TIMEOUT (10 * 1000 * 100)
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
#define VCAP2 0x0008 /* 32bit */
#define PVC 0x000c /* 16bit */
#define PVS 0x000e /* 16bit */
#define V0CAP 0x0010 /* 32bit */
#define V0CTL 0x0014 /* 32bit */
#define V0STS 0x001a /* 16bit */
#define V1CAP 0x001c /* 32bit */
#define V1CTL 0x0020 /* 32bit */
#define V1STS 0x0026 /* 16bit */
#define RCTCL 0x0100 /* 32bit */
#define ESD 0x0104 /* 32bit */
#define ULD 0x0110 /* 32bit */
#define ULBA 0x0118 /* 64bit */
#define RP1D 0x0120 /* 32bit */
#define RP1BA 0x0128 /* 64bit */
#define RP2D 0x0130 /* 32bit */
#define RP2BA 0x0138 /* 64bit */
#define RP3D 0x0140 /* 32bit */
#define RP3BA 0x0148 /* 64bit */
#define RP4D 0x0150 /* 32bit */
#define RP4BA 0x0158 /* 64bit */
#define HDD 0x0160 /* 32bit */
#define HDBA 0x0168 /* 64bit */
#define RP5D 0x0170 /* 32bit */
#define RP5BA 0x0178 /* 64bit */
#define RP6D 0x0180 /* 32bit */
#define RP6BA 0x0188 /* 64bit */
#define RPC 0x0400 /* 32bit */
#define RPFN 0x0404 /* 32bit */
#define TRSR 0x1e00 /* 8bit */
#define TRCR 0x1e10 /* 64bit */
#define TWDR 0x1e18 /* 64bit */
#define IOTR0 0x1e80 /* 64bit */
#define IOTR1 0x1e88 /* 64bit */
#define IOTR2 0x1e90 /* 64bit */
#define IOTR3 0x1e98 /* 64bit */
#define TCTL 0x3000 /* 8bit */
#define NOINT 0
#define INTA 1
#define INTB 2
#define INTC 3
#define INTD 4
#define DIR_IDR 12 /* Interrupt D Pin Offset */
#define DIR_ICR 8 /* Interrupt C Pin Offset */
#define DIR_IBR 4 /* Interrupt B Pin Offset */
#define DIR_IAR 0 /* Interrupt A Pin Offset */
#define PIRQA 0
#define PIRQB 1
#define PIRQC 2
#define PIRQD 3
#define PIRQE 4
#define PIRQF 5
#define PIRQG 6
#define PIRQH 7
/* IO Buffer Programming */
#define IOBPIRI 0x2330
#define IOBPD 0x2334
#define IOBPS 0x2338
#define IOBPS_RW_BX ((1 << 9)|(1 << 10))
#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
#define D31IP 0x3100 /* 32bit */
#define D31IP_TTIP 24 /* Thermal Throttle Pin */
#define D31IP_SIP2 20 /* SATA Pin 2 */
#define D31IP_SMIP 12 /* SMBUS Pin */
#define D31IP_SIP 8 /* SATA Pin */
#define D30IP 0x3104 /* 32bit */
#define D30IP_PIP 0 /* PCI Bridge Pin */
#define D29IP 0x3108 /* 32bit */
#define D29IP_E1P 0 /* EHCI #1 Pin */
#define D28IP 0x310c /* 32bit */
#define D28IP_P8IP 28 /* PCI Express Port 8 */
#define D28IP_P7IP 24 /* PCI Express Port 7 */
#define D28IP_P6IP 20 /* PCI Express Port 6 */
#define D28IP_P5IP 16 /* PCI Express Port 5 */
#define D28IP_P4IP 12 /* PCI Express Port 4 */
#define D28IP_P3IP 8 /* PCI Express Port 3 */
#define D28IP_P2IP 4 /* PCI Express Port 2 */
#define D28IP_P1IP 0 /* PCI Express Port 1 */
#define D27IP 0x3110 /* 32bit */
#define D27IP_ZIP 0 /* HD Audio Pin */
#define D26IP 0x3114 /* 32bit */
#define D26IP_E2P 0 /* EHCI #2 Pin */
#define D25IP 0x3118 /* 32bit */
#define D25IP_LIP 0 /* GbE LAN Pin */
#define D22IP 0x3124 /* 32bit */
#define D22IP_KTIP 12 /* KT Pin */
#define D22IP_IDERIP 8 /* IDE-R Pin */
#define D22IP_MEI2IP 4 /* MEI #2 Pin */
#define D22IP_MEI1IP 0 /* MEI #1 Pin */
#define D20IP 0x3128 /* 32bit */
#define D20IP_XHCIIP 0
#define D31IR 0x3140 /* 16bit */
#define D30IR 0x3142 /* 16bit */
#define D29IR 0x3144 /* 16bit */
#define D28IR 0x3146 /* 16bit */
#define D27IR 0x3148 /* 16bit */
#define D26IR 0x314c /* 16bit */
#define D25IR 0x3150 /* 16bit */
#define D22IR 0x315c /* 16bit */
#define D20IR 0x3160 /* 16bit */
#define OIC 0x31fe /* 16bit */
#define SPI_FREQ_SWSEQ 0x3893
#define SPI_DESC_COMP0 0x38b0
#define SPI_FREQ_WR_ERA 0x38b4
#define DIR_ROUTE(a, b, c, d) \
(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
((b) << DIR_IBR) | ((a) << DIR_IAR))
#define HPTC 0x3404 /* 32bit */
#define BUC 0x3414 /* 32bit */
#define PCH_DISABLE_GBE (1 << 5)
#define FD 0x3418 /* 32bit */
#define DISPBDF 0x3424 /* 16bit */
#define FD2 0x3428 /* 32bit */
#define CG 0x341c /* 32bit */
/* Function Disable 1 RCBA 0x3418 */
#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
#define PCH_DISABLE_P2P (1 << 1)
#define PCH_DISABLE_SATA1 (1 << 2)
#define PCH_DISABLE_SMBUS (1 << 3)
#define PCH_DISABLE_HD_AUDIO (1 << 4)
#define PCH_DISABLE_EHCI2 (1 << 13)
#define PCH_DISABLE_LPC (1 << 14)
#define PCH_DISABLE_EHCI1 (1 << 15)
#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
#define PCH_DISABLE_THERMAL (1 << 24)
#define PCH_DISABLE_SATA2 (1 << 25)
#define PCH_DISABLE_XHCI (1 << 27)
/* Function Disable 2 RCBA 0x3428 */
#define PCH_DISABLE_KT (1 << 4)
#define PCH_DISABLE_IDER (1 << 3)
#define PCH_DISABLE_MEI2 (1 << 2)
#define PCH_DISABLE_MEI1 (1 << 1)
#define PCH_ENABLE_DBDF (1 << 0)
/* ICH7 GPIOBASE */
#define GPIO_USE_SEL 0x00
#define GP_IO_SEL 0x04
#define GP_LVL 0x0c
#define GPO_BLINK 0x18
#define GPI_INV 0x2c
#define GPIO_USE_SEL2 0x30
#define GP_IO_SEL2 0x34
#define GP_LVL2 0x38
#define GPIO_USE_SEL3 0x40
#define GP_IO_SEL3 0x44
#define GP_LVL3 0x48
#define GP_RST_SEL1 0x60
#define GP_RST_SEL2 0x64
#define GP_RST_SEL3 0x68
/* ICH7 PMBASE */
#define PM1_STS 0x00
#define WAK_STS (1 << 15)
#define PCIEXPWAK_STS (1 << 14)
#define PRBTNOR_STS (1 << 11)
#define RTC_STS (1 << 10)
#define PWRBTN_STS (1 << 8)
#define GBL_STS (1 << 5)
#define BM_STS (1 << 4)
#define TMROF_STS (1 << 0)
#define PM1_EN 0x02
#define PCIEXPWAK_DIS (1 << 14)
#define RTC_EN (1 << 10)
#define PWRBTN_EN (1 << 8)
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
#define SLP_EN (1 << 13)
#define SLP_TYP (7 << 10)
#define SLP_TYP_S0 0
#define SLP_TYP_S1 1
#define SLP_TYP_S3 5
#define SLP_TYP_S4 6
#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)
#define PM1_TMR 0x08
#define PROC_CNT 0x10
#define LV2 0x14
#define LV3 0x15
#define LV4 0x16
#define PM2_CNT 0x50 /* mobile only */
#define GPE0_STS 0x20
#define PME_B0_STS (1 << 13)
#define PME_STS (1 << 11)
#define BATLOW_STS (1 << 10)
#define PCI_EXP_STS (1 << 9)
#define RI_STS (1 << 8)
#define SMB_WAK_STS (1 << 7)
#define TCOSCI_STS (1 << 6)
#define SWGPE_STS (1 << 2)
#define HOT_PLUG_STS (1 << 1)
#define GPE0_EN 0x28
#define PME_B0_EN (1 << 13)
#define PME_EN (1 << 11)
#define TCOSCI_EN (1 << 6)
#define SMI_EN 0x30
#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
#define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
#define MCSMI_EN (1 << 11) /* Trap microcontroller range access */
#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
#define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */
#define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */
#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
#define EOS (1 << 1) /* End of SMI (deassert SMI#) */
#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
#define SMI_STS 0x34
#define ALT_GP_SMI_EN 0x38
#define ALT_GP_SMI_STS 0x3a
#define GPE_CNTL 0x42
#define DEVACT_STS 0x44
#define SS_CNT 0x50
#define C3_RES 0x54
#define TCO1_STS 0x64
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
/**
* pch_silicon_revision() - Read silicon device ID from the PCH
*
* @dev: PCH device
* @return silicon device ID
*/
int pch_silicon_type(struct udevice *dev);
/**
* pch_pch_iobp_update() - Update a pch register
*
* @dev: PCH device
* @address: Address to update
* @andvalue: Value to AND with existing value
* @orvalue: Value to OR with existing value
*/
void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
u32 orvalue);
#endif

123
u-boot/arch/x86/include/asm/arch-ivybridge/pei_data.h Normal file
View File

@@ -0,0 +1,123 @@
/*
* Copyright (c) 2011, Google Inc.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef ASM_ARCH_PEI_DATA_H
#define ASM_ARCH_PEI_DATA_H
#include <linux/linkage.h>
struct pch_usb3_controller_settings {
/* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */
uint16_t mode;
/* 4 bit mask, 1: switchable, 0: not switchable */
uint16_t hs_port_switch_mask;
/* 0: No xHCI preOS driver, 1: xHCI preOS driver */
uint16_t preboot_support;
/* 0: Disable, 1: Enable */
uint16_t xhci_streams;
};
typedef asmlinkage void (*tx_byte_func)(unsigned char byte);
#define PEI_VERSION 6
struct __packed pei_data {
uint32_t pei_version;
uint32_t mchbar;
uint32_t dmibar;
uint32_t epbar;
uint32_t pciexbar;
uint16_t smbusbar;
uint32_t wdbbar;
uint32_t wdbsize;
uint32_t hpet_address;
uint32_t rcba;
uint32_t pmbase;
uint32_t gpiobase;
uint32_t thermalbase;
uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */
uint32_t tseg_size;
uint8_t spd_addresses[4];
uint8_t ts_addresses[4];
int boot_mode;
int ec_present;
int gbe_enable;
/*
* 0 = leave channel enabled
* 1 = disable dimm 0 on channel
* 2 = disable dimm 1 on channel
* 3 = disable dimm 0+1 on channel
*/
int dimm_channel0_disabled;
int dimm_channel1_disabled;
/* Seed values saved in CMOS */
uint32_t scrambler_seed;
uint32_t scrambler_seed_s3;
/* Data read from flash and passed into MRC */
unsigned char *mrc_input;
unsigned int mrc_input_len;
/* Data from MRC that should be saved to flash */
unsigned char *mrc_output;
unsigned int mrc_output_len;
/*
* Max frequency DDR3 could be ran at. Could be one of four values:
* 800, 1067, 1333, 1600
*/
uint32_t max_ddr3_freq;
/*
* USB Port Configuration:
* [0] = enable
* [1] = overcurrent pin
* [2] = length
*
* Ports 0-7 can be mapped to OC0-OC3
* Ports 8-13 can be mapped to OC4-OC7
*
* Port Length
* MOBILE:
* < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
* < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude)
* DESKTOP:
* < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude)
* < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude)
* < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
*/
uint16_t usb_port_config[16][3];
/* See the usb3 struct above for details */
struct pch_usb3_controller_settings usb3;
/*
* SPD data array for onboard RAM. Specify address 0xf0,
* 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
* spd_address for a given "DIMM".
*/
uint8_t spd_data[4][256];
tx_byte_func tx_byte;
int ddr3lv_support;
/*
* pcie_init needs to be set to 1 to have the system agent initialise
* PCIe. Note: This should only be required if your system has Gen3
* devices and it will increase your boot time by at least 100ms.
*/
int pcie_init;
/*
* N mode functionality. Leave this setting at 0.
* 0 Auto
* 1 1N
* 2 2N
*/
int nmode;
/*
* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows
* for DIMM SPD data to specify whether double-rate is required for
* extended operating temperature range.
* 0 Enable double rate based upon temperature thresholds
* 1 Normal rate
* 2 Always enable double rate
*/
int ddr_refresh_rate_config;
};
#endif

116
u-boot/arch/x86/include/asm/arch-ivybridge/sandybridge.h Normal file
View File

@@ -0,0 +1,116 @@
/*
* Copyright (c) 2014 Google, Inc
*
* From Coreboot file of the same name
*
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2011 Google Inc.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ACH_ASM_SANDYBRIDGE_H
#define _ACH_ASM_SANDYBRIDGE_H
/* Chipset types */
#define SANDYBRIDGE_MOBILE 0
#define SANDYBRIDGE_DESKTOP 1
#define SANDYBRIDGE_SERVER 2
/* Device ID for SandyBridge and IvyBridge */
#define BASE_REV_SNB 0x00
#define BASE_REV_IVB 0x50
#define BASE_REV_MASK 0x50
/* SandyBridge CPU stepping */
#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */
#define SNB_STEP_D1 (BASE_REV_SNB + 6)
#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */
/* IvyBridge CPU stepping */
#define IVB_STEP_A0 (BASE_REV_IVB + 0)
#define IVB_STEP_B0 (BASE_REV_IVB + 2)
#define IVB_STEP_C0 (BASE_REV_IVB + 4)
#define IVB_STEP_K0 (BASE_REV_IVB + 5)
#define IVB_STEP_D0 (BASE_REV_IVB + 6)
/* Intel Enhanced Debug region must be 4MB */
#define IED_SIZE 0x400000
/* Northbridge BARs */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#define DEFAULT_RCBABASE 0xfed1c000
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE
/* Device 0:0.0 PCI configuration space (Host Bridge) */
#define EPBAR 0x40
#define MCHBAR 0x48
#define PCIEXBAR 0x60
#define DMIBAR 0x68
#define X60BAR 0x60
#define GGC 0x50 /* GMCH Graphics Control */
#define DEVEN 0x54 /* Device Enable */
#define DEVEN_PEG60 (1 << 13)
#define DEVEN_IGD (1 << 4)
#define DEVEN_PEG10 (1 << 3)
#define DEVEN_PEG11 (1 << 2)
#define DEVEN_PEG12 (1 << 1)
#define DEVEN_HOST (1 << 0)
#define PAM0 0x80
#define PAM1 0x81
#define PAM2 0x82
#define PAM3 0x83
#define PAM4 0x84
#define PAM5 0x85
#define PAM6 0x86
#define LAC 0x87 /* Legacy Access Control */
#define SMRAM 0x88 /* System Management RAM Control */
#define D_OPEN (1 << 6)
#define D_CLS (1 << 5)
#define D_LCK (1 << 4)
#define G_SMRAME (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#define TOM 0xa0
#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
#define TSEG 0xb8 /* TSEG base */
#define TOLUD 0xbc /* Top of Low Used Memory */
#define SKPAD 0xdc /* Scratchpad Data */
/* Device 0:1.0 PCI configuration space (PCI Express) */
#define BCTRL1 0x3e /* 16bit */
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */
#define SWSCI 0xe8 /* SWSCI enable */
#define ASLS 0xfc /* OpRegion Base */
/*
* MCHBAR
*/
#define SSKPD 0x5d14 /* 16bit (scratchpad) */
#define BIOS_RESET_CPL 0x5da8 /* 8bit */
/*
* DMIBAR
*/
#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x)
/**
* bridge_silicon_revision() - Get the Northbridge revision
*
* @dev: Northbridge device
* @return revision ID (bits 3:0) and bridge ID (bits 7:4)
*/
int bridge_silicon_revision(struct udevice *dev);
#endif

23
u-boot/arch/x86/include/asm/arch-qemu/device.h Normal file
View File

@@ -0,0 +1,23 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _QEMU_DEVICE_H_
#define _QEMU_DEVICE_H_
#include <pci.h>
#define QEMU_I440FX PCI_BDF(0, 0, 0)
#define PIIX_ISA PCI_BDF(0, 1, 0)
#define PIIX_IDE PCI_BDF(0, 1, 1)
#define PIIX_USB PCI_BDF(0, 1, 2)
#define PIIX_PM PCI_BDF(0, 1, 3)
#define ICH9_PM PCI_BDF(0, 0x1f, 0)
#define I440FX_VGA PCI_BDF(0, 2, 0)
#define QEMU_Q35 PCI_BDF(0, 0, 0)
#define Q35_VGA PCI_BDF(0, 1, 0)
#endif /* _QEMU_DEVICE_H_ */

41
u-boot/arch/x86/include/asm/arch-qemu/qemu.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ARCH_QEMU_H_
#define _ARCH_QEMU_H_
/* Programmable Attribute Map (PAM) Registers */
#define I440FX_PAM 0x59
#define Q35_PAM 0x90
#define PAM_NUM 7
#define PAM_RW 0x33
/* X-Bus Chip Select Register */
#define XBCS 0x4e
#define APIC_EN (1 << 8)
/* IDE Timing Register */
#define IDE0_TIM 0x40
#define IDE1_TIM 0x42
#define IDE_DECODE_EN (1 << 15)
/* PCIe ECAM Base Address Register */
#define PCIEX_BAR 0x60
#define BAR_EN (1 << 0)
/* I/O Ports */
#define CMOS_ADDR_PORT 0x70
#define CMOS_DATA_PORT 0x71
#define LOW_RAM_ADDR 0x34
#define HIGH_RAM_ADDR 0x35
/* PM registers */
#define PMBA 0x40
#define PMREGMISC 0x80
#define PMIOSE (1 << 0)
#endif /* _ARCH_QEMU_H_ */

15
u-boot/arch/x86/include/asm/arch-quark/acpi/irqroute.h Normal file
View File

@@ -0,0 +1,15 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/device.h>
#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D)
#define PCIE_BRIDGE_IRQ_ROUTES \
PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D)

125
u-boot/arch/x86/include/asm/arch-quark/acpi/lpc.asl Normal file
View File

@@ -0,0 +1,125 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Intel LPC Bus Device - 0:1f.0 */
Device (LPCB)
{
Name(_ADR, 0x001f0000)
OperationRegion(PRTX, PCI_Config, 0x60, 8)
Field(PRTX, AnyAcc, NoLock, Preserve) {
PRTA, 8,
PRTB, 8,
PRTC, 8,
PRTD, 8,
PRTE, 8,
PRTF, 8,
PRTG, 8,
PRTH, 8,
}
#include <asm/acpi/irqlinks.asl>
/* Firmware Hub */
Device (FWH)
{
Name(_HID, EISAID("INT0800"))
Name(_CRS, ResourceTemplate()
{
Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
})
}
/* 8259 Interrupt Controller */
Device (PIC)
{
Name(_HID, EISAID("PNP0000"))
Name(_CRS, ResourceTemplate()
{
IO(Decode16, 0x20, 0x20, 0x01, 0x02)
IO(Decode16, 0x24, 0x24, 0x01, 0x02)
IO(Decode16, 0x28, 0x28, 0x01, 0x02)
IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
IO(Decode16, 0x30, 0x30, 0x01, 0x02)
IO(Decode16, 0x34, 0x34, 0x01, 0x02)
IO(Decode16, 0x38, 0x38, 0x01, 0x02)
IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
IO(Decode16, 0xac, 0xac, 0x01, 0x02)
IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
IRQNoFlags () { 2 }
})
}
/* 8254 timer */
Device (TIMR)
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
{
IO(Decode16, 0x40, 0x40, 0x01, 0x04)
IO(Decode16, 0x50, 0x50, 0x10, 0x04)
IRQNoFlags() { 0 }
})
}
/* HPET */
Device (HPET)
{
Name(_HID, EISAID("PNP0103"))
Name(_CID, 0x010CD041)
Name(_CRS, ResourceTemplate()
{
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
})
Method(_STA)
{
Return (STA_VISIBLE)
}
}
/* Real Time Clock */
Device (RTC)
{
Name(_HID, EISAID("PNP0B00"))
Name(_CRS, ResourceTemplate()
{
IO(Decode16, 0x70, 0x70, 1, 8)
IRQNoFlags() { 8 }
})
}
/* LPC device: Resource consumption */
Device (LDRC)
{
Name(_HID, EISAID("PNP0C02"))
Name(_UID, 2)
Name(RBUF, ResourceTemplate()
{
IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
})
Method(_CRS, 0, NotSerialized)
{
Return (RBUF)
}
}
}

33
u-boot/arch/x86/include/asm/arch-quark/acpi/platform.asl Normal file
View File

@@ -0,0 +1,33 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/acpi/statdef.asl>
#include <asm/arch/iomap.h>
#include <asm/arch/irq.h>
/*
* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0.
*/
Method(_PTS, 1)
{
}
/* The _WAK method is called on system wakeup */
Method(_WAK, 1)
{
Return (Package() {0, 0})
}
/* TODO: add CPU ASL support */
Scope (\_SB)
{
#include "southcluster.asl"
}
/* Chipset specific sleep states */
#include "sleepstates.asl"

10
u-boot/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl Normal file
View File

@@ -0,0 +1,10 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})

184
u-boot/arch/x86/include/asm/arch-quark/acpi/southcluster.asl Normal file
View File

@@ -0,0 +1,184 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
Device (PCI0)
{
Name(_HID, EISAID("PNP0A08")) /* PCIe */
Name(_CID, EISAID("PNP0A03")) /* PCI */
Name(_ADR, 0)
Name(_BBN, 0)
Name(MCRS, ResourceTemplate()
{
/* Bus Numbers */
WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
/* IO Region 0 */
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
/* PCI Config Space */
IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
/* IO Region 1 */
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
/* VGA memory (0xa0000-0xbffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
0x00020000, , , ASEG)
/* OPROM reserved (0xc0000-0xc3fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
0x00004000, , , OPR0)
/* OPROM reserved (0xc4000-0xc7fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
0x00004000, , , OPR1)
/* OPROM reserved (0xc8000-0xcbfff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
0x00004000, , , OPR2)
/* OPROM reserved (0xcc000-0xcffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
0x00004000, , , OPR3)
/* OPROM reserved (0xd0000-0xd3fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
0x00004000, , , OPR4)
/* OPROM reserved (0xd4000-0xd7fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
0x00004000, , , OPR5)
/* OPROM reserved (0xd8000-0xdbfff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
0x00004000, , , OPR6)
/* OPROM reserved (0xdc000-0xdffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
0x00004000, , , OPR7)
/* BIOS Extension (0xe0000-0xe3fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
0x00004000, , , ESG0)
/* BIOS Extension (0xe4000-0xe7fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
0x00004000, , , ESG1)
/* BIOS Extension (0xe8000-0xebfff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
0x00004000, , , ESG2)
/* BIOS Extension (0xec000-0xeffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000ec000, 0x000effff, 0x00000000,
0x00004000, , , ESG3)
/* System BIOS (0xf0000-0xfffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000, , , FSEG)
/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, , , PMEM)
})
Method(_CRS, 0, Serialized)
{
/* Update PCI resource area */
CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
/*
* Hardcode TOLM to 2GB for now (see DRAM_MAX_SIZE in quark.h)
*
* TODO: for generic usage, read TOLM value from register, or
* from global NVS (not implemented by U-Boot yet).
*/
Store(0x80000000, PMIN)
Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
Add(Subtract(PMAX, PMIN), 1, PLEN)
Return (MCRS)
}
/* Device Resource Consumption */
Device (PDRC)
{
Name(_HID, EISAID("PNP0C02"))
Name(_UID, 1)
Name(PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_ESRAM_BASE, 0x80000)
Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
IO(Decode16, SPI_DMA_BASE_ADDRESS, SPI_DMA_BASE_ADDRESS, 0x0010, SPI_DMA_BASE_SIZE)
IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE)
IO(Decode16, WDT_BASE_ADDRESS, WDT_BASE_ADDRESS, 0x0040, WDT_BASE_SIZE)
})
/* Current Resource Settings */
Method(_CRS, 0, Serialized)
{
Return (PDRS)
}
}
Method(_OSC, 4)
{
/* Check for proper GUID */
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
/* Let OS control everything */
Return (Arg3)
} Else {
/* Unrecognized UUID */
CreateDWordField(Arg3, 0, CDW1)
Or(CDW1, 4, CDW1)
Return (Arg3)
}
}
/* LPC Bridge 0:1f.0 */
#include "lpc.asl"
/* IRQ routing for each PCI device */
#include <asm/acpi/irqroute.asl>
}

77
u-boot/arch/x86/include/asm/arch-quark/device.h Normal file
View File

@@ -0,0 +1,77 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _QUARK_DEVICE_H_
#define _QUARK_DEVICE_H_
/*
* Internal PCI device numbers within the SoC.
*
* Note it must start with 0x_ prefix, as the device number macro will be
* included in the ACPI ASL files (see irq_helper.h and irq_route.h).
*/
#define QUARK_HOST_BRIDGE_DEV 0x00
#define QUARK_HOST_BRIDGE_FUNC 0
#define QUARK_DEV_20 0x14
#define QUARK_MMC_SDIO_FUNC 0
#define QUARK_UART0_FUNC 1
#define QUARK_USB_DEVICE_FUNC 2
#define QUARK_USB_EHCI_FUNC 3
#define QUARK_USB_OHCI_FUNC 4
#define QUARK_UART1_FUNC 5
#define QUARK_EMAC0_FUNC 6
#define QUARK_EMAC1_FUNC 7
#define QUARK_DEV_21 0x15
#define QUARK_SPI0_FUNC 0
#define QUARK_SPI1_FUNC 1
#define QUARK_I2C_GPIO_FUNC 2
#define QUARK_DEV_23 0x17
#define QUARK_PCIE0_FUNC 0
#define QUARK_PCIE1_FUNC 1
#define QUARK_LGC_BRIDGE_DEV 0x1f
#define QUARK_LGC_BRIDGE_FUNC 0
#ifndef __ASSEMBLY__
#include <pci.h>
#define QUARK_HOST_BRIDGE \
PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC)
#define QUARK_MMC_SDIO \
PCI_BDF(0, QUARK_DEV_20, QUARK_MMC_SDIO_FUNC)
#define QUARK_UART0 \
PCI_BDF(0, QUARK_DEV_20, QUARK_UART0_FUNC)
#define QUARK_USB_DEVICE \
PCI_BDF(0, QUARK_DEV_20, QUARK_USB_DEVICE_FUNC)
#define QUARK_USB_EHCI \
PCI_BDF(0, QUARK_DEV_20, QUARK_USB_EHCI_FUNC)
#define QUARK_USB_OHCI \
PCI_BDF(0, QUARK_DEV_20, QUARK_USB_OHCI_FUNC)
#define QUARK_UART1 \
PCI_BDF(0, QUARK_DEV_20, QUARK_UART1_FUNC)
#define QUARK_EMAC0 \
PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC0_FUNC)
#define QUARK_EMAC1 \
PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC1_FUNC)
#define QUARK_SPI0 \
PCI_BDF(0, QUARK_DEV_21, QUARK_SPI0_FUNC)
#define QUARK_SPI1 \
PCI_BDF(0, QUARK_DEV_21, QUARK_SPI1_FUNC)
#define QUARK_I2C_GPIO \
PCI_BDF(0, QUARK_DEV_21, QUARK_I2C_GPIO_FUNC)
#define QUARK_PCIE0 \
PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE0_FUNC)
#define QUARK_PCIE1 \
PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC)
#define QUARK_LEGACY_BRIDGE \
PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC)
#endif /* __ASSEMBLY__ */
#endif /* _QUARK_DEVICE_H_ */

47
u-boot/arch/x86/include/asm/arch-quark/iomap.h Normal file
View File

@@ -0,0 +1,47 @@
/*
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _QUARK_IOMAP_H_
#define _QUARK_IOMAP_H_
/* Memory Mapped IO bases */
/* ESRAM */
#define ESRAM_BASE_ADDRESS CONFIG_ESRAM_BASE
#define ESRAM_BASE_SIZE ESRAM_SIZE
/* PCI Configuration Space */
#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
#define MCFG_BASE_SIZE 0x10000000
/* High Performance Event Timer */
#define HPET_BASE_ADDRESS 0xfed00000
#define HPET_BASE_SIZE 0x400
/* Root Complex Base Address */
#define RCBA_BASE_ADDRESS CONFIG_RCBA_BASE
#define RCBA_BASE_SIZE 0x4000
/* IO Port bases */
#define ACPI_PM1_BASE_ADDRESS CONFIG_ACPI_PM1_BASE
#define ACPI_PM1_BASE_SIZE 0x10
#define ACPI_PBLK_BASE_ADDRESS CONFIG_ACPI_PBLK_BASE
#define ACPI_PBLK_BASE_SIZE 0x10
#define SPI_DMA_BASE_ADDRESS CONFIG_SPI_DMA_BASE
#define SPI_DMA_BASE_SIZE 0x10
#define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE
#define GPIO_BASE_SIZE 0x80
#define ACPI_GPE0_BASE_ADDRESS CONFIG_ACPI_GPE0_BASE
#define ACPI_GPE0_BASE_SIZE 0x40
#define WDT_BASE_ADDRESS CONFIG_WDT_BASE
#define WDT_BASE_SIZE 0x40
#endif /* _QUARK_IOMAP_H_ */

19
u-boot/arch/x86/include/asm/arch-quark/irq.h Normal file
View File

@@ -0,0 +1,19 @@
/*
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _QUARK_IRQ_H_
#define _QUARK_IRQ_H_
#define PIRQA_APIC_IRQ 16
#define PIRQB_APIC_IRQ 17
#define PIRQC_APIC_IRQ 18
#define PIRQD_APIC_IRQ 19
#define PIRQE_APIC_IRQ 20
#define PIRQF_APIC_IRQ 21
#define PIRQG_APIC_IRQ 22
#define PIRQH_APIC_IRQ 23
#endif /* _QUARK_IRQ_H_ */

187
u-boot/arch/x86/include/asm/arch-quark/mrc.h Normal file
View File

@@ -0,0 +1,187 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* Ported from Intel released Quark UEFI BIOS
* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
*
* SPDX-License-Identifier: Intel
*/
#ifndef _MRC_H_
#define _MRC_H_
#define MRC_VERSION 0x0111
/* architectural definitions */
#define NUM_CHANNELS 1 /* number of channels */
#define NUM_RANKS 2 /* number of ranks per channel */
#define NUM_BYTE_LANES 4 /* number of byte lanes per channel */
/* software limitations */
#define MAX_CHANNELS 1
#define MAX_RANKS 2
#define MAX_BYTE_LANES 4
#define MAX_SOCKETS 1
#define MAX_SIDES 1
#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
/* Specify DRAM and channel width */
enum {
X8, /* DRAM width */
X16, /* DRAM width & Channel Width */
X32 /* Channel Width */
};
/* Specify DRAM speed */
enum {
DDRFREQ_800,
DDRFREQ_1066
};
/* Specify DRAM type */
enum {
DDR3,
DDR3L
};
/*
* density: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb
* cl: DRAM CAS Latency in clocks
* ras: ACT to PRE command period
* wtr: Delay from start of internal write transaction to internal read command
* rrd: ACT to ACT command period (JESD79 specific to page size 1K/2K)
* faw: Four activate window (JESD79 specific to page size 1K/2K)
*
* ras/wtr/rrd/faw timings are in picoseconds
*
* Refer to JEDEC spec (or DRAM datasheet) when changing these values.
*/
struct dram_params {
uint8_t density;
uint8_t cl;
uint32_t ras;
uint32_t wtr;
uint32_t rrd;
uint32_t faw;
};
/*
* Delay configuration for individual signals
* Vref setting
* Scrambler seed
*/
struct mrc_timings {
uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
uint32_t wcmd[NUM_CHANNELS];
uint32_t scrambler_seed;
/* need to save for the case of frequency change */
uint8_t ddr_speed;
};
/* Boot mode defined as bit mask (1<<n) */
enum {
BM_UNKNOWN,
BM_COLD = 1, /* full training */
BM_FAST = 2, /* restore timing parameters */
BM_S3 = 4, /* resume from S3 */
BM_WARM = 8
};
/* MRC execution status */
#define MRC_SUCCESS 0 /* initialization ok */
#define MRC_E_MEMTEST 1 /* memtest failed */
/*
* Memory Reference Code parameters
*
* It includes 3 parts:
* - input parameters like boot mode and DRAM parameters
* - context parameters for MRC internal state
* - output parameters like initialization result and memory size
*/
struct mrc_params {
/* Input parameters */
uint32_t boot_mode; /* BM_COLD, BM_FAST, BM_WARM, BM_S3 */
/* DRAM parameters */
uint8_t dram_width; /* x8, x16 */
uint8_t ddr_speed; /* DDRFREQ_800, DDRFREQ_1066 */
uint8_t ddr_type; /* DDR3, DDR3L */
uint8_t ecc_enables; /* 0, 1 (memory size reduced to 7/8) */
uint8_t scrambling_enables; /* 0, 1 */
/* 1, 3 (1'st rank has to be populated if 2'nd rank present) */
uint32_t rank_enables;
uint32_t channel_enables; /* 1 only */
uint32_t channel_width; /* x16 only */
/* 0, 1, 2 (mode 2 forced if ecc enabled) */
uint32_t address_mode;
/* REFRESH_RATE: 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED */
uint8_t refresh_rate;
/* SR_TEMP_RANGE: 0=normal, 1=extended, others=RESERVED */
uint8_t sr_temp_range;
/*
* RON_VALUE: 0=34ohm, 1=40ohm, others=RESERVED
* (select MRS1.DIC driver impedance control)
*/
uint8_t ron_value;
/* RTT_NOM_VALUE: 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */
uint8_t rtt_nom_value;
/* RD_ODT_VALUE: 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
uint8_t rd_odt_value;
struct dram_params params;
/* Internally used context parameters */
uint32_t board_id; /* board layout (use x8 or x16 memory) */
uint32_t hte_setup; /* when set hte reconfiguration requested */
uint32_t menu_after_mrc;
uint32_t power_down_disable;
uint32_t tune_rcvn;
uint32_t channel_size[NUM_CHANNELS];
uint32_t column_bits[NUM_CHANNELS];
uint32_t row_bits[NUM_CHANNELS];
uint32_t mrs1; /* register content saved during training */
uint8_t first_run;
/* Output parameters */
/* initialization result (non zero specifies error code) */
uint32_t status;
/* total memory size in bytes (excludes ECC banks) */
uint32_t mem_size;
/* training results (also used on input) */
struct mrc_timings timings;
};
/*
* MRC memory initialization structure
*
* post_code: a 16-bit post code of a specific initialization routine
* boot_path: bitwise or of BM_COLD, BM_FAST, BM_WARM and BM_S3
* init_fn: real memory initialization routine
*/
struct mem_init {
uint16_t post_code;
uint16_t boot_path;
void (*init_fn)(struct mrc_params *mrc_params);
};
/* MRC platform data flags */
#define MRC_FLAG_ECC_EN 0x00000001
#define MRC_FLAG_SCRAMBLE_EN 0x00000002
#define MRC_FLAG_MEMTEST_EN 0x00000004
/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
#define MRC_FLAG_TOP_TREE_EN 0x00000008
/* If set ODR signal is asserted to DRAM devices on writes */
#define MRC_FLAG_WR_ODT_EN 0x00000010
/**
* mrc_init - Memory Reference Code initialization entry routine
*
* @mrc_params: parameters for MRC
*/
void mrc_init(struct mrc_params *mrc_params);
#endif /* _MRC_H_ */

137
u-boot/arch/x86/include/asm/arch-quark/msg_port.h Normal file
View File

@@ -0,0 +1,137 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _QUARK_MSG_PORT_H_
#define _QUARK_MSG_PORT_H_
/*
* In the Quark SoC, some chipset commands are accomplished by utilizing
* the internal message network within the host bridge (D0:F0). Accesses
* to this network are accomplished by populating the message control
* register (MCR), Message Control Register eXtension (MCRX) and the
* message data register (MDR).
*/
#define MSG_CTRL_REG 0xd0 /* Message Control Register */
#define MSG_DATA_REG 0xd4 /* Message Data Register */
#define MSG_CTRL_EXT_REG 0xd8 /* Message Control Register EXT */
/* Normal Read/Write OpCodes */
#define MSG_OP_READ 0x10
#define MSG_OP_WRITE 0x11
/* Alternative Read/Write OpCodes */
#define MSG_OP_ALT_READ 0x06
#define MSG_OP_ALT_WRITE 0x07
/* IO Read/Write OpCodes */
#define MSG_OP_IO_READ 0x02
#define MSG_OP_IO_WRITE 0x03
/* All byte enables */
#define MSG_BYTE_ENABLE 0xf0
#ifndef __ASSEMBLY__
/**
* msg_port_setup - set up the message port control register
*
* @op: message bus access opcode
* @port: port number on the message bus
* @reg: register number within a port
*/
void msg_port_setup(int op, int port, int reg);
/**
* msg_port_read - read a message port register using normal opcode
*
* @port: port number on the message bus
* @reg: register number within a port
*
* @return: message port register value
*/
u32 msg_port_read(u8 port, u32 reg);
/**
* msg_port_write - write a message port register using normal opcode
*
* @port: port number on the message bus
* @reg: register number within a port
* @value: register value to write
*/
void msg_port_write(u8 port, u32 reg, u32 value);
/**
* msg_port_alt_read - read a message port register using alternative opcode
*
* @port: port number on the message bus
* @reg: register number within a port
*
* @return: message port register value
*/
u32 msg_port_alt_read(u8 port, u32 reg);
/**
* msg_port_alt_write - write a message port register using alternative opcode
*
* @port: port number on the message bus
* @reg: register number within a port
* @value: register value to write
*/
void msg_port_alt_write(u8 port, u32 reg, u32 value);
/**
* msg_port_io_read - read a message port register using I/O opcode
*
* @port: port number on the message bus
* @reg: register number within a port
*
* @return: message port register value
*/
u32 msg_port_io_read(u8 port, u32 reg);
/**
* msg_port_io_write - write a message port register using I/O opcode
*
* @port: port number on the message bus
* @reg: register number within a port
* @value: register value to write
*/
void msg_port_io_write(u8 port, u32 reg, u32 value);
/* clrbits, setbits, clrsetbits macros for message port access */
#define msg_port_normal_read msg_port_read
#define msg_port_normal_write msg_port_write
#define msg_port_generic_clrsetbits(type, port, reg, clr, set) \
msg_port_##type##_write(port, reg, \
(msg_port_##type##_read(port, reg) \
& ~(clr)) | (set))
#define msg_port_clrbits(port, reg, clr) \
msg_port_generic_clrsetbits(normal, port, reg, clr, 0)
#define msg_port_setbits(port, reg, set) \
msg_port_generic_clrsetbits(normal, port, reg, 0, set)
#define msg_port_clrsetbits(port, reg, clr, set) \
msg_port_generic_clrsetbits(normal, port, reg, clr, set)
#define msg_port_alt_clrbits(port, reg, clr) \
msg_port_generic_clrsetbits(alt, port, reg, clr, 0)
#define msg_port_alt_setbits(port, reg, set) \
msg_port_generic_clrsetbits(alt, port, reg, 0, set)
#define msg_port_alt_clrsetbits(port, reg, clr, set) \
msg_port_generic_clrsetbits(alt, port, reg, clr, set)
#define msg_port_io_clrbits(port, reg, clr) \
msg_port_generic_clrsetbits(io, port, reg, clr, 0)
#define msg_port_io_setbits(port, reg, set) \
msg_port_generic_clrsetbits(io, port, reg, 0, set)
#define msg_port_io_clrsetbits(port, reg, clr, set) \
msg_port_generic_clrsetbits(io, port, reg, clr, set)
#endif /* __ASSEMBLY__ */
#endif /* _QUARK_MSG_PORT_H_ */

260
u-boot/arch/x86/include/asm/arch-quark/quark.h Normal file
View File

@@ -0,0 +1,260 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _QUARK_H_
#define _QUARK_H_
/* Message Bus Ports */
#define MSG_PORT_MEM_ARBITER 0x00
#define MSG_PORT_HOST_BRIDGE 0x03
#define MSG_PORT_RMU 0x04
#define MSG_PORT_MEM_MGR 0x05
#define MSG_PORT_USB_AFE 0x14
#define MSG_PORT_PCIE_AFE 0x16
#define MSG_PORT_SOC_UNIT 0x31
/* Port 0x00: Memory Arbiter Message Port Registers */
/* Enhanced Configuration Space */
#define AEC_CTRL 0x00
/* Port 0x03: Host Bridge Message Port Registers */
/* Host Miscellaneous Controls 2 */
#define HMISC2 0x03
#define HMISC2_SEGE 0x00000002
#define HMISC2_SEGF 0x00000004
#define HMISC2_SEGAB 0x00000010
/* Host Memory I/O Boundary */
#define HM_BOUND 0x08
#define HM_BOUND_LOCK 0x00000001
/* Extended Configuration Space */
#define HEC_REG 0x09
/* MTRR Registers */
#define MTRR_CAP 0x40
#define MTRR_DEF_TYPE 0x41
#define MTRR_FIX_64K_00000 0x42
#define MTRR_FIX_64K_40000 0x43
#define MTRR_FIX_16K_80000 0x44
#define MTRR_FIX_16K_90000 0x45
#define MTRR_FIX_16K_A0000 0x46
#define MTRR_FIX_16K_B0000 0x47
#define MTRR_FIX_4K_C0000 0x48
#define MTRR_FIX_4K_C4000 0x49
#define MTRR_FIX_4K_C8000 0x4a
#define MTRR_FIX_4K_CC000 0x4b
#define MTRR_FIX_4K_D0000 0x4c
#define MTRR_FIX_4K_D4000 0x4d
#define MTRR_FIX_4K_D8000 0x4e
#define MTRR_FIX_4K_DC000 0x4f
#define MTRR_FIX_4K_E0000 0x50
#define MTRR_FIX_4K_E4000 0x51
#define MTRR_FIX_4K_E8000 0x52
#define MTRR_FIX_4K_EC000 0x53
#define MTRR_FIX_4K_F0000 0x54
#define MTRR_FIX_4K_F4000 0x55
#define MTRR_FIX_4K_F8000 0x56
#define MTRR_FIX_4K_FC000 0x57
#define MTRR_SMRR_PHYBASE 0x58
#define MTRR_SMRR_PHYMASK 0x59
#define MTRR_VAR_PHYBASE(n) (0x5a + 2 * (n))
#define MTRR_VAR_PHYMASK(n) (0x5b + 2 * (n))
#ifndef __ASSEMBLY__
/* variable range MTRR usage */
enum {
MTRR_VAR_ROM,
MTRR_VAR_ESRAM,
MTRR_VAR_RAM
};
#endif /* __ASSEMBLY__ */
/* Port 0x04: Remote Management Unit Message Port Registers */
/* ACPI PBLK Base Address Register */
#define PBLK_BA 0x70
/* Control Register */
#define RMU_CTRL 0x71
/* SPI DMA Base Address Register */
#define SPI_DMA_BA 0x7a
/* Thermal Sensor Register */
#define TS_MODE 0xb0
#define TS_TEMP 0xb1
#define TS_TRIP 0xb2
/* Port 0x05: Memory Manager Message Port Registers */
/* eSRAM Block Page Control */
#define ESRAM_BLK_CTRL 0x82
#define ESRAM_BLOCK_MODE 0x10000000
/* Port 0x14: USB2 AFE Unit Port Registers */
#define USB2_GLOBAL_PORT 0x4001
#define USB2_PLL1 0x7f02
#define USB2_PLL2 0x7f03
#define USB2_COMPBG 0x7f04
/* Port 0x16: PCIe AFE Unit Port Registers */
#define PCIE_RXPICTRL0_L0 0x2080
#define PCIE_RXPICTRL0_L1 0x2180
/* Port 0x31: SoC Unit Port Registers */
/* Thermal Sensor Config */
#define TS_CFG1 0x31
#define TS_CFG2 0x32
#define TS_CFG3 0x33
#define TS_CFG4 0x34
/* PCIe Controller Config */
#define PCIE_CFG 0x36
#define PCIE_CTLR_PRI_RST 0x00010000
#define PCIE_PHY_SB_RST 0x00020000
#define PCIE_CTLR_SB_RST 0x00040000
#define PCIE_PHY_LANE_RST 0x00090000
#define PCIE_CTLR_MAIN_RST 0x00100000
/* DRAM */
#define DRAM_BASE 0x00000000
#define DRAM_MAX_SIZE 0x80000000
/* eSRAM */
#define ESRAM_SIZE 0x80000
/* Memory BAR Enable */
#define MEM_BAR_EN 0x00000001
/* I/O BAR Enable */
#define IO_BAR_EN 0x80000000
/* 64KiB of RMU binary in flash */
#define RMU_BINARY_SIZE 0x10000
/* PCIe Root Port Configuration Registers */
#define PCIE_RP_CCFG 0xd0
#define CCFG_UPRS (1 << 14)
#define CCFG_UNRS (1 << 15)
#define CCFG_UNSD (1 << 23)
#define CCFG_UPSD (1 << 24)
#define PCIE_RP_MPC2 0xd4
#define MPC2_IPF (1 << 11)
#define PCIE_RP_MBC 0xf4
#define MBC_SBIC (3 << 16)
/* Legacy Bridge PCI Configuration Registers */
#define LB_GBA 0x44
#define LB_PM1BLK 0x48
#define LB_GPE0BLK 0x4c
#define LB_ACTL 0x58
#define LB_PABCDRC 0x60
#define LB_PEFGHRC 0x64
#define LB_WDTBA 0x84
#define LB_BCE 0xd4
#define LB_BC 0xd8
#define LB_RCBA 0xf0
/* USB EHCI memory-mapped registers */
#define EHCI_INSNREG01 0x94
/* USB device memory-mapped registers */
#define USBD_INT_MASK 0x410
#define USBD_EP_INT_STS 0x414
#define USBD_EP_INT_MASK 0x418
#ifndef __ASSEMBLY__
/* Root Complex Register Block */
struct quark_rcba {
u32 rctl;
u32 esd;
u32 rsvd1[3150];
u16 rmu_ir;
u16 d23_ir;
u16 core_ir;
u16 d20d21_ir;
};
#include <asm/io.h>
#include <asm/pci.h>
/**
* qrk_pci_read_config_dword() - Read a configuration value
*
* @dev: PCI device address: bus, device and function
* @offset: Dword offset within the device's configuration space
* @valuep: Place to put the returned value
*
* Note: This routine is inlined to provide better performance on Quark
*/
static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset,
u32 *valuep)
{
outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
*valuep = inl(PCI_REG_DATA);
}
/**
* qrk_pci_write_config_dword() - Write a PCI configuration value
*
* @dev: PCI device address: bus, device and function
* @offset: Dword offset within the device's configuration space
* @value: Value to write
*
* Note: This routine is inlined to provide better performance on Quark
*/
static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset,
u32 value)
{
outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
outl(value, PCI_REG_DATA);
}
/**
* board_assert_perst() - Assert the PERST# pin
*
* The CPU interface to the PERST# signal on Quark is platform dependent.
* Board-specific codes need supply this routine to assert PCIe slot reset.
*
* The tricky part in this routine is that any APIs that may trigger PCI
* enumeration process are strictly forbidden, as any access to PCIe root
* port's configuration registers will cause system hang while it is held
* in reset.
*/
void board_assert_perst(void);
/**
* board_deassert_perst() - De-assert the PERST# pin
*
* The CPU interface to the PERST# signal on Quark is platform dependent.
* Board-specific codes need supply this routine to de-assert PCIe slot reset.
*
* The tricky part in this routine is that any APIs that may trigger PCI
* enumeration process are strictly forbidden, as any access to PCIe root
* port's configuration registers will cause system hang while it is held
* in reset.
*/
void board_deassert_perst(void);
#endif /* __ASSEMBLY__ */
#endif /* _QUARK_H_ */

94
u-boot/arch/x86/include/asm/arch-queensbay/device.h Normal file
View File

@@ -0,0 +1,94 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _QUEENSBAY_DEVICE_H_
#define _QUEENSBAY_DEVICE_H_
#include <pci.h>
/* TunnelCreek PCI Devices */
#define TNC_HOST_BRIDGE_DEV 0
#define TNC_HOST_BRIDGE_FUNC 0
#define TNC_IGD_DEV 2
#define TNC_IGD_FUNC 0
#define TNC_SDVO_DEV 3
#define TNC_SDVO_FUNC 0
#define TNC_PCIE0_DEV 23
#define TNC_PCIE0_FUNC 0
#define TNC_PCIE1_DEV 24
#define TNC_PCIE1_FUNC 0
#define TNC_PCIE2_DEV 25
#define TNC_PCIE2_FUNC 0
#define TNC_PCIE3_DEV 26
#define TNC_PCIE3_FUNC 0
#define TNC_HDA_DEV 27
#define TNC_HDA_FUNC 0
#define TNC_LPC_DEV 31
#define TNC_LPC_FUNC 0
#define TNC_HOST_BRIDGE \
PCI_BDF(0, TNC_HOST_BRIDGE_DEV, TNC_HOST_BRIDGE_FUNC)
#define TNC_IGD \
PCI_BDF(0, TNC_IGD_DEV, TNC_IGD_FUNC)
#define TNC_SDVO \
PCI_BDF(0, TNC_SDVO_DEV, TNC_SDVO_FUNC)
#define TNC_PCIE0 \
PCI_BDF(0, TNC_PCIE0_DEV, TNC_PCIE0_FUNC)
#define TNC_PCIE1 \
PCI_BDF(0, TNC_PCIE1_DEV, TNC_PCIE1_FUNC)
#define TNC_PCIE2 \
PCI_BDF(0, TNC_PCIE2_DEV, TNC_PCIE2_FUNC)
#define TNC_PCIE3 \
PCI_BDF(0, TNC_PCIE3_DEV, TNC_PCIE3_FUNC)
#define TNC_HDA \
PCI_BDF(0, TNC_HDA_DEV, TNC_HDA_FUNC)
#define TNC_LPC \
PCI_BDF(0, TNC_LPC_DEV, TNC_LPC_FUNC)
/* Topcliff IOH PCI Devices */
#define TCF_PCIE_PORT_DEV 0
#define TCF_PCIE_PORT_FUNC 0
#define TCF_DEV_0 0
#define TCF_PKT_HUB_FUNC 0
#define TCF_GBE_FUNC 1
#define TCF_GPIO_FUNC 2
#define TCF_DEV_2 2
#define TCF_USB1_OHCI0_FUNC 0
#define TCF_USB1_OHCI1_FUNC 1
#define TCF_USB1_OHCI2_FUNC 2
#define TCF_USB1_EHCI_FUNC 3
#define TCF_USB_DEVICE_FUNC 4
#define TCF_DEV_4 4
#define TCF_SDIO0_FUNC 0
#define TCF_SDIO1_FUNC 1
#define TCF_DEV_6 6
#define TCF_SATA_FUNC 0
#define TCF_DEV_8 8
#define TCF_USB2_OHCI0_FUNC 0
#define TCF_USB2_OHCI1_FUNC 1
#define TCF_USB2_OHCI2_FUNC 2
#define TCF_USB2_EHCI_FUNC 3
#define TCF_DEV_10 10
#define TCF_DMA1_FUNC 0
#define TCF_UART0_FUNC 1
#define TCF_UART1_FUNC 2
#define TCF_UART2_FUNC 3
#define TCF_UART3_FUNC 4
#define TCF_DEV_12 12
#define TCF_DMA2_FUNC 0
#define TCF_SPI_FUNC 1
#define TCF_I2C_FUNC 2
#define TCF_CAN_FUNC 3
#define TCF_1588_FUNC 4
#endif /* _QUEENSBAY_DEVICE_H_ */

19
u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h Normal file
View File

@@ -0,0 +1,19 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: Intel
*/
#ifndef __FSP_CONFIGS_H__
#define __FSP_CONFIGS_H__
struct fsp_config_data {
struct fsp_cfg_common common;
struct upd_region fsp_upd;
};
struct fspinit_rtbuf {
struct common_buf common; /* FSP common runtime data structure */
};
#endif /* __FSP_CONFIGS_H__ */

53
u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h Normal file
View File

@@ -0,0 +1,53 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* This file is automatically generated. Please do NOT modify !!!
*
* SPDX-License-Identifier: Intel
*/
#ifndef __VPDHEADER_H__
#define __VPDHEADER_H__
struct __packed upd_region {
u64 sign; /* Offset 0x0000 */
u64 reserved; /* Offset 0x0008 */
u8 dummy[240]; /* Offset 0x0010 */
u8 hda_verb_header[12]; /* Offset 0x0100 */
u32 hda_verb_length; /* Offset 0x010C */
u8 hda_verb_data0[16]; /* Offset 0x0110 */
u8 hda_verb_data1[16]; /* Offset 0x0120 */
u8 hda_verb_data2[16]; /* Offset 0x0130 */
u8 hda_verb_data3[16]; /* Offset 0x0140 */
u8 hda_verb_data4[16]; /* Offset 0x0150 */
u8 hda_verb_data5[16]; /* Offset 0x0160 */
u8 hda_verb_data6[16]; /* Offset 0x0170 */
u8 hda_verb_data7[16]; /* Offset 0x0180 */
u8 hda_verb_data8[16]; /* Offset 0x0190 */
u8 hda_verb_data9[16]; /* Offset 0x01A0 */
u8 hda_verb_data10[16]; /* Offset 0x01B0 */
u8 hda_verb_data11[16]; /* Offset 0x01C0 */
u8 hda_verb_data12[16]; /* Offset 0x01D0 */
u8 hda_verb_data13[16]; /* Offset 0x01E0 */
u8 hda_verb_pad[47]; /* Offset 0x01F0 */
u16 terminator; /* Offset 0x021F */
};
#define VPD_IMAGE_ID 0x445056574F4E4E4D /* 'MNNOWVPD' */
struct __packed vpd_region {
u64 sign; /* Offset 0x0000 */
u32 img_rev; /* Offset 0x0008 */
u32 upd_offset; /* Offset 0x000C */
u8 unused[16]; /* Offset 0x0010 */
u32 fsp_res_memlen; /* Offset 0x0020 */
u8 disable_pcie1; /* Offset 0x0024 */
u8 disable_pcie2; /* Offset 0x0025 */
u8 disable_pcie3; /* Offset 0x0026 */
u8 enable_azalia; /* Offset 0x0027 */
u8 legacy_seg_decode; /* Offset 0x0028 */
u8 pcie_port_ioh; /* Offset 0x0029 */
};
#endif

53
u-boot/arch/x86/include/asm/arch-queensbay/tnc.h Normal file
View File

@@ -0,0 +1,53 @@
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _X86_ARCH_TNC_H_
#define _X86_ARCH_TNC_H_
/* IGD Function Disable Register */
#define IGD_FD 0xc4
#define FUNC_DISABLE 0x00000001
/* Memory BAR Enable */
#define MEM_BAR_EN 0x00000001
/* LPC PCI Configuration Registers */
#define LPC_RCBA 0xf0
/* Root Complex Register Block */
struct tnc_rcba {
u32 rctl;
u32 esd;
u32 rsvd1[2];
u32 hdd;
u32 rsvd2;
u32 hdba;
u32 rsvd3[3129];
u32 d31ip;
u32 rsvd4[3];
u32 d27ip;
u32 rsvd5;
u32 d02ip;
u32 rsvd6;
u32 d26ip;
u32 d25ip;
u32 d24ip;
u32 d23ip;
u32 d03ip;
u32 rsvd7[3];
u16 d31ir;
u16 rsvd8[3];
u16 d27ir;
u16 d26ir;
u16 d25ir;
u16 d24ir;
u16 d23ir;
u16 rsvd9[7];
u16 d02ir;
u16 d03ir;
};
#endif /* _X86_ARCH_TNC_H_ */

115
u-boot/arch/x86/include/asm/atomic.h Normal file
View File

@@ -0,0 +1,115 @@
#ifndef _ASM_X86_ATOMIC_H
#define _ASM_X86_ATOMIC_H
#include <linux/compiler.h>
#include <linux/types.h>
#include <asm/processor.h>
typedef struct { volatile int counter; } atomic_t;
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*/
#define ATOMIC_INIT(i) { (i) }
/**
* atomic_read - read atomic variable
* @v: pointer of type atomic_t
*
* Atomically reads the value of @v.
*/
static inline int atomic_read(const atomic_t *v)
{
return ACCESS_ONCE((v)->counter);
}
/**
* atomic_set - set atomic variable
* @v: pointer of type atomic_t
* @i: required value
*
* Atomically sets the value of @v to @i.
*/
static inline void atomic_set(atomic_t *v, int i)
{
v->counter = i;
}
/**
* atomic_add - add integer to atomic variable
* @i: integer value to add
* @v: pointer of type atomic_t
*
* Atomically adds @i to @v.
*/
static inline void atomic_add(int i, atomic_t *v)
{
asm volatile(LOCK_PREFIX "addl %1,%0"
: "+m" (v->counter)
: "ir" (i));
}
/**
* atomic_sub - subtract integer from atomic variable
* @i: integer value to subtract
* @v: pointer of type atomic_t
*
* Atomically subtracts @i from @v.
*/
static inline void atomic_sub(int i, atomic_t *v)
{
asm volatile(LOCK_PREFIX "subl %1,%0"
: "+m" (v->counter)
: "ir" (i));
}
/**
* atomic_inc - increment atomic variable
* @v: pointer of type atomic_t
*
* Atomically increments @v by 1.
*/
static inline void atomic_inc(atomic_t *v)
{
asm volatile(LOCK_PREFIX "incl %0"
: "+m" (v->counter));
}
/**
* atomic_dec - decrement atomic variable
* @v: pointer of type atomic_t
*
* Atomically decrements @v by 1.
*/
static inline void atomic_dec(atomic_t *v)
{
asm volatile(LOCK_PREFIX "decl %0"
: "+m" (v->counter));
}
/**
* atomic_inc_short - increment of a short integer
* @v: pointer to type int
*
* Atomically adds 1 to @v
* Returns the new value of @u
*/
static inline short int atomic_inc_short(short int *v)
{
asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v));
return *v;
}
/* These are x86-specific, used by some header files */
#define atomic_clear_mask(mask, addr) \
asm volatile(LOCK_PREFIX "andl %0,%1" \
: : "r" (~(mask)), "m" (*(addr)) : "memory")
#define atomic_set_mask(mask, addr) \
asm volatile(LOCK_PREFIX "orl %0,%1" \
: : "r" ((unsigned)(mask)), "m" (*(addr)) \
: "memory")
#endif /* _ASM_X86_ATOMIC_H */

408
u-boot/arch/x86/include/asm/bitops.h Normal file
View File

@@ -0,0 +1,408 @@
#ifndef _I386_BITOPS_H
#define _I386_BITOPS_H
/*
* Copyright 1992, Linus Torvalds.
*/
/*
* These have to be done with inline assembly: that way the bit-setting
* is guaranteed to be atomic. All bit operations return 0 if the bit
* was cleared before the operation and != 0 if it was not.
*
* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
*/
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls64.h>
#ifdef CONFIG_SMP
#define LOCK_PREFIX "lock ; "
#else
#define LOCK_PREFIX ""
#endif
#define ADDR (*(volatile long *) addr)
/**
* set_bit - Atomically set a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
* This function is atomic and may not be reordered. See __set_bit()
* if you do not require the atomic guarantees.
* Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
static __inline__ void set_bit(int nr, volatile void * addr)
{
__asm__ __volatile__( LOCK_PREFIX
"btsl %1,%0"
:"=m" (ADDR)
:"Ir" (nr));
}
/**
* __set_bit - Set a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
* Unlike set_bit(), this function is non-atomic and may be reordered.
* If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds.
*/
static __inline__ void __set_bit(int nr, volatile void * addr)
{
__asm__(
"btsl %1,%0"
:"=m" (ADDR)
:"Ir" (nr));
}
/**
* clear_bit - Clears a bit in memory
* @nr: Bit to clear
* @addr: Address to start counting from
*
* clear_bit() is atomic and may not be reordered. However, it does
* not contain a memory barrier, so if it is used for locking purposes,
* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
* in order to ensure changes are visible on other processors.
*/
static __inline__ void clear_bit(int nr, volatile void * addr)
{
__asm__ __volatile__( LOCK_PREFIX
"btrl %1,%0"
:"=m" (ADDR)
:"Ir" (nr));
}
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
/**
* __change_bit - Toggle a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
* Unlike change_bit(), this function is non-atomic and may be reordered.
* If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds.
*/
static __inline__ void __change_bit(int nr, volatile void * addr)
{
__asm__ __volatile__(
"btcl %1,%0"
:"=m" (ADDR)
:"Ir" (nr));
}
/**
* change_bit - Toggle a bit in memory
* @nr: Bit to clear
* @addr: Address to start counting from
*
* change_bit() is atomic and may not be reordered.
* Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
static __inline__ void change_bit(int nr, volatile void * addr)
{
__asm__ __volatile__( LOCK_PREFIX
"btcl %1,%0"
:"=m" (ADDR)
:"Ir" (nr));
}
/**
* test_and_set_bit - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static __inline__ int test_and_set_bit(int nr, volatile void * addr)
{
int oldbit;
__asm__ __volatile__( LOCK_PREFIX
"btsl %2,%1\n\tsbbl %0,%0"
:"=r" (oldbit),"=m" (ADDR)
:"Ir" (nr) : "memory");
return oldbit;
}
/**
* __test_and_set_bit - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is non-atomic and can be reordered.
* If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock.
*/
static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
{
int oldbit;
__asm__(
"btsl %2,%1\n\tsbbl %0,%0"
:"=r" (oldbit),"=m" (ADDR)
:"Ir" (nr));
return oldbit;
}
/**
* test_and_clear_bit - Clear a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
{
int oldbit;
__asm__ __volatile__( LOCK_PREFIX
"btrl %2,%1\n\tsbbl %0,%0"
:"=r" (oldbit),"=m" (ADDR)
:"Ir" (nr) : "memory");
return oldbit;
}
/**
* __test_and_clear_bit - Clear a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is non-atomic and can be reordered.
* If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock.
*/
static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
{
int oldbit;
__asm__(
"btrl %2,%1\n\tsbbl %0,%0"
:"=r" (oldbit),"=m" (ADDR)
:"Ir" (nr));
return oldbit;
}
/* WARNING: non atomic and it can be reordered! */
static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
{
int oldbit;
__asm__ __volatile__(
"btcl %2,%1\n\tsbbl %0,%0"
:"=r" (oldbit),"=m" (ADDR)
:"Ir" (nr) : "memory");
return oldbit;
}
/**
* test_and_change_bit - Change a bit and return its new value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static __inline__ int test_and_change_bit(int nr, volatile void * addr)
{
int oldbit;
__asm__ __volatile__( LOCK_PREFIX
"btcl %2,%1\n\tsbbl %0,%0"
:"=r" (oldbit),"=m" (ADDR)
:"Ir" (nr) : "memory");
return oldbit;
}
#if 0 /* Fool kernel-doc since it doesn't do macros yet */
/**
* test_bit - Determine whether a bit is set
* @nr: bit number to test
* @addr: Address to start counting from
*/
static int test_bit(int nr, const volatile void * addr);
#endif
static __inline__ int constant_test_bit(int nr, const volatile void * addr)
{
return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
}
static __inline__ int variable_test_bit(int nr, volatile void * addr)
{
int oldbit;
__asm__ __volatile__(
"btl %2,%1\n\tsbbl %0,%0"
:"=r" (oldbit)
:"m" (ADDR),"Ir" (nr));
return oldbit;
}
#define test_bit(nr,addr) \
(__builtin_constant_p(nr) ? \
constant_test_bit((nr),(addr)) : \
variable_test_bit((nr),(addr)))
/**
* find_first_zero_bit - find the first zero bit in a memory region
* @addr: The address to start the search at
* @size: The maximum size to search
*
* Returns the bit-number of the first zero bit, not the number of the byte
* containing a bit.
*/
static __inline__ int find_first_zero_bit(void * addr, unsigned size)
{
int d0, d1, d2;
int res;
if (!size)
return 0;
/* This looks at memory. Mark it volatile to tell gcc not to move it around */
__asm__ __volatile__(
"movl $-1,%%eax\n\t"
"xorl %%edx,%%edx\n\t"
"repe; scasl\n\t"
"je 1f\n\t"
"xorl -4(%%edi),%%eax\n\t"
"subl $4,%%edi\n\t"
"bsfl %%eax,%%edx\n"
"1:\tsubl %%ebx,%%edi\n\t"
"shll $3,%%edi\n\t"
"addl %%edi,%%edx"
:"=d" (res), "=&c" (d0), "=&D" (d1), "=&a" (d2)
:"1" ((size + 31) >> 5), "2" (addr), "b" (addr));
return res;
}
/**
* find_next_zero_bit - find the first zero bit in a memory region
* @addr: The address to base the search on
* @offset: The bitnumber to start searching at
* @size: The maximum size to search
*/
static __inline__ int find_next_zero_bit (void * addr, int size, int offset)
{
unsigned long * p = ((unsigned long *) addr) + (offset >> 5);
int set = 0, bit = offset & 31, res;
if (bit) {
/*
* Look for zero in first byte
*/
__asm__("bsfl %1,%0\n\t"
"jne 1f\n\t"
"movl $32, %0\n"
"1:"
: "=r" (set)
: "r" (~(*p >> bit)));
if (set < (32 - bit))
return set + offset;
set = 32 - bit;
p++;
}
/*
* No zero yet, search remaining full bytes for a zero
*/
res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr));
return (offset + set + res);
}
/**
* ffz - find first zero in word.
* @word: The word to search
*
* Undefined if no zero exists, so code should check against ~0UL first.
*/
static __inline__ unsigned long ffz(unsigned long word)
{
__asm__("bsfl %1,%0"
:"=r" (word)
:"r" (~word));
return word;
}
#ifdef __KERNEL__
/**
* __ffs - find first set bit in word
* @word: The word to search
*
* Undefined if no bit exists, so code should check against 0 first.
*/
static inline unsigned long __ffs(unsigned long word)
{
__asm__("rep; bsf %1,%0"
: "=r" (word)
: "rm" (word));
return word;
}
/**
* ffs - find first bit set
* @x: the word to search
*
* This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
static __inline__ int ffs(int x)
{
int r;
__asm__("bsfl %1,%0\n\t"
"jnz 1f\n\t"
"movl $-1,%0\n"
"1:" : "=r" (r) : "rm" (x));
return r+1;
}
#define PLATFORM_FFS
static inline int __ilog2(unsigned int x)
{
return generic_fls(x) - 1;
}
/**
* hweightN - returns the hamming weight of a N-bit word
* @x: the word to weigh
*
* The Hamming Weight of a number is the total number of bits set in it.
*/
#define hweight32(x) generic_hweight32(x)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
#endif /* __KERNEL__ */
#ifdef __KERNEL__
#define ext2_set_bit __test_and_set_bit
#define ext2_clear_bit __test_and_clear_bit
#define ext2_test_bit test_bit
#define ext2_find_first_zero_bit find_first_zero_bit
#define ext2_find_next_zero_bit find_next_zero_bit
/* Bitmap functions for the minix filesystem. */
#define minix_test_and_set_bit(nr,addr) __test_and_set_bit(nr,addr)
#define minix_set_bit(nr,addr) __set_bit(nr,addr)
#define minix_test_and_clear_bit(nr,addr) __test_and_clear_bit(nr,addr)
#define minix_test_bit(nr,addr) test_bit(nr,addr)
#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
#endif /* __KERNEL__ */
#endif /* _I386_BITOPS_H */

28
u-boot/arch/x86/include/asm/bootm.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* Copyright (c) 2013, Google Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARM_BOOTM_H
#define ARM_BOOTM_H
void bootm_announce_and_cleanup(void);
/**
* boot_linux_kernel() - boot a linux kernel
*
* This boots a kernel image, either 32-bit or 64-bit. It will also work with
* a self-extracting kernel, if you set @image_64bit to false.
*
* @setup_base: Pointer to the setup.bin information for the kernel
* @load_address: Pointer to the start of the kernel image
* @image_64bit: true if the image is a raw 64-bit kernel, false if it
* is raw 32-bit or any type of self-extracting kernel
* such as a bzImage.
* @return -ve error code. This function does not return if the kernel was
* booted successfully.
*/
int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit);
#endif

120
u-boot/arch/x86/include/asm/bootparam.h Normal file
View File

@@ -0,0 +1,120 @@
#ifndef _ASM_X86_BOOTPARAM_H
#define _ASM_X86_BOOTPARAM_H
#include <linux/types.h>
#include <linux/screen_info.h>
#include <linux/apm_bios.h>
#include <linux/edd.h>
#include <asm/e820.h>
#include <asm/ist.h>
#include <asm/video/edid.h>
/* setup data types */
#define SETUP_NONE 0
#define SETUP_E820_EXT 1
/* extensible setup data list node */
struct setup_data {
__u64 next;
__u32 type;
__u32 len;
__u8 data[0];
};
struct setup_header {
__u8 setup_sects;
__u16 root_flags;
__u32 syssize;
__u16 ram_size;
#define RAMDISK_IMAGE_START_MASK 0x07FF
#define RAMDISK_PROMPT_FLAG 0x8000
#define RAMDISK_LOAD_FLAG 0x4000
__u16 vid_mode;
__u16 root_dev;
__u16 boot_flag;
__u16 jump;
__u32 header;
__u16 version;
__u32 realmode_swtch;
__u16 start_sys;
__u16 kernel_version;
__u8 type_of_loader;
__u8 loadflags;
#define LOADED_HIGH (1<<0)
#define QUIET_FLAG (1<<5)
#define KEEP_SEGMENTS (1<<6)
#define CAN_USE_HEAP (1<<7)
__u16 setup_move_size;
__u32 code32_start;
__u32 ramdisk_image;
__u32 ramdisk_size;
__u32 bootsect_kludge;
__u16 heap_end_ptr;
__u8 ext_loader_ver;
__u8 ext_loader_type;
__u32 cmd_line_ptr;
__u32 initrd_addr_max;
__u32 kernel_alignment;
__u8 relocatable_kernel;
__u8 _pad2[3];
__u32 cmdline_size;
__u32 hardware_subarch;
__u64 hardware_subarch_data;
__u32 payload_offset;
__u32 payload_length;
__u64 setup_data;
} __attribute__((packed));
struct sys_desc_table {
__u16 length;
__u8 table[14];
};
struct efi_info {
__u32 efi_loader_signature;
__u32 efi_systab;
__u32 efi_memdesc_size;
__u32 efi_memdesc_version;
__u32 efi_memmap;
__u32 efi_memmap_size;
__u32 efi_systab_hi;
__u32 efi_memmap_hi;
};
/* The so-called "zeropage" */
struct boot_params {
struct screen_info screen_info; /* 0x000 */
struct apm_bios_info apm_bios_info; /* 0x040 */
__u8 _pad2[4]; /* 0x054 */
__u64 tboot_addr; /* 0x058 */
struct ist_info ist_info; /* 0x060 */
__u8 _pad3[16]; /* 0x070 */
__u8 hd0_info[16]; /* obsolete! */ /* 0x080 */
__u8 hd1_info[16]; /* obsolete! */ /* 0x090 */
struct sys_desc_table sys_desc_table; /* 0x0a0 */
__u8 _pad4[144]; /* 0x0b0 */
struct edid_info edid_info; /* 0x140 */
struct efi_info efi_info; /* 0x1c0 */
__u32 alt_mem_k; /* 0x1e0 */
__u32 scratch; /* Scratch field! */ /* 0x1e4 */
__u8 e820_entries; /* 0x1e8 */
__u8 eddbuf_entries; /* 0x1e9 */
__u8 edd_mbr_sig_buf_entries; /* 0x1ea */
__u8 _pad6[6]; /* 0x1eb */
struct setup_header hdr; /* setup header */ /* 0x1f1 */
__u8 _pad7[0x290-0x1f1-sizeof(struct setup_header)];
__u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX]; /* 0x290 */
struct e820entry e820_map[E820MAX]; /* 0x2d0 */
__u8 _pad8[48]; /* 0xcd0 */
struct edd_info eddbuf[EDDMAXNR]; /* 0xd00 */
__u8 _pad9[276]; /* 0xeec */
} __attribute__((packed));
enum {
X86_SUBARCH_PC = 0,
X86_SUBARCH_LGUEST,
X86_SUBARCH_XEN,
X86_SUBARCH_MRST,
X86_NR_SUBARCHS,
};
#endif /* _ASM_X86_BOOTPARAM_H */

43
u-boot/arch/x86/include/asm/byteorder.h Normal file
View File

@@ -0,0 +1,43 @@
#ifndef _I386_BYTEORDER_H
#define _I386_BYTEORDER_H
#include <asm/types.h>
#ifdef __GNUC__
static __inline__ __u32 ___arch__swab32(__u32 x)
{
#ifdef CONFIG_X86_BSWAP
__asm__("bswap %0" : "=r" (x) : "0" (x));
#else
__asm__("xchgb %b0,%h0\n\t" /* swap lower bytes */
"rorl $16,%0\n\t" /* swap words */
"xchgb %b0,%h0" /* swap higher bytes */
:"=q" (x)
: "0" (x));
#endif
return x;
}
static __inline__ __u16 ___arch__swab16(__u16 x)
{
__asm__("xchgb %b0,%h0" /* swap bytes */ \
: "=q" (x) \
: "0" (x)); \
return x;
}
#define __arch__swab32(x) ___arch__swab32(x)
#define __arch__swab16(x) ___arch__swab16(x)
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
#endif
#endif /* __GNUC__ */
#include <linux/byteorder/little_endian.h>
#endif /* _I386_BYTEORDER_H */

36
u-boot/arch/x86/include/asm/cache.h Normal file
View File

@@ -0,0 +1,36 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __X86_CACHE_H__
#define __X86_CACHE_H__
/*
* If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise
* use 64-bytes, a safe default for x86.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 64
#endif
static inline void wbinvd(void)
{
asm volatile ("wbinvd" : : : "memory");
}
static inline void invd(void)
{
asm volatile("invd" : : : "memory");
}
/* Enable caches and write buffer */
void enable_caches(void);
/* Disable caches and write buffer */
void disable_caches(void);
#endif /* __X86_CACHE_H__ */

13
u-boot/arch/x86/include/asm/config.h Normal file
View File

@@ -0,0 +1,13 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif

89
u-boot/arch/x86/include/asm/control_regs.h Normal file
View File

@@ -0,0 +1,89 @@
/*
* Copyright (c) 2012 The Chromium OS Authors.
*
* (C) Copyright 2008-2011
* Graeme Russ, <graeme.russ@gmail.com>
*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
*
* Portions of this file are derived from the Linux kernel source
* Copyright (C) 1991, 1992 Linus Torvalds
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __X86_CONTROL_REGS_H
#define __X86_CONTROL_REGS_H
/*
* The memory clobber prevents the GCC from reordering the read/write order
* of CR0
*/
static inline unsigned long read_cr0(void)
{
unsigned long val;
asm volatile ("movl %%cr0, %0" : "=r" (val) : : "memory");
return val;
}
static inline void write_cr0(unsigned long val)
{
asm volatile ("movl %0, %%cr0" : : "r" (val) : "memory");
}
static inline unsigned long read_cr2(void)
{
unsigned long val;
asm volatile("mov %%cr2,%0\n\t" : "=r" (val) : : "memory");
return val;
}
static inline unsigned long read_cr3(void)
{
unsigned long val;
asm volatile("mov %%cr3,%0\n\t" : "=r" (val) : : "memory");
return val;
}
static inline unsigned long read_cr4(void)
{
unsigned long val;
asm volatile("mov %%cr4,%0\n\t" : "=r" (val) : : "memory");
return val;
}
static inline unsigned long get_debugreg(int regno)
{
unsigned long val = 0; /* Damn you, gcc! */
switch (regno) {
case 0:
asm("mov %%db0, %0" : "=r" (val));
break;
case 1:
asm("mov %%db1, %0" : "=r" (val));
break;
case 2:
asm("mov %%db2, %0" : "=r" (val));
break;
case 3:
asm("mov %%db3, %0" : "=r" (val));
break;
case 6:
asm("mov %%db6, %0" : "=r" (val));
break;
case 7:
asm("mov %%db7, %0" : "=r" (val));
break;
default:
val = 0;
}
return val;
}
#endif

326
u-boot/arch/x86/include/asm/coreboot_tables.h Normal file
View File

@@ -0,0 +1,326 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _COREBOOT_TABLES_H
#define _COREBOOT_TABLES_H
struct cbuint64 {
u32 lo;
u32 hi;
};
struct cb_header {
u8 signature[4];
u32 header_bytes;
u32 header_checksum;
u32 table_bytes;
u32 table_checksum;
u32 table_entries;
};
struct cb_record {
u32 tag;
u32 size;
};
#define CB_TAG_UNUSED 0x0000
#define CB_TAG_MEMORY 0x0001
struct cb_memory_range {
struct cbuint64 start;
struct cbuint64 size;
u32 type;
};
#define CB_MEM_RAM 1
#define CB_MEM_RESERVED 2
#define CB_MEM_ACPI 3
#define CB_MEM_NVS 4
#define CB_MEM_UNUSABLE 5
#define CB_MEM_VENDOR_RSVD 6
#define CB_MEM_TABLE 16
struct cb_memory {
u32 tag;
u32 size;
struct cb_memory_range map[0];
};
#define CB_TAG_HWRPB 0x0002
struct cb_hwrpb {
u32 tag;
u32 size;
u64 hwrpb;
};
#define CB_TAG_MAINBOARD 0x0003
struct cb_mainboard {
u32 tag;
u32 size;
u8 vendor_idx;
u8 part_number_idx;
u8 strings[0];
};
#define CB_TAG_VERSION 0x0004
#define CB_TAG_EXTRA_VERSION 0x0005
#define CB_TAG_BUILD 0x0006
#define CB_TAG_COMPILE_TIME 0x0007
#define CB_TAG_COMPILE_BY 0x0008
#define CB_TAG_COMPILE_HOST 0x0009
#define CB_TAG_COMPILE_DOMAIN 0x000a
#define CB_TAG_COMPILER 0x000b
#define CB_TAG_LINKER 0x000c
#define CB_TAG_ASSEMBLER 0x000d
struct cb_string {
u32 tag;
u32 size;
u8 string[0];
};
#define CB_TAG_SERIAL 0x000f
struct cb_serial {
u32 tag;
u32 size;
#define CB_SERIAL_TYPE_IO_MAPPED 1
#define CB_SERIAL_TYPE_MEMORY_MAPPED 2
u32 type;
u32 baseaddr;
u32 baud;
};
#define CB_TAG_CONSOLE 0x0010
struct cb_console {
u32 tag;
u32 size;
u16 type;
};
#define CB_TAG_CONSOLE_SERIAL8250 0
#define CB_TAG_CONSOLE_VGA 1 /* OBSOLETE */
#define CB_TAG_CONSOLE_BTEXT 2 /* OBSOLETE */
#define CB_TAG_CONSOLE_LOGBUF 3
#define CB_TAG_CONSOLE_SROM 4 /* OBSOLETE */
#define CB_TAG_CONSOLE_EHCI 5
#define CB_TAG_FORWARD 0x0011
struct cb_forward {
u32 tag;
u32 size;
u64 forward;
};
#define CB_TAG_FRAMEBUFFER 0x0012
struct cb_framebuffer {
u32 tag;
u32 size;
u64 physical_address;
u32 x_resolution;
u32 y_resolution;
u32 bytes_per_line;
u8 bits_per_pixel;
u8 red_mask_pos;
u8 red_mask_size;
u8 green_mask_pos;
u8 green_mask_size;
u8 blue_mask_pos;
u8 blue_mask_size;
u8 reserved_mask_pos;
u8 reserved_mask_size;
};
#define CB_TAG_GPIO 0x0013
#define GPIO_MAX_NAME_LENGTH 16
struct cb_gpio {
u32 port;
u32 polarity;
u32 value;
u8 name[GPIO_MAX_NAME_LENGTH];
};
struct cb_gpios {
u32 tag;
u32 size;
u32 count;
struct cb_gpio gpios[0];
};
#define CB_TAG_FDT 0x0014
struct cb_fdt {
uint32_t tag;
uint32_t size; /* size of the entire entry */
/* the actual FDT gets placed here */
};
#define CB_TAG_VDAT 0x0015
struct cb_vdat {
uint32_t tag;
uint32_t size; /* size of the entire entry */
void *vdat_addr;
uint32_t vdat_size;
};
#define CB_TAG_TIMESTAMPS 0x0016
#define CB_TAG_CBMEM_CONSOLE 0x0017
#define CB_TAG_MRC_CACHE 0x0018
struct cb_cbmem_tab {
uint32_t tag;
uint32_t size;
void *cbmem_tab;
};
#define CB_TAG_VBNV 0x0019
struct cb_vbnv {
uint32_t tag;
uint32_t size;
uint32_t vbnv_start;
uint32_t vbnv_size;
};
#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
struct cb_cmos_option_table {
u32 tag;
u32 size;
u32 header_length;
};
#define CB_TAG_OPTION 0x00c9
#define CMOS_MAX_NAME_LENGTH 32
struct cb_cmos_entries {
u32 tag;
u32 size;
u32 bit;
u32 length;
u32 config;
u32 config_id;
u8 name[CMOS_MAX_NAME_LENGTH];
};
#define CB_TAG_OPTION_ENUM 0x00ca
#define CMOS_MAX_TEXT_LENGTH 32
struct cb_cmos_enums {
u32 tag;
u32 size;
u32 config_id;
u32 value;
u8 text[CMOS_MAX_TEXT_LENGTH];
};
#define CB_TAG_OPTION_DEFAULTS 0x00cb
#define CMOS_IMAGE_BUFFER_SIZE 128
struct cb_cmos_defaults {
u32 tag;
u32 size;
u32 name_length;
u8 name[CMOS_MAX_NAME_LENGTH];
u8 default_set[CMOS_IMAGE_BUFFER_SIZE];
};
#define CB_TAG_OPTION_CHECKSUM 0x00cc
#define CHECKSUM_NONE 0
#define CHECKSUM_PCBIOS 1
struct cb_cmos_checksum {
u32 tag;
u32 size;
u32 range_start;
u32 range_end;
u32 location;
u32 type;
};
/* Helpful macros */
#define MEM_RANGE_COUNT(_rec) \
(((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
#define MEM_RANGE_PTR(_rec, _idx) \
(((u8 *) (_rec)) + sizeof(*(_rec)) \
+ (sizeof((_rec)->map[0]) * (_idx)))
#define MB_VENDOR_STRING(_mb) \
(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
#define MB_PART_STRING(_mb) \
(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
#define UNPACK_CB64(_in) \
((((u64) _in.hi) << 32) | _in.lo)
#define CBMEM_TOC_RESERVED 512
#define MAX_CBMEM_ENTRIES 16
#define CBMEM_MAGIC 0x434f5245
struct cbmem_entry {
u32 magic;
u32 id;
u64 base;
u64 size;
} __packed;
#define CBMEM_ID_FREESPACE 0x46524545
#define CBMEM_ID_GDT 0x4c474454
#define CBMEM_ID_ACPI 0x41435049
#define CBMEM_ID_CBTABLE 0x43425442
#define CBMEM_ID_PIRQ 0x49525154
#define CBMEM_ID_MPTABLE 0x534d5054
#define CBMEM_ID_RESUME 0x5245534d
#define CBMEM_ID_RESUME_SCRATCH 0x52455343
#define CBMEM_ID_SMBIOS 0x534d4254
#define CBMEM_ID_TIMESTAMP 0x54494d45
#define CBMEM_ID_MRCDATA 0x4d524344
#define CBMEM_ID_CONSOLE 0x434f4e53
#define CBMEM_ID_NONE 0x00000000
/**
* high_table_reserve() - reserve configuration table in high memory
*
* This reserves configuration table in high memory.
*
* @return: always 0
*/
int high_table_reserve(void);
/**
* high_table_malloc() - allocate configuration table in high memory
*
* This allocates configuration table in high memory.
*
* @bytes: size of configuration table to be allocated
* @return: pointer to configuration table in high memory
*/
void *high_table_malloc(size_t bytes);
/**
* write_coreboot_table() - write coreboot table
*
* This writes coreboot table at a given address.
*
* @addr: start address to write coreboot table
* @cfg_tables: pointer to configuration table memory area
*/
void write_coreboot_table(u32 addr, struct memory_area *cfg_tables);
#endif

290
u-boot/arch/x86/include/asm/cpu.h Normal file
View File

@@ -0,0 +1,290 @@
/*
* Copyright (c) 2014 The Chromium OS Authors.
*
* Part of this file is adapted from coreboot
* src/arch/x86/include/arch/cpu.h and
* src/arch/x86/lib/cpu.c
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_H
#define _ASM_CPU_H
enum {
X86_VENDOR_INVALID = 0,
X86_VENDOR_INTEL,
X86_VENDOR_CYRIX,
X86_VENDOR_AMD,
X86_VENDOR_UMC,
X86_VENDOR_NEXGEN,
X86_VENDOR_CENTAUR,
X86_VENDOR_RISE,
X86_VENDOR_TRANSMETA,
X86_VENDOR_NSC,
X86_VENDOR_SIS,
X86_VENDOR_ANY = 0xfe,
X86_VENDOR_UNKNOWN = 0xff
};
/* Global descriptor table (GDT) bits */
enum {
GDT_4KB = 1ULL << 55,
GDT_32BIT = 1ULL << 54,
GDT_LONG = 1ULL << 53,
GDT_PRESENT = 1ULL << 47,
GDT_NOTSYS = 1ULL << 44,
GDT_CODE = 1ULL << 43,
GDT_LIMIT_LOW_SHIFT = 0,
GDT_LIMIT_LOW_MASK = 0xffff,
GDT_LIMIT_HIGH_SHIFT = 48,
GDT_LIMIT_HIGH_MASK = 0xf,
GDT_BASE_LOW_SHIFT = 16,
GDT_BASE_LOW_MASK = 0xffff,
GDT_BASE_HIGH_SHIFT = 56,
GDT_BASE_HIGH_MASK = 0xf,
};
/*
* System controllers in an x86 system. We mostly need to just find these and
* use them on PCI. At some point these might have their own uclass (e.g.
* UCLASS_VIDEO for the GMA device).
*/
enum {
X86_NONE,
X86_SYSCON_ME, /* Intel Management Engine */
X86_SYSCON_GMA, /* Intel Graphics Media Accelerator */
X86_SYSCON_PINCONF, /* Intel x86 pin configuration */
};
struct cpuid_result {
uint32_t eax;
uint32_t ebx;
uint32_t ecx;
uint32_t edx;
};
/*
* Generic CPUID function
*/
static inline struct cpuid_result cpuid(int op)
{
struct cpuid_result result;
asm volatile(
"mov %%ebx, %%edi;"
"cpuid;"
"mov %%ebx, %%esi;"
"mov %%edi, %%ebx;"
: "=a" (result.eax),
"=S" (result.ebx),
"=c" (result.ecx),
"=d" (result.edx)
: "0" (op)
: "edi");
return result;
}
/*
* Generic Extended CPUID function
*/
static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
{
struct cpuid_result result;
asm volatile(
"mov %%ebx, %%edi;"
"cpuid;"
"mov %%ebx, %%esi;"
"mov %%edi, %%ebx;"
: "=a" (result.eax),
"=S" (result.ebx),
"=c" (result.ecx),
"=d" (result.edx)
: "0" (op), "2" (ecx)
: "edi");
return result;
}
/*
* CPUID functions returning a single datum
*/
static inline unsigned int cpuid_eax(unsigned int op)
{
unsigned int eax;
__asm__("mov %%ebx, %%edi;"
"cpuid;"
"mov %%edi, %%ebx;"
: "=a" (eax)
: "0" (op)
: "ecx", "edx", "edi");
return eax;
}
static inline unsigned int cpuid_ebx(unsigned int op)
{
unsigned int eax, ebx;
__asm__("mov %%ebx, %%edi;"
"cpuid;"
"mov %%ebx, %%esi;"
"mov %%edi, %%ebx;"
: "=a" (eax), "=S" (ebx)
: "0" (op)
: "ecx", "edx", "edi");
return ebx;
}
static inline unsigned int cpuid_ecx(unsigned int op)
{
unsigned int eax, ecx;
__asm__("mov %%ebx, %%edi;"
"cpuid;"
"mov %%edi, %%ebx;"
: "=a" (eax), "=c" (ecx)
: "0" (op)
: "edx", "edi");
return ecx;
}
static inline unsigned int cpuid_edx(unsigned int op)
{
unsigned int eax, edx;
__asm__("mov %%ebx, %%edi;"
"cpuid;"
"mov %%edi, %%ebx;"
: "=a" (eax), "=d" (edx)
: "0" (op)
: "ecx", "edi");
return edx;
}
/* Standard macro to see if a specific flag is changeable */
static inline int flag_is_changeable_p(uint32_t flag)
{
uint32_t f1, f2;
asm(
"pushfl\n\t"
"pushfl\n\t"
"popl %0\n\t"
"movl %0,%1\n\t"
"xorl %2,%0\n\t"
"pushl %0\n\t"
"popfl\n\t"
"pushfl\n\t"
"popl %0\n\t"
"popfl\n\t"
: "=&r" (f1), "=&r" (f2)
: "ir" (flag));
return ((f1^f2) & flag) != 0;
}
static inline void mfence(void)
{
__asm__ __volatile__("mfence" : : : "memory");
}
/**
* cpu_enable_paging_pae() - Enable PAE-paging
*
* @cr3: Value to set in cr3 (PDPT or PML4T)
*/
void cpu_enable_paging_pae(ulong cr3);
/**
* cpu_disable_paging_pae() - Disable paging and PAE
*/
void cpu_disable_paging_pae(void);
/**
* cpu_has_64bit() - Check if the CPU has 64-bit support
*
* @return 1 if this CPU supports long mode (64-bit), 0 if not
*/
int cpu_has_64bit(void);
/**
* cpu_vendor_name() - Get CPU vendor name
*
* @vendor: CPU vendor enumeration number
*
* @return: Address to hold the CPU vendor name string
*/
const char *cpu_vendor_name(int vendor);
#define CPU_MAX_NAME_LEN 49
/**
* cpu_get_name() - Get the name of the current cpu
*
* @name: Place to put name, which must be CPU_MAX_NAME_LEN bytes including
* @return pointer to name, which will likely be a few bytes after the start
* of @name
* \0 terminator
*/
char *cpu_get_name(char *name);
/**
* cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
*
* The kernel is uncompressed and the 64-bit entry point is expected to be
* at @target.
*
* This function is used internally - see cpu_jump_to_64bit() for a more
* useful function.
*
* @pgtable: Address of 24KB area containing the page table
* @setup_base: Pointer to the setup.bin information for the kernel
* @target: Pointer to the start of the kernel image
*/
void cpu_call64(ulong pgtable, ulong setup_base, ulong target);
/**
* cpu_call32() - Jump to a 32-bit entry point
*
* @code_seg32: 32-bit code segment to use (GDT offset, e.g. 0x20)
* @target: Pointer to the start of the 32-bit U-Boot image/entry point
* @table: Pointer to start of info table to pass to U-Boot
*/
void cpu_call32(ulong code_seg32, ulong target, ulong table);
/**
* cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel
*
* The kernel is uncompressed and the 64-bit entry point is expected to be
* at @target.
*
* @setup_base: Pointer to the setup.bin information for the kernel
* @target: Pointer to the start of the kernel image
*/
int cpu_jump_to_64bit(ulong setup_base, ulong target);
/**
* cpu_get_family_model() - Get the family and model for the CPU
*
* @return the CPU ID masked with 0x0fff0ff0
*/
u32 cpu_get_family_model(void);
/**
* cpu_get_stepping() - Get the stepping value for the CPU
*
* @return the CPU ID masked with 0xf
*/
u32 cpu_get_stepping(void);
/**
* cpu_run_reference_code() - Run the platform reference code
*
* Some platforms require a binary blob to be executed once SDRAM is
* available. This is used to set up various platform features, such as the
* platform controller hub (PCH). This function should be implemented by the
* CPU-specific code.
*
* @return 0 on success, -ve on failure
*/
int cpu_run_reference_code(void);
#endif

35
u-boot/arch/x86/include/asm/cpu_common.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* Copyright (c) 2016 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_CPU_COMMON_H
#define __ASM_CPU_COMMON_H
#define IA32_PERF_CTL 0x199
/**
* cpu_common_init() - Set up common CPU init
*
* This reports BIST failure, enables the LAPIC, updates microcode, enables
* the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA.
*
* @return 0 if OK, -ve on error
*/
int cpu_common_init(void);
/**
* cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate
*
* If a change is needed, this function will do a soft reset so it takes
* effect.
*
* Some details are available here:
* http://forum.hwbot.org/showthread.php?t=76092
*
* @return 0 if OK, -ve on error
*/
int cpu_set_flex_ratio_to_tdp_nominal(void);
#endif

34
u-boot/arch/x86/include/asm/cpu_x86.h Normal file
View File

@@ -0,0 +1,34 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_X86_H
#define _ASM_CPU_X86_H
/**
* cpu_x86_bind() - Bind an x86 CPU with the driver
*
* This updates cpu device's platform data with information from device tree,
* like the processor local apic id.
*
* @dev: Device to check (UCLASS_CPU)
* @return 0 always
*/
int cpu_x86_bind(struct udevice *dev);
/**
* cpu_x86_get_desc() - Get a description string for an x86 CPU
*
* This uses cpu_get_name() and is suitable to use as the get_desc() method for
* the CPU uclass.
*
* @dev: Device to check (UCLASS_CPU)
* @buf: Buffer to place string
* @size: Size of string space
* @return: 0 if OK, -ENOSPC if buffer is too small, other -ve on error
*/
int cpu_x86_get_desc(struct udevice *dev, char *buf, int size);
#endif /* _ASM_CPU_X86_H */

29
u-boot/arch/x86/include/asm/e820.h Normal file
View File

@@ -0,0 +1,29 @@
#ifndef _ASM_X86_E820_H
#define _ASM_X86_E820_H
#define E820MAX 128 /* number of entries in E820MAP */
#define E820_RAM 1
#define E820_RESERVED 2
#define E820_ACPI 3
#define E820_NVS 4
#define E820_UNUSABLE 5
#ifndef __ASSEMBLY__
#include <linux/types.h>
struct e820entry {
__u64 addr; /* start of memory segment */
__u64 size; /* size of memory segment */
__u32 type; /* type of memory segment */
} __attribute__((packed));
#define ISA_START_ADDRESS 0xa0000
#define ISA_END_ADDRESS 0x100000
#endif /* __ASSEMBLY__ */
/* Implementation defined function to install an e820 map */
unsigned install_e820_map(unsigned max_entries, struct e820entry *);
#endif /* _ASM_X86_E820_H */

46
u-boot/arch/x86/include/asm/elf.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* Brought in from Linux 4.1, removed things not useful to U-Boot.
* The definitions perhaps came from the GNU Library which is GPL.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_X86_ELF_H
#define _ASM_X86_ELF_H
/* ELF register definitions */
#define R_386_NONE 0
#define R_386_32 1
#define R_386_PC32 2
#define R_386_GOT32 3
#define R_386_PLT32 4
#define R_386_COPY 5
#define R_386_GLOB_DAT 6
#define R_386_JMP_SLOT 7
#define R_386_RELATIVE 8
#define R_386_GOTOFF 9
#define R_386_GOTPC 10
#define R_386_NUM 11
/* x86-64 relocation types */
#define R_X86_64_NONE 0 /* No reloc */
#define R_X86_64_64 1 /* Direct 64 bit */
#define R_X86_64_PC32 2 /* PC relative 32 bit signed */
#define R_X86_64_GOT32 3 /* 32 bit GOT entry */
#define R_X86_64_PLT32 4 /* 32 bit PLT address */
#define R_X86_64_COPY 5 /* Copy symbol at runtime */
#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */
#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
#define R_X86_64_RELATIVE 8 /* Adjust by program base */
/* 32 bit signed pc relative offset to GOT */
#define R_X86_64_GOTPCREL 9
#define R_X86_64_32 10 /* Direct 32 bit zero extended */
#define R_X86_64_32S 11 /* Direct 32 bit sign extended */
#define R_X86_64_16 12 /* Direct 16 bit zero extended */
#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */
#define R_X86_64_8 14 /* Direct 8 bit sign extended */
#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */
#define R_X86_64_NUM 16
#endif

1
u-boot/arch/x86/include/asm/errno.h Normal file
View File

@@ -0,0 +1 @@
#include <asm-generic/errno.h>

67
u-boot/arch/x86/include/asm/fsp/fsp_api.h Normal file
View File

@@ -0,0 +1,67 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: Intel
*/
#ifndef __FSP_API_H__
#define __FSP_API_H__
#include <linux/linkage.h>
/*
* FSP common configuration structure.
* This needs to be included in the platform-specific struct fsp_config_data.
*/
struct fsp_cfg_common {
struct fsp_header *fsp_hdr;
u32 stack_top;
u32 boot_mode;
};
/*
* FspInit continuation function prototype.
* Control will be returned to this callback function after FspInit API call.
*/
typedef void (*fsp_continuation_f)(u32 status, void *hob_list);
struct fsp_init_params {
/* Non-volatile storage buffer pointer */
void *nvs_buf;
/* Runtime buffer pointer */
void *rt_buf;
/* Continuation function address */
fsp_continuation_f continuation;
};
struct common_buf {
/*
* Stack top pointer used by the bootloader. The new stack frame will be
* set up at this location after FspInit API call.
*/
u32 stack_top;
u32 boot_mode; /* Current system boot mode */
void *upd_data; /* User platform configuraiton data region */
u32 reserved[7]; /* Reserved */
};
enum fsp_phase {
/* Notification code for post PCI enuermation */
INIT_PHASE_PCI = 0x20,
/* Notification code before transfering control to the payload */
INIT_PHASE_BOOT = 0x40
};
struct fsp_notify_params {
/* Notification phase used for NotifyPhase API */
enum fsp_phase phase;
};
/* FspInit API function prototype */
typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params);
/* FspNotify API function prototype */
typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params);
#endif

24
u-boot/arch/x86/include/asm/fsp/fsp_bootmode.h Normal file
View File

@@ -0,0 +1,24 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: Intel
*/
#ifndef __FSP_BOOT_MODE_H__
#define __FSP_BOOT_MODE_H__
/* 0x21 - 0xf..f are reserved */
#define BOOT_FULL_CONFIG 0x00
#define BOOT_MINIMAL_CONFIG 0x01
#define BOOT_NO_CONFIG_CHANGES 0x02
#define BOOT_FULL_CONFIG_PLUS_DIAG 0x03
#define BOOT_DEFAULT_SETTINGS 0x04
#define BOOT_ON_S4_RESUME 0x05
#define BOOT_ON_S5_RESUME 0x06
#define BOOT_ON_S2_RESUME 0x10
#define BOOT_ON_S3_RESUME 0x11
#define BOOT_ON_FLASH_UPDATE 0x12
#define BOOT_IN_RECOVERY_MODE 0x20
#endif

154
u-boot/arch/x86/include/asm/fsp/fsp_ffs.h Normal file
View File

@@ -0,0 +1,154 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: Intel
*/
#ifndef __FSP_FFS_H__
#define __FSP_FFS_H__
/* Used to verify the integrity of the file */
union __packed ffs_integrity {
struct {
/*
* The IntegrityCheck.checksum.header field is an 8-bit
* checksum of the file header. The State and
* IntegrityCheck.checksum.file fields are assumed to be zero
* and the checksum is calculated such that the entire header
* sums to zero.
*/
u8 header;
/*
* If the FFS_ATTRIB_CHECKSUM (see definition below) bit of
* the Attributes field is set to one, the
* IntegrityCheck.checksum.file field is an 8-bit checksum of
* the file data. If the FFS_ATTRIB_CHECKSUM bit of the
* Attributes field is cleared to zero, the
* IntegrityCheck.checksum.file field must be initialized with
* a value of 0xAA. The IntegrityCheck.checksum.file field is
* valid any time the EFI_FILE_DATA_VALID bit is set in the
* State field.
*/
u8 file;
} checksum;
/* This is the full 16 bits of the IntegrityCheck field */
u16 checksum16;
};
/*
* Each file begins with the header that describe the
* contents and state of the files.
*/
struct __packed ffs_file_header {
/*
* This GUID is the file name.
* It is used to uniquely identify the file.
*/
struct efi_guid name;
/* Used to verify the integrity of the file */
union ffs_integrity integrity;
/* Identifies the type of file */
u8 type;
/* Declares various file attribute bits */
u8 attr;
/* The length of the file in bytes, including the FFS header */
u8 size[3];
/*
* Used to track the state of the file throughout the life of
* the file from creation to deletion.
*/
u8 state;
};
struct __packed ffs_file_header2 {
/*
* This GUID is the file name. It is used to uniquely identify the file.
* There may be only one instance of a file with the file name GUID of
* Name in any given firmware volume, except if the file type is
* EFI_FV_FILE_TYPE_FFS_PAD.
*/
struct efi_guid name;
/* Used to verify the integrity of the file */
union ffs_integrity integrity;
/* Identifies the type of file */
u8 type;
/* Declares various file attribute bits */
u8 attr;
/*
* The length of the file in bytes, including the FFS header.
* The length of the file data is either
* (size - sizeof(struct ffs_file_header)). This calculation means a
* zero-length file has a size of 24 bytes, which is
* sizeof(struct ffs_file_header). Size is not required to be a
* multiple of 8 bytes. Given a file F, the next file header is located
* at the next 8-byte aligned firmware volume offset following the last
* byte of the file F.
*/
u8 size[3];
/*
* Used to track the state of the file throughout the life of
* the file from creation to deletion.
*/
u8 state;
/*
* If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists
* and size must be set to zero.
* If FFS_ATTRIB_LARGE_FILE is not set then
* struct ffs_file_header is used.
*/
u32 ext_size;
};
/*
* Pseudo type. It is used as a wild card when retrieving sections.
* The section type EFI_SECTION_ALL matches all section types.
*/
#define EFI_SECTION_ALL 0x00
/* Encapsulation section Type values */
#define EFI_SECTION_COMPRESSION 0x01
#define EFI_SECTION_GUID_DEFINED 0x02
#define EFI_SECTION_DISPOSABLE 0x03
/* Leaf section Type values */
#define EFI_SECTION_PE32 0x10
#define EFI_SECTION_PIC 0x11
#define EFI_SECTION_TE 0x12
#define EFI_SECTION_DXE_DEPEX 0x13
#define EFI_SECTION_VERSION 0x14
#define EFI_SECTION_USER_INTERFACE 0x15
#define EFI_SECTION_COMPATIBILITY16 0x16
#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
#define EFI_SECTION_RAW 0x19
#define EFI_SECTION_PEI_DEPEX 0x1B
#define EFI_SECTION_SMM_DEPEX 0x1C
/* Common section header */
struct __packed raw_section {
/*
* A 24-bit unsigned integer that contains the total size of
* the section in bytes, including the EFI_COMMON_SECTION_HEADER.
*/
u8 size[3];
u8 type;
};
struct __packed raw_section2 {
/*
* A 24-bit unsigned integer that contains the total size of
* the section in bytes, including the EFI_COMMON_SECTION_HEADER.
*/
u8 size[3];
u8 type;
/*
* If size is 0xFFFFFF, then ext_size contains the size of
* the section. If size is not equal to 0xFFFFFF, then this
* field does not exist.
*/
u32 ext_size;
};
#endif

137
u-boot/arch/x86/include/asm/fsp/fsp_fv.h Normal file
View File

@@ -0,0 +1,137 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: Intel
*/
#ifndef __FSP_FV___
#define __FSP_FV___
/* Value of EFI_FV_FILE_ATTRIBUTES */
#define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F
#define EFI_FV_FILE_ATTR_FIXED 0x00000100
#define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200
/* Attributes bit definitions */
#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
#define EFI_FVB2_READ_STATUS 0x00000004
#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
#define EFI_FVB2_WRITE_STATUS 0x00000020
#define EFI_FVB2_LOCK_CAP 0x00000040
#define EFI_FVB2_LOCK_STATUS 0x00000080
#define EFI_FVB2_STICKY_WRITE 0x00000200
#define EFI_FVB2_MEMORY_MAPPED 0x00000400
#define EFI_FVB2_ERASE_POLARITY 0x00000800
#define EFI_FVB2_READ_LOCK_CAP 0x00001000
#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
#define EFI_FVB2_ALIGNMENT 0x001F0000
#define EFI_FVB2_ALIGNMENT_1 0x00000000
#define EFI_FVB2_ALIGNMENT_2 0x00010000
#define EFI_FVB2_ALIGNMENT_4 0x00020000
#define EFI_FVB2_ALIGNMENT_8 0x00030000
#define EFI_FVB2_ALIGNMENT_16 0x00040000
#define EFI_FVB2_ALIGNMENT_32 0x00050000
#define EFI_FVB2_ALIGNMENT_64 0x00060000
#define EFI_FVB2_ALIGNMENT_128 0x00070000
#define EFI_FVB2_ALIGNMENT_256 0x00080000
#define EFI_FVB2_ALIGNMENT_512 0x00090000
#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
#define EFI_FVB2_ALIGNMENT_64K 0x00100000
#define EFI_FVB2_ALIGNMENT_128K 0x00110000
#define EFI_FVB2_ALIGNMENT_256K 0x00120000
#define EFI_FVB2_ALIGNMENT_512K 0x00130000
#define EFI_FVB2_ALIGNMENT_1M 0x00140000
#define EFI_FVB2_ALIGNMENT_2M 0x00150000
#define EFI_FVB2_ALIGNMENT_4M 0x00160000
#define EFI_FVB2_ALIGNMENT_8M 0x00170000
#define EFI_FVB2_ALIGNMENT_16M 0x00180000
#define EFI_FVB2_ALIGNMENT_32M 0x00190000
#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
struct fv_blkmap_entry {
/* The number of sequential blocks which are of the same size */
u32 num_blocks;
/* The size of the blocks */
u32 length;
};
/* Describes the features and layout of the firmware volume */
struct fv_header {
/*
* The first 16 bytes are reserved to allow for the reset vector of
* processors whose reset vector is at address 0.
*/
u8 zero_vec[16];
/*
* Declares the file system with which the firmware volume
* is formatted.
*/
struct efi_guid fs_guid;
/*
* Length in bytes of the complete firmware volume, including
* the header.
*/
u64 fv_len;
/* Set to EFI_FVH_SIGNATURE */
u32 sign;
/*
* Declares capabilities and power-on defaults for the firmware
* volume.
*/
u32 attr;
/* Length in bytes of the complete firmware volume header */
u16 hdr_len;
/*
* A 16-bit checksum of the firmware volume header.
* A valid header sums to zero.
*/
u16 checksum;
/*
* Offset, relative to the start of the header, of the extended
* header (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is
* no extended header.
*/
u16 ext_hdr_off;
/* This field must always be set to zero */
u8 reserved[1];
/*
* Set to 2. Future versions of this specification may define new
* header fields and will increment the Revision field accordingly.
*/
u8 rev;
/*
* An array of run-length encoded FvBlockMapEntry structures.
* The array is terminated with an entry of {0,0}.
*/
struct fv_blkmap_entry block_map[1];
};
#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H')
/* Firmware Volume Header Revision definition */
#define EFI_FVH_REVISION 0x02
/* Extension header pointed by ExtHeaderOffset of volume header */
struct fv_ext_header {
/* firmware volume name */
struct efi_guid fv_name;
/* Size of the rest of the extension header including this structure */
u32 ext_hdr_size;
};
#endif

245
u-boot/arch/x86/include/asm/fsp/fsp_hob.h Normal file
View File

@@ -0,0 +1,245 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: Intel
*/
#ifndef __FSP_HOB_H__
#define __FSP_HOB_H__
#include <efi.h>
/* Type of HOB Header */
#define HOB_TYPE_MEM_ALLOC 0x0002
#define HOB_TYPE_RES_DESC 0x0003
#define HOB_TYPE_GUID_EXT 0x0004
#define HOB_TYPE_UNUSED 0xFFFE
#define HOB_TYPE_EOH 0xFFFF
/*
* Describes the format and size of the data inside the HOB.
* All HOBs must contain this generic HOB header.
*/
struct hob_header {
u16 type; /* HOB type */
u16 len; /* HOB length */
u32 reserved; /* always zero */
};
/*
* Describes all memory ranges used during the HOB producer phase that
* exist outside the HOB list. This HOB type describes how memory is used,
* not the physical attributes of memory.
*/
struct hob_mem_alloc {
struct hob_header hdr;
/*
* A GUID that defines the memory allocation region's type and purpose,
* as well as other fields within the memory allocation HOB. This GUID
* is used to define the additional data within the HOB that may be
* present for the memory allocation HOB. Type efi_guid is defined in
* InstallProtocolInterface() in the UEFI 2.0 specification.
*/
struct efi_guid name;
/*
* The base address of memory allocated by this HOB.
* Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0
* specification.
*/
phys_addr_t mem_base;
/* The length in bytes of memory allocated by this HOB */
phys_size_t mem_len;
/*
* Defines the type of memory allocated by this HOB.
* The memory type definition follows the EFI_MEMORY_TYPE definition.
* Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0
* specification.
*/
enum efi_mem_type mem_type;
/* padding */
u8 reserved[4];
};
/* Value of ResourceType in HOB_RES_DESC */
#define RES_SYS_MEM 0x00000000
#define RES_MMAP_IO 0x00000001
#define RES_IO 0x00000002
#define RES_FW_DEVICE 0x00000003
#define RES_MMAP_IO_PORT 0x00000004
#define RES_MEM_RESERVED 0x00000005
#define RES_IO_RESERVED 0x00000006
#define RES_MAX_MEM_TYPE 0x00000007
/*
* These types can be ORed together as needed.
*
* The first three enumerations describe settings
* The rest of the settings describe capabilities
*/
#define RES_ATTR_PRESENT 0x00000001
#define RES_ATTR_INITIALIZED 0x00000002
#define RES_ATTR_TESTED 0x00000004
#define RES_ATTR_SINGLE_BIT_ECC 0x00000008
#define RES_ATTR_MULTIPLE_BIT_ECC 0x00000010
#define RES_ATTR_ECC_RESERVED_1 0x00000020
#define RES_ATTR_ECC_RESERVED_2 0x00000040
#define RES_ATTR_READ_PROTECTED 0x00000080
#define RES_ATTR_WRITE_PROTECTED 0x00000100
#define RES_ATTR_EXECUTION_PROTECTED 0x00000200
#define RES_ATTR_UNCACHEABLE 0x00000400
#define RES_ATTR_WRITE_COMBINEABLE 0x00000800
#define RES_ATTR_WRITE_THROUGH_CACHEABLE 0x00001000
#define RES_ATTR_WRITE_BACK_CACHEABLE 0x00002000
#define RES_ATTR_16_BIT_IO 0x00004000
#define RES_ATTR_32_BIT_IO 0x00008000
#define RES_ATTR_64_BIT_IO 0x00010000
#define RES_ATTR_UNCACHED_EXPORTED 0x00020000
/*
* Describes the resource properties of all fixed, nonrelocatable resource
* ranges found on the processor host bus during the HOB producer phase.
*/
struct hob_res_desc {
struct hob_header hdr;
/*
* A GUID representing the owner of the resource. This GUID is
* used by HOB consumer phase components to correlate device
* ownership of a resource.
*/
struct efi_guid owner;
u32 type;
u32 attr;
/* The physical start address of the resource region */
phys_addr_t phys_start;
/* The number of bytes of the resource region */
phys_size_t len;
};
/*
* Allows writers of executable content in the HOB producer phase to
* maintain and manage HOBs with specific GUID.
*/
struct hob_guid {
struct hob_header hdr;
/* A GUID that defines the contents of this HOB */
struct efi_guid name;
/* GUID specific data goes here */
};
/**
* get_next_hob() - return a pointer to the next HOB in the HOB list
*
* This macro returns a pointer to HOB that follows the HOB specified by hob
* in the HOB List.
*
* @hdr: A pointer to a HOB.
*
* @return: A pointer to the next HOB in the HOB list.
*/
static inline const struct hob_header *get_next_hob(const struct hob_header *hdr)
{
return (const struct hob_header *)((u32)hdr + hdr->len);
}
/**
* end_of_hob() - determine if a HOB is the last HOB in the HOB list
*
* This macro determine if the HOB specified by hob is the last HOB in the
* HOB list. If hob is last HOB in the HOB list, then true is returned.
* Otherwise, false is returned.
*
* @hdr: A pointer to a HOB.
*
* @retval true: The HOB specified by hdr is the last HOB in the HOB list.
* @retval false: The HOB specified by hdr is not the last HOB in the HOB list.
*/
static inline bool end_of_hob(const struct hob_header *hdr)
{
return hdr->type == HOB_TYPE_EOH;
}
/**
* get_guid_hob_data() - return a pointer to data buffer from a HOB of
* type HOB_TYPE_GUID_EXT
*
* This macro returns a pointer to the data buffer in a HOB specified by hob.
* hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
*
* @hdr: A pointer to a HOB.
*
* @return: A pointer to the data buffer in a HOB.
*/
static inline void *get_guid_hob_data(const struct hob_header *hdr)
{
return (void *)((u32)hdr + sizeof(struct hob_guid));
}
/**
* get_guid_hob_data_size() - return the size of the data buffer from a HOB
* of type HOB_TYPE_GUID_EXT
*
* This macro returns the size, in bytes, of the data buffer in a HOB
* specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
*
* @hdr: A pointer to a HOB.
*
* @return: The size of the data buffer.
*/
static inline u16 get_guid_hob_data_size(const struct hob_header *hdr)
{
return hdr->len - sizeof(struct hob_guid);
}
/* FSP specific GUID HOB definitions */
#define FSP_GUID_DATA1 0x912740be
#define FSP_GUID_DATA2 0x2284
#define FSP_GUID_DATA3 0x4734
#define FSP_GUID_DATA4_0 0xb9
#define FSP_GUID_DATA4_1 0x71
#define FSP_GUID_DATA4_2 0x84
#define FSP_GUID_DATA4_3 0xb0
#define FSP_GUID_DATA4_4 0x27
#define FSP_GUID_DATA4_5 0x35
#define FSP_GUID_DATA4_6 0x3f
#define FSP_GUID_DATA4_7 0x0c
#define FSP_HEADER_GUID \
{ \
FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \
{ FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \
FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \
FSP_GUID_DATA4_6, FSP_GUID_DATA4_7 } \
}
#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
{ \
0x721acf02, 0x4d77, 0x4c2a, \
{ 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \
}
#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \
{ \
0xbbcff46c, 0xc8d3, 0x4113, \
{ 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \
}
#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \
{ \
0x69a79759, 0x1373, 0x4367, \
{ 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \
}
#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
{ \
0xd038747c, 0xd00c, 0x4980, \
{ 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \
}
#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \
{ \
0x9c7c3aa7, 0x5332, 0x4917, \
{ 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \
}
#endif

32
u-boot/arch/x86/include/asm/fsp/fsp_infoheader.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: Intel
*/
#ifndef _FSP_HEADER_H_
#define _FSP_HEADER_H_
#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */
struct __packed fsp_header {
u32 sign; /* 'FSPH' */
u32 hdr_len; /* header length */
u8 reserved1[3];
u8 hdr_rev; /* header rev */
u32 img_rev; /* image rev */
char img_id[8]; /* signature string */
u32 img_size; /* image size */
u32 img_base; /* image base */
u32 img_attr; /* image attribute */
u32 cfg_region_off; /* configuration region offset */
u32 cfg_region_size; /* configuration region size */
u32 api_num; /* number of API entries */
u32 fsp_tempram_init; /* tempram_init offset */
u32 fsp_init; /* fsp_init offset */
u32 fsp_notify; /* fsp_notify offset */
u32 reserved2;
};
#endif

211
u-boot/arch/x86/include/asm/fsp/fsp_support.h Normal file
View File

@@ -0,0 +1,211 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: Intel
*/
#ifndef __FSP_SUPPORT_H__
#define __FSP_SUPPORT_H__
#include "fsp_types.h"
#include "fsp_fv.h"
#include "fsp_ffs.h"
#include "fsp_api.h"
#include "fsp_hob.h"
#include "fsp_infoheader.h"
#include "fsp_bootmode.h"
#include <asm/arch/fsp/fsp_vpd.h>
#include <asm/arch/fsp/fsp_configs.h>
#define FSP_LOWMEM_BASE 0x100000UL
#define FSP_HIGHMEM_BASE 0x100000000ULL
#define UPD_TERMINATOR 0x55AA
/**
* FSP Continuation assembly helper routine
*
* This routine jumps to the C version of FSP continuation function
*/
void asm_continuation(void);
/**
* FSP initialization complete
*
* This is the function that indicates FSP initialization is complete and jumps
* back to the bootloader with HOB list pointer as the parameter.
*
* @hob_list: HOB list pointer
*/
void fsp_init_done(void *hob_list);
/**
* FSP Continuation function
*
* @status: Always 0
* @hob_list: HOB list pointer
*
* @retval: Never returns
*/
void fsp_continue(u32 status, void *hob_list);
/**
* Find FSP header offset in FSP image
*
* @retval: the offset of FSP header. If signature is invalid, returns 0.
*/
struct fsp_header *find_fsp_header(void);
/**
* FSP initialization wrapper function.
*
* @stack_top: bootloader stack top address
* @boot_mode: boot mode defined in fsp_bootmode.h
* @nvs_buf: Non-volatile memory buffer pointer
*/
void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf);
/**
* FSP notification wrapper function
*
* @fsp_hdr: Pointer to FSP information header
* @phase: FSP initialization phase defined in enum fsp_phase
*
* @retval: compatible status code with EFI_STATUS defined in PI spec
*/
u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
/**
* This function retrieves the top of usable low memory.
*
* @hob_list: A HOB list pointer.
*
* @retval: Usable low memory top.
*/
u32 fsp_get_usable_lowmem_top(const void *hob_list);
/**
* This function retrieves the top of usable high memory.
*
* @hob_list: A HOB list pointer.
*
* @retval: Usable high memory top.
*/
u64 fsp_get_usable_highmem_top(const void *hob_list);
/**
* This function retrieves a special reserved memory region.
*
* @hob_list: A HOB list pointer.
* @len: A pointer to the GUID HOB data buffer length.
* If the GUID HOB is located, the length will be updated.
* @guid: A pointer to the owner guild.
*
* @retval: Reserved region start address.
* 0 if this region does not exist.
*/
u64 fsp_get_reserved_mem_from_guid(const void *hob_list,
u64 *len, struct efi_guid *guid);
/**
* This function retrieves the FSP reserved normal memory.
*
* @hob_list: A HOB list pointer.
* @len: A pointer to the FSP reserved memory length buffer.
* If the GUID HOB is located, the length will be updated.
* @retval: FSP reserved memory base
* 0 if this region does not exist.
*/
u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len);
/**
* This function retrieves the TSEG reserved normal memory.
*
* @hob_list: A HOB list pointer.
* @len: A pointer to the TSEG reserved memory length buffer.
* If the GUID HOB is located, the length will be updated.
*
* @retval NULL: Failed to find the TSEG reserved memory.
* @retval others: TSEG reserved memory base.
*/
u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len);
/**
* Returns the next instance of a HOB type from the starting HOB.
*
* @type: HOB type to search
* @hob_list: A pointer to the HOB list
*
* @retval: A HOB object with matching type; Otherwise NULL.
*/
const struct hob_header *fsp_get_next_hob(uint type, const void *hob_list);
/**
* Returns the next instance of the matched GUID HOB from the starting HOB.
*
* @guid: GUID to search
* @hob_list: A pointer to the HOB list
*
* @retval: A HOB object with matching GUID; Otherwise NULL.
*/
const struct hob_header *fsp_get_next_guid_hob(const struct efi_guid *guid,
const void *hob_list);
/**
* This function retrieves a GUID HOB data buffer and size.
*
* @hob_list: A HOB list pointer.
* @len: A pointer to the GUID HOB data buffer length.
* If the GUID HOB is located, the length will be updated.
* @guid A pointer to HOB GUID.
*
* @retval NULL: Failed to find the GUID HOB.
* @retval others: GUID HOB data buffer pointer.
*/
void *fsp_get_guid_hob_data(const void *hob_list, u32 *len,
struct efi_guid *guid);
/**
* This function retrieves FSP Non-volatile Storage HOB buffer and size.
*
* @hob_list: A HOB list pointer.
* @len: A pointer to the NVS data buffer length.
* If the HOB is located, the length will be updated.
*
* @retval NULL: Failed to find the NVS HOB.
* @retval others: FSP NVS data buffer pointer.
*/
void *fsp_get_nvs_data(const void *hob_list, u32 *len);
/**
* This function retrieves Bootloader temporary stack buffer and size.
*
* @hob_list: A HOB list pointer.
* @len: A pointer to the bootloader temporary stack length.
* If the HOB is located, the length will be updated.
*
* @retval NULL: Failed to find the bootloader temporary stack HOB.
* @retval others: Bootloader temporary stackbuffer pointer.
*/
void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
/**
* This function overrides the default configurations of FSP.
*
* @config: A pointer to the FSP configuration data structure
* @rt_buf: A pointer to the FSP runtime buffer data structure
*
* @return: None
*/
void update_fsp_configs(struct fsp_config_data *config,
struct fspinit_rtbuf *rt_buf);
/**
* fsp_init_phase_pci() - Tell the FSP that we have completed PCI init
*
* @return 0 if OK, -EPERM if the FSP gave an error.
*/
int fsp_init_phase_pci(void);
#endif

71
u-boot/arch/x86/include/asm/fsp/fsp_types.h Normal file
View File

@@ -0,0 +1,71 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: Intel
*/
#ifndef __FSP_TYPES_H__
#define __FSP_TYPES_H__
/* 128 bit buffer containing a unique identifier value */
struct efi_guid {
u32 data1;
u16 data2;
u16 data3;
u8 data4[8];
};
/**
* Returns a 16-bit signature built from 2 ASCII characters.
*
* This macro returns a 16-bit value built from the two ASCII characters
* specified by A and B.
*
* @A: The first ASCII character.
* @B: The second ASCII character.
*
* @return: A 16-bit value built from the two ASCII characters specified by
* A and B.
*/
#define SIGNATURE_16(A, B) ((A) | (B << 8))
/**
* Returns a 32-bit signature built from 4 ASCII characters.
*
* This macro returns a 32-bit value built from the four ASCII characters
* specified by A, B, C, and D.
*
* @A: The first ASCII character.
* @B: The second ASCII character.
* @C: The third ASCII character.
* @D: The fourth ASCII character.
*
* @return: A 32-bit value built from the two ASCII characters specified by
* A, B, C and D.
*/
#define SIGNATURE_32(A, B, C, D) \
(SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
/**
* Returns a 64-bit signature built from 8 ASCII characters.
*
* This macro returns a 64-bit value built from the eight ASCII characters
* specified by A, B, C, D, E, F, G,and H.
*
* @A: The first ASCII character.
* @B: The second ASCII character.
* @C: The third ASCII character.
* @D: The fourth ASCII character.
* @E: The fifth ASCII character.
* @F: The sixth ASCII character.
* @G: The seventh ASCII character.
* @H: The eighth ASCII character.
*
* @return: A 64-bit value built from the two ASCII characters specified by
* A, B, C, D, E, F, G and H.
*/
#define SIGNATURE_64(A, B, C, D, E, F, G, H) \
(SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
#endif

135
u-boot/arch/x86/include/asm/global_data.h Normal file
View File

@@ -0,0 +1,135 @@
/*
* (C) Copyright 2002-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
#ifndef __ASSEMBLY__
#include <asm/processor.h>
enum pei_boot_mode_t {
PEI_BOOT_NONE = 0,
PEI_BOOT_SOFT_RESET,
PEI_BOOT_RESUME,
};
struct dimm_info {
uint32_t dimm_size;
uint16_t ddr_type;
uint16_t ddr_frequency;
uint8_t rank_per_dimm;
uint8_t channel_num;
uint8_t dimm_num;
uint8_t bank_locator;
/* The 5th byte is '\0' for the end of string */
uint8_t serial[5];
/* The 19th byte is '\0' for the end of string */
uint8_t module_part_number[19];
uint16_t mod_id;
uint8_t mod_type;
uint8_t bus_width;
} __packed;
struct pei_memory_info {
uint8_t dimm_cnt;
/* Maximum num of dimm is 8 */
struct dimm_info dimm[8];
} __packed;
struct memory_area {
uint64_t start;
uint64_t size;
};
struct memory_info {
int num_areas;
uint64_t total_memory;
uint64_t total_32bit_memory;
struct memory_area area[CONFIG_NR_DRAM_BANKS];
};
#define MAX_MTRR_REQUESTS 8
/**
* A request for a memory region to be set up in a particular way. These
* requests are processed before board_init_r() is called. They are generally
* optional and can be ignored with some performance impact.
*/
struct mtrr_request {
int type; /* MTRR_TYPE_... */
uint64_t start;
uint64_t size;
};
/* Architecture-specific global data */
struct arch_global_data {
u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16);
struct global_data *gd_addr; /* Location of Global Data */
uint8_t x86; /* CPU family */
uint8_t x86_vendor; /* CPU vendor */
uint8_t x86_model;
uint8_t x86_mask;
uint32_t x86_device;
uint64_t tsc_base; /* Initial value returned by rdtsc() */
void *new_fdt; /* Relocated FDT */
uint32_t bist; /* Built-in self test value */
enum pei_boot_mode_t pei_boot_mode;
const struct pch_gpio_map *gpio_map; /* board GPIO map */
struct memory_info meminfo; /* Memory information */
struct pei_memory_info pei_meminfo; /* PEI memory information */
#ifdef CONFIG_HAVE_FSP
void *hob_list; /* FSP HOB list */
#endif
struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
int mtrr_req_count;
int has_mtrr;
/* MRC training data to save for the next boot */
char *mrc_output;
unsigned int mrc_output_len;
ulong table; /* Table pointer from previous loader */
#ifdef CONFIG_SEABIOS
u32 high_table_ptr;
u32 high_table_limit;
#endif
};
#endif
#include <asm-generic/global_data.h>
#ifndef __ASSEMBLY__
# ifdef CONFIG_EFI_APP
#define gd global_data_ptr
#define DECLARE_GLOBAL_DATA_PTR extern struct global_data *global_data_ptr
# else
static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void)
{
gd_t *gd_ptr;
asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
return gd_ptr;
}
#define gd get_fs_gd_ptr()
#define DECLARE_GLOBAL_DATA_PTR
# endif
#endif
/*
* Our private Global Data Flags
*/
#define GD_FLG_COLD_BOOT 0x10000 /* Cold Boot */
#define GD_FLG_WARM_BOOT 0x20000 /* Warm Boot */
#endif /* __ASM_GBL_DATA_H */

17
u-boot/arch/x86/include/asm/gpio.h Normal file
View File

@@ -0,0 +1,17 @@
/*
* Copyright (c) 2012, Google Inc. All rights reserved.
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _X86_GPIO_H_
#define _X86_GPIO_H_
#include <asm-generic/gpio.h>
struct ich6_bank_platdata {
uint16_t base_addr;
const char *bank_name;
int offset;
};
#endif /* _X86_GPIO_H_ */

39
u-boot/arch/x86/include/asm/i8254.h Normal file
View File

@@ -0,0 +1,39 @@
/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* i8254.h Intel 8254 PIT registers */
#ifndef _ASMI386_I8254_H_
#define _ASMI386_I8954_H_
#define PIT_T0 0x00 /* PIT channel 0 count/status */
#define PIT_T1 0x01 /* PIT channel 1 count/status */
#define PIT_T2 0x02 /* PIT channel 2 count/status */
#define PIT_COMMAND 0x03 /* PIT mode control, latch and read back */
/* PIT Command Register Bit Definitions */
#define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */
#define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */
#define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */
#define PIT_CMD_LATCH 0x00 /* Counter Latch Command */
#define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */
#define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */
#define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */
#define PIT_CMD_MODE0 0x00 /* Select mode 0 */
#define PIT_CMD_MODE1 0x02 /* Select mode 1 */
#define PIT_CMD_MODE2 0x04 /* Select mode 2 */
#define PIT_CMD_MODE3 0x06 /* Select mode 3 */
#define PIT_CMD_MODE4 0x08 /* Select mode 4 */
#define PIT_CMD_MODE5 0x0a /* Select mode 5 */
/* The clock frequency of the i8253/i8254 PIT */
#define PIT_TICK_RATE 1193182
#endif /* _ASMI386_I8954_H_ */

77
u-boot/arch/x86/include/asm/i8259.h Normal file
View File

@@ -0,0 +1,77 @@
/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* i8259.h i8259 PIC Registers */
#ifndef _ASMI386_I8259_H_
#define _ASMI386_I8959_H_
/* PIC I/O mapped registers */
#define IRR 0x0 /* Interrupt Request Register */
#define ISR 0x0 /* In-Service Register */
#define ICW1 0x0 /* Initialization Control Word 1 */
#define OCW2 0x0 /* Operation Control Word 2 */
#define OCW3 0x0 /* Operation Control Word 3 */
#define ICW2 0x1 /* Initialization Control Word 2 */
#define ICW3 0x1 /* Initialization Control Word 3 */
#define ICW4 0x1 /* Initialization Control Word 4 */
#define IMR 0x1 /* Interrupt Mask Register */
/* IRR, IMR, ISR and ICW3 bits */
#define IR7 0x80 /* IR7 */
#define IR6 0x40 /* IR6 */
#define IR5 0x20 /* IR5 */
#define IR4 0x10 /* IR4 */
#define IR3 0x08 /* IR3 */
#define IR2 0x04 /* IR2 */
#define IR1 0x02 /* IR1 */
#define IR0 0x01 /* IR0 */
/* SEOI bits */
#define SEOI_IR7 0x07 /* IR7 */
#define SEOI_IR6 0x06 /* IR6 */
#define SEOI_IR5 0x05 /* IR5 */
#define SEOI_IR4 0x04 /* IR4 */
#define SEOI_IR3 0x03 /* IR3 */
#define SEOI_IR2 0x02 /* IR2 */
#define SEOI_IR1 0x01 /* IR1 */
#define SEOI_IR0 0x00 /* IR0 */
/* OCW2 bits */
#define OCW2_RCLR 0x00 /* Rotate/clear */
#define OCW2_NEOI 0x20 /* Non specific EOI */
#define OCW2_NOP 0x40 /* NOP */
#define OCW2_SEOI 0x60 /* Specific EOI */
#define OCW2_RSET 0x80 /* Rotate/set */
#define OCW2_REOI 0xa0 /* Rotate on non specific EOI */
#define OCW2_PSET 0xc0 /* Priority Set Command */
#define OCW2_RSEOI 0xe0 /* Rotate on specific EOI */
/* ICW1 bits */
#define ICW1_SEL 0x10 /* Select ICW1 */
#define ICW1_LTIM 0x08 /* Level-Triggered Interrupt Mode */
#define ICW1_ADI 0x04 /* Address Interval */
#define ICW1_SNGL 0x02 /* Single PIC */
#define ICW1_EICW4 0x01 /* Expect initilization ICW4 */
/*
* ICW2 is the starting vector number
*
* ICW2 is bit-mask of present slaves for a master device,
* or the slave ID for a slave device
*/
/* ICW4 bits */
#define ICW4_AEOI 0x02 /* Automatic EOI Mode */
#define ICW4_PM 0x01 /* Microprocessor Mode */
#define ELCR1 0x4d0
#define ELCR2 0x4d1
int i8259_init(void);
#endif /* _ASMI386_I8959_H_ */

30
u-boot/arch/x86/include/asm/ibmpc.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_IBMPC_H_
#define __ASM_IBMPC_H_ 1
/* misc ports in an ibm compatible pc */
#define MASTER_PIC 0x20
#define PIT_BASE 0x40
#define KBDDATA 0x60
#define SYSCTLB 0x62
#define KBDCMD 0x64
#define SYSCTLA 0x92
#define SLAVE_PIC 0xa0
#define UART0_BASE 0x3f8
#define UART1_BASE 0x2f8
#define UART0_IRQ 4
#define UART1_IRQ 3
#define KBD_IRQ 1
#define MSE_IRQ 12
#endif

15
u-boot/arch/x86/include/asm/init_helpers.h Normal file
View File

@@ -0,0 +1,15 @@
/*
* (C) Copyright 2011
* Graeme Russ, <graeme.russ@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _INIT_HELPERS_H_
#define _INIT_HELPERS_H_
int init_cache_f_r(void);
int init_bd_struct_r(void);
int init_func_spi(void);
#endif /* !_INIT_HELPERS_H_ */

28
u-boot/arch/x86/include/asm/intel_regs.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* Copyright (c) 2016 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_INTEL_REGS_H
#define __ASM_INTEL_REGS_H
/* Access the memory-controller hub */
#define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE 0x8000
#define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg))
#define MCHBAR_PEI_VERSION 0x5034
#define MCH_PKG_POWER_LIMIT_LO 0x59a0
#define MCH_PKG_POWER_LIMIT_HI 0x59a4
#define MCH_DDR_POWER_LIMIT_LO 0x58e0
#define MCH_DDR_POWER_LIMIT_HI 0x58e4
/* Access the Root Complex Register Block */
#define RCB_BASE_ADDRESS 0xfed1c000
#define RCB_REG(reg) (RCB_BASE_ADDRESS + (reg))
#define SOFT_RESET_CTRL 0x38f4
#define SOFT_RESET_DATA 0x38f8
#endif

65
u-boot/arch/x86/include/asm/interrupt.h Normal file
View File

@@ -0,0 +1,65 @@
/*
* (C) Copyright 2009
* Graeme Russ, graeme.russ@gmail.com
*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_INTERRUPT_H_
#define __ASM_INTERRUPT_H_ 1
#include <asm/types.h>
#define SYS_NUM_IRQS 16
/* Architecture defined exceptions */
enum x86_exception {
EXC_DE = 0,
EXC_DB,
EXC_NMI,
EXC_BP,
EXC_OF,
EXC_BR,
EXC_UD,
EXC_NM,
EXC_DF,
EXC_CSO,
EXC_TS,
EXC_NP,
EXC_SS,
EXC_GP,
EXC_PF,
EXC_MF = 16,
EXC_AC,
EXC_MC,
EXC_XM,
EXC_VE
};
/* arch/x86/cpu/interrupts.c */
void set_vector(u8 intnum, void *routine);
/* Architecture specific functions */
void mask_irq(int irq);
void unmask_irq(int irq);
void specific_eoi(int irq);
extern char exception_stack[];
/**
* configure_irq_trigger() - Configure IRQ triggering
*
* Switch the given interrupt to be level / edge triggered
*
* @param int_num legacy interrupt number (3-7, 9-15)
* @param is_level_triggered true for level triggered interrupt, false for
* edge triggered interrupt
*/
void configure_irq_trigger(int int_num, bool is_level_triggered);
void *x86_get_idt(void);
#endif

328
u-boot/arch/x86/include/asm/io.h Normal file
View File

@@ -0,0 +1,328 @@
#ifndef _ASM_IO_H
#define _ASM_IO_H
#include <linux/compiler.h>
/*
* This file contains the definitions for the x86 IO instructions
* inb/inw/inl/outb/outw/outl and the "string versions" of the same
* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
* versions of the single-IO instructions (inb_p/inw_p/..).
*
* This file is not meant to be obfuscating: it's just complicated
* to (a) handle it all in a way that makes gcc able to optimize it
* as well as possible and (b) trying to avoid writing the same thing
* over and over again with slight variations and possibly making a
* mistake somewhere.
*/
/*
* Thanks to James van Artsdalen for a better timing-fix than
* the two short jumps: using outb's to a nonexistent port seems
* to guarantee better timings even on fast machines.
*
* On the other hand, I'd like to be sure of a non-existent port:
* I feel a bit unsafe about using 0x80 (should be safe, though)
*
* Linus
*/
/*
* Bit simplified and optimized by Jan Hubicka
* Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
*
* isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
* isa_read[wl] and isa_write[wl] fixed
* - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
*/
#define IO_SPACE_LIMIT 0xffff
#include <asm/types.h>
#ifdef __KERNEL__
/*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the x86 architecture, we just read/write the
* memory location directly.
*/
#define readb(addr) (*(volatile unsigned char *) (addr))
#define readw(addr) (*(volatile unsigned short *) (addr))
#define readl(addr) (*(volatile unsigned int *) (addr))
#define __raw_readb readb
#define __raw_readw readw
#define __raw_readl readl
#define writeb(b,addr) (*(volatile unsigned char *) (addr) = (b))
#define writew(b,addr) (*(volatile unsigned short *) (addr) = (b))
#define writel(b,addr) (*(volatile unsigned int *) (addr) = (b))
#define __raw_writeb writeb
#define __raw_writew writew
#define __raw_writel writel
#define memset_io(a,b,c) memset((a),(b),(c))
#define memcpy_fromio(a,b,c) memcpy((a),(b),(c))
#define memcpy_toio(a,b,c) memcpy((a),(b),(c))
#define write_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
#define read_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
#define write_le64(a, v) write_arch(q, le64, a, v)
#define write_le32(a, v) write_arch(l, le32, a, v)
#define write_le16(a, v) write_arch(w, le16, a, v)
#define read_le64(a) read_arch(q, le64, a)
#define read_le32(a) read_arch(l, le32, a)
#define read_le16(a) read_arch(w, le16, a)
#define write_be32(a, v) write_arch(l, be32, a, v)
#define write_be16(a, v) write_arch(w, be16, a, v)
#define read_be32(a) read_arch(l, be32, a)
#define read_be16(a) read_arch(w, be16, a)
#define write_8(a, v) __raw_writeb(v, a)
#define read_8(a) __raw_readb(a)
#define clrbits(type, addr, clear) \
write_##type((addr), read_##type(addr) & ~(clear))
#define setbits(type, addr, set) \
write_##type((addr), read_##type(addr) | (set))
#define clrsetbits(type, addr, clear, set) \
write_##type((addr), (read_##type(addr) & ~(clear)) | (set))
#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
#define setbits_be32(addr, set) setbits(be32, addr, set)
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
#define setbits_le32(addr, set) setbits(le32, addr, set)
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
#define setbits_be16(addr, set) setbits(be16, addr, set)
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
#define setbits_le16(addr, set) setbits(le16, addr, set)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrbits_8(addr, clear) clrbits(8, addr, clear)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
/*
* ISA space is 'always mapped' on a typical x86 system, no need to
* explicitly ioremap() it. The fact that the ISA IO space is mapped
* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
* are physical addresses. The following constant pointer can be
* used as the IO-area pointer (it can be iounmapped as well, so the
* analogy with PCI is quite large):
*/
#define isa_readb(a) readb((a))
#define isa_readw(a) readw((a))
#define isa_readl(a) readl((a))
#define isa_writeb(b,a) writeb(b,(a))
#define isa_writew(w,a) writew(w,(a))
#define isa_writel(l,a) writel(l,(a))
#define isa_memset_io(a,b,c) memset_io((a),(b),(c))
#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c))
static inline int check_signature(unsigned long io_addr,
const unsigned char *signature, int length)
{
int retval = 0;
do {
if (readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
/**
* isa_check_signature - find BIOS signatures
* @io_addr: mmio address to check
* @signature: signature block
* @length: length of signature
*
* Perform a signature comparison with the ISA mmio address io_addr.
* Returns 1 on a match.
*
* This function is deprecated. New drivers should use ioremap and
* check_signature.
*/
static inline int isa_check_signature(unsigned long io_addr,
const unsigned char *signature, int length)
{
int retval = 0;
do {
if (isa_readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
#endif /* __KERNEL__ */
#ifdef SLOW_IO_BY_JUMPING
#define __SLOW_DOWN_IO "\njmp 1f\n1:\tjmp 1f\n1:"
#else
#define __SLOW_DOWN_IO "\noutb %%al,$0xed"
#endif
#ifdef REALLY_SLOW_IO
#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO
#else
#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO
#endif
/*
* Talk about misusing macros..
*/
#define __OUT1(s,x) \
static inline void _out##s(unsigned x value, unsigned short port) {
#define __OUT2(s,s1,s2) \
__asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
#define __OUT(s,s1,x) \
__OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \
__OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));}
#define __IN1(s) \
static inline RETURN_TYPE _in##s(unsigned short port) { RETURN_TYPE _v;
#define __IN2(s,s1,s2) \
__asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
#define __IN(s,s1,i...) \
__IN1(s) __IN2(s,s1,"w") : "=a" (_v) : "Nd" (port) ,##i ); return _v; } \
__IN1(s##_p) __IN2(s,s1,"w") __FULL_SLOW_DOWN_IO : "=a" (_v) : "Nd" (port) ,##i ); return _v; }
#define __INS(s) \
static inline void ins##s(unsigned short port, void * addr, unsigned long count) \
{ __asm__ __volatile__ ("rep ; ins" #s \
: "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
#define __OUTS(s) \
static inline void outs##s(unsigned short port, const void * addr, unsigned long count) \
{ __asm__ __volatile__ ("rep ; outs" #s \
: "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
#define RETURN_TYPE unsigned char
__IN(b,"")
#undef RETURN_TYPE
#define RETURN_TYPE unsigned short
__IN(w,"")
#undef RETURN_TYPE
#define RETURN_TYPE unsigned int
__IN(l,"")
#undef RETURN_TYPE
#define inb(port) _inb((uintptr_t)(port))
#define inw(port) _inw((uintptr_t)(port))
#define inl(port) _inl((uintptr_t)(port))
__OUT(b,"b",char)
__OUT(w,"w",short)
__OUT(l,,int)
#define outb(val, port) _outb(val, (uintptr_t)(port))
#define outw(val, port) _outw(val, (uintptr_t)(port))
#define outl(val, port) _outl(val, (uintptr_t)(port))
__INS(b)
__INS(w)
__INS(l)
__OUTS(b)
__OUTS(w)
__OUTS(l)
/* IO space accessors */
#define clrio(type, addr, clear) \
out##type(in##type(addr) & ~(clear), (addr))
#define setio(type, addr, set) \
out##type(in##type(addr) | (set), (addr))
#define clrsetio(type, addr, clear, set) \
out##type((in##type(addr) & ~(clear)) | (set), (addr))
#define clrio_32(addr, clear) clrio(l, addr, clear)
#define clrio_16(addr, clear) clrio(w, addr, clear)
#define clrio_8(addr, clear) clrio(b, addr, clear)
#define setio_32(addr, set) setio(l, addr, set)
#define setio_16(addr, set) setio(w, addr, set)
#define setio_8(addr, set) setio(b, addr, set)
#define clrsetio_32(addr, clear, set) clrsetio(l, addr, clear, set)
#define clrsetio_16(addr, clear, set) clrsetio(w, addr, clear, set)
#define clrsetio_8(addr, clear, set) clrsetio(b, addr, clear, set)
static inline void sync(void)
{
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)(uintptr_t)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
static inline phys_addr_t virt_to_phys(void * vaddr)
{
return (phys_addr_t)(uintptr_t)(vaddr);
}
/*
* TODO: The kernel offers some more advanced versions of barriers, it might
* have some advantages to use them instead of the simple one here.
*/
#define dmb() __asm__ __volatile__ ("" : : : "memory")
#define __iormb() dmb()
#define __iowmb() dmb()
#endif

44
u-boot/arch/x86/include/asm/ioapic.h Normal file
View File

@@ -0,0 +1,44 @@
/*
* From coreboot file of the same name
*
* Copyright (C) 2010 coresystems GmbH
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_IOAPIC_H
#define __ASM_IOAPIC_H
#define IO_APIC_ADDR 0xfec00000
/* Direct addressed register */
#define IO_APIC_INDEX (IO_APIC_ADDR + 0x00)
#define IO_APIC_DATA (IO_APIC_ADDR + 0x10)
/* Indirect addressed register offset */
#define IO_APIC_ID 0x00
#define IO_APIC_VER 0x01
/**
* io_apic_read() - Read I/O APIC register
*
* This routine reads I/O APIC indirect addressed register.
*
* @reg: address of indirect addressed register
* @return: register value to read
*/
u32 io_apic_read(u32 reg);
/**
* io_apic_write() - Write I/O APIC register
*
* This routine writes I/O APIC indirect addressed register.
*
* @reg: address of indirect addressed register
* @val: register value to write
*/
void io_apic_write(u32 reg, u32 val);
void io_apic_set_id(int ioapic_id);
#endif

1
u-boot/arch/x86/include/asm/ioctl.h Normal file
View File

@@ -0,0 +1 @@
#include <asm-generic/ioctl.h>

69
u-boot/arch/x86/include/asm/irq.h Normal file
View File

@@ -0,0 +1,69 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ARCH_IRQ_H_
#define _ARCH_IRQ_H_
#include <dt-bindings/interrupt-router/intel-irq.h>
/**
* Intel interrupt router configuration mechanism
*
* There are two known ways of Intel interrupt router configuration mechanism
* so far. On most cases, the IRQ routing configuraiton is controlled by PCI
* configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
* On some newer platforms like BayTrail and Braswell, the IRQ routing is now
* in the IBASE register block where IBASE is memory-mapped.
*/
enum pirq_config {
PIRQ_VIA_PCI,
PIRQ_VIA_IBASE
};
/**
* Intel interrupt router control block
*
* Its members' value will be filled in based on device tree's input.
*
* @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE
* @link_base: link value base number
* @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
* IRQ N is available to be routed
* @lb_bdf: irq router's PCI bus/device/function number encoding
* @ibase: IBASE register block base address
* @actl_8bit: ACTL register width is 8-bit (for ICH series chipset)
* @actl_addr: ACTL register offset
*/
struct irq_router {
int config;
u32 link_base;
u16 irq_mask;
u32 bdf;
u32 ibase;
bool actl_8bit;
int actl_addr;
};
struct pirq_routing {
int bdf;
int pin;
int pirq;
};
/* PIRQ link number and value conversion */
#define LINK_V2N(link, base) (link - base)
#define LINK_N2V(link, base) (link + base)
#define PIRQ_BITMAP 0xdef8
/**
* irq_router_common_init() - Perform common x86 interrupt init
*
* This creates the PIRQ routing table and routes the IRQs
*/
int irq_router_common_init(struct udevice *dev);
#endif /* _ARCH_IRQ_H_ */

26
u-boot/arch/x86/include/asm/ist.h Normal file
View File

@@ -0,0 +1,26 @@
#ifndef _ASM_X86_IST_H
#define _ASM_X86_IST_H
/*
* Include file for the interface to IST BIOS
* Copyright 2002 Andy Grover <andrew.grover@intel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/types.h>
struct ist_info {
__u32 signature;
__u32 command;
__u32 event;
__u32 perf_level;
};
#ifdef __KERNEL__
extern struct ist_info ist_info;
#endif /* __KERNEL__ */
#endif /* _ASM_X86_IST_H */

78
u-boot/arch/x86/include/asm/lapic.h Normal file
View File

@@ -0,0 +1,78 @@
/*
* From coreboot file of same name
*
* Copyright (C) 2014 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ARCH_ASM_LAPIC_H
#define _ARCH_ASM_LAPIC_H
#define LAPIC_DEFAULT_BASE 0xfee00000
#define LAPIC_ID 0x020
#define LAPIC_LVR 0x030
#define LAPIC_TASKPRI 0x080
#define LAPIC_TPRI_MASK 0xff
#define LAPIC_RRR 0x0c0
#define LAPIC_SPIV 0x0f0
#define LAPIC_SPIV_ENABLE 0x100
#define LAPIC_ICR 0x300
#define LAPIC_DEST_SELF 0x40000
#define LAPIC_DEST_ALLINC 0x80000
#define LAPIC_DEST_ALLBUT 0xc0000
#define LAPIC_ICR_RR_MASK 0x30000
#define LAPIC_ICR_RR_INVALID 0x00000
#define LAPIC_ICR_RR_INPROG 0x10000
#define LAPIC_ICR_RR_VALID 0x20000
#define LAPIC_INT_LEVELTRIG 0x08000
#define LAPIC_INT_ASSERT 0x04000
#define LAPIC_ICR_BUSY 0x01000
#define LAPIC_DEST_LOGICAL 0x00800
#define LAPIC_DM_FIXED 0x00000
#define LAPIC_DM_LOWEST 0x00100
#define LAPIC_DM_SMI 0x00200
#define LAPIC_DM_REMRD 0x00300
#define LAPIC_DM_NMI 0x00400
#define LAPIC_DM_INIT 0x00500
#define LAPIC_DM_STARTUP 0x00600
#define LAPIC_DM_EXTINT 0x00700
#define LAPIC_VECTOR_MASK 0x000ff
#define LAPIC_ICR2 0x310
#define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xff)
#define SET_LAPIC_DEST_FIELD(x) ((x) << 24)
#define LAPIC_LVT0 0x350
#define LAPIC_LVT1 0x360
#define LAPIC_LVT_MASKED (1 << 16)
#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15)
#define LAPIC_LVT_REMOTE_IRR (1 << 14)
#define LAPIC_INPUT_POLARITY (1 << 13)
#define LAPIC_SEND_PENDING (1 << 12)
#define LAPIC_LVT_RESERVED_1 (1 << 11)
#define LAPIC_DELIVERY_MODE_MASK (7 << 8)
#define LAPIC_DELIVERY_MODE_FIXED (0 << 8)
#define LAPIC_DELIVERY_MODE_NMI (4 << 8)
#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8)
unsigned long lapic_read(unsigned long reg);
void lapic_write(unsigned long reg, unsigned long v);
void enable_lapic(void);
void disable_lapic(void);
unsigned long lapicid(void);
int lapic_remote_read(int apicid, int reg, unsigned long *pvalue);
void lapic_setup(void);
#endif

6
u-boot/arch/x86/include/asm/linkage.h Normal file
View File

@@ -0,0 +1,6 @@
#ifndef _ASM_X86_LINKAGE_H
#define _ASM_X86_LINKAGE_H
#define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0)))
#endif /* _ASM_X86_LINKAGE_H */

59
u-boot/arch/x86/include/asm/lpc_common.h Normal file
View File

@@ -0,0 +1,59 @@
/*
* Copyright (c) 2016 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_LPC_COMMON_H
#define __ASM_LPC_COMMON_H
#define PCH_RCBA_BASE 0xf0
#define RC 0x3400 /* 32bit */
#define GCS 0x3410 /* 32bit */
#define PMBASE 0x40
#define ACPI_CNTL 0x44
#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */
#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */
#define LPC_EN 0x82 /* LPC IF Enables Register */
#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */
#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */
#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */
#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */
#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */
#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */
#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */
#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */
/**
* lpc_common_early_init() - Set up common LPC init
*
* This sets up the legacy decode areas, GEN_DEC, SPI prefetch and Port80. It
* also puts the RCB in the correct place so that RCB_REG() works.
*
* @dev: LPC device (a child of the PCH)
* @return 0 on success, -ve on error
*/
int lpc_common_early_init(struct udevice *dev);
int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect);
#endif

373
u-boot/arch/x86/include/asm/me_common.h Normal file
View File

@@ -0,0 +1,373 @@
/*
* From Coreboot src/southbridge/intel/bd82x6x/me.h
*
* Coreboot copies lots of code around. Here we are trying to keep the common
* code in a separate file to reduce code duplication and hopefully make it
* easier to add new platform.
*
* Copyright (C) 2016 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ME_COMMON_H
#define __ASM_ME_COMMON_H
#include <linux/compiler.h>
#include <linux/types.h>
#include <pci.h>
#define MCHBAR_PEI_VERSION 0x5034
#define ME_RETRY 100000 /* 1 second */
#define ME_DELAY 10 /* 10 us */
/*
* Management Engine PCI registers
*/
#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */
#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
#define PCI_ME_HFS 0x40
#define ME_HFS_CWS_RESET 0
#define ME_HFS_CWS_INIT 1
#define ME_HFS_CWS_REC 2
#define ME_HFS_CWS_NORMAL 5
#define ME_HFS_CWS_WAIT 6
#define ME_HFS_CWS_TRANS 7
#define ME_HFS_CWS_INVALID 8
#define ME_HFS_STATE_PREBOOT 0
#define ME_HFS_STATE_M0_UMA 1
#define ME_HFS_STATE_M3 4
#define ME_HFS_STATE_M0 5
#define ME_HFS_STATE_BRINGUP 6
#define ME_HFS_STATE_ERROR 7
#define ME_HFS_ERROR_NONE 0
#define ME_HFS_ERROR_UNCAT 1
#define ME_HFS_ERROR_IMAGE 3
#define ME_HFS_ERROR_DEBUG 4
#define ME_HFS_MODE_NORMAL 0
#define ME_HFS_MODE_DEBUG 2
#define ME_HFS_MODE_DIS 3
#define ME_HFS_MODE_OVER_JMPR 4
#define ME_HFS_MODE_OVER_MEI 5
#define ME_HFS_BIOS_DRAM_ACK 1
#define ME_HFS_ACK_NO_DID 0
#define ME_HFS_ACK_RESET 1
#define ME_HFS_ACK_PWR_CYCLE 2
#define ME_HFS_ACK_S3 3
#define ME_HFS_ACK_S4 4
#define ME_HFS_ACK_S5 5
#define ME_HFS_ACK_GBL_RESET 6
#define ME_HFS_ACK_CONTINUE 7
struct me_hfs {
u32 working_state:4;
u32 mfg_mode:1;
u32 fpt_bad:1;
u32 operation_state:3;
u32 fw_init_complete:1;
u32 ft_bup_ld_flr:1;
u32 update_in_progress:1;
u32 error_code:4;
u32 operation_mode:4;
u32 reserved:4;
u32 boot_options_present:1;
u32 ack_data:3;
u32 bios_msg_ack:4;
} __packed;
#define PCI_ME_UMA 0x44
struct me_uma {
u32 size:6;
u32 reserved_1:10;
u32 valid:1;
u32 reserved_0:14;
u32 set_to_one:1;
} __packed;
#define PCI_ME_H_GS 0x4c
#define ME_INIT_DONE 1
#define ME_INIT_STATUS_SUCCESS 0
#define ME_INIT_STATUS_NOMEM 1
#define ME_INIT_STATUS_ERROR 2
struct me_did {
u32 uma_base:16;
u32 reserved:7;
u32 rapid_start:1; /* Broadwell only */
u32 status:4;
u32 init_done:4;
} __packed;
#define PCI_ME_GMES 0x48
#define ME_GMES_PHASE_ROM 0
#define ME_GMES_PHASE_BUP 1
#define ME_GMES_PHASE_UKERNEL 2
#define ME_GMES_PHASE_POLICY 3
#define ME_GMES_PHASE_MODULE 4
#define ME_GMES_PHASE_UNKNOWN 5
#define ME_GMES_PHASE_HOST 6
struct me_gmes {
u32 bist_in_prog:1;
u32 icc_prog_sts:2;
u32 invoke_mebx:1;
u32 cpu_replaced_sts:1;
u32 mbp_rdy:1;
u32 mfs_failure:1;
u32 warm_rst_req_for_df:1;
u32 cpu_replaced_valid:1;
u32 reserved_1:2;
u32 fw_upd_ipu:1;
u32 reserved_2:4;
u32 current_state:8;
u32 current_pmevent:4;
u32 progress_code:4;
} __packed;
#define PCI_ME_HERES 0xbc
#define PCI_ME_EXT_SHA1 0x00
#define PCI_ME_EXT_SHA256 0x02
#define PCI_ME_HER(x) (0xc0+(4*(x)))
struct me_heres {
u32 extend_reg_algorithm:4;
u32 reserved:26;
u32 extend_feature_present:1;
u32 extend_reg_valid:1;
} __packed;
/*
* Management Engine MEI registers
*/
#define MEI_H_CB_WW 0x00
#define MEI_H_CSR 0x04
#define MEI_ME_CB_RW 0x08
#define MEI_ME_CSR_HA 0x0c
struct mei_csr {
u32 interrupt_enable:1;
u32 interrupt_status:1;
u32 interrupt_generate:1;
u32 ready:1;
u32 reset:1;
u32 reserved:3;
u32 buffer_read_ptr:8;
u32 buffer_write_ptr:8;
u32 buffer_depth:8;
} __packed;
#define MEI_ADDRESS_CORE 0x01
#define MEI_ADDRESS_AMT 0x02
#define MEI_ADDRESS_RESERVED 0x03
#define MEI_ADDRESS_WDT 0x04
#define MEI_ADDRESS_MKHI 0x07
#define MEI_ADDRESS_ICC 0x08
#define MEI_ADDRESS_THERMAL 0x09
#define MEI_HOST_ADDRESS 0
struct mei_header {
u32 client_address:8;
u32 host_address:8;
u32 length:9;
u32 reserved:6;
u32 is_complete:1;
} __packed;
#define MKHI_GROUP_ID_CBM 0x00
#define MKHI_GROUP_ID_FWCAPS 0x03
#define MKHI_GROUP_ID_MDES 0x08
#define MKHI_GROUP_ID_GEN 0xff
#define MKHI_GET_FW_VERSION 0x02
#define MKHI_END_OF_POST 0x0c
#define MKHI_FEATURE_OVERRIDE 0x14
/* Ivybridge only: */
#define MKHI_GLOBAL_RESET 0x0b
#define MKHI_FWCAPS_GET_RULE 0x02
#define MKHI_MDES_ENABLE 0x09
/* Broadwell only: */
#define MKHI_GLOBAL_RESET 0x0b
#define MKHI_FWCAPS_GET_RULE 0x02
#define MKHI_GROUP_ID_HMRFPO 0x05
#define MKHI_HMRFPO_LOCK 0x02
#define MKHI_HMRFPO_LOCK_NOACK 0x05
#define MKHI_MDES_ENABLE 0x09
#define MKHI_END_OF_POST_NOACK 0x1a
struct mkhi_header {
u32 group_id:8;
u32 command:7;
u32 is_response:1;
u32 reserved:8;
u32 result:8;
} __packed;
struct me_fw_version {
u16 code_minor;
u16 code_major;
u16 code_build_number;
u16 code_hot_fix;
u16 recovery_minor;
u16 recovery_major;
u16 recovery_build_number;
u16 recovery_hot_fix;
} __packed;
#define HECI_EOP_STATUS_SUCCESS 0x0
#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
#define CBM_RR_GLOBAL_RESET 0x01
#define GLOBAL_RESET_BIOS_MRC 0x01
#define GLOBAL_RESET_BIOS_POST 0x02
#define GLOBAL_RESET_MEBX 0x03
struct me_global_reset {
u8 request_origin;
u8 reset_type;
} __packed;
enum me_bios_path {
ME_NORMAL_BIOS_PATH,
ME_S3WAKE_BIOS_PATH,
ME_ERROR_BIOS_PATH,
ME_RECOVERY_BIOS_PATH,
ME_DISABLE_BIOS_PATH,
ME_FIRMWARE_UPDATE_BIOS_PATH,
};
struct __packed mefwcaps_sku {
u32 full_net:1;
u32 std_net:1;
u32 manageability:1;
u32 small_business:1;
u32 l3manageability:1;
u32 intel_at:1;
u32 intel_cls:1;
u32 reserved:3;
u32 intel_mpc:1;
u32 icc_over_clocking:1;
u32 pavp:1;
u32 reserved_1:4;
u32 ipv6:1;
u32 kvm:1;
u32 och:1;
u32 vlan:1;
u32 tls:1;
u32 reserved_4:1;
u32 wlan:1;
u32 reserved_5:8;
};
struct __packed tdt_state_flag {
u16 lock_state:1;
u16 authenticate_module:1;
u16 s3authentication:1;
u16 flash_wear_out:1;
u16 flash_variable_security:1;
u16 wwan3gpresent:1; /* ivybridge only */
u16 wwan3goob:1; /* ivybridge only */
u16 reserved:9;
};
struct __packed tdt_state_info {
u8 state;
u8 last_theft_trigger;
struct tdt_state_flag flags;
};
struct __packed mbp_rom_bist_data {
u16 device_id;
u16 fuse_test_flags;
u32 umchid[4];
};
struct __packed mbp_platform_key {
u32 key[8];
};
struct __packed mbp_header {
u32 mbp_size:8;
u32 num_entries:8;
u32 rsvd:16;
};
struct __packed mbp_item_header {
u32 app_id:8;
u32 item_id:8;
u32 length:8;
u32 rsvd:8;
};
struct __packed me_fwcaps {
u32 id;
u8 length;
struct mefwcaps_sku caps_sku;
u8 reserved[3];
};
/**
* intel_me_status() - Check Intel Management Engine status
*
* @me_dev: Management engine PCI device
*/
void intel_me_status(struct udevice *me_dev);
/**
* intel_early_me_init() - Early Intel Management Engine init
*
* @me_dev: Management engine PCI device
* @return 0 if OK, -ve on error
*/
int intel_early_me_init(struct udevice *me_dev);
/**
* intel_early_me_uma_size() - Get UMA size from the Intel Management Engine
*
* @me_dev: Management engine PCI device
* @return UMA size if OK, -EINVAL on error
*/
int intel_early_me_uma_size(struct udevice *me_dev);
/**
* intel_early_me_init_done() - Complete Intel Management Engine init
*
* @dev: Northbridge device
* @me_dev: Management engine PCI device
* @status: Status result (ME_INIT_...)
* @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT
* if ME did not respond
*/
int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
uint status);
int intel_me_hsio_version(struct udevice *dev, uint16_t *version,
uint16_t *checksum);
static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
int offset)
{
u32 dword;
dm_pci_read_config32(me_dev, offset, &dword);
memcpy(ptr, &dword, sizeof(dword));
}
static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
dm_pci_write_config32(me_dev, offset, dword);
}
#endif

35
u-boot/arch/x86/include/asm/microcode.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* Copyright (c) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MICROCODE_H
#define __ASM_ARCH_MICROCODE_H
#ifndef __ASSEMBLY__
/* This is a declaration for ucode_base in start.S */
extern u32 ucode_base;
/**
* microcode_update_intel() - Apply microcode updates
*
* Applies any microcode updates in the device tree.
*
* @return 0 if OK, -EEXIST if the updates were already applied, -ENOENT if
* not updates were found, -EINVAL if an update was invalid
*/
int microcode_update_intel(void);
/**
* microcode_read_rev() - Read the microcode version
*
* This reads the microcode version of the currently running CPU
*
* @return microcode version number
*/
int microcode_read_rev(void);
#endif /* __ASSEMBLY__ */
#endif

93
u-boot/arch/x86/include/asm/mp.h Normal file
View File

@@ -0,0 +1,93 @@
/*
* Copyright (c) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*
* Taken from coreboot file of the same name
*/
#ifndef _X86_MP_H_
#define _X86_MP_H_
#include <asm/atomic.h>
typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);
/*
* A mp_flight_record details a sequence of calls for the APs to perform
* along with the BSP to coordinate sequencing. Each flight record either
* provides a barrier for each AP before calling the callback or the APs
* are allowed to perform the callback without waiting. Regardless, each
* record has the cpus_entered field incremented for each record. When
* the BSP observes that the cpus_entered matches the number of APs
* the bsp_call is called with bsp_arg and upon returning releases the
* barrier allowing the APs to make further progress.
*
* Note that ap_call() and bsp_call() can be NULL. In the NULL case the
* callback will just not be called.
*/
struct mp_flight_record {
atomic_t barrier;
atomic_t cpus_entered;
mp_callback_t ap_call;
void *ap_arg;
mp_callback_t bsp_call;
void *bsp_arg;
} __attribute__((aligned(ARCH_DMA_MINALIGN)));
#define MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
{ \
.barrier = ATOMIC_INIT(barrier_), \
.cpus_entered = ATOMIC_INIT(0), \
.ap_call = ap_func_, \
.ap_arg = ap_arg_, \
.bsp_call = bsp_func_, \
.bsp_arg = bsp_arg_, \
}
#define MP_FR_BLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
MP_FLIGHT_RECORD(0, ap_func, ap_arg, bsp_func, bsp_arg)
#define MP_FR_NOBLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
MP_FLIGHT_RECORD(1, ap_func, ap_arg, bsp_func, bsp_arg)
/*
* The mp_params structure provides the arguments to the mp subsystem
* for bringing up APs.
*
* At present this is overkill for U-Boot, but it may make it easier to add
* SMM support.
*/
struct mp_params {
int parallel_microcode_load;
const void *microcode_pointer;
/* Flight plan for APs and BSP */
struct mp_flight_record *flight_plan;
int num_records;
};
/*
* mp_init() will set up the SIPI vector and bring up the APs according to
* mp_params. Each flight record will be executed according to the plan. Note
* that the MP infrastructure uses SMM default area without saving it. It's
* up to the chipset or mainboard to either e820 reserve this area or save this
* region prior to calling mp_init() and restoring it after mp_init returns.
*
* At the time mp_init() is called the MTRR MSRs are mirrored into APs then
* caching is enabled before running the flight plan.
*
* The MP init has the following properties:
* 1. APs are brought up in parallel.
* 2. The ordering of cpu number and APIC ids is not deterministic.
* Therefore, one cannot rely on this property or the order of devices in
* the device tree unless the chipset or mainboard know the APIC ids
* a priori.
*
* mp_init() returns < 0 on error, 0 on success.
*/
int mp_init(struct mp_params *params);
/* Probes the CPU device */
int mp_init_cpu(struct udevice *cpu, void *unused);
#endif /* _X86_MP_H_ */

Some files were not shown because too many files have changed in this diff Show More