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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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150
u-boot/arch/sh/Kconfig Normal file
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menu "SuperH architecture"
depends on SH
config CPU_SH2
bool
config CPU_SH2A
bool
select CPU_SH2
config CPU_SH3
bool
config CPU_SH4
bool
config CPU_SH4A
bool
select CPU_SH4
config SH_32BIT
bool "32bit mode"
depends on CPU_SH4A
default n
help
SH4A has 2 physical memory maps. This use 32bit mode.
And this is board specific. Please check your board if you
want to use this.
choice
prompt "Target select"
optional
config TARGET_RSK7203
bool "RSK+ 7203"
select CPU_SH2A
config TARGET_RSK7264
bool "RSK2+SH7264"
select CPU_SH2A
config TARGET_RSK7269
bool "RSK2+SH7269"
select CPU_SH2A
config TARGET_MPR2
bool "Magic Panel Release 2 board"
select CPU_SH3
config TARGET_MS7720SE
bool "Support ms7720se"
select CPU_SH3
config TARGET_SHMIN
bool "SHMIN"
select CPU_SH3
config TARGET_ESPT
bool "Data Technology ESPT-GIGA board"
select CPU_SH4
config TARGET_MS7722SE
bool "SolutionEngine 7722"
select CPU_SH4
config TARGET_MS7750SE
bool "SolutionEngine 7750"
select CPU_SH4
config TARGET_AP_SH4A_4A
bool "ALPHAPROJECT AP-SH4A-4A"
select CPU_SH4A
config TARGET_AP325RXA
bool "Renesas AP-325RXA"
select CPU_SH4
config TARGET_ECOVEC
bool "EcoVec"
select CPU_SH4A
config TARGET_MIGOR
bool "Migo-R"
select CPU_SH4
config TARGET_R0P7734
bool "Support r0p7734"
select CPU_SH4A
config TARGET_R2DPLUS
bool "Renesas R2D-PLUS"
select CPU_SH4
config TARGET_R7780MP
bool "R7780MP board"
select CPU_SH4A
config TARGET_SH7752EVB
bool "SH7752EVB"
select CPU_SH4A
config TARGET_SH7753EVB
bool "SH7753EVB"
select CPU_SH4
config TARGET_SH7757LCR
bool "SH7757LCR"
select CPU_SH4A
config TARGET_SH7763RDP
bool "SH7763RDP"
select CPU_SH4
config TARGET_SH7785LCR
bool "SH7785LCR"
select CPU_SH4A
endchoice
config SYS_ARCH
default "sh"
config SYS_CPU
default "sh2" if CPU_SH2
default "sh3" if CPU_SH3
default "sh4" if CPU_SH4
source "board/alphaproject/ap_sh4a_4a/Kconfig"
source "board/espt/Kconfig"
source "board/mpr2/Kconfig"
source "board/ms7720se/Kconfig"
source "board/ms7722se/Kconfig"
source "board/ms7750se/Kconfig"
source "board/renesas/MigoR/Kconfig"
source "board/renesas/ap325rxa/Kconfig"
source "board/renesas/ecovec/Kconfig"
source "board/renesas/r0p7734/Kconfig"
source "board/renesas/r2dplus/Kconfig"
source "board/renesas/r7780mp/Kconfig"
source "board/renesas/rsk7203/Kconfig"
source "board/renesas/rsk7264/Kconfig"
source "board/renesas/rsk7269/Kconfig"
source "board/renesas/sh7752evb/Kconfig"
source "board/renesas/sh7753evb/Kconfig"
source "board/renesas/sh7757lcr/Kconfig"
source "board/renesas/sh7763rdp/Kconfig"
source "board/renesas/sh7785lcr/Kconfig"
source "board/shmin/Kconfig"
endmenu

8
u-boot/arch/sh/Makefile Normal file
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#
# SPDX-License-Identifier: GPL-2.0+
#
head-y := arch/sh/cpu/$(CPU)/start.o
libs-y += arch/sh/cpu/$(CPU)/
libs-y += arch/sh/lib/

20
u-boot/arch/sh/config.mk Normal file
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#
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := sh4-linux-
endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000
ifeq ($(CPU),sh2)
CONFIG_STANDALONE_LOAD_ADDR += -EB
endif
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
LDFLAGS_FINAL = --gc-sections
PLATFORM_RELFLAGS += -ffixed-r13

12
u-boot/arch/sh/cpu/sh2/Makefile Normal file
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
# Copyright (C) 2008 Renesas Solutions Corp.
#
# SPDX-License-Identifier: GPL-2.0+
#
extra-y = start.o
obj-y = cpu.o interrupts.o watchdog.o

17
u-boot/arch/sh/cpu/sh2/config.mk Normal file
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#
# (C) Copyright 2007-2008
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# SPDX-License-Identifier: GPL-2.0+
#
#
ENDIANNESS += -EB
ifdef CONFIG_CPU_SH2A
PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb
else # SH2
PLATFORM_CPPFLAGS += -m3e -mb
endif
PLATFORM_CPPFLAGS += $(call cc-option,-mno-fdpic)
PLATFORM_LDFLAGS += $(ENDIANNESS)

91
u-boot/arch/sh/cpu/sh2/cpu.c Normal file
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/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#define STBCR4 0xFFFE040C
#define cmt_clock_enable() do {\
writeb(readb(STBCR4) & ~0x04, STBCR4);\
} while (0)
#define scif0_enable() do {\
writeb(readb(STBCR4) & ~0x80, STBCR4);\
} while (0)
#define scif3_enable() do {\
writeb(readb(STBCR4) & ~0x10, STBCR4);\
} while (0)
int checkcpu(void)
{
puts("CPU: SH2\n");
return 0;
}
int cpu_init(void)
{
/* SCIF enable */
#if defined(CONFIG_CONS_SCIF3)
scif3_enable();
#else
scif0_enable();
#endif
/* CMT clock enable */
cmt_clock_enable() ;
return 0;
}
int cleanup_before_linux(void)
{
disable_interrupts();
return 0;
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
reset_cpu(0);
return 0;
}
void flush_cache(unsigned long addr, unsigned long size)
{
}
void icache_enable(void)
{
}
void icache_disable(void)
{
}
int icache_status(void)
{
return 0;
}
void dcache_enable(void)
{
}
void dcache_disable(void)
{
}
int dcache_status(void)
{
return 0;
}
void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
{
/* TODO(sh maintainer): Implement this */
while (1);
}

23
u-boot/arch/sh/cpu/sh2/interrupts.c Normal file
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/*
* Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
int interrupt_init(void)
{
return 0;
}
void enable_interrupts(void)
{
}
int disable_interrupts(void)
{
return 0;
}

66
u-boot/arch/sh/cpu/sh2/start.S Normal file
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/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
.text
.align 2
.global _start
_sh_start:
.long 0x00000010 /* Ppower ON reset PC*/
.long 0x00000000
.long 0x00000010 /* Manual reset PC */
.long 0x00000000
_init:
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
bsr 1f
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
add #(_sh_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
mov.l r1, @r4
add #4, r4
cmp/hs r6, r4
bf 2b
mov.l ._bss_start, r4
mov.l ._bss_end, r5
mov #0, r1
3: mov.l r1, @r4 /* bss clear */
add #4, r4
cmp/hs r5, r4
bf 3b
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
#TODO(sh maintainer): Fix this up to call the correct code
#mov.l ._sh_generic_init, r0
#jsr @r0
nop
loop:
bra loop
.align 2
._lowlevel_init: .long (lowlevel_init - (100b + 4))
._reloc_dst: .long reloc_dst
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
#._sh_generic_init: .long sh_generic_init

24
u-boot/arch/sh/cpu/sh2/watchdog.c Normal file
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/*
* Copyright (C) 2008,2010 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2008,2010 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/system.h>
int watchdog_init(void)
{
return 0;
}
void reset_cpu(unsigned long ignored)
{
/* Address error with SR.BL=1 first. */
trigger_address_error();
while (1)
;
}

15
u-boot/arch/sh/cpu/sh3/Makefile Normal file
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# (C) Copyright 2007
# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
extra-y = start.o
obj-y = cpu.o interrupts.o watchdog.o cache.o

96
u-boot/arch/sh/cpu/sh3/cache.c Normal file
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/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* (C) Copyright 2007
* Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
/*
* Jump to P2 area.
* When handling TLB or caches, we need to do it from P2 area.
*/
#define jump_to_P2() \
do { \
unsigned long __dummy; \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"or %1, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy) \
: "r" (0x20000000)); \
} while (0)
/*
* Back to P1 area.
*/
#define back_to_P1() \
do { \
unsigned long __dummy; \
__asm__ __volatile__( \
"nop;nop;nop;nop;nop;nop;nop\n\t" \
"mov.l 1f, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy)); \
} while (0)
#define CACHE_VALID 1
#define CACHE_UPDATED 2
static inline void cache_wback_all(void)
{
unsigned long addr, data, i, j;
jump_to_P2();
for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
addr = CACHE_OC_ADDRESS_ARRAY
| (j << CACHE_OC_WAY_SHIFT)
| (i << CACHE_OC_ENTRY_SHIFT);
data = inl(addr);
if (data & CACHE_UPDATED) {
data &= ~CACHE_UPDATED;
outl(data, addr);
}
}
}
back_to_P1();
}
#define CACHE_ENABLE 0
#define CACHE_DISABLE 1
int cache_control(unsigned int cmd)
{
unsigned long ccr;
jump_to_P2();
ccr = inl(CCR);
if (ccr & CCR_CACHE_ENABLE)
cache_wback_all();
if (cmd == CACHE_DISABLE)
outl(CCR_CACHE_STOP, CCR);
else
outl(CCR_CACHE_INIT, CCR);
back_to_P1();
return 0;
}

14
u-boot/arch/sh/cpu/sh3/config.mk Normal file
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#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# (C) Copyright 2007
# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
#
PLATFORM_CPPFLAGS += -m3

74
u-boot/arch/sh/cpu/sh3/cpu.c Normal file
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/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
int checkcpu(void)
{
puts("CPU: SH3\n");
return 0;
}
int cpu_init(void)
{
return 0;
}
int cleanup_before_linux(void)
{
disable_interrupts();
return 0;
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
reset_cpu(0);
return 0;
}
void flush_cache(unsigned long addr, unsigned long size)
{
}
void icache_enable(void)
{
}
void icache_disable(void)
{
}
int icache_status(void)
{
return 0;
}
void dcache_enable(void)
{
}
void dcache_disable(void)
{
}
int dcache_status(void)
{
return 0;
}
void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
{
/* TODO(sh maintainer): Implement this */
while (1);
}

26
u-boot/arch/sh/cpu/sh3/interrupts.c Normal file
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/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
int interrupt_init(void)
{
return 0;
}
void enable_interrupts(void)
{
}
int disable_interrupts(void)
{
return 0;
}

65
u-boot/arch/sh/cpu/sh3/start.S Normal file
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/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
.text
.align 2
.global _start
_sh_start:
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
bsr 1f
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
add #(_sh_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
mov.l r1, @r4
add #4, r4
cmp/hs r6, r4
bf 2b
mov.l ._bss_start, r4
mov.l ._bss_end, r5
mov #0, r1
3: mov.l r1, @r4 /* bss clear */
add #4, r4
cmp/hs r5, r4
bf 3b
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
#TODO(sh maintainer): Fix this up to call the correct code
#mov.l ._sh_generic_init, r0
#jsr @r0
nop
loop:
bra loop
.align 2
._lowlevel_init: .long (lowlevel_init - (100b + 4))
._reloc_dst: .long reloc_dst
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
#._sh_generic_init: .long sh_generic_init

27
u-boot/arch/sh/cpu/sh3/watchdog.c Normal file
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/*
* (C) Copyright 2010
* Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/system.h>
int watchdog_init(void)
{
return 0;
}
void reset_cpu(unsigned long ignored)
{
/* Address error with SR.BL=1 first. */
trigger_address_error();
while (1)
;
}

12
u-boot/arch/sh/cpu/sh4/Makefile Normal file
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# SPDX-License-Identifier: GPL-2.0+
#
extra-y = start.o
obj-y = cpu.o interrupts.o watchdog.o cache.o

114
u-boot/arch/sh/cpu/sh4/cache.c Normal file
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/*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
/*
* Jump to P2 area.
* When handling TLB or caches, we need to do it from P2 area.
*/
#define jump_to_P2() \
do { \
unsigned long __dummy; \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"or %1, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy) \
: "r" (0x20000000)); \
} while (0)
/*
* Back to P1 area.
*/
#define back_to_P1() \
do { \
unsigned long __dummy; \
__asm__ __volatile__( \
"nop;nop;nop;nop;nop;nop;nop\n\t" \
"mov.l 1f, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy)); \
} while (0)
#define CACHE_VALID 1
#define CACHE_UPDATED 2
static inline void cache_wback_all(void)
{
unsigned long addr, data, i, j;
jump_to_P2();
for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){
for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT)
| (i << CACHE_OC_ENTRY_SHIFT);
data = inl(addr);
if (data & CACHE_UPDATED) {
data &= ~CACHE_UPDATED;
outl(data, addr);
}
}
}
back_to_P1();
}
#define CACHE_ENABLE 0
#define CACHE_DISABLE 1
int cache_control(unsigned int cmd)
{
unsigned long ccr;
jump_to_P2();
ccr = inl(CCR);
if (ccr & CCR_CACHE_ENABLE)
cache_wback_all();
if (cmd == CACHE_DISABLE)
outl(CCR_CACHE_STOP, CCR);
else
outl(CCR_CACHE_INIT, CCR);
back_to_P1();
return 0;
}
void flush_dcache_range(unsigned long start, unsigned long end)
{
u32 v;
start &= ~(L1_CACHE_BYTES - 1);
for (v = start; v < end; v += L1_CACHE_BYTES) {
asm volatile ("ocbwb %0" : /* no output */
: "m" (__m(v)));
}
}
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
u32 v;
start &= ~(L1_CACHE_BYTES - 1);
for (v = start; v < end; v += L1_CACHE_BYTES) {
asm volatile ("ocbi %0" : /* no output */
: "m" (__m(v)));
}
}

11
u-boot/arch/sh/cpu/sh4/config.mk Normal file
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#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# SPDX-License-Identifier: GPL-2.0+
#
#
PLATFORM_CPPFLAGS += -m4-nofpu

83
u-boot/arch/sh/cpu/sh4/cpu.c Normal file
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/*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/processor.h>
#include <asm/cache.h>
int checkcpu(void)
{
puts("CPU: SH4\n");
return 0;
}
int cpu_init (void)
{
return 0;
}
int cleanup_before_linux (void)
{
disable_interrupts();
return 0;
}
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
reset_cpu (0);
return 0;
}
void flush_cache (unsigned long addr, unsigned long size)
{
invalidate_dcache_range(addr , addr + size);
}
void icache_enable (void)
{
cache_control(0);
}
void icache_disable (void)
{
cache_control(1);
}
int icache_status (void)
{
return 0;
}
void dcache_enable (void)
{
}
void dcache_disable (void)
{
}
int dcache_status (void)
{
return 0;
}
int cpu_eth_init(bd_t *bis)
{
#ifdef CONFIG_SH_ETHER
sh_eth_initialize(bis);
#endif
return 0;
}
void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
{
/* TODO(sh maintainer): Implement this */
while (1);
}

22
u-boot/arch/sh/cpu/sh4/interrupts.c Normal file
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/*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
int interrupt_init (void)
{
return 0;
}
void enable_interrupts (void)
{
}
int disable_interrupts (void){
return 0;
}

62
u-boot/arch/sh/cpu/sh4/start.S Normal file
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/*
* (C) Copyright 2007, 2010
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
.text
.align 2
.global _start
_sh_start:
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
bsr 1f
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
add #(_sh_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
mov.l r1, @r4
add #4, r4
cmp/hs r6, r4
bf 2b
mov.l ._bss_start, r4
mov.l ._bss_end, r5
mov #0, r1
3: mov.l r1, @r4 /* bss clear */
add #4, r4
cmp/hs r5, r4
bf 3b
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
#TODO(sh maintainer): Fix this up to call the correct code
#mov.l ._sh_generic_init, r0
#jsr @r0
nop
loop:
bra loop
.align 2
._lowlevel_init: .long (lowlevel_init - (100b + 4))
._reloc_dst: .long reloc_dst
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
#._sh_generic_init: .long sh_generic_init

62
u-boot/arch/sh/cpu/sh4/watchdog.c Normal file
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/*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/io.h>
#define WDT_BASE WTCNT
#define WDT_WD (1 << 6)
#define WDT_RST_P (0)
#define WDT_RST_M (1 << 5)
#define WDT_ENABLE (1 << 7)
#if defined(CONFIG_WATCHDOG)
static unsigned char csr_read(void)
{
return inb(WDT_BASE + 0x04);
}
static void cnt_write(unsigned char value)
{
outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
}
static void csr_write(unsigned char value)
{
outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
}
void watchdog_reset(void)
{
outl(0x55000000, WDT_BASE + 0x08);
}
int watchdog_init(void)
{
/* Set overflow time*/
cnt_write(0);
/* Power on reset */
csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
return 0;
}
int watchdog_disable(void)
{
csr_write(csr_read() & ~WDT_ENABLE);
return 0;
}
#endif
void reset_cpu(unsigned long ignored)
{
/* Address error with SR.BL=1 first. */
trigger_address_error();
while (1)
;
}

84
u-boot/arch/sh/cpu/u-boot.lds Normal file
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/*
* Copyright (C) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* Copyright (C) 2008-2009
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* Copyright (C) 2008
* Mark Jonas <mark.jonas@de.bosch.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
OUTPUT_ARCH(sh)
ENTRY(_start)
SECTIONS
{
/*
* entry and reloct_dst will be provided via ldflags
*/
. = .;
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
PROVIDE (_start = .);
.text :
{
KEEP(*/start.o (.text))
. = ALIGN(8192);
common/env_embedded.o (.ppcenv)
. = ALIGN(8192);
common/env_embedded.o (.ppcenvr)
. = ALIGN(8192);
*(.text)
. = ALIGN(4);
} =0xFF
PROVIDE (_ecode = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
. = ALIGN(4);
}
PROVIDE (_etext = .);
PROVIDE (_fdata = .);
.data :
{
*(.data)
. = ALIGN(4);
}
PROVIDE (_edata = .);
PROVIDE (_fgot = .);
.got :
{
*(.got)
. = ALIGN(4);
}
PROVIDE (_egot = .);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
.bss :
{
*(.bss)
. = ALIGN(4);
}
PROVIDE (bss_end = .);
PROVIDE (__bss_end = .);
}

158
u-boot/arch/sh/include/asm/bitops.h Normal file
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#ifndef __ASM_SH_BITOPS_H
#define __ASM_SH_BITOPS_H
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/__ffs.h>
#ifdef __KERNEL__
#include <asm/irqflags.h>
/* For __swab32 */
#include <asm/byteorder.h>
static inline void set_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a |= mask;
local_irq_restore(flags);
}
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
static inline void clear_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a &= ~mask;
local_irq_restore(flags);
}
static inline void change_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a ^= mask;
local_irq_restore(flags);
}
static inline int test_and_set_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a |= mask;
local_irq_restore(flags);
return retval;
}
static inline int test_and_clear_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a &= ~mask;
local_irq_restore(flags);
return retval;
}
static inline int test_and_change_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a ^= mask;
local_irq_restore(flags);
return retval;
}
static inline unsigned long ffz(unsigned long word)
{
unsigned long result;
__asm__("1:\n\t"
"shlr %1\n\t"
"bt/s 1b\n\t"
" add #1, %0"
: "=r" (result), "=r" (word)
: "0" (~0L), "1" (word)
: "t");
return result;
}
/**
* ffs - find first bit in word.
* @word: The word to search
*
* Undefined if no bit exists, so code should check against 0 first.
*/
static inline int ffs (int x)
{
int r = 1;
if (!x)
return 0;
if (!(x & 0xffff)) {
x >>= 16;
r += 16;
}
if (!(x & 0xff)) {
x >>= 8;
r += 8;
}
if (!(x & 0xf)) {
x >>= 4;
r += 4;
}
if (!(x & 3)) {
x >>= 2;
r += 2;
}
if (!(x & 1)) {
x >>= 1;
r += 1;
}
return r;
}
#define PLATFORM_FFS
#endif /* __KERNEL__ */
#endif /* __ASM_SH_BITOPS_H */

17
u-boot/arch/sh/include/asm/byteorder.h Normal file
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/*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_SH_BYTEORDER_H_
#define __ASM_SH_BYTEORDER_H_
#include <config.h>
#include <asm/types.h>
#ifdef __LITTLE_ENDIAN__
#include <linux/byteorder/little_endian.h>
#else
#include <linux/byteorder/big_endian.h>
#endif
#endif

31
u-boot/arch/sh/include/asm/cache.h Normal file
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#ifndef __ASM_SH_CACHE_H
#define __ASM_SH_CACHE_H
#if defined(CONFIG_CPU_SH4)
int cache_control(unsigned int cmd);
#define L1_CACHE_BYTES 32
struct __large_struct { unsigned long buf[100]; };
#define __m(x) (*(struct __large_struct *)(x))
#else
/*
* 32-bytes is the largest L1 data cache line size for SH the architecture. So
* it is a safe default for DMA alignment.
*/
#define ARCH_DMA_MINALIGN 32
#endif /* CONFIG_CPU_SH4 */
/*
* Use the L1 data cache line size value for the minimum DMA buffer alignment
* on SH.
*/
#ifndef ARCH_DMA_MINALIGN
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
#endif
#endif /* __ASM_SH_CACHE_H */

10
u-boot/arch/sh/include/asm/config.h Normal file
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/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#endif

31
u-boot/arch/sh/include/asm/cpu_sh2.h Normal file
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/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH2_H_
#define _ASM_CPU_SH2_H_
/* cache control */
#define CCR_CACHE_STOP 0x00000008
#define CCR_CACHE_ENABLE 0x00000005
#define CCR_CACHE_ICI 0x00000008
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_WAY_SHIFT 13
#define CACHE_OC_NUM_ENTRIES 256
#define CACHE_OC_ENTRY_SHIFT 4
#if defined(CONFIG_CPU_SH7203)
# include <asm/cpu_sh7203.h>
#elif defined(CONFIG_CPU_SH7264)
# include <asm/cpu_sh7264.h>
#elif defined(CONFIG_CPU_SH7269)
# include <asm/cpu_sh7269.h>
#else
# error "Unknown SH2 variant"
#endif
#endif /* _ASM_CPU_SH2_H_ */

31
u-boot/arch/sh/include/asm/cpu_sh3.h Normal file
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/*
* (C) Copyright 2007-2009 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH3_H_
#define _ASM_CPU_SH3_H_
/* cache control */
#define CCR_CACHE_STOP 0x00000008
#define CCR_CACHE_ENABLE 0x00000005
#define CCR_CACHE_ICI 0x00000008
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_WAY_SHIFT 13
#define CACHE_OC_NUM_ENTRIES 256
#define CACHE_OC_ENTRY_SHIFT 4
#if defined(CONFIG_CPU_SH7706)
#include <asm/cpu_sh7706.h>
#elif defined(CONFIG_CPU_SH7710)
#include <asm/cpu_sh7710.h>
#elif defined(CONFIG_CPU_SH7720)
#include <asm/cpu_sh7720.h>
#else
#error "Unknown SH3 variant"
#endif
#endif /* _ASM_CPU_SH3_H_ */

79
u-boot/arch/sh/include/asm/cpu_sh4.h Normal file
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/*
* (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH4_H_
#define _ASM_CPU_SH4_H_
/* cache control */
#define CCR_CACHE_STOP 0x00000808
#define CCR_CACHE_ENABLE 0x00000101
#define CCR_CACHE_ICI 0x00000800
#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
#if defined (CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751)
#define CACHE_OC_WAY_SHIFT 14
#define CACHE_OC_NUM_ENTRIES 512
#else
#define CACHE_OC_WAY_SHIFT 13
#define CACHE_OC_NUM_ENTRIES 256
#endif
#define CACHE_OC_ENTRY_SHIFT 5
#if defined (CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751)
# include <asm/cpu_sh7750.h>
#elif defined (CONFIG_CPU_SH7722)
# include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7723)
# include <asm/cpu_sh7723.h>
#elif defined (CONFIG_CPU_SH7724)
# include <asm/cpu_sh7724.h>
#elif defined (CONFIG_CPU_SH7734)
# include <asm/cpu_sh7734.h>
#elif defined (CONFIG_CPU_SH7752)
# include <asm/cpu_sh7752.h>
#elif defined (CONFIG_CPU_SH7753)
# include <asm/cpu_sh7753.h>
#elif defined (CONFIG_CPU_SH7757)
# include <asm/cpu_sh7757.h>
#elif defined (CONFIG_CPU_SH7763)
# include <asm/cpu_sh7763.h>
#elif defined (CONFIG_CPU_SH7780)
# include <asm/cpu_sh7780.h>
#elif defined (CONFIG_CPU_SH7785)
# include <asm/cpu_sh7785.h>
#else
# error "Unknown SH4 variant"
#endif
#if defined(CONFIG_SH_32BIT)
#define PMB_ADDR_ARRAY 0xf6100000
#define PMB_ADDR_ENTRY 8
#define PMB_VPN 24
#define PMB_DATA_ARRAY 0xf7100000
#define PMB_DATA_ENTRY 8
#define PMB_PPN 24
#define PMB_UB 9 /* Buffered write */
#define PMB_V 8 /* Valid */
#define PMB_SZ1 7 /* Page size (upper bit) */
#define PMB_SZ0 4 /* Page size (lower bit) */
#define PMB_C 3 /* Cacheability */
#define PMB_WT 0 /* Write-through */
#define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
#define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
#define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN))
#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \
((ppn << PMB_PPN) | (ub << PMB_UB) | \
(v << PMB_V) | (sz1 << PMB_SZ1) | \
(sz0 << PMB_SZ0) | (c << PMB_C) | \
(wt << PMB_WT))
#endif
#endif /* _ASM_CPU_SH4_H_ */

41
u-boot/arch/sh/include/asm/cpu_sh7203.h Normal file
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#ifndef _ASM_CPU_SH7203_H_
#define _ASM_CPU_SH7203_H_
/* Cache */
#define CCR1 0xFFFC1000
#define CCR CCR1
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PETCR 0xA4050106
/* Port Data Registers */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
/* BSC */
/* SDRAM controller */
/* SCIF */
#define SCSMR_0 0xFFFE8000
#define SCIF0_BASE SCSMR_0
/* Timer(CMT) */
#define CMSTR 0xFFFEC000
#define CMCSR_0 0xFFFEC002
#define CMCNT_0 0xFFFEC004
#define CMCOR_0 0xFFFEC006
#define CMCSR_1 0xFFFEC008
#define CMCNT_1 0xFFFEC00A
#define CMCOR_1 0xFFFEC00C
/* On chip oscillator circuits */
#define FRQCR 0xA415FF80
#define WTCNT 0xA415FF84
#define WTCSR 0xA415FF86
#endif /* _ASM_CPU_SH7203_H_ */

41
u-boot/arch/sh/include/asm/cpu_sh7264.h Normal file
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#ifndef _ASM_CPU_SH7264_H_
#define _ASM_CPU_SH7264_H_
/* Cache */
#define CCR1 0xFFFC1000
#define CCR CCR1
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PETCR 0xA4050106
/* Port Data Registers */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
/* BSC */
/* SDRAM controller */
/* SCIF */
#define SCSMR_3 0xFFFE9800
#define SCIF3_BASE SCSMR_3
/* Timer(CMT) */
#define CMSTR 0xFFFEC000
#define CMCSR_0 0xFFFEC002
#define CMCNT_0 0xFFFEC004
#define CMCOR_0 0xFFFEC006
#define CMCSR_1 0xFFFEC008
#define CMCNT_1 0xFFFEC00A
#define CMCOR_1 0xFFFEC00C
/* On chip oscillator circuits */
#define FRQCR 0xA415FF80
#define WTCNT 0xA415FF84
#define WTCSR 0xA415FF86
#endif /* _ASM_CPU_SH7264_H_ */

26
u-boot/arch/sh/include/asm/cpu_sh7269.h Normal file
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#ifndef _ASM_CPU_SH7269_H_
#define _ASM_CPU_SH7269_H_
/* Cache */
#define CCR1 0xFFFC1000
#define CCR CCR1
/* SCIF */
#define SCSMR_0 0xE8007000
#define SCIF0_BASE SCSMR_0
#define SCSMR_1 0xE8007800
#define SCIF1_BASE SCSMR_1
#define SCSMR_2 0xE8008000
#define SCIF2_BASE SCSMR_2
#define SCSMR_3 0xE8008800
#define SCIF3_BASE SCSMR_3
#define SCSMR_7 0xE800A800
#define SCIF7_BASE SCSMR_7
/* Timer(CMT) */
#define CMSTR 0xFFFEC000
#define CMCSR_0 0xFFFEC002
#define CMCNT_0 0xFFFEC004
#define CMCOR_0 0xFFFEC006
#endif /* _ASM_CPU_SH7269_H_ */

50
u-boot/arch/sh/include/asm/cpu_sh7706.h Normal file
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#ifndef _ASM_CPU_SH7706_H_
#define _ASM_CPU_SH7706_H_
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000000D
/* MMU and Cache control */
#define MMUCR 0xFFFFFFE0
#define CCR 0xFFFFFFEC
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PETCR 0xA4050106
/* Port Data Registers */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
/* BSC */
#define FRQCR 0xffffff80
#define BCR1 0xffffff60
#define BCR2 0xffffff62
#define WCR1 0xffffff64
#define WCR2 0xffffff66
#define MCR 0xffffff68
/* SDRAM controller */
#define DCR 0xffffff6a
#define RTCSR 0xffffff6e
#define RTCNT 0xffffff70
#define RTCOR 0xffffff72
#define RFCR 0xffffff74
#define SDMR 0xFFFFD000
#define CS3_R 0xFFFFE460
/* SCIF */
#define SCSMR_2 0xA4000150
#define SCIF0_BASE SCSMR_2
/* Timer */
#define TMU_BASE 0xFFFFFE90
/* On chip oscillator circuits */
#define WTCNT 0xFFFFFF84
#define WTCSR 0xFFFFFF86
#endif /* _ASM_CPU_SH7706_H_ */

61
u-boot/arch/sh/include/asm/cpu_sh7710.h Normal file
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#ifndef _ASM_CPU_SH7710_H_
#define _ASM_CPU_SH7710_H_
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000000D
/* MMU and Cache control */
#define MMUCR 0xFFFFFFE0
#define CCR 0xFFFFFFEC
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PETCR 0xA4050106
/* Port Data Registers */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
/* BSC */
#define CMNCR 0xA4FD0000
#define CS0BCR 0xA4FD0004
#define CS2BCR 0xA4FD0008
#define CS3BCR 0xA4FD000C
#define CS4BCR 0xA4FD0010
#define CS5ABCR 0xA4FD0014
#define CS5BBCR 0xA4FD0018
#define CS6ABCR 0xA4FD001C
#define CS6BBCR 0xA4FD0020
#define CS0WCR 0xA4FD0024
#define CS2WCR 0xA4FD0028
#define CS3WCR 0xA4FD002C
#define CS4WCR 0xA4FD0030
#define CS5AWCR 0xA4FD0034
#define CS5BWCR 0xA4FD0038
#define CS6AWCR 0xA4FD003C
#define CS6BWCR 0xA4FD0040
/* SDRAM controller */
#define SDCR 0xA4FD0044
#define RTCSR 0xA4FD0048
#define RTCNT 0xA4FD004C
#define RTCOR 0xA4FD0050
/* SCIF */
#define SCSMR_0 0xA4400000
#define SCIF0_BASE SCSMR_0
#define SCSMR_0 0xA4410000
#define SCIF1_BASE SCSMR_1
/* Timer */
#define TMU_BASE 0xA412FE90
/* On chip oscillator circuits */
#define FRQCR 0xA415FF80
#define WTCNT 0xA415FF84
#define WTCSR 0xA415FF86
#endif /* _ASM_CPU_SH7710_H_ */

207
u-boot/arch/sh/include/asm/cpu_sh7720.h Normal file
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/*
* Copyright 2007 (C)
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* Copyright 2008 (C)
* Mark Jonas <mark.jonas@de.bosch.com>
*
* SH7720 Internal I/O register
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH7720_H_
#define _ASM_CPU_SH7720_H_
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000000B
/* EXP */
#define TRA 0xFFFFFFD0
#define EXPEVT 0xFFFFFFD4
#define INTEVT 0xFFFFFFD8
/* MMU */
#define MMUCR 0xFFFFFFE0
#define PTEH 0xFFFFFFF0
#define PTEL 0xFFFFFFF4
#define TTB 0xFFFFFFF8
/* CACHE */
#define CCR 0xFFFFFFEC
/* INTC */
#define IPRF 0xA4080000
#define IPRG 0xA4080002
#define IPRH 0xA4080004
#define IPRI 0xA4080006
#define IPRJ 0xA4080008
#define IRR5 0xA4080020
#define IRR6 0xA4080022
#define IRR7 0xA4080024
#define IRR8 0xA4080026
#define IRR9 0xA4080028
#define IRR0 0xA4140004
#define IRR1 0xA4140006
#define IRR2 0xA4140008
#define IRR3 0xA414000A
#define IRR4 0xA414000C
#define ICR1 0xA4140010
#define ICR2 0xA4140012
#define PINTER 0xA4140014
#define IPRC 0xA4140016
#define IPRD 0xA4140018
#define IPRE 0xA414001A
#define ICR0 0xA414FEE0
#define IPRA 0xA414FEE2
#define IPRB 0xA414FEE4
/* BSC */
#define BSC_BASE 0xA4FD0000
#define CMNCR (BSC_BASE + 0x00)
#define CS0BCR (BSC_BASE + 0x04)
#define CS2BCR (BSC_BASE + 0x08)
#define CS3BCR (BSC_BASE + 0x0C)
#define CS4BCR (BSC_BASE + 0x10)
#define CS5ABCR (BSC_BASE + 0x14)
#define CS5BBCR (BSC_BASE + 0x18)
#define CS6ABCR (BSC_BASE + 0x1C)
#define CS6BBCR (BSC_BASE + 0x20)
#define CS0WCR (BSC_BASE + 0x24)
#define CS2WCR (BSC_BASE + 0x28)
#define CS3WCR (BSC_BASE + 0x2C)
#define CS4WCR (BSC_BASE + 0x30)
#define CS5AWCR (BSC_BASE + 0x34)
#define CS5BWCR (BSC_BASE + 0x38)
#define CS6AWCR (BSC_BASE + 0x3C)
#define CS6BWCR (BSC_BASE + 0x40)
#define SDCR (BSC_BASE + 0x44)
#define RTCSR (BSC_BASE + 0x48)
#define RTCNR (BSC_BASE + 0x4C)
#define RTCOR (BSC_BASE + 0x50)
#define SDMR2 (BSC_BASE + 0x4000)
#define SDMR3 (BSC_BASE + 0x5000)
/* DMAC */
/* CPG */
#define UCLKCR 0xA40A0008
#define FRQCR 0xA415FF80
/* LOW POWER MODE */
/* TMU */
#define TMU_BASE 0xA412FE90
/* TPU */
#define TPU_BASE 0xA4480000
#define TPU_TSTR (TPU_BASE + 0x00)
#define TPU_TCR0 (TPU_BASE + 0x10)
#define TPU_TMDR0 (TPU_BASE + 0x14)
#define TPU_TIOR0 (TPU_BASE + 0x18)
#define TPU_TIER0 (TPU_BASE + 0x1C)
#define TPU_TSR0 (TPU_BASE + 0x20)
#define TPU_TCNT0 (TPU_BASE + 0x24)
#define TPU_TGRA0 (TPU_BASE + 0x28)
#define TPU_TGRB0 (TPU_BASE + 0x2C)
#define TPU_TGRC0 (TPU_BASE + 0x30)
#define TPU_TGRD0 (TPU_BASE + 0x34)
#define TPU_TCR1 (TPU_BASE + 0x50)
#define TPU_TMDR1 (TPU_BASE + 0x54)
#define TPU_TIOR1 (TPU_BASE + 0x58)
#define TPU_TIER1 (TPU_BASE + 0x5C)
#define TPU_TSR1 (TPU_BASE + 0x60)
#define TPU_TCNT1 (TPU_BASE + 0x64)
#define TPU_TGRA1 (TPU_BASE + 0x68)
#define TPU_TGRB1 (TPU_BASE + 0x6C)
#define TPU_TGRC1 (TPU_BASE + 0x70)
#define TPU_TGRD1 (TPU_BASE + 0x74)
#define TPU_TCR2 (TPU_BASE + 0x90)
#define TPU_TMDR2 (TPU_BASE + 0x94)
#define TPU_TIOR2 (TPU_BASE + 0x98)
#define TPU_TIER2 (TPU_BASE + 0x9C)
#define TPU_TSR2 (TPU_BASE + 0xB0)
#define TPU_TCNT2 (TPU_BASE + 0xB4)
#define TPU_TGRA2 (TPU_BASE + 0xB8)
#define TPU_TGRB2 (TPU_BASE + 0xBC)
#define TPU_TGRC2 (TPU_BASE + 0xC0)
#define TPU_TGRD2 (TPU_BASE + 0xC4)
#define TPU_TCR3 (TPU_BASE + 0xD0)
#define TPU_TMDR3 (TPU_BASE + 0xD4)
#define TPU_TIOR3 (TPU_BASE + 0xD8)
#define TPU_TIER3 (TPU_BASE + 0xDC)
#define TPU_TSR3 (TPU_BASE + 0xE0)
#define TPU_TCNT3 (TPU_BASE + 0xE4)
#define TPU_TGRA3 (TPU_BASE + 0xE8)
#define TPU_TGRB3 (TPU_BASE + 0xEC)
#define TPU_TGRC3 (TPU_BASE + 0xF0)
#define TPU_TGRD3 (TPU_BASE + 0xF4)
/* CMT */
/* SIOF */
/* SCIF */
#define SCIF0_BASE 0xA4430000
/* SIM */
/* IrDA */
/* IIC */
/* LCDC */
/* USBF */
/* MMCIF */
/* PFC */
#define PFC_BASE 0xA4050100
#define PACR (PFC_BASE + 0x00)
#define PBCR (PFC_BASE + 0x02)
#define PCCR (PFC_BASE + 0x04)
#define PDCR (PFC_BASE + 0x06)
#define PECR (PFC_BASE + 0x08)
#define PFCR (PFC_BASE + 0x0A)
#define PGCR (PFC_BASE + 0x0C)
#define PHCR (PFC_BASE + 0x0E)
#define PJCR (PFC_BASE + 0x10)
#define PKCR (PFC_BASE + 0x12)
#define PLCR (PFC_BASE + 0x14)
#define PMCR (PFC_BASE + 0x16)
#define PPCR (PFC_BASE + 0x18)
#define PRCR (PFC_BASE + 0x1A)
#define PSCR (PFC_BASE + 0x1C)
#define PTCR (PFC_BASE + 0x1E)
#define PUCR (PFC_BASE + 0x20)
#define PVCR (PFC_BASE + 0x22)
#define PSELA (PFC_BASE + 0x24)
#define PSELB (PFC_BASE + 0x26)
#define PSELC (PFC_BASE + 0x28)
#define PSELD (PFC_BASE + 0x2A)
/* I/O Port */
#define PORT_BASE 0xA4050100
#define PADR (PORT_BASE + 0x40)
#define PBDR (PORT_BASE + 0x42)
#define PCDR (PORT_BASE + 0x44)
#define PDDR (PORT_BASE + 0x46)
#define PEDR (PORT_BASE + 0x48)
#define PFDR (PORT_BASE + 0x4A)
#define PGDR (PORT_BASE + 0x4C)
#define PHDR (PORT_BASE + 0x4E)
#define PJDR (PORT_BASE + 0x50)
#define PKDR (PORT_BASE + 0x52)
#define PLDR (PORT_BASE + 0x54)
#define PMDR (PORT_BASE + 0x56)
#define PPDR (PORT_BASE + 0x58)
#define PRDR (PORT_BASE + 0x5A)
#define PSDR (PORT_BASE + 0x5C)
#define PTDR (PORT_BASE + 0x5E)
#define PUDR (PORT_BASE + 0x60)
#define PVDR (PORT_BASE + 0x62)
/* H-UDI */
#endif /* _ASM_CPU_SH7720_H_ */

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/*
* (C) Copyright 2008 Renesas Solutions Corp.
*
* SH7723 Internal I/O register
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH7723_H_
#define _ASM_CPU_SH7723_H_
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000090d
/* EXP */
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
/* MMU */
#define PTEH 0xFF000000
#define PTEL 0xFF000004
#define TTB 0xFF000008
#define TEA 0xFF00000C
#define MMUCR 0xFF000010
#define PASCR 0xFF000070
#define IRMCR 0xFF000078
/* CACHE */
#define CCR 0xFF00001C
#define RAMCR 0xFF000074
/* INTC */
/* BSC */
#define CMNCR 0xFEC10000
#define CS0BCR 0xFEC10004
#define CS2BCR 0xFEC10008
#define CS4BCR 0xFEC10010
#define CS5ABCR 0xFEC10014
#define CS5BBCR 0xFEC10018
#define CS6ABCR 0xFEC1001C
#define CS6BBCR 0xFEC10020
#define CS0WCR 0xFEC10024
#define CS2WCR 0xFEC10028
#define CS4WCR 0xFEC10030
#define CS5AWCR 0xFEC10034
#define CS5BWCR 0xFEC10038
#define CS6AWCR 0xFEC1003C
#define CS6BWCR 0xFEC10040
#define RBWTCNT 0xFEC10054
/* SBSC */
#define SBSC_SDCR 0xFE400008
#define SBSC_SDWCR 0xFE40000C
#define SBSC_SDPCR 0xFE400010
#define SBSC_RTCSR 0xFE400014
#define SBSC_RTCNT 0xFE400018
#define SBSC_RTCOR 0xFE40001C
#define SBSC_RFCR 0xFE400020
/* DMAC */
/* CPG */
#define FRQCR 0xA4150000
#define VCLKCR 0xA4150004
#define SCLKACR 0xA4150008
#define SCLKBCR 0xA415000C
#define IRDACLKCR 0xA4150018
#define PLLCR 0xA4150024
#define DLLFRQ 0xA4150050
/* LOW POWER MODE */
#define STBCR 0xA4150020
#define MSTPCR0 0xA4150030
#define MSTPCR1 0xA4150034
#define MSTPCR2 0xA4150038
/* RWDT */
#define RWTCNT 0xA4520000
#define RWTCSR 0xA4520004
#define WTCNT RWTCNT
/* TMU */
#define TMU_BASE 0xFFD80000
/* TPU */
/* CMT */
#define CMSTR 0xA44A0000
#define CMCSR 0xA44A0060
#define CMCNT 0xA44A0064
#define CMCOR 0xA44A0068
/* MSIOF */
/* SCIF */
#define SCIF0_BASE 0xFFE00000
#define SCIF1_BASE 0xFFE10000
#define SCIF2_BASE 0xFFE20000
#define SCIF3_BASE 0xa4e30000
#define SCIF4_BASE 0xa4e40000
#define SCIF5_BASE 0xa4e50000
/* RTC */
/* IrDA */
/* KEYSC */
/* USB */
/* IIC */
/* FLCTL */
/* VPU */
/* VIO(CEU) */
/* VIO(VEU) */
/* VIO(BEU) */
/* 2DG */
/* LCDC */
/* VOU */
/* TSIF */
/* SIU */
/* ATAPI */
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PDCR 0xA4050106
#define PECR 0xA4050108
#define PFCR 0xA405010A
#define PGCR 0xA405010C
#define PHCR 0xA405010E
#define PJCR 0xA4050110
#define PKCR 0xA4050112
#define PLCR 0xA4050114
#define PMCR 0xA4050116
#define PNCR 0xA4050118
#define PQCR 0xA405011A
#define PRCR 0xA405011C
#define PSCR 0xA405011E
#define PTCR 0xA4050140
#define PUCR 0xA4050142
#define PVCR 0xA4050144
#define PWCR 0xA4050146
#define PXCR 0xA4050148
#define PYCR 0xA405014A
#define PZCR 0xA405014C
#define PSELA 0xA405014E
#define PSELB 0xA4050150
#define PSELC 0xA4050152
#define PSELD 0xA4050154
#define HIZCRA 0xA4050158
#define HIZCRB 0xA405015A
#define HIZCRC 0xA405015C
#define HIZCRD 0xA405015E
#define MSELCRA 0xA4050180
#define MSELCRB 0xA4050182
#define PULCR 0xA4050184
#define DRVCRA 0xA405018A
#define DRVCRB 0xA405018C
/* I/O Port */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
#define PDDR 0xA4050126
#define PEDR 0xA4050128
#define PFDR 0xA405012A
#define PGDR 0xA405012C
#define PHDR 0xA405012E
#define PJDR 0xA4050130
#define PKDR 0xA4050132
#define PLDR 0xA4050134
#define PMDR 0xA4050136
#define PNDR 0xA4050138
#define PQDR 0xA405013A
#define PRDR 0xA405013C
#define PSDR 0xA405013E
#define PTDR 0xA4050160
#define PUDR 0xA4050162
#define PVDR 0xA4050164
#define PWDR 0xA4050166
#define PXDR 0xA4050168
#define PYDR 0xA405016A
#define PZDR 0xA405016C
/* UBC */
/* H-UDI */
#endif /* _ASM_CPU_SH7723_H_ */

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/*
* (C) Copyright 2008, 2011 Renesas Solutions Corp.
*
* SH7724 Internal I/O register
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH7724_H_
#define _ASM_CPU_SH7724_H_
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000090d
/* EXP */
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
/* MMU */
#define PTEH 0xFF000000
#define PTEL 0xFF000004
#define TTB 0xFF000008
#define TEA 0xFF00000C
#define MMUCR 0xFF000010
#define PASCR 0xFF000070
#define IRMCR 0xFF000078
/* CACHE */
#define CCR 0xFF00001C
#define RAMCR 0xFF000074
/* INTC */
/* BSC */
#define MMSELR 0xFF800020
#define CMNCR 0xFEC10000
#define CS0BCR 0xFEC10004
#define CS2BCR 0xFEC10008
#define CS4BCR 0xFEC10010
#define CS5ABCR 0xFEC10014
#define CS5BBCR 0xFEC10018
#define CS6ABCR 0xFEC1001C
#define CS6BBCR 0xFEC10020
#define CS0WCR 0xFEC10024
#define CS2WCR 0xFEC10028
#define CS4WCR 0xFEC10030
#define CS5AWCR 0xFEC10034
#define CS5BWCR 0xFEC10038
#define CS6AWCR 0xFEC1003C
#define CS6BWCR 0xFEC10040
#define RBWTCNT 0xFEC10054
/* SBSC */
#define SBSC_SDCR 0xFE400008
#define SBSC_SDWCR 0xFE40000C
#define SBSC_SDPCR 0xFE400010
#define SBSC_RTCSR 0xFE400014
#define SBSC_RTCNT 0xFE400018
#define SBSC_RTCOR 0xFE40001C
#define SBSC_RFCR 0xFE400020
/* DSBC */
#define DBKIND 0xFD000008
#define DBSTATE 0xFD00000C
#define DBEN 0xFD000010
#define DBCMDCNT 0xFD000014
#define DBCKECNT 0xFD000018
#define DBCONF 0xFD000020
#define DBTR0 0xFD000030
#define DBTR1 0xFD000034
#define DBTR2 0xFD000038
#define DBTR3 0xFD00003C
#define DBRFPDN0 0xFD000040
#define DBRFPDN1 0xFD000044
#define DBRFPDN2 0xFD000048
#define DBRFSTS 0xFD00004C
#define DBMRCNT 0xFD000060
#define DBPDCNT0 0xFD000108
/* DMAC */
/* CPG */
#define FRQCRA 0xA4150000
#define FRQCRB 0xA4150004
#define FRQCR FRQCRA
#define VCLKCR 0xA4150004
#define SCLKACR 0xA4150008
#define SCLKBCR 0xA415000C
#define IRDACLKCR 0xA4150018
#define PLLCR 0xA4150024
#define DLLFRQ 0xA4150050
/* LOW POWER MODE */
#define STBCR 0xA4150020
#define MSTPCR0 0xA4150030
#define MSTPCR1 0xA4150034
#define MSTPCR2 0xA4150038
/* RWDT */
#define RWTCNT 0xA4520000
#define RWTCSR 0xA4520004
#define WTCNT RWTCNT
/* TMU */
#define TMU_BASE 0xFFD80000
/* TPU */
/* CMT */
#define CMSTR 0xA44A0000
#define CMCSR 0xA44A0060
#define CMCNT 0xA44A0064
#define CMCOR 0xA44A0068
/* MSIOF */
/* SCIF */
#define SCIF0_BASE 0xFFE00000
#define SCIF1_BASE 0xFFE10000
#define SCIF2_BASE 0xFFE20000
#define SCIF3_BASE 0xa4e30000
#define SCIF4_BASE 0xa4e40000
#define SCIF5_BASE 0xa4e50000
/* RTC */
/* IrDA */
/* KEYSC */
/* USB */
/* IIC */
/* FLCTL */
/* VPU */
/* VIO(CEU) */
/* VIO(VEU) */
/* VIO(BEU) */
/* 2DG */
/* LCDC */
/* VOU */
/* TSIF */
/* SIU */
/* ATAPI */
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PDCR 0xA4050106
#define PECR 0xA4050108
#define PFCR 0xA405010A
#define PGCR 0xA405010C
#define PHCR 0xA405010E
#define PJCR 0xA4050110
#define PKCR 0xA4050112
#define PLCR 0xA4050114
#define PMCR 0xA4050116
#define PNCR 0xA4050118
#define PQCR 0xA405011A
#define PRCR 0xA405011C
#define PSCR 0xA405011E
#define PTCR 0xA4050140
#define PUCR 0xA4050142
#define PVCR 0xA4050144
#define PWCR 0xA4050146
#define PXCR 0xA4050148
#define PYCR 0xA405014A
#define PZCR 0xA405014C
#define PSELA 0xA405014E
#define PSELB 0xA4050150
#define PSELC 0xA4050152
#define PSELD 0xA4050154
#define PSELE 0xA4050156
#define HIZCRA 0xA4050158
#define HIZCRB 0xA405015A
#define HIZCRC 0xA405015C
#define HIZCRD 0xA405015E
#define MSELCRA 0xA4050180
#define MSELCRB 0xA4050182
#define PULCR 0xA4050184
#define DRVCRA 0xA405018A
#define DRVCRB 0xA405018C
/* I/O Port */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
#define PDDR 0xA4050126
#define PEDR 0xA4050128
#define PFDR 0xA405012A
#define PGDR 0xA405012C
#define PHDR 0xA405012E
#define PJDR 0xA4050130
#define PKDR 0xA4050132
#define PLDR 0xA4050134
#define PMDR 0xA4050136
#define PNDR 0xA4050138
#define PQDR 0xA405013A
#define PRDR 0xA405013C
#define PSDR 0xA405013E
#define PTDR 0xA4050160
#define PUDR 0xA4050162
#define PVDR 0xA4050164
#define PWDR 0xA4050166
#define PXDR 0xA4050168
#define PYDR 0xA405016A
#define PZDR 0xA405016C
/* Ether */
#define EDMR 0xA4600000
/* UBC */
/* H-UDI */
#endif /* _ASM_CPU_SH7724_H_ */

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/*
* (C) Copyright 2008, 2011 Renesas Solutions Corp.
*
* SH7734 Internal I/O register
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH7734_H_
#define _ASM_CPU_SH7734_H_
#define CCR 0xFF00001C
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000090d
/* SCIF */
#define SCIF0_BASE 0xFFE40000
#define SCIF1_BASE 0xFFE41000
#define SCIF2_BASE 0xFFE42000
#define SCIF3_BASE 0xFFE43000
#define SCIF4_BASE 0xFFE44000
#define SCIF5_BASE 0xFFE45000
/* Timer */
#define TMU_BASE 0xFFD80000
/* PFC */
#define PMMR (0xFFFC0000)
#define MODESEL0 (0xFFFC004C)
#define MODESEL2 (MODESEL0 + 0x4)
#define MODESEL2_INIT (0x00003000)
#define IPSR0 (0xFFFC001C)
#define IPSR1 (IPSR0 + 0x4)
#define IPSR2 (IPSR0 + 0x8)
#define IPSR3 (IPSR0 + 0xC)
#define IPSR4 (IPSR0 + 0x10)
#define IPSR5 (IPSR0 + 0x14)
#define IPSR6 (IPSR0 + 0x18)
#define IPSR7 (IPSR0 + 0x1C)
#define IPSR8 (IPSR0 + 0x20)
#define IPSR9 (IPSR0 + 0x24)
#define IPSR10 (IPSR0 + 0x28)
#define IPSR11 (IPSR0 + 0x2C)
#define GPSR0 (0xFFFC0004)
#define GPSR1 (GPSR0 + 0x4)
#define GPSR2 (GPSR0 + 0x8)
#define GPSR3 (GPSR0 + 0xC)
#define GPSR4 (GPSR0 + 0x10)
#define GPSR5 (GPSR0 + 0x14)
#endif /* _ASM_CPU_SH7734_H_ */

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/*
* (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SH7750/SH7750S/SH7750R/SH7751/SH7751R
* Internal I/O register
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH7750_H_
#define _ASM_CPU_SH7750_H_
#ifdef CONFIG_CPU_TYPE_R
#define CACHE_OC_NUM_WAYS 2
#define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
#else
#define CACHE_OC_NUM_WAYS 1
#define CCR_CACHE_INIT 0x0000090B
#endif
/* OCN */
#define PTEH 0xFF000000
#define PTEL 0xFF000004
#define TTB 0xFF000008
#define TEA 0xFF00000C
#define MMUCR 0xFF000010
#define BASRA 0xFF000014
#define BASRB 0xFF000018
#define CCR 0xFF00001C
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
#define PTEA 0xFF000034
#define QACR0 0xFF000038
#define QACR1 0xFF00003C
/* UBC */
#define BARA 0xFF200000
#define BAMRA 0xFF200004
#define BBRA 0xFF200008
#define BARB 0xFF20000C
#define BAMRB 0xFF200010
#define BBRB 0xFF200014
#define BDRB 0xFF200018
#define BDMRB 0xFF20001C
#define BRCR 0xFF200020
/* BSC */
#define BCR1 0xFF800000
#define BCR2 0xFF800004
#define BCR3 0xFF800050
#define BCR4 0xFE0A00F0
#define WCR1 0xFF800008
#define WCR2 0xFF80000C
#define WCR3 0xFF800010
#define MCR 0xFF800014
#define PCR 0xFF800018
#define RTCSR 0xFF80001C
#define RTCNT 0xFF800020
#define RTCOR 0xFF800024
#define RFCR 0xFF800028
#define PCTRA 0xFF80002C
#define PDTRA 0xFF800030
#define PCTRB 0xFF800040
#define PDTRB 0xFF800044
#define GPIOIC 0xFF800048
/* DMAC */
#define SAR0 0xFFA00000
#define DAR0 0xFFA00004
#define DMATCR0 0xFFA00008
#define CHCR0 0xFFA0000C
#define SAR1 0xFFA00010
#define DAR1 0xFFA00014
#define DMATCR1 0xFFA00018
#define CHCR1 0xFFA0001C
#define SAR2 0xFFA00020
#define DAR2 0xFFA00024
#define DMATCR2 0xFFA00028
#define CHCR2 0xFFA0002C
#define SAR3 0xFFA00030
#define DAR3 0xFFA00034
#define DMATCR3 0xFFA00038
#define CHCR3 0xFFA0003C
#define DMAOR 0xFFA00040
#define SAR4 0xFFA00050
#define DAR4 0xFFA00054
#define DMATCR4 0xFFA00058
/* CPG */
#define FRQCR 0xFFC00000
#define STBCR 0xFFC00004
#define WTCNT 0xFFC00008
#define WTCSR 0xFFC0000C
#define STBCR2 0xFFC00010
/* RTC */
#define R64CNT 0xFFC80000
#define RSECCNT 0xFFC80004
#define RMINCNT 0xFFC80008
#define RHRCNT 0xFFC8000C
#define RWKCNT 0xFFC80010
#define RDAYCNT 0xFFC80014
#define RMONCNT 0xFFC80018
#define RYRCNT 0xFFC8001C
#define RSECAR 0xFFC80020
#define RMINAR 0xFFC80024
#define RHRAR 0xFFC80028
#define RWKAR 0xFFC8002C
#define RDAYAR 0xFFC80030
#define RMONAR 0xFFC80034
#define RCR1 0xFFC80038
#define RCR2 0xFFC8003C
#define RCR3 0xFFC80050
#define RYRAR 0xFFC80054
/* ICR */
#define ICR 0xFFD00000
#define IPRA 0xFFD00004
#define IPRB 0xFFD00008
#define IPRC 0xFFD0000C
#define IPRD 0xFFD00010
#define INTPRI 0xFE080000
#define INTREQ 0xFE080020
#define INTMSK 0xFE080040
#define INTMSKCL 0xFE080060
/* CPG */
#define CLKSTP 0xFE0A0000
#define CLKSTPCLR 0xFE0A0008
/* TMU */
#define TMU_BASE 0xFFD80000
/* SCI */
#define SCSMR1 0xFFE00000
#define SCF0_BASE SCSMR1
/* SCIF */
#define SCSMR2 0xFFE80000
#define SCIF1_BASE SCSMR2
/* H-UDI */
#define SDIR 0xFFF00000
#define SDDR 0xFFF00008
#define SDINT 0xFFF00014
#endif /* _ASM_CPU_SH7750_H_ */

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/*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH7752_H_
#define _ASM_CPU_SH7752_H_
#define CCR 0xFF00001C
#define WTCNT 0xFFCC0000
#define CCR_CACHE_INIT 0x0000090b
#define CACHE_OC_NUM_WAYS 1
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
/* MMU */
struct mmu_regs {
unsigned int reserved[4];
unsigned int mmucr;
};
#define MMU_BASE ((struct mmu_regs *)0xff000000)
/* Watchdog */
#define WTCSR0 0xffcc0002
#define WRSTCSR_R 0xffcc0003
#define WRSTCSR_W 0xffcc0002
#define WTCSR_PREFIX 0xa500
#define WRSTCSR_PREFIX 0x6900
#define WRSTCSR_WOVF_PREFIX 0x9600
/* SCIF */
#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
/* TMU0 */
#define TMU_BASE 0xFE430000
/* ETHER, GETHER MAC address */
struct ether_mac_regs {
unsigned int reserved[114];
unsigned int mahr;
unsigned int reserved2;
unsigned int malr;
};
#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
/* GETHER */
struct gether_control_regs {
unsigned int gbecont;
};
#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
#define GBECONT_RMII1 0x00020000
#define GBECONT_RMII0 0x00010000
/* SerMux */
struct sermux_regs {
unsigned char smr0;
unsigned char smr1;
unsigned char smr2;
unsigned char smr3;
unsigned char smr4;
unsigned char smr5;
};
#define SERMUX_BASE ((struct sermux_regs *)0xfe470000)
/* USB0/1 */
struct usb_common_regs {
unsigned short reserved[129];
unsigned short suspmode;
};
#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
struct usb0_phy_regs {
unsigned short reset;
unsigned short reserved[4];
unsigned short portsel;
};
#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
struct usb1_port_regs {
unsigned int port1sel;
unsigned int reserved;
unsigned int usb1intsts;
};
#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
struct usb1_alignment_regs {
unsigned int ehcidatac; /* 0xfe4fe018 */
unsigned int reserved[63];
unsigned int ohcidatac;
};
#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
/* GPIO */
struct gpio_regs {
unsigned short pacr;
unsigned short pbcr;
unsigned short pccr;
unsigned short pdcr;
unsigned short pecr;
unsigned short pfcr;
unsigned short pgcr;
unsigned short phcr;
unsigned short picr;
unsigned short pjcr;
unsigned short pkcr;
unsigned short plcr;
unsigned short pmcr;
unsigned short pncr;
unsigned short pocr;
unsigned short reserved;
unsigned short pqcr;
unsigned short prcr;
unsigned short pscr;
unsigned short ptcr;
unsigned short pucr;
unsigned short pvcr;
unsigned short pwcr;
unsigned short pxcr;
unsigned short pycr;
unsigned short pzcr;
unsigned char padr;
unsigned char reserved_a;
unsigned char pbdr;
unsigned char reserved_b;
unsigned char pcdr;
unsigned char reserved_c;
unsigned char pddr;
unsigned char reserved_d;
unsigned char pedr;
unsigned char reserved_e;
unsigned char pfdr;
unsigned char reserved_f;
unsigned char pgdr;
unsigned char reserved_g;
unsigned char phdr;
unsigned char reserved_h;
unsigned char pidr;
unsigned char reserved_i;
unsigned char pjdr;
unsigned char reserved_j;
unsigned char pkdr;
unsigned char reserved_k;
unsigned char pldr;
unsigned char reserved_l;
unsigned char pmdr;
unsigned char reserved_m;
unsigned char pndr;
unsigned char reserved_n;
unsigned char podr;
unsigned char reserved_o;
unsigned char ppdr;
unsigned char reserved_p;
unsigned char pqdr;
unsigned char reserved_q;
unsigned char prdr;
unsigned char reserved_r;
unsigned char psdr;
unsigned char reserved_s;
unsigned char ptdr;
unsigned char reserved_t;
unsigned char pudr;
unsigned char reserved_u;
unsigned char pvdr;
unsigned char reserved_v;
unsigned char pwdr;
unsigned char reserved_w;
unsigned char pxdr;
unsigned char reserved_x;
unsigned char pydr;
unsigned char reserved_y;
unsigned char pzdr;
unsigned char reserved_z;
unsigned short ncer;
unsigned short ncmcr;
unsigned short nccsr;
unsigned char reserved2[2];
unsigned short psel0; /* +0x70 */
unsigned short psel1;
unsigned short psel2;
unsigned short psel3;
unsigned short psel4;
unsigned short psel5;
unsigned short psel6;
unsigned short reserved3[2];
unsigned short psel7;
};
#define GPIO_BASE ((struct gpio_regs *)0xffec0000)
#endif /* ifndef __ASSEMBLY__ */
#endif /* _ASM_CPU_SH7752_H_ */

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/*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH7753_H_
#define _ASM_CPU_SH7753_H_
#define CCR 0xFF00001C
#define WTCNT 0xFFCC0000
#define CCR_CACHE_INIT 0x0000090b
#define CACHE_OC_NUM_WAYS 1
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
/* MMU */
struct mmu_regs {
unsigned int reserved[4];
unsigned int mmucr;
};
#define MMU_BASE ((struct mmu_regs *)0xff000000)
/* Watchdog */
#define WTCSR0 0xffcc0002
#define WRSTCSR_R 0xffcc0003
#define WRSTCSR_W 0xffcc0002
#define WTCSR_PREFIX 0xa500
#define WRSTCSR_PREFIX 0x6900
#define WRSTCSR_WOVF_PREFIX 0x9600
/* SCIF */
#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
/* TMU0 */
#define TMU_BASE 0xFE430000
/* ETHER, GETHER MAC address */
struct ether_mac_regs {
unsigned int reserved[114];
unsigned int mahr;
unsigned int reserved2;
unsigned int malr;
};
#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
/* GETHER */
struct gether_control_regs {
unsigned int gbecont;
};
#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
#define GBECONT_RMII1 0x00020000
#define GBECONT_RMII0 0x00010000
/* SerMux */
struct sermux_regs {
unsigned char smr0;
unsigned char smr1;
unsigned char smr2;
unsigned char smr3;
unsigned char smr4;
unsigned char smr5;
};
#define SERMUX_BASE ((struct sermux_regs *)0xfe470000)
/* USB0/1 */
struct usb_common_regs {
unsigned short reserved[129];
unsigned short suspmode;
};
#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
struct usb0_phy_regs {
unsigned short reset;
unsigned short reserved[4];
unsigned short portsel;
};
#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
struct usb1_port_regs {
unsigned int port1sel;
unsigned int reserved;
unsigned int usb1intsts;
};
#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
struct usb1_alignment_regs {
unsigned int ehcidatac; /* 0xfe4fe018 */
unsigned int reserved[63];
unsigned int ohcidatac;
};
#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
/* GPIO */
struct gpio_regs {
unsigned short pacr;
unsigned short pbcr;
unsigned short pccr;
unsigned short pdcr;
unsigned short pecr;
unsigned short pfcr;
unsigned short pgcr;
unsigned short phcr;
unsigned short picr;
unsigned short pjcr;
unsigned short pkcr;
unsigned short plcr;
unsigned short pmcr;
unsigned short pncr;
unsigned short pocr;
unsigned short reserved;
unsigned short pqcr;
unsigned short prcr;
unsigned short pscr;
unsigned short ptcr;
unsigned short pucr;
unsigned short pvcr;
unsigned short pwcr;
unsigned short pxcr;
unsigned short pycr;
unsigned short pzcr;
unsigned char padr;
unsigned char reserved_a;
unsigned char pbdr;
unsigned char reserved_b;
unsigned char pcdr;
unsigned char reserved_c;
unsigned char pddr;
unsigned char reserved_d;
unsigned char pedr;
unsigned char reserved_e;
unsigned char pfdr;
unsigned char reserved_f;
unsigned char pgdr;
unsigned char reserved_g;
unsigned char phdr;
unsigned char reserved_h;
unsigned char pidr;
unsigned char reserved_i;
unsigned char pjdr;
unsigned char reserved_j;
unsigned char pkdr;
unsigned char reserved_k;
unsigned char pldr;
unsigned char reserved_l;
unsigned char pmdr;
unsigned char reserved_m;
unsigned char pndr;
unsigned char reserved_n;
unsigned char podr;
unsigned char reserved_o;
unsigned char ppdr;
unsigned char reserved_p;
unsigned char pqdr;
unsigned char reserved_q;
unsigned char prdr;
unsigned char reserved_r;
unsigned char psdr;
unsigned char reserved_s;
unsigned char ptdr;
unsigned char reserved_t;
unsigned char pudr;
unsigned char reserved_u;
unsigned char pvdr;
unsigned char reserved_v;
unsigned char pwdr;
unsigned char reserved_w;
unsigned char pxdr;
unsigned char reserved_x;
unsigned char pydr;
unsigned char reserved_y;
unsigned char pzdr;
unsigned char reserved_z;
unsigned short ncer;
unsigned short ncmcr;
unsigned short nccsr;
unsigned char reserved2[2];
unsigned short psel0; /* +0x70 */
unsigned short psel1;
unsigned short psel2;
unsigned short psel3;
unsigned short psel4;
unsigned short psel5;
unsigned short psel6;
unsigned short reserved3[2];
unsigned short psel7;
};
#define GPIO_BASE ((struct gpio_regs *)0xffec0000)
#endif /* ifndef __ASSEMBLY__ */
#endif /* _ASM_CPU_SH7753_H_ */

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/*
* Copyright (C) 2011 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH7757_H_
#define _ASM_CPU_SH7757_H_
#define CCR 0xFF00001C
#define WTCNT 0xFFCC0000
#define CCR_CACHE_INIT 0x0000090b
#define CACHE_OC_NUM_WAYS 1
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
/* MMU */
struct mmu_regs {
unsigned int reserved[4];
unsigned int mmucr;
};
#define MMU_BASE ((struct mmu_regs *)0xff000000)
/* Watchdog */
#define WTCSR0 0xffcc0002
#define WRSTCSR_R 0xffcc0003
#define WRSTCSR_W 0xffcc0002
#define WTCSR_PREFIX 0xa500
#define WRSTCSR_PREFIX 0x6900
#define WRSTCSR_WOVF_PREFIX 0x9600
/* SCIF */
#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
/* SerMux */
#define SMR0 0xfe470000
/* TMU0 */
#define TMU_BASE 0xFE430000
/* ETHER, GETHER MAC address */
struct ether_mac_regs {
unsigned int reserved[114];
unsigned int mahr;
unsigned int reserved2;
unsigned int malr;
};
#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
/* GETHER */
struct gether_control_regs {
unsigned int gbecont;
};
#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
#define GBECONT_RMII1 0x00020000
#define GBECONT_RMII0 0x00010000
/* USB0/1 */
struct usb_common_regs {
unsigned short reserved[129];
unsigned short suspmode;
};
#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
struct usb0_phy_regs {
unsigned short reset;
unsigned short reserved[4];
unsigned short portsel;
};
#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
struct usb1_port_regs {
unsigned int port1sel;
unsigned int reserved;
unsigned int usb1intsts;
};
#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
struct usb1_alignment_regs {
unsigned int ehcidatac; /* 0xfe4fe018 */
unsigned int reserved[63];
unsigned int ohcidatac;
};
#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
/* GCTRL, GRA */
struct gctrl_regs {
unsigned int wprotect;
unsigned int gplldiv;
unsigned int gracr2; /* GRA */
unsigned int gracr3; /* GRA */
unsigned int reserved[4];
unsigned int fcntcr1;
unsigned int fcntcr2;
unsigned int reserved2[2];
unsigned int gpll1div;
unsigned int vcompsel;
unsigned int reserved3[62];
unsigned int fdlmon;
unsigned int reserved4[2];
unsigned int flcrmon;
unsigned int reserved5[944];
unsigned int spibootcan;
};
#define GCTRL_BASE ((struct gctrl_regs *)0xffc10000)
/* PCIe setup */
struct pcie_setup_regs {
unsigned int pbictl0;
unsigned int gradevctl;
unsigned int reserved[2];
unsigned int bmcinf[6];
unsigned int reserved2[118];
unsigned int idset[2];
unsigned int subidset;
unsigned int reserved3[2];
unsigned int linkconfset[4];
unsigned int trsid;
unsigned int reserved4[6];
unsigned int toutset;
unsigned int reserved5[7];
unsigned int lad0;
unsigned int ladmsk0;
unsigned int lad1;
unsigned int ladmsk1;
unsigned int lad2;
unsigned int ladmsk2;
unsigned int lad3;
unsigned int ladmsk3;
unsigned int lad4;
unsigned int ladmsk4;
unsigned int lad5;
unsigned int ladmsk5;
unsigned int reserved6[94];
unsigned int vdmrxvid[2];
unsigned int reserved7;
unsigned int pbiintfr;
unsigned int pbiinten;
unsigned int msimap;
unsigned int barmap;
unsigned int baracsize;
unsigned int advserest;
unsigned int pbictl3;
unsigned int reserved8[8];
unsigned int pbictl1;
unsigned int scratch0;
unsigned int reserved9[6];
unsigned int pbictl2;
unsigned int reserved10;
unsigned int pbirev;
};
#define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000)
struct pcie_system_bus_regs {
unsigned int reserved[3];
unsigned int endictl0;
unsigned int endictl1;
};
#define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600)
/* PCIe-Bridge */
struct pciebrg_regs {
unsigned short ctrl_h8s;
unsigned short reserved[7];
unsigned short cp_addr;
unsigned short reserved2;
unsigned short cp_data;
unsigned short reserved3;
unsigned short cp_ctrl;
};
#define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000)
/* CPU version */
#define CCN_PRR 0xff000044
#define prr_mask(_val) ((_val >> 4) & 0xff)
#define PRR_SH7757_B0 0x10
#define PRR_SH7757_C0 0x11
#define is_sh7757_b0(_val) \
({ \
int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \
__ret; \
})
#endif /* ifndef __ASSEMBLY__ */
#endif /* _ASM_CPU_SH7757_H_ */

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/*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CPU_SH7763_H_
#define _ASM_CPU_SH7763_H_
/* CACHE */
#define CACHE_OC_NUM_WAYS 1
#define CCR 0xFF00001C
#define CCR_CACHE_INIT 0x0000090b
/* SCIF */
/* SCIF0 */
#define SCIF0_BASE SCSMR0
#define SCSMR0 0xFFE00000
/* SCIF1 */
#define SCIF1_BASE SCSMR1
#define SCSMR1 0xFFE08000
/* SCIF2 */
#define SCIF2_BASE SCSMR2
#define SCSMR2 0xFFE10000
/* Watchdog Timer */
#define WTCNT WDTST
#define WDTST 0xFFCC0000
/* TMU */
#define TMU_BASE 0xFFD80000
#endif /* _ASM_CPU_SH7763_H_ */

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#ifndef _ASM_CPU_SH7780_H_
#define _ASM_CPU_SH7780_H_
/*
* Copyright (c) 2007,2008 Nobuhiro Iwamatsu
* Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define CACHE_OC_NUM_WAYS 1
#define CCR_CACHE_INIT 0x0000090b
/* Exceptions */
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
/* Memory Management Unit */
#define PTEH 0xFF000000
#define PTEL 0xFF000004
#define TTB 0xFF000008
#define TEA 0xFF00000C
#define MMUCR 0xFF000010
#define PASCR 0xFF000070
#define IRMCR 0xFF000078
/* Cache Controller */
#define CCR 0xFF00001C
#define QACR0 0xFF000038
#define QACR1 0xFF00003C
#define RAMCR 0xFF000074
/* L Memory */
#define RAMCR 0xFF000074
#define LSA0 0xFF000050
#define LSA1 0xFF000054
#define LDA0 0xFF000058
#define LDA1 0xFF00005C
/* Interrupt Controller */
#define ICR0 0xFFD00000
#define ICR1 0xFFD0001C
#define INTPRI 0xFFD00010
#define INTREQ 0xFFD00024
#define INTMSK0 0xFFD00044
#define INTMSK1 0xFFD00048
#define INTMSK2 0xFFD40080
#define INTMSKCLR0 0xFFD00064
#define INTMSKCLR1 0xFFD00068
#define INTMSKCLR2 0xFFD40084
#define NMIFCR 0xFFD000C0
#define USERIMASK 0xFFD30000
#define INT2PRI0 0xFFD40000
#define INT2PRI1 0xFFD40004
#define INT2PRI2 0xFFD40008
#define INT2PRI3 0xFFD4000C
#define INT2PRI4 0xFFD40010
#define INT2PRI5 0xFFD40014
#define INT2PRI6 0xFFD40018
#define INT2PRI7 0xFFD4001C
#define INT2A0 0xFFD40030
#define INT2A1 0xFFD40034
#define INT2MSKR 0xFFD40038
#define INT2MSKCR 0xFFD4003C
#define INT2B0 0xFFD40040
#define INT2B1 0xFFD40044
#define INT2B2 0xFFD40048
#define INT2B3 0xFFD4004C
#define INT2B4 0xFFD40050
#define INT2B5 0xFFD40054
#define INT2B6 0xFFD40058
#define INT2B7 0xFFD4005C
#define INT2GPIC 0xFFD40090
/* local Bus State Controller */
#define MMSELR 0xFF400020
#define BCR 0xFF801000
#define CS0BCR 0xFF802000
#define CS1BCR 0xFF802010
#define CS2BCR 0xFF802020
#define CS4BCR 0xFF802040
#define CS5BCR 0xFF802050
#define CS6BCR 0xFF802060
#define CS0WCR 0xFF802008
#define CS1WCR 0xFF802018
#define CS2WCR 0xFF802028
#define CS4WCR 0xFF802048
#define CS5WCR 0xFF802058
#define CS6WCR 0xFF802068
#define CS5PCR 0xFF802070
#define CS6PCR 0xFF802080
/* DDR-SDRAM I/F */
#define MIM_1 0xFE800008
#define MIM_2 0xFE80000C
#define SCR_1 0xFE800010
#define SCR_2 0xFE800014
#define STR_1 0xFE800018
#define STR_2 0xFE80001C
#define SDR_1 0xFE800030
#define SDR_2 0xFE800034
#define DBK_1 0xFE800400
#define DBK_2 0xFE800404
/* PCI Controller */
#define SH7780_PCIECR 0xFE000008
#define SH7780_PCIVID 0xFE040000
#define SH7780_PCIDID 0xFE040002
#define SH7780_PCICMD 0xFE040004
#define SH7780_PCISTATUS 0xFE040006
#define SH7780_PCIRID 0xFE040008
#define SH7780_PCIPIF 0xFE040009
#define SH7780_PCISUB 0xFE04000A
#define SH7780_PCIBCC 0xFE04000B
#define SH7780_PCICLS 0xFE04000C
#define SH7780_PCILTM 0xFE04000D
#define SH7780_PCIHDR 0xFE04000E
#define SH7780_PCIBIST 0xFE04000F
#define SH7780_PCIIBAR 0xFE040010
#define SH7780_PCIMBAR0 0xFE040014
#define SH7780_PCIMBAR1 0xFE040018
#define SH7780_PCISVID 0xFE04002C
#define SH7780_PCISID 0xFE04002E
#define SH7780_PCICP 0xFE040034
#define SH7780_PCIINTLINE 0xFE04003C
#define SH7780_PCIINTPIN 0xFE04003D
#define SH7780_PCIMINGNT 0xFE04003E
#define SH7780_PCIMAXLAT 0xFE04003F
#define SH7780_PCICID 0xFE040040
#define SH7780_PCINIP 0xFE040041
#define SH7780_PCIPMC 0xFE040042
#define SH7780_PCIPMCSR 0xFE040044
#define SH7780_PCIPMCSRBSE 0xFE040046
#define SH7780_PCI_CDD 0xFE040047
#define SH7780_PCICR 0xFE040100
#define SH7780_PCILSR0 0xFE040104
#define SH7780_PCILSR1 0xFE040108
#define SH7780_PCILAR0 0xFE04010C
#define SH7780_PCILAR1 0xFE040110
#define SH7780_PCIIR 0xFE040114
#define SH7780_PCIIMR 0xFE040118
#define SH7780_PCIAIR 0xFE04011C
#define SH7780_PCICIR 0xFE040120
#define SH7780_PCIAINT 0xFE040130
#define SH7780_PCIAINTM 0xFE040134
#define SH7780_PCIBMIR 0xFE040138
#define SH7780_PCIPAR 0xFE0401C0
#define SH7780_PCIPINT 0xFE0401CC
#define SH7780_PCIPINTM 0xFE0401D0
#define SH7780_PCIMBR0 0xFE0401E0
#define SH7780_PCIMBMR0 0xFE0401E4
#define SH7780_PCIMBR1 0xFE0401E8
#define SH7780_PCIMBMR1 0xFE0401EC
#define SH7780_PCIMBR2 0xFE0401F0
#define SH7780_PCIMBMR2 0xFE0401F4
#define SH7780_PCIIOBR 0xFE0401F8
#define SH7780_PCIIOBMR 0xFE0401FC
#define SH7780_PCICSCR0 0xFE040210
#define SH7780_PCICSCR1 0xFE040214
#define SH7780_PCICSAR0 0xFE040218
#define SH7780_PCICSAR1 0xFE04021C
#define SH7780_PCIPDR 0xFE040220
/* DMAC */
#define DMAC_SAR0 0xFC808020
#define DMAC_DAR0 0xFC808024
#define DMAC_TCR0 0xFC808028
#define DMAC_CHCR0 0xFC80802C
#define DMAC_SAR1 0xFC808030
#define DMAC_DAR1 0xFC808034
#define DMAC_TCR1 0xFC808038
#define DMAC_CHCR1 0xFC80803C
#define DMAC_SAR2 0xFC808040
#define DMAC_DAR2 0xFC808044
#define DMAC_TCR2 0xFC808048
#define DMAC_CHCR2 0xFC80804C
#define DMAC_SAR3 0xFC808050
#define DMAC_DAR3 0xFC808054
#define DMAC_TCR3 0xFC808058
#define DMAC_CHCR3 0xFC80805C
#define DMAC_DMAOR0 0xFC808060
#define DMAC_SAR4 0xFC808070
#define DMAC_DAR4 0xFC808074
#define DMAC_TCR4 0xFC808078
#define DMAC_CHCR4 0xFC80807C
#define DMAC_SAR5 0xFC808080
#define DMAC_DAR5 0xFC808084
#define DMAC_TCR5 0xFC808088
#define DMAC_CHCR5 0xFC80808C
#define DMAC_SARB0 0xFC808120
#define DMAC_DARB0 0xFC808124
#define DMAC_TCRB0 0xFC808128
#define DMAC_SARB1 0xFC808130
#define DMAC_DARB1 0xFC808134
#define DMAC_TCRB1 0xFC808138
#define DMAC_SARB2 0xFC808140
#define DMAC_DARB2 0xFC808144
#define DMAC_TCRB2 0xFC808148
#define DMAC_SARB3 0xFC808150
#define DMAC_DARB3 0xFC808154
#define DMAC_TCRB3 0xFC808158
#define DMAC_DMARS0 0xFC809000
#define DMAC_DMARS1 0xFC809004
#define DMAC_DMARS2 0xFC809008
#define DMAC_SAR6 0xFC818020
#define DMAC_DAR6 0xFC818024
#define DMAC_TCR6 0xFC818028
#define DMAC_CHCR6 0xFC81802C
#define DMAC_SAR7 0xFC818030
#define DMAC_DAR7 0xFC818034
#define DMAC_TCR7 0xFC818038
#define DMAC_CHCR7 0xFC81803C
#define DMAC_SAR8 0xFC818040
#define DMAC_DAR8 0xFC818044
#define DMAC_TCR8 0xFC818048
#define DMAC_CHCR8 0xFC81804C
#define DMAC_SAR9 0xFC818050
#define DMAC_DAR9 0xFC818054
#define DMAC_TCR9 0xFC818058
#define DMAC_CHCR9 0xFC81805C
#define DMAC_DMAOR1 0xFC818060
#define DMAC_SAR10 0xFC818070
#define DMAC_DAR10 0xFC818074
#define DMAC_TCR10 0xFC818078
#define DMAC_CHCR10 0xFC81807C
#define DMAC_SAR11 0xFC818080
#define DMAC_DAR11 0xFC818084
#define DMAC_TCR11 0xFC818088
#define DMAC_CHCR11 0xFC81808C
#define DMAC_SARB6 0xFC818120
#define DMAC_DARB6 0xFC818124
#define DMAC_TCRB6 0xFC818128
#define DMAC_SARB7 0xFC818130
#define DMAC_DARB7 0xFC818134
#define DMAC_TCRB7 0xFC818138
#define DMAC_SARB8 0xFC818140
#define DMAC_DARB8 0xFC818144
#define DMAC_TCRB8 0xFC818148
#define DMAC_SARB9 0xFC818150
#define DMAC_DARB9 0xFC818154
#define DMAC_TCRB9 0xFC818158
/* Clock Pulse Generator */
#define FRQCR 0xFFC80000
#define PLLCR 0xFFC80024
#define MSTPCR 0xFFC80030
/* Watchdog Timer and Reset */
#define WTCNT WDTCNT
#define WDTST 0xFFCC0000
#define WDTCSR 0xFFCC0004
#define WDTBST 0xFFCC0008
#define WDTCNT 0xFFCC0010
#define WDTBCNT 0xFFCC0018
/* System Control */
#define MSTPCR 0xFFC80030
/* Timer Unit */
#define TMU_BASE 0xFFD80000
/* Timer/Counter */
#define CMTCFG 0xFFE30000
#define CMTFRT 0xFFE30004
#define CMTCTL 0xFFE30008
#define CMTIRQS 0xFFE3000C
#define CMTCH0T 0xFFE30010
#define CMTCH0ST 0xFFE30020
#define CMTCH0C 0xFFE30030
#define CMTCH1T 0xFFE30014
#define CMTCH1ST 0xFFE30024
#define CMTCH1C 0xFFE30034
#define CMTCH2T 0xFFE30018
#define CMTCH2C 0xFFE30038
#define CMTCH3T 0xFFE3001C
#define CMTCH3C 0xFFE3003C
/* Realtime Clock */
#define R64CNT 0xFFE80000
#define RSECCNT 0xFFE80004
#define RMINCNT 0xFFE80008
#define RHRCNT 0xFFE8000C
#define RWKCNT 0xFFE80010
#define RDAYCNT 0xFFE80014
#define RMONCNT 0xFFE80018
#define RYRCNT 0xFFE8001C
#define RSECAR 0xFFE80020
#define RMINAR 0xFFE80024
#define RHRAR 0xFFE80028
#define RWKAR 0xFFE8002C
#define RDAYAR 0xFFE80030
#define RMONAR 0xFFE80034
#define RCR1 0xFFE80038
#define RCR2 0xFFE8003C
#define RCR3 0xFFE80050
#define RYRAR 0xFFE80054
/* Serial Communication Interface with FIFO */
#define SCSMR0 0xFFE00000
#define SCIF0_BASE SCSMR0
/* Serial I/O with FIFO */
#define SIMDR 0xFFE20000
#define SISCR 0xFFE20002
#define SITDAR 0xFFE20004
#define SIRDAR 0xFFE20006
#define SICDAR 0xFFE20008
#define SICTR 0xFFE2000C
#define SIFCTR 0xFFE20010
#define SISTR 0xFFE20014
#define SIIER 0xFFE20016
#define SITCR 0xFFE20028
#define SIRCR 0xFFE2002C
#define SPICR 0xFFE20030
/* Serial Protocol Interface */
#define SPCR 0xFFE50000
#define SPSR 0xFFE50004
#define SPSCR 0xFFE50008
#define SPTBR 0xFFE5000C
#define SPRBR 0xFFE50010
/* Multimedia Card Interface */
#define CMDR0 0xFFE60000
#define CMDR1 0xFFE60001
#define CMDR2 0xFFE60002
#define CMDR3 0xFFE60003
#define CMDR4 0xFFE60004
#define CMDR5 0xFFE60005
#define CMDSTRT 0xFFE60006
#define OPCR 0xFFE6000A
#define CSTR 0xFFE6000B
#define INTCR0 0xFFE6000C
#define INTCR1 0xFFE6000D
#define INTSTR0 0xFFE6000E
#define INTSTR1 0xFFE6000F
#define CLKON 0xFFE60010
#define CTOCR 0xFFE60011
#define TBCR 0xFFE60014
#define MODER 0xFFE60016
#define CMDTYR 0xFFE60018
#define RSPTYR 0xFFE60019
#define TBNCR 0xFFE6001A
#define RSPR0 0xFFE60020
#define RSPR1 0xFFE60021
#define RSPR2 0xFFE60022
#define RSPR3 0xFFE60023
#define RSPR4 0xFFE60024
#define RSPR5 0xFFE60025
#define RSPR6 0xFFE60026
#define RSPR7 0xFFE60027
#define RSPR8 0xFFE60028
#define RSPR9 0xFFE60029
#define RSPR10 0xFFE6002A
#define RSPR11 0xFFE6002B
#define RSPR12 0xFFE6002C
#define RSPR13 0xFFE6002D
#define RSPR14 0xFFE6002E
#define RSPR15 0xFFE6002F
#define RSPR16 0xFFE60030
#define RSPRD 0xFFE60031
#define DTOUTR 0xFFE60032
#define DR 0xFFE60040
#define DMACR 0xFFE60044
#define INTCR2 0xFFE60046
#define INTSTR2 0xFFE60048
/* Audio Codec Interface */
#define HACCR 0xFFE40008
#define HACCSAR 0xFFE40020
#define HACCSDR 0xFFE40024
#define HACPCML 0xFFE40028
#define HACPCMR 0xFFE4002C
#define HACTIER 0xFFE40050
#define HACTSR 0xFFE40054
#define HACRIER 0xFFE40058
#define HACRSR 0xFFE4005C
#define HACACR 0xFFE40060
/* Serial Sound Interface */
#define SSICR 0xFFE70000
#define SSISR 0xFFE70004
#define SSITDR 0xFFE70008
#define SSIRDR 0xFFE7000C
/* Flash memory Controller */
#define FLCMNCR 0xFFE90000
#define FLCMDCR 0xFFE90004
#define FLCMCDR 0xFFE90008
#define FLADR 0xFFE9000C
#define FLDATAR 0xFFE90010
#define FLDTCNTR 0xFFE90014
#define FLINTDMACR 0xFFE90018
#define FLBSYTMR 0xFFE9001C
#define FLBSYCNT 0xFFE90020
#define FLTRCR 0xFFE9002C
/* General Purpose I/O */
#define PACR 0xFFEA0000
#define PBCR 0xFFEA0002
#define PCCR 0xFFEA0004
#define PDCR 0xFFEA0006
#define PECR 0xFFEA0008
#define PFCR 0xFFEA000A
#define PGCR 0xFFEA000C
#define PHCR 0xFFEA000E
#define PJCR 0xFFEA0010
#define PKCR 0xFFEA0012
#define PLCR 0xFFEA0014
#define PMCR 0xFFEA0016
#define PADR 0xFFEA0020
#define PBDR 0xFFEA0022
#define PCDR 0xFFEA0024
#define PDDR 0xFFEA0026
#define PEDR 0xFFEA0028
#define PFDR 0xFFEA002A
#define PGDR 0xFFEA002C
#define PHDR 0xFFEA002E
#define PJDR 0xFFEA0030
#define PKDR 0xFFEA0032
#define PLDR 0xFFEA0034
#define PMDR 0xFFEA0036
#define PEPUPR 0xFFEA0048
#define PHPUPR 0xFFEA004E
#define PJPUPR 0xFFEA0050
#define PKPUPR 0xFFEA0052
#define PMPUPR 0xFFEA0056
#define PPUPR1 0xFFEA0060
#define PPUPR2 0xFFEA0062
#define PMSELR 0xFFEA0080
/* User Break Controller */
#define CBR0 0xFF200000
#define CRR0 0xFF200004
#define CAR0 0xFF200008
#define CAMR0 0xFF20000C
#define CBR1 0xFF200020
#define CRR1 0xFF200024
#define CAR1 0xFF200028
#define CAMR1 0xFF20002C
#define CDR1 0xFF200030
#define CDMR1 0xFF200034
#define CETR1 0xFF200038
#define CCMFR 0xFF200600
#define CBCR 0xFF200620
#endif /* _ASM_CPU_SH7780_H_ */

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#ifndef _ASM_CPU_SH7785_H_
#define _ASM_CPU_SH7785_H_
/*
* Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
* Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define CACHE_OC_NUM_WAYS 1
#define CCR_CACHE_INIT 0x0000090b
/* Exceptions */
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
/* Cache Controller */
#define CCR 0xFF00001C
#define QACR0 0xFF000038
#define QACR1 0xFF00003C
#define RAMCR 0xFF000074
/* Watchdog Timer and Reset */
#define WTCNT WDTCNT
#define WDTST 0xFFCC0000
#define WDTCSR 0xFFCC0004
#define WDTBST 0xFFCC0008
#define WDTCNT 0xFFCC0010
#define WDTBCNT 0xFFCC0018
/* Timer Unit */
#define TMU_BASE 0xFFD80000
/* Serial Communication Interface with FIFO */
#define SCIF1_BASE 0xffeb0000
/* LBSC */
#define MMSELR 0xfc400020
#define LBSC_BASE 0xff800000
#define BCR (LBSC_BASE + 0x1000)
#define CS0BCR (LBSC_BASE + 0x2000)
#define CS1BCR (LBSC_BASE + 0x2010)
#define CS2BCR (LBSC_BASE + 0x2020)
#define CS3BCR (LBSC_BASE + 0x2030)
#define CS4BCR (LBSC_BASE + 0x2040)
#define CS5BCR (LBSC_BASE + 0x2050)
#define CS6BCR (LBSC_BASE + 0x2060)
#define CS0WCR (LBSC_BASE + 0x2008)
#define CS1WCR (LBSC_BASE + 0x2018)
#define CS2WCR (LBSC_BASE + 0x2028)
#define CS3WCR (LBSC_BASE + 0x2038)
#define CS4WCR (LBSC_BASE + 0x2048)
#define CS5WCR (LBSC_BASE + 0x2058)
#define CS6WCR (LBSC_BASE + 0x2068)
#define CS5PCR (LBSC_BASE + 0x2070)
#define CS6PCR (LBSC_BASE + 0x2080)
/* PCI Controller */
#define SH7780_PCIECR 0xFE000008
#define SH7780_PCIVID 0xFE040000
#define SH7780_PCIDID 0xFE040002
#define SH7780_PCICMD 0xFE040004
#define SH7780_PCISTATUS 0xFE040006
#define SH7780_PCIRID 0xFE040008
#define SH7780_PCIPIF 0xFE040009
#define SH7780_PCISUB 0xFE04000A
#define SH7780_PCIBCC 0xFE04000B
#define SH7780_PCICLS 0xFE04000C
#define SH7780_PCILTM 0xFE04000D
#define SH7780_PCIHDR 0xFE04000E
#define SH7780_PCIBIST 0xFE04000F
#define SH7780_PCIIBAR 0xFE040010
#define SH7780_PCIMBAR0 0xFE040014
#define SH7780_PCIMBAR1 0xFE040018
#define SH7780_PCISVID 0xFE04002C
#define SH7780_PCISID 0xFE04002E
#define SH7780_PCICP 0xFE040034
#define SH7780_PCIINTLINE 0xFE04003C
#define SH7780_PCIINTPIN 0xFE04003D
#define SH7780_PCIMINGNT 0xFE04003E
#define SH7780_PCIMAXLAT 0xFE04003F
#define SH7780_PCICID 0xFE040040
#define SH7780_PCINIP 0xFE040041
#define SH7780_PCIPMC 0xFE040042
#define SH7780_PCIPMCSR 0xFE040044
#define SH7780_PCIPMCSRBSE 0xFE040046
#define SH7780_PCI_CDD 0xFE040047
#define SH7780_PCICR 0xFE040100
#define SH7780_PCILSR0 0xFE040104
#define SH7780_PCILSR1 0xFE040108
#define SH7780_PCILAR0 0xFE04010C
#define SH7780_PCILAR1 0xFE040110
#define SH7780_PCIIR 0xFE040114
#define SH7780_PCIIMR 0xFE040118
#define SH7780_PCIAIR 0xFE04011C
#define SH7780_PCICIR 0xFE040120
#define SH7780_PCIAINT 0xFE040130
#define SH7780_PCIAINTM 0xFE040134
#define SH7780_PCIBMIR 0xFE040138
#define SH7780_PCIPAR 0xFE0401C0
#define SH7780_PCIPINT 0xFE0401CC
#define SH7780_PCIPINTM 0xFE0401D0
#define SH7780_PCIMBR0 0xFE0401E0
#define SH7780_PCIMBMR0 0xFE0401E4
#define SH7780_PCIMBR1 0xFE0401E8
#define SH7780_PCIMBMR1 0xFE0401EC
#define SH7780_PCIMBR2 0xFE0401F0
#define SH7780_PCIMBMR2 0xFE0401F4
#define SH7780_PCIIOBR 0xFE0401F8
#define SH7780_PCIIOBMR 0xFE0401FC
#define SH7780_PCICSCR0 0xFE040210
#define SH7780_PCICSCR1 0xFE040214
#define SH7780_PCICSAR0 0xFE040218
#define SH7780_PCICSAR1 0xFE04021C
#define SH7780_PCIPDR 0xFE040220
#endif /* _ASM_CPU_SH7780_H_ */

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#include <asm-generic/errno.h>

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u-boot/arch/sh/include/asm/global_data.h Normal file
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/*
* (C) Copyright 2002-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_SH_GLOBALDATA_H_
#define __ASM_SH_GLOBALDATA_H_
/* Architecture-specific global data */
struct arch_global_data {
};
#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13")
#endif /* __ASM_SH_GLOBALDATA_H_ */

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/*
* linux/include/asm-sh/io.h
*
* Copyright (C) 1996-2000 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Modifications:
* 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
* constant addresses and variable addresses.
* 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
* specific IO header files.
* 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
* 04-Apr-1999 PJB Added check_signature.
* 12-Dec-1999 RMK More cleanups
* 18-Jun-2000 RMK Removed virt_to_* and friends definitions
*/
#ifndef __ASM_SH_IO_H
#define __ASM_SH_IO_H
#ifdef __KERNEL__
#include <linux/types.h>
#include <asm/byteorder.h>
/*
* Generic virtual read/write. Note that we don't support half-word
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
* to the architecture specific code.
*/
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
extern void __raw_readsl(unsigned int addr, void *data, int longlen);
#define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a)
#define __raw_writel(v, a) __arch_putl(v, a)
#define __raw_readb(a) __arch_getb(a)
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
/*
* The compiler seems to be incapable of optimising constants
* properly. Spell it out to the compiler in some cases.
* These are only valid for small values of "off" (< 1<<12)
*/
#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off)
#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off)
#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off)
#define __raw_base_readb(base, off) __arch_base_getb(base, off)
#define __raw_base_readw(base, off) __arch_base_getw(base, off)
#define __raw_base_readl(base, off) __arch_base_getl(base, off)
/*
* Now, pick up the machine-defined IO definitions
*/
#if 0 /* XXX###XXX */
#include <asm/arch/io.h>
#endif /* XXX###XXX */
/*
* IO port access primitives
* -------------------------
*
* The SH doesn't have special IO access instructions; all IO is memory
* mapped. Note that these are defined to perform little endian accesses
* only. Their primary purpose is to access PCI and ISA peripherals.
*
* The machine specific io.h include defines __io to translate an "IO"
* address to a memory address.
*
* Note that we prevent GCC re-ordering or caching values in expressions
* by introducing sequence points into the in*() definitions. Note that
* __raw_* do not guarantee this behaviour.
*
* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
*/
#define outb(v, p) __raw_writeb(v, p)
#define outw(v, p) __raw_writew(cpu_to_le16(v), p)
#define outl(v, p) __raw_writel(cpu_to_le32(v), p)
#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; })
#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
#define outsb(p, d, l) __raw_writesb(p, d, l)
#define outsw(p, d, l) __raw_writesw(p, d, l)
#define outsl(p, d, l) __raw_writesl(p, d, l)
#define insb(p, d, l) __raw_readsb(p, d, l)
#define insw(p, d, l) __raw_readsw(p, d, l)
#define insl(p, d, l) __raw_readsl(p, d, l)
#define outb_p(val, port) outb((val), (port))
#define outw_p(val, port) outw((val), (port))
#define outl_p(val, port) outl((val), (port))
#define inb_p(port) inb((port))
#define inw_p(port) inw((port))
#define inl_p(port) inl((port))
#define outsb_p(port, from, len) outsb(port, from, len)
#define outsw_p(port, from, len) outsw(port, from, len)
#define outsl_p(port, from, len) outsl(port, from, len)
#define insb_p(port, to, len) insb(port, to, len)
#define insw_p(port, to, len) insw(port, to, len)
#define insl_p(port, to, len) insl(port, to, len)
/* for U-Boot PCI */
#define out_8(port, val) outb(val, port)
#define out_le16(port, val) outw(val, port)
#define out_le32(port, val) outl(val, port)
#define in_8(port) inb(port)
#define in_le16(port) inw(port)
#define in_le32(port) inl(port)
/*
* ioremap and friends.
*
* ioremap takes a PCI memory address, as specified in
* linux/Documentation/IO-mapping.txt. If you want a
* physical address, use __ioremap instead.
*/
extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
extern void __iounmap(void *addr);
/*
* Generic ioremap support.
*
* Define:
* iomem_valid_addr(off,size)
* iomem_to_phys(off)
*/
#ifdef iomem_valid_addr
#define __arch_ioremap(off, sz, nocache) \
({ \
unsigned long _off = (off), _size = (sz); \
void *_ret = (void *)0; \
if (iomem_valid_addr(_off, _size)) \
_ret = __ioremap(iomem_to_phys(_off), _size, 0); \
_ret; \
})
#define __arch_iounmap __iounmap
#endif
#define ioremap(off, sz) __arch_ioremap((off), (sz), 0)
#define ioremap_nocache(off, sz) __arch_ioremap((off), (sz), 1)
#define iounmap(_addr) __arch_iounmap(_addr)
/*
* DMA-consistent mapping functions. These allocate/free a region of
* uncached, unwrite-buffered mapped memory space for use with DMA
* devices. This is the "generic" version. The PCI specific version
* is in pci.h
*/
extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
extern void consistent_sync(void *vaddr, size_t size, int rw);
/*
* String version of IO memory access ops:
*/
extern void _memcpy_fromio(void *, unsigned long, size_t);
extern void _memcpy_toio(unsigned long, const void *, size_t);
extern void _memset_io(unsigned long, int, size_t);
/*
* If this architecture has PCI memory IO, then define the read/write
* macros. These should only be used with the cookie passed from
* ioremap.
*/
#ifdef __mem_pci
#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
#define readw(c)\
({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
#define readl(c)\
({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
#define writeb(v, c) __raw_writeb(v, __mem_pci(c))
#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
#define eth_io_copy_and_sum(s, c, l, b) \
eth_copy_and_sum((s), __mem_pci(c), (l), (b))
static inline int
check_signature(unsigned long io_addr, const unsigned char *signature,
int length)
{
int retval = 0;
do {
if (readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
#elif !defined(readb)
#define readb(addr) __raw_readb(addr)
#define readw(addr) __raw_readw(addr)
#define readl(addr) __raw_readl(addr)
#define writeb(v, addr) __raw_writeb(v, addr)
#define writew(v, addr) __raw_writew(v, addr)
#define writel(v, addr) __raw_writel(v, addr)
#define check_signature(io, sig, len) (0)
#endif /* __mem_pci */
static inline void sync(void)
{
}
/*
* Clear and set bits in one shot. These macros can be used to clear and
* set multiple bits in a register using a single call. These macros can
* also be used to set a multiple-bit bit pattern using a mask, by
* specifying the mask in the 'clear' parameter and the new bit pattern
* in the 'set' parameter.
*/
#define clrbits(type, addr, clear) \
out_##type((addr), in_##type(addr) & ~(clear))
#define setbits(type, addr, set) \
out_##type((addr), in_##type(addr) | (set))
#define clrsetbits(type, addr, clear, set) \
out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
#define setbits_be32(addr, set) setbits(be32, addr, set)
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
#define setbits_le32(addr, set) setbits(le32, addr, set)
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
#define setbits_be16(addr, set) setbits(be16, addr, set)
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
#define setbits_le16(addr, set) setbits(le16, addr, set)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrbits_8(addr, clear) clrbits(8, addr, clear)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
static inline phys_addr_t virt_to_phys(void *vaddr)
{
return (phys_addr_t)(vaddr);
}
#endif /* __KERNEL__ */
#endif /* __ASM_SH_IO_H */

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u-boot/arch/sh/include/asm/irqflags.h Normal file
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#ifndef __ASM_SH_IRQFLAGS_H
#define __ASM_SH_IRQFLAGS_H
static inline void raw_local_irq_enable(void)
{
unsigned long __dummy0, __dummy1;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"and %1, %0\n\t"
#ifdef CONFIG_CPU_HAS_SR_RB
"stc r6_bank, %1\n\t"
"or %1, %0\n\t"
#endif
"ldc %0, sr\n\t"
: "=&r" (__dummy0), "=r" (__dummy1)
: "1" (~0x000000f0)
: "memory"
);
}
static inline void raw_local_irq_disable(void)
{
unsigned long flags;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"or #0xf0, %0\n\t"
"ldc %0, sr\n\t"
: "=&z" (flags)
: /* no inputs */
: "memory"
);
}
static inline void set_bl_bit(void)
{
unsigned long __dummy0, __dummy1;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"or %2, %0\n\t"
"and %3, %0\n\t"
"ldc %0, sr\n\t"
: "=&r" (__dummy0), "=r" (__dummy1)
: "r" (0x10000000), "r" (0xffffff0f)
: "memory"
);
}
static inline void clear_bl_bit(void)
{
unsigned long __dummy0, __dummy1;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"and %2, %0\n\t"
"ldc %0, sr\n\t"
: "=&r" (__dummy0), "=r" (__dummy1)
: "1" (~0x10000000)
: "memory"
);
}
static inline unsigned long __raw_local_save_flags(void)
{
unsigned long flags;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"and #0xf0, %0\n\t"
: "=&z" (flags)
: /* no inputs */
: "memory"
);
return flags;
}
#define raw_local_save_flags(flags) \
do { (flags) = __raw_local_save_flags(); } while (0)
static inline int raw_irqs_disabled_flags(unsigned long flags)
{
return (flags != 0);
}
static inline int raw_irqs_disabled(void)
{
unsigned long flags = __raw_local_save_flags();
return raw_irqs_disabled_flags(flags);
}
static inline unsigned long __raw_local_irq_save(void)
{
unsigned long flags, __dummy;
__asm__ __volatile__ (
"stc sr, %1\n\t"
"mov %1, %0\n\t"
"or #0xf0, %0\n\t"
"ldc %0, sr\n\t"
"mov %1, %0\n\t"
"and #0xf0, %0\n\t"
: "=&z" (flags), "=&r" (__dummy)
: /* no inputs */
: "memory"
);
return flags;
}
#define raw_local_irq_save(flags) \
do { (flags) = __raw_local_irq_save(); } while (0)
#define local_irq_save raw_local_irq_save
static inline void raw_local_irq_restore(unsigned long flags)
{
if ((flags & 0xf0) != 0xf0)
raw_local_irq_enable();
}
#define local_irq_restore raw_local_irq_restore
#endif /* __ASM_SH_IRQFLAGS_H */

39
u-boot/arch/sh/include/asm/macro.h Normal file
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/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MACRO_H__
#define __MACRO_H__
#ifdef __ASSEMBLY__
.macro write32, addr, data
mov.l \addr ,r1
mov.l \data ,r0
mov.l r0, @r1
.endm
.macro write16, addr, data
mov.l \addr ,r1
mov.w \data ,r0
mov.w r0, @r1
.endm
.macro write8, addr, data
mov.l \addr ,r1
mov.l \data ,r0
mov.b r0, @r1
.endm
.macro wait_timer, time
mov.l \time ,r3
1:
nop
tst r3, r3
bf/s 1b
dt r3
.endm
#endif /* __ASSEMBLY__ */
#endif /* __MACRO_H__ */

15
u-boot/arch/sh/include/asm/mmc.h Normal file
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@@ -0,0 +1,15 @@
/*
* Renesas SuperH MMCIF driver.
*
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2012 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0
*
*/
#ifndef _SH_MMC_H_
#define _SH_MMC_H_
int mmcif_mmc_init(void);
#endif /* _SH_MMC_H_ */

32
u-boot/arch/sh/include/asm/pci.h Normal file
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/*
* SH4 PCI Controller (PCIC) for U-Boot.
* (C) Dustin McIntire (dustin@sensoria.com)
* (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* u-boot/include/asm-sh/pci.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_PCI_H_
#define _ASM_PCI_H_
#include <pci.h>
#if defined(CONFIG_SH7751_PCI)
int pci_sh7751_init(struct pci_controller *hose);
#elif defined(CONFIG_SH7780_PCI)
int pci_sh7780_init(struct pci_controller *hose);
#else
#error "Not support PCI."
#endif
int pci_sh4_init(struct pci_controller *hose);
/* PCI dword read for sh4 */
int pci_sh4_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 *value);
/* PCI dword write for sh4 */
int pci_sh4_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value);
#endif /* _ASM_PCI_H_ */

123
u-boot/arch/sh/include/asm/posix_types.h Normal file
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#ifndef __ASM_SH_POSIX_TYPES_H
#define __ASM_SH_POSIX_TYPES_H
/*
* This file is generally used by user-level software, so you need to
* be a little careful about namespace pollution etc. Also, we cannot
* assume GCC is being used.
*/
typedef unsigned short __kernel_dev_t;
typedef unsigned long __kernel_ino_t;
typedef unsigned short __kernel_mode_t;
typedef unsigned short __kernel_nlink_t;
typedef long __kernel_off_t;
typedef int __kernel_pid_t;
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
typedef int __kernel_timer_t;
typedef int __kernel_clockid_t;
typedef int __kernel_daddr_t;
typedef char * __kernel_caddr_t;
typedef unsigned short __kernel_uid16_t;
typedef unsigned short __kernel_gid16_t;
typedef unsigned int __kernel_uid32_t;
typedef unsigned int __kernel_gid32_t;
typedef unsigned short __kernel_old_uid_t;
typedef unsigned short __kernel_old_gid_t;
typedef unsigned short __kernel_old_dev_t;
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
typedef struct {
#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
int __val[2];
#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
#undef __FD_SET
static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
{
unsigned long __tmp = __fd / __NFDBITS;
unsigned long __rem = __fd % __NFDBITS;
__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
}
#undef __FD_CLR
static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
{
unsigned long __tmp = __fd / __NFDBITS;
unsigned long __rem = __fd % __NFDBITS;
__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
}
#undef __FD_ISSET
static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
{
unsigned long __tmp = __fd / __NFDBITS;
unsigned long __rem = __fd % __NFDBITS;
return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
}
/*
* This will unroll the loop for the normal constant case (8 ints,
* for a 256-bit fd_set)
*/
#undef __FD_ZERO
static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
{
unsigned long *__tmp = __p->fds_bits;
int __i;
if (__builtin_constant_p(__FDSET_LONGS)) {
switch (__FDSET_LONGS) {
case 16:
__tmp[ 0] = 0; __tmp[ 1] = 0;
__tmp[ 2] = 0; __tmp[ 3] = 0;
__tmp[ 4] = 0; __tmp[ 5] = 0;
__tmp[ 6] = 0; __tmp[ 7] = 0;
__tmp[ 8] = 0; __tmp[ 9] = 0;
__tmp[10] = 0; __tmp[11] = 0;
__tmp[12] = 0; __tmp[13] = 0;
__tmp[14] = 0; __tmp[15] = 0;
return;
case 8:
__tmp[ 0] = 0; __tmp[ 1] = 0;
__tmp[ 2] = 0; __tmp[ 3] = 0;
__tmp[ 4] = 0; __tmp[ 5] = 0;
__tmp[ 6] = 0; __tmp[ 7] = 0;
return;
case 4:
__tmp[ 0] = 0; __tmp[ 1] = 0;
__tmp[ 2] = 0; __tmp[ 3] = 0;
return;
}
}
__i = __FDSET_LONGS;
while (__i) {
__i--;
*__tmp = 0;
__tmp++;
}
}
#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
#endif /* __ASM_SH_POSIX_TYPES_H */

10
u-boot/arch/sh/include/asm/processor.h Normal file
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#ifndef _ASM_SH_PROCESSOR_H_
#define _ASM_SH_PROCESSOR_H_
#if defined(CONFIG_CPU_SH2)
# include <asm/cpu_sh2.h>
#elif defined(CONFIG_CPU_SH3)
# include <asm/cpu_sh3.h>
#elif defined(CONFIG_CPU_SH4)
# include <asm/cpu_sh4.h>
#endif
#endif

112
u-boot/arch/sh/include/asm/ptrace.h Normal file
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#ifndef __ASM_SH_PTRACE_H
#define __ASM_SH_PTRACE_H
/*
* Copyright (C) 1999, 2000 Niibe Yutaka
* from linux kernel code.
*/
/*
* GCC defines register number like this:
* -----------------------------
* 0 - 15 are integer registers
* 17 - 22 are control/special registers
* 24 - 39 fp registers
* 40 - 47 xd registers
* 48 - fpscr register
* -----------------------------
*
* We follows above, except:
* 16 --- program counter (PC)
* 22 --- syscall #
* 23 --- floating point communication register
*/
#define REG_REG0 0
#define REG_REG15 15
#define REG_PC 16
#define REG_PR 17
#define REG_SR 18
#define REG_GBR 19
#define REG_MACH 20
#define REG_MACL 21
#define REG_SYSCALL 22
#define REG_FPREG0 23
#define REG_FPREG15 38
#define REG_XFREG0 39
#define REG_XFREG15 54
#define REG_FPSCR 55
#define REG_FPUL 56
/* options set using PTRACE_SETOPTIONS */
#define PTRACE_O_TRACESYSGOOD 0x00000001
/*
* This struct defines the way the registers are stored on the
* kernel stack during a system call or other kernel entry.
*/
struct pt_regs {
unsigned long regs[16];
unsigned long pc;
unsigned long pr;
unsigned long sr;
unsigned long gbr;
unsigned long mach;
unsigned long macl;
long tra;
};
/*
* This struct defines the way the DSP registers are stored on the
* kernel stack during a system call or other kernel entry.
*/
struct pt_dspregs {
unsigned long a1;
unsigned long a0g;
unsigned long a1g;
unsigned long m0;
unsigned long m1;
unsigned long a0;
unsigned long x0;
unsigned long x1;
unsigned long y0;
unsigned long y1;
unsigned long dsr;
unsigned long rs;
unsigned long re;
unsigned long mod;
};
#define PTRACE_GETDSPREGS 55
#define PTRACE_SETDSPREGS 56
#ifdef __KERNEL__
#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
#define instruction_pointer(regs) ((regs)->pc)
extern void show_regs(struct pt_regs *);
#ifdef CONFIG_SH_DSP
#define task_pt_regs(task) \
((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
- sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
#else
#define task_pt_regs(task) \
((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
- sizeof(unsigned long)) - 1)
#endif
static inline unsigned long profile_pc(struct pt_regs *regs)
{
unsigned long pc = instruction_pointer(regs);
if (pc >= 0xa0000000UL && pc < 0xc0000000UL)
pc -= 0x20000000;
return pc;
}
#endif
#endif /* __ASM_SH_PTRACE_H */

11
u-boot/arch/sh/include/asm/sections.h Normal file
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/*
* Copyright (c) 2012 The Chromium OS Authors.
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_SH_SECTIONS_H
#define __ASM_SH_SECTIONS_H
#include <asm-generic/sections.h>
#endif

162
u-boot/arch/sh/include/asm/string.h Normal file
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#ifndef __ASM_SH_STRING_H
#define __ASM_SH_STRING_H
/*
* Copyright (C) 1999 Niibe Yutaka
* But consider these trivial functions to be public domain.
*
* from linux kernel code.
*/
#ifdef __KERNEL__ /* only set these up for kernel code */
#define __HAVE_ARCH_STRCPY
static inline char *strcpy(char *__dest, const char *__src)
{
register char *__xdest = __dest;
unsigned long __dummy;
__asm__ __volatile__("1:\n\t"
"mov.b @%1+, %2\n\t"
"mov.b %2, @%0\n\t"
"cmp/eq #0, %2\n\t"
"bf/s 1b\n\t"
" add #1, %0\n\t"
: "=r" (__dest), "=r" (__src), "=&z" (__dummy)
: "0" (__dest), "1" (__src)
: "memory", "t");
return __xdest;
}
#define __HAVE_ARCH_STRNCPY
static inline char *strncpy(char *__dest, const char *__src, size_t __n)
{
register char *__xdest = __dest;
unsigned long __dummy;
if (__n == 0)
return __xdest;
__asm__ __volatile__(
"1:\n"
"mov.b @%1+, %2\n\t"
"mov.b %2, @%0\n\t"
"cmp/eq #0, %2\n\t"
"bt/s 2f\n\t"
" cmp/eq %5,%1\n\t"
"bf/s 1b\n\t"
" add #1, %0\n"
"2:"
: "=r" (__dest), "=r" (__src), "=&z" (__dummy)
: "0" (__dest), "1" (__src), "r" (__src+__n)
: "memory", "t");
return __xdest;
}
#define __HAVE_ARCH_STRCMP
static inline int strcmp(const char *__cs, const char *__ct)
{
register int __res;
unsigned long __dummy;
__asm__ __volatile__(
"mov.b @%1+, %3\n"
"1:\n\t"
"mov.b @%0+, %2\n\t"
"cmp/eq #0, %3\n\t"
"bt 2f\n\t"
"cmp/eq %2, %3\n\t"
"bt/s 1b\n\t"
" mov.b @%1+, %3\n\t"
"add #-2, %1\n\t"
"mov.b @%1, %3\n\t"
"sub %3, %2\n"
"2:"
: "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
: "0" (__cs), "1" (__ct)
: "t");
return __res;
}
#define __HAVE_ARCH_STRNCMP
static inline int strncmp(const char *__cs, const char *__ct, size_t __n)
{
register int __res;
unsigned long __dummy;
if (__n == 0)
return 0;
__asm__ __volatile__(
"mov.b @%1+, %3\n"
"1:\n\t"
"mov.b @%0+, %2\n\t"
"cmp/eq %6, %0\n\t"
"bt/s 2f\n\t"
" cmp/eq #0, %3\n\t"
"bt/s 3f\n\t"
" cmp/eq %3, %2\n\t"
"bt/s 1b\n\t"
" mov.b @%1+, %3\n\t"
"add #-2, %1\n\t"
"mov.b @%1, %3\n"
"2:\n\t"
"sub %3, %2\n"
"3:"
:"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
: "0" (__cs), "1" (__ct), "r" (__cs+__n)
: "t");
return __res;
}
#undef __HAVE_ARCH_MEMSET
extern void *memset(void *__s, int __c, size_t __count);
#undef __HAVE_ARCH_MEMCPY
extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
#undef __HAVE_ARCH_MEMMOVE
extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
#undef __HAVE_ARCH_MEMCHR
extern void *memchr(const void *__s, int __c, size_t __n);
#undef __HAVE_ARCH_STRLEN
extern size_t strlen(const char *);
/* arch/sh/lib/strcasecmp.c */
extern int strcasecmp(const char *, const char *);
#else /* KERNEL */
/*
* let user libraries deal with these,
* IMHO the kernel has no place defining these functions for user apps
*/
#define __HAVE_ARCH_STRCPY 1
#define __HAVE_ARCH_STRNCPY 1
#define __HAVE_ARCH_STRCAT 1
#define __HAVE_ARCH_STRNCAT 1
#define __HAVE_ARCH_STRCMP 1
#define __HAVE_ARCH_STRNCMP 1
#define __HAVE_ARCH_STRNICMP 1
#define __HAVE_ARCH_STRCHR 1
#define __HAVE_ARCH_STRRCHR 1
#define __HAVE_ARCH_STRSTR 1
#define __HAVE_ARCH_STRLEN 1
#define __HAVE_ARCH_STRNLEN 1
#define __HAVE_ARCH_MEMSET 1
#define __HAVE_ARCH_MEMCPY 1
#define __HAVE_ARCH_MEMMOVE 1
#define __HAVE_ARCH_MEMSCAN 1
#define __HAVE_ARCH_MEMCMP 1
#define __HAVE_ARCH_MEMCHR 1
#define __HAVE_ARCH_STRTOK 1
#endif /* KERNEL */
#endif /* __ASM_SH_STRING_H */

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#ifndef __ASM_SH_SYSTEM_H
#define __ASM_SH_SYSTEM_H
/*
* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
* Copyright (C) 2002 Paul Mundt
*
* from linux kernel code.
*/
#include <asm/irqflags.h>
#include <asm/types.h>
/*
* switch_to() should switch tasks to task nr n, first
*/
#define switch_to(prev, next, last) do { \
struct task_struct *__last; \
register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
__asm__ __volatile__ (".balign 4\n\t" \
"stc.l gbr, @-r15\n\t" \
"sts.l pr, @-r15\n\t" \
"mov.l r8, @-r15\n\t" \
"mov.l r9, @-r15\n\t" \
"mov.l r10, @-r15\n\t" \
"mov.l r11, @-r15\n\t" \
"mov.l r12, @-r15\n\t" \
"mov.l r13, @-r15\n\t" \
"mov.l r14, @-r15\n\t" \
"mov.l r15, @r1 ! save SP\n\t" \
"mov.l @r6, r15 ! change to new stack\n\t" \
"mova 1f, %0\n\t" \
"mov.l %0, @r2 ! save PC\n\t" \
"mov.l 2f, %0\n\t" \
"jmp @%0 ! call __switch_to\n\t" \
" lds r7, pr ! with return to new PC\n\t" \
".balign 4\n" \
"2:\n\t" \
".long __switch_to\n" \
"1:\n\t" \
"mov.l @r15+, r14\n\t" \
"mov.l @r15+, r13\n\t" \
"mov.l @r15+, r12\n\t" \
"mov.l @r15+, r11\n\t" \
"mov.l @r15+, r10\n\t" \
"mov.l @r15+, r9\n\t" \
"mov.l @r15+, r8\n\t" \
"lds.l @r15+, pr\n\t" \
"ldc.l @r15+, gbr\n\t" \
: "=z" (__last) \
: "r" (__ts1), "r" (__ts2), "r" (__ts4), \
"r" (__ts5), "r" (__ts6), "r" (__ts7) \
: "r3", "t"); \
last = __last; \
} while (0)
/*
* On SMP systems, when the scheduler does migration-cost autodetection,
* it needs a way to flush as much of the CPU's caches as possible.
*
* TODO: fill this in!
*/
static inline void sched_cacheflush(void)
{
}
#ifdef CONFIG_CPU_SH4A
#define __icbi() \
{ \
unsigned long __addr; \
__addr = 0xa8000000; \
__asm__ __volatile__( \
"icbi %0\n\t" \
: /* no output */ \
: "m" (__m(__addr))); \
}
#endif
static inline unsigned long tas(volatile int *m)
{
unsigned long retval;
__asm__ __volatile__ ("tas.b @%1\n\t"
"movt %0"
: "=r" (retval): "r" (m): "t", "memory");
return retval;
}
/*
* A brief note on ctrl_barrier(), the control register write barrier.
*
* Legacy SH cores typically require a sequence of 8 nops after
* modification of a control register in order for the changes to take
* effect. On newer cores (like the sh4a and sh5) this is accomplished
* with icbi.
*
* Also note that on sh4a in the icbi case we can forego a synco for the
* write barrier, as it's not necessary for control registers.
*
* Historically we have only done this type of barrier for the MMUCR, but
* it's also necessary for the CCR, so we make it generic here instead.
*/
#ifdef CONFIG_CPU_SH4A
#define mb() __asm__ __volatile__ ("synco": : :"memory")
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("synco": : :"memory")
#define ctrl_barrier() __icbi()
#define read_barrier_depends() do { } while(0)
#else
#define mb() __asm__ __volatile__ ("": : :"memory")
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("": : :"memory")
#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
#define read_barrier_depends() do { } while(0)
#endif
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() wmb()
#define smp_read_barrier_depends() read_barrier_depends()
#else
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#define smp_read_barrier_depends() do { } while(0)
#endif
#define set_mb(var, value) do { xchg(&var, value); } while (0)
/*
* Jump to P2 area.
* When handling TLB or caches, we need to do it from P2 area.
*/
#define jump_to_P2() \
do { \
unsigned long __dummy; \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"or %1, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy) \
: "r" (0x20000000)); \
} while (0)
/*
* Back to P1 area.
*/
#define back_to_P1() \
do { \
unsigned long __dummy; \
ctrl_barrier(); \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy)); \
} while (0)
static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
{
unsigned long flags, retval;
local_irq_save(flags);
retval = *m;
*m = val;
local_irq_restore(flags);
return retval;
}
static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
{
unsigned long flags, retval;
local_irq_save(flags);
retval = *m;
*m = val & 0xff;
local_irq_restore(flags);
return retval;
}
extern void __xchg_called_with_bad_pointer(void);
#define __xchg(ptr, x, size) \
({ \
unsigned long __xchg__res; \
volatile void *__xchg_ptr = (ptr); \
switch (size) { \
case 4: \
__xchg__res = xchg_u32(__xchg_ptr, x); \
break; \
case 1: \
__xchg__res = xchg_u8(__xchg_ptr, x); \
break; \
default: \
__xchg_called_with_bad_pointer(); \
__xchg__res = x; \
break; \
} \
\
__xchg__res; \
})
#define xchg(ptr,x) \
((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
unsigned long new)
{
__u32 retval;
unsigned long flags;
local_irq_save(flags);
retval = *m;
if (retval == old)
*m = new;
local_irq_restore(flags); /* implies memory barrier */
return retval;
}
/* This function doesn't exist, so you'll get a linker error
* if something tries to do an invalid cmpxchg(). */
extern void __cmpxchg_called_with_bad_pointer(void);
#define __HAVE_ARCH_CMPXCHG 1
static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
unsigned long new, int size)
{
switch (size) {
case 4:
return __cmpxchg_u32(ptr, old, new);
}
__cmpxchg_called_with_bad_pointer();
return old;
}
#define cmpxchg(ptr,o,n) \
({ \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
(unsigned long)_n_, sizeof(*(ptr))); \
})
extern void *set_exception_table_vec(unsigned int vec, void *handler);
static inline void *set_exception_table_evt(unsigned int evt, void *handler)
{
return set_exception_table_vec(evt >> 5, handler);
}
/* XXX
* disable hlt during certain critical i/o operations
*/
#define HAVE_DISABLE_HLT
void disable_hlt(void);
void enable_hlt(void);
#define arch_align_stack(x) (x)
static inline void trigger_address_error(void)
{
set_bl_bit();
__asm__ __volatile__ (
"mov.l @%1, %0"
:
: "r" (0x10000000), "r" (0x80000001)
);
}
#endif

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#ifndef __ASM_SH_TYPES_H
#define __ASM_SH_TYPES_H
#ifndef __ASSEMBLY__
typedef unsigned short umode_t;
/*
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
* header files exported to user space
*/
typedef __signed__ char __s8;
typedef unsigned char __u8;
typedef __signed__ short __s16;
typedef unsigned short __u16;
typedef __signed__ int __s32;
typedef unsigned int __u32;
#if defined(__GNUC__)
__extension__ typedef __signed__ long long __s64;
__extension__ typedef unsigned long long __u64;
#endif
#endif /* __ASSEMBLY__ */
/*
* These aren't exported outside the kernel to avoid name space clashes
*/
#ifdef __KERNEL__
#define BITS_PER_LONG 32
#ifndef __ASSEMBLY__
typedef __signed__ char s8;
typedef unsigned char u8;
typedef __signed__ short s16;
typedef unsigned short u16;
typedef __signed__ int s32;
typedef unsigned int u32;
typedef __signed__ long long s64;
typedef unsigned long long u64;
/* Dma addresses are 32-bits wide. */
typedef u32 dma_addr_t;
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* __ASM_SH_TYPES_H */

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/*
* SPDX-License-Identifier: GPL-2.0+
*
********************************************************************
* NOTE: This header file defines an interface to U-Boot. Including
* this (unmodified) header file in another file is considered normal
* use of U-Boot, and does *not* fall under the heading of "derived
* work".
********************************************************************
*/
#ifndef __ASM_SH_U_BOOT_H_
#define __ASM_SH_U_BOOT_H_
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_SH
#endif

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u-boot/arch/sh/include/asm/unaligned-sh4a.h Normal file
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#ifndef __ASM_SH_UNALIGNED_SH4A_H
#define __ASM_SH_UNALIGNED_SH4A_H
/*
* SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
* Support for 64-bit accesses are done through shifting and masking
* relative to the endianness. Unaligned stores are not supported by the
* instruction encoding, so these continue to use the packed
* struct.
*
* The same note as with the movli.l/movco.l pair applies here, as long
* as the load is gauranteed to be inlined, nothing else will hook in to
* r0 and we get the return value for free.
*
* NOTE: Due to the fact we require r0 encoding, care should be taken to
* avoid mixing these heavily with other r0 consumers, such as the atomic
* ops. Failure to adhere to this can result in the compiler running out
* of spill registers and blowing up when building at low optimization
* levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777.
*/
#include <linux/types.h>
#include <asm/byteorder.h>
static __always_inline u32 __get_unaligned_cpu32(const u8 *p)
{
unsigned long unaligned;
__asm__ __volatile__ (
"movua.l @%1, %0\n\t"
: "=z" (unaligned)
: "r" (p)
);
return unaligned;
}
struct __una_u16 { u16 x __attribute__((packed)); };
struct __una_u32 { u32 x __attribute__((packed)); };
struct __una_u64 { u64 x __attribute__((packed)); };
static inline u16 __get_unaligned_cpu16(const u8 *p)
{
#ifdef __LITTLE_ENDIAN
return p[0] | p[1] << 8;
#else
return p[0] << 8 | p[1];
#endif
}
/*
* Even though movua.l supports auto-increment on the read side, it can
* only store to r0 due to instruction encoding constraints, so just let
* the compiler sort it out on its own.
*/
static inline u64 __get_unaligned_cpu64(const u8 *p)
{
#ifdef __LITTLE_ENDIAN
return (u64)__get_unaligned_cpu32(p + 4) << 32 |
__get_unaligned_cpu32(p);
#else
return (u64)__get_unaligned_cpu32(p) << 32 |
__get_unaligned_cpu32(p + 4);
#endif
}
static inline u16 get_unaligned_le16(const void *p)
{
return le16_to_cpu(__get_unaligned_cpu16(p));
}
static inline u32 get_unaligned_le32(const void *p)
{
return le32_to_cpu(__get_unaligned_cpu32(p));
}
static inline u64 get_unaligned_le64(const void *p)
{
return le64_to_cpu(__get_unaligned_cpu64(p));
}
static inline u16 get_unaligned_be16(const void *p)
{
return be16_to_cpu(__get_unaligned_cpu16(p));
}
static inline u32 get_unaligned_be32(const void *p)
{
return be32_to_cpu(__get_unaligned_cpu32(p));
}
static inline u64 get_unaligned_be64(const void *p)
{
return be64_to_cpu(__get_unaligned_cpu64(p));
}
static inline void __put_le16_noalign(u8 *p, u16 val)
{
*p++ = val;
*p++ = val >> 8;
}
static inline void __put_le32_noalign(u8 *p, u32 val)
{
__put_le16_noalign(p, val);
__put_le16_noalign(p + 2, val >> 16);
}
static inline void __put_le64_noalign(u8 *p, u64 val)
{
__put_le32_noalign(p, val);
__put_le32_noalign(p + 4, val >> 32);
}
static inline void __put_be16_noalign(u8 *p, u16 val)
{
*p++ = val >> 8;
*p++ = val;
}
static inline void __put_be32_noalign(u8 *p, u32 val)
{
__put_be16_noalign(p, val >> 16);
__put_be16_noalign(p + 2, val);
}
static inline void __put_be64_noalign(u8 *p, u64 val)
{
__put_be32_noalign(p, val >> 32);
__put_be32_noalign(p + 4, val);
}
static inline void put_unaligned_le16(u16 val, void *p)
{
#ifdef __LITTLE_ENDIAN
((struct __una_u16 *)p)->x = val;
#else
__put_le16_noalign(p, val);
#endif
}
static inline void put_unaligned_le32(u32 val, void *p)
{
#ifdef __LITTLE_ENDIAN
((struct __una_u32 *)p)->x = val;
#else
__put_le32_noalign(p, val);
#endif
}
static inline void put_unaligned_le64(u64 val, void *p)
{
#ifdef __LITTLE_ENDIAN
((struct __una_u64 *)p)->x = val;
#else
__put_le64_noalign(p, val);
#endif
}
static inline void put_unaligned_be16(u16 val, void *p)
{
#ifdef __BIG_ENDIAN
((struct __una_u16 *)p)->x = val;
#else
__put_be16_noalign(p, val);
#endif
}
static inline void put_unaligned_be32(u32 val, void *p)
{
#ifdef __BIG_ENDIAN
((struct __una_u32 *)p)->x = val;
#else
__put_be32_noalign(p, val);
#endif
}
static inline void put_unaligned_be64(u64 val, void *p)
{
#ifdef __BIG_ENDIAN
((struct __una_u64 *)p)->x = val;
#else
__put_be64_noalign(p, val);
#endif
}
/*
* Cause a link-time error if we try an unaligned access other than
* 1,2,4 or 8 bytes long
*/
extern void __bad_unaligned_access_size(void);
#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({ \
__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)), \
__bad_unaligned_access_size())))); \
}))
#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({ \
__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)), \
__bad_unaligned_access_size())))); \
}))
#define __put_unaligned_le(val, ptr) ({ \
void *__gu_p = (ptr); \
switch (sizeof(*(ptr))) { \
case 1: \
*(u8 *)__gu_p = (__force u8)(val); \
break; \
case 2: \
put_unaligned_le16((__force u16)(val), __gu_p); \
break; \
case 4: \
put_unaligned_le32((__force u32)(val), __gu_p); \
break; \
case 8: \
put_unaligned_le64((__force u64)(val), __gu_p); \
break; \
default: \
__bad_unaligned_access_size(); \
break; \
} \
(void)0; })
#define __put_unaligned_be(val, ptr) ({ \
void *__gu_p = (ptr); \
switch (sizeof(*(ptr))) { \
case 1: \
*(u8 *)__gu_p = (__force u8)(val); \
break; \
case 2: \
put_unaligned_be16((__force u16)(val), __gu_p); \
break; \
case 4: \
put_unaligned_be32((__force u32)(val), __gu_p); \
break; \
case 8: \
put_unaligned_be64((__force u64)(val), __gu_p); \
break; \
default: \
__bad_unaligned_access_size(); \
break; \
} \
(void)0; })
#ifdef __LITTLE_ENDIAN
# define get_unaligned __get_unaligned_le
# define put_unaligned __put_unaligned_le
#else
# define get_unaligned __get_unaligned_be
# define put_unaligned __put_unaligned_be
#endif
#endif /* __ASM_SH_UNALIGNED_SH4A_H */

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#ifndef _ASM_SH_UNALIGNED_H
#define _ASM_SH_UNALIGNED_H
/* Copy from linux-kernel. */
#ifdef CONFIG_CPU_SH4A
/* SH-4A can handle unaligned loads in a relatively neutered fashion. */
#include <asm/unaligned-sh4a.h>
#else
/* Otherwise, SH can't handle unaligned accesses. */
#include <linux/compiler.h>
#if defined(__BIG_ENDIAN__)
#define get_unaligned __get_unaligned_be
#define put_unaligned __put_unaligned_be
#elif defined(__LITTLE_ENDIAN__)
#define get_unaligned __get_unaligned_le
#define put_unaligned __put_unaligned_le
#endif
#include <linux/unaligned/le_byteshift.h>
#include <linux/unaligned/be_byteshift.h>
#include <linux/unaligned/generic.h>
#endif
#endif /* _ASM_SH_UNALIGNED_H */

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u-boot/arch/sh/include/asm/zimage.h Normal file
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/*
* (C) Copyright 2010
* Renesas Solutions Corp.
* Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ZIMAGE_H_
#define _ASM_ZIMAGE_H_
#define MOUNT_ROOT_RDONLY 0x000
#define RAMDISK_FLAGS 0x004
#define ORIG_ROOT_DEV 0x008
#define LOADER_TYPE 0x00c
#define INITRD_START 0x010
#define INITRD_SIZE 0x014
#define COMMAND_LINE 0x100
#define RD_PROMPT (1<<15)
#define RD_DOLOAD (1<<14)
#define CMD_ARG_RD_PROMPT "prompt_ramdisk="
#define CMD_ARG_RD_DOLOAD "load_ramdisk="
#endif

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u-boot/arch/sh/lib/Makefile Normal file
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#
# Copyright (c) 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_CMD_BOOTM) += bootm.o
ifeq ($(CONFIG_CPU_SH2),y)
obj-y += time_sh2.o
else
obj-y += time.o
endif
obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
udivsi3-y := udivsi3_i4i-Os.o
ifneq ($(CONFIG_CC_OPTIMIZE_FOR_SIZE),y)
udivsi3-$(CONFIG_CPU_SH3) := udivsi3_i4i.o
udivsi3-$(CONFIG_CPU_SH4) := udivsi3_i4i.o
endif
udivsi3-y += udivsi3.o
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += movmem.o ashldi3.o ashrdi3.o lshrdi3.o \
ashlsi3.o ashrsi3.o ashiftrt.o lshrsi3.o \
udiv_qrnnd.o $(udivsi3-y)

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/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
* SPDX-License-Identifier: GPL-2.0+
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
.global __ashiftrt_r4_0
.global __ashiftrt_r4_1
.global __ashiftrt_r4_2
.global __ashiftrt_r4_3
.global __ashiftrt_r4_4
.global __ashiftrt_r4_5
.global __ashiftrt_r4_6
.global __ashiftrt_r4_7
.global __ashiftrt_r4_8
.global __ashiftrt_r4_9
.global __ashiftrt_r4_10
.global __ashiftrt_r4_11
.global __ashiftrt_r4_12
.global __ashiftrt_r4_13
.global __ashiftrt_r4_14
.global __ashiftrt_r4_15
.global __ashiftrt_r4_16
.global __ashiftrt_r4_17
.global __ashiftrt_r4_18
.global __ashiftrt_r4_19
.global __ashiftrt_r4_20
.global __ashiftrt_r4_21
.global __ashiftrt_r4_22
.global __ashiftrt_r4_23
.global __ashiftrt_r4_24
.global __ashiftrt_r4_25
.global __ashiftrt_r4_26
.global __ashiftrt_r4_27
.global __ashiftrt_r4_28
.global __ashiftrt_r4_29
.global __ashiftrt_r4_30
.global __ashiftrt_r4_31
.global __ashiftrt_r4_32
.align 1
__ashiftrt_r4_32:
__ashiftrt_r4_31:
rotcl r4
rts
subc r4,r4
__ashiftrt_r4_30:
shar r4
__ashiftrt_r4_29:
shar r4
__ashiftrt_r4_28:
shar r4
__ashiftrt_r4_27:
shar r4
__ashiftrt_r4_26:
shar r4
__ashiftrt_r4_25:
shar r4
__ashiftrt_r4_24:
shlr16 r4
shlr8 r4
rts
exts.b r4,r4
__ashiftrt_r4_23:
shar r4
__ashiftrt_r4_22:
shar r4
__ashiftrt_r4_21:
shar r4
__ashiftrt_r4_20:
shar r4
__ashiftrt_r4_19:
shar r4
__ashiftrt_r4_18:
shar r4
__ashiftrt_r4_17:
shar r4
__ashiftrt_r4_16:
shlr16 r4
rts
exts.w r4,r4
__ashiftrt_r4_15:
shar r4
__ashiftrt_r4_14:
shar r4
__ashiftrt_r4_13:
shar r4
__ashiftrt_r4_12:
shar r4
__ashiftrt_r4_11:
shar r4
__ashiftrt_r4_10:
shar r4
__ashiftrt_r4_9:
shar r4
__ashiftrt_r4_8:
shar r4
__ashiftrt_r4_7:
shar r4
__ashiftrt_r4_6:
shar r4
__ashiftrt_r4_5:
shar r4
__ashiftrt_r4_4:
shar r4
__ashiftrt_r4_3:
shar r4
__ashiftrt_r4_2:
shar r4
__ashiftrt_r4_1:
rts
shar r4
__ashiftrt_r4_0:
rts
nop

25
u-boot/arch/sh/lib/ashldi3.c Normal file
View File

@@ -0,0 +1,25 @@
#include "libgcc.h"
long long __ashldi3(long long u, word_type b)
{
DWunion uu, w;
word_type bm;
if (b == 0)
return u;
uu.ll = u;
bm = 32 - b;
if (bm <= 0) {
w.s.low = 0;
w.s.high = (unsigned int) uu.s.low << -bm;
} else {
const unsigned int carries = (unsigned int) uu.s.low >> bm;
w.s.low = (unsigned int) uu.s.low << b;
w.s.high = ((unsigned int) uu.s.high << b) | carries;
}
return w.ll;
}

171
u-boot/arch/sh/lib/ashlsi3.S Normal file
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@@ -0,0 +1,171 @@
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
* SPDX-License-Identifier: GPL-2.0+
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
!
! GLOBAL(ashlsi3)
!
! Entry:
!
! r4: Value to shift
! r5: Shifts
!
! Exit:
!
! r0: Result
!
! Destroys:
!
! (none)
!
.global __ashlsi3
.align 2
__ashlsi3:
mov #31,r0
and r0,r5
mova __ashlsi3_table,r0
mov.b @(r0,r5),r5
#ifdef __sh1__
add r5,r0
jmp @r0
#else
braf r5
#endif
mov r4,r0
.align 2
__ashlsi3_table:
.byte __ashlsi3_0-__ashlsi3_table
.byte __ashlsi3_1-__ashlsi3_table
.byte __ashlsi3_2-__ashlsi3_table
.byte __ashlsi3_3-__ashlsi3_table
.byte __ashlsi3_4-__ashlsi3_table
.byte __ashlsi3_5-__ashlsi3_table
.byte __ashlsi3_6-__ashlsi3_table
.byte __ashlsi3_7-__ashlsi3_table
.byte __ashlsi3_8-__ashlsi3_table
.byte __ashlsi3_9-__ashlsi3_table
.byte __ashlsi3_10-__ashlsi3_table
.byte __ashlsi3_11-__ashlsi3_table
.byte __ashlsi3_12-__ashlsi3_table
.byte __ashlsi3_13-__ashlsi3_table
.byte __ashlsi3_14-__ashlsi3_table
.byte __ashlsi3_15-__ashlsi3_table
.byte __ashlsi3_16-__ashlsi3_table
.byte __ashlsi3_17-__ashlsi3_table
.byte __ashlsi3_18-__ashlsi3_table
.byte __ashlsi3_19-__ashlsi3_table
.byte __ashlsi3_20-__ashlsi3_table
.byte __ashlsi3_21-__ashlsi3_table
.byte __ashlsi3_22-__ashlsi3_table
.byte __ashlsi3_23-__ashlsi3_table
.byte __ashlsi3_24-__ashlsi3_table
.byte __ashlsi3_25-__ashlsi3_table
.byte __ashlsi3_26-__ashlsi3_table
.byte __ashlsi3_27-__ashlsi3_table
.byte __ashlsi3_28-__ashlsi3_table
.byte __ashlsi3_29-__ashlsi3_table
.byte __ashlsi3_30-__ashlsi3_table
.byte __ashlsi3_31-__ashlsi3_table
__ashlsi3_6:
shll2 r0
__ashlsi3_4:
shll2 r0
__ashlsi3_2:
rts
shll2 r0
__ashlsi3_7:
shll2 r0
__ashlsi3_5:
shll2 r0
__ashlsi3_3:
shll2 r0
__ashlsi3_1:
rts
shll r0
__ashlsi3_14:
shll2 r0
__ashlsi3_12:
shll2 r0
__ashlsi3_10:
shll2 r0
__ashlsi3_8:
rts
shll8 r0
__ashlsi3_15:
shll2 r0
__ashlsi3_13:
shll2 r0
__ashlsi3_11:
shll2 r0
__ashlsi3_9:
shll8 r0
rts
shll r0
__ashlsi3_22:
shll2 r0
__ashlsi3_20:
shll2 r0
__ashlsi3_18:
shll2 r0
__ashlsi3_16:
rts
shll16 r0
__ashlsi3_23:
shll2 r0
__ashlsi3_21:
shll2 r0
__ashlsi3_19:
shll2 r0
__ashlsi3_17:
shll16 r0
rts
shll r0
__ashlsi3_30:
shll2 r0
__ashlsi3_28:
shll2 r0
__ashlsi3_26:
shll2 r0
__ashlsi3_24:
shll16 r0
rts
shll8 r0
__ashlsi3_31:
shll2 r0
__ashlsi3_29:
shll2 r0
__ashlsi3_27:
shll2 r0
__ashlsi3_25:
shll16 r0
shll8 r0
rts
shll r0
__ashlsi3_0:
rts
nop

27
u-boot/arch/sh/lib/ashrdi3.c Normal file
View File

@@ -0,0 +1,27 @@
#include "libgcc.h"
long long __ashrdi3(long long u, word_type b)
{
DWunion uu, w;
word_type bm;
if (b == 0)
return u;
uu.ll = u;
bm = 32 - b;
if (bm <= 0) {
/* w.s.high = 1..1 or 0..0 */
w.s.high =
uu.s.high >> 31;
w.s.low = uu.s.high >> -bm;
} else {
const unsigned int carries = (unsigned int) uu.s.high << bm;
w.s.high = uu.s.high >> b;
w.s.low = ((unsigned int) uu.s.low >> b) | carries;
}
return w.ll;
}

164
u-boot/arch/sh/lib/ashrsi3.S Normal file
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@@ -0,0 +1,164 @@
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
* SPDX-License-Identifier: GPL-2.0+
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
!
! __ashrsi3
!
! Entry:
!
! r4: Value to shift
! r5: Shifts
!
! Exit:
!
! r0: Result
!
! Destroys:
!
! (none)
!
.global __ashrsi3
.align 2
__ashrsi3:
mov #31,r0
and r0,r5
mova ashrsi3_table,r0
mov.b @(r0,r5),r5
#ifdef __sh1__
add r5,r0
jmp @r0
#else
braf r5
#endif
mov r4,r0
.align 2
ashrsi3_table:
.byte ashrsi3_0-ashrsi3_table
.byte ashrsi3_1-ashrsi3_table
.byte ashrsi3_2-ashrsi3_table
.byte ashrsi3_3-ashrsi3_table
.byte ashrsi3_4-ashrsi3_table
.byte ashrsi3_5-ashrsi3_table
.byte ashrsi3_6-ashrsi3_table
.byte ashrsi3_7-ashrsi3_table
.byte ashrsi3_8-ashrsi3_table
.byte ashrsi3_9-ashrsi3_table
.byte ashrsi3_10-ashrsi3_table
.byte ashrsi3_11-ashrsi3_table
.byte ashrsi3_12-ashrsi3_table
.byte ashrsi3_13-ashrsi3_table
.byte ashrsi3_14-ashrsi3_table
.byte ashrsi3_15-ashrsi3_table
.byte ashrsi3_16-ashrsi3_table
.byte ashrsi3_17-ashrsi3_table
.byte ashrsi3_18-ashrsi3_table
.byte ashrsi3_19-ashrsi3_table
.byte ashrsi3_20-ashrsi3_table
.byte ashrsi3_21-ashrsi3_table
.byte ashrsi3_22-ashrsi3_table
.byte ashrsi3_23-ashrsi3_table
.byte ashrsi3_24-ashrsi3_table
.byte ashrsi3_25-ashrsi3_table
.byte ashrsi3_26-ashrsi3_table
.byte ashrsi3_27-ashrsi3_table
.byte ashrsi3_28-ashrsi3_table
.byte ashrsi3_29-ashrsi3_table
.byte ashrsi3_30-ashrsi3_table
.byte ashrsi3_31-ashrsi3_table
ashrsi3_31:
rotcl r0
rts
subc r0,r0
ashrsi3_30:
shar r0
ashrsi3_29:
shar r0
ashrsi3_28:
shar r0
ashrsi3_27:
shar r0
ashrsi3_26:
shar r0
ashrsi3_25:
shar r0
ashrsi3_24:
shlr16 r0
shlr8 r0
rts
exts.b r0,r0
ashrsi3_23:
shar r0
ashrsi3_22:
shar r0
ashrsi3_21:
shar r0
ashrsi3_20:
shar r0
ashrsi3_19:
shar r0
ashrsi3_18:
shar r0
ashrsi3_17:
shar r0
ashrsi3_16:
shlr16 r0
rts
exts.w r0,r0
ashrsi3_15:
shar r0
ashrsi3_14:
shar r0
ashrsi3_13:
shar r0
ashrsi3_12:
shar r0
ashrsi3_11:
shar r0
ashrsi3_10:
shar r0
ashrsi3_9:
shar r0
ashrsi3_8:
shar r0
ashrsi3_7:
shar r0
ashrsi3_6:
shar r0
ashrsi3_5:
shar r0
ashrsi3_4:
shar r0
ashrsi3_3:
shar r0
ashrsi3_2:
shar r0
ashrsi3_1:
rts
shar r0
ashrsi3_0:
rts
nop

111
u-boot/arch/sh/lib/bootm.c Normal file
View File

@@ -0,0 +1,111 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (c) Copyright 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
* (c) Copyright 2008 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/byteorder.h>
#include <asm/zimage.h>
#ifdef CONFIG_SYS_DEBUG
static void hexdump(unsigned char *buf, int len)
{
int i;
for (i = 0; i < len; i++) {
if ((i % 16) == 0)
printf("%s%08x: ", i ? "\n" : "",
(unsigned int)&buf[i]);
printf("%02x ", buf[i]);
}
printf("\n");
}
#endif
#ifdef CONFIG_SH_SDRAM_OFFSET
#define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET)
#else
#define GET_INITRD_START(initrd, linux) (initrd - linux)
#endif
static void set_sh_linux_param(unsigned long param_addr, unsigned long data)
{
*(unsigned long *)(param_addr) = data;
}
static unsigned long sh_check_cmd_arg(char *cmdline, char *key, int base)
{
unsigned long val = 0;
char *p = strstr(cmdline, key);
if (p) {
p += strlen(key);
val = simple_strtol(p, NULL, base);
}
return val;
}
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
/* Linux kernel load address */
void (*kernel) (void) = (void (*)(void))images->ep;
/* empty_zero_page */
unsigned char *param
= (unsigned char *)image_get_load(images->legacy_hdr_os);
/* Linux kernel command line */
char *cmdline = (char *)param + COMMAND_LINE;
/* PAGE_SIZE */
unsigned long size = images->ep - (unsigned long)param;
char *bootargs = getenv("bootargs");
/*
* allow the PREP bootm subcommand, it is required for bootm to work
*/
if (flag & BOOTM_STATE_OS_PREP)
return 0;
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
return 1;
/* Clear zero page */
memset(param, 0, size);
/* Set commandline */
strcpy(cmdline, bootargs);
/* Initrd */
if (images->rd_start || images->rd_end) {
unsigned long ramdisk_flags = 0;
int val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_PROMPT, 10);
if (val == 1)
ramdisk_flags |= RD_PROMPT;
else
ramdisk_flags &= ~RD_PROMPT;
val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
if (val == 1)
ramdisk_flags |= RD_DOLOAD;
else
ramdisk_flags &= ~RD_DOLOAD;
set_sh_linux_param((unsigned long)param + MOUNT_ROOT_RDONLY, 0x0001);
set_sh_linux_param((unsigned long)param + RAMDISK_FLAGS, ramdisk_flags);
set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200);
set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001);
set_sh_linux_param((unsigned long)param + INITRD_START,
GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE));
set_sh_linux_param((unsigned long)param + INITRD_SIZE,
images->rd_end - images->rd_start);
}
/* Boot kernel */
kernel();
/* does not return */
return 1;
}

25
u-boot/arch/sh/lib/libgcc.h Normal file
View File

@@ -0,0 +1,25 @@
#ifndef __ASM_LIBGCC_H
#define __ASM_LIBGCC_H
#include <asm/byteorder.h>
typedef int word_type __attribute__ ((mode (__word__)));
#ifdef __BIG_ENDIAN
struct DWstruct {
int high, low;
};
#elif defined(__LITTLE_ENDIAN)
struct DWstruct {
int low, high;
};
#else
#error I feel sick.
#endif
typedef union {
struct DWstruct s;
long long ll;
} DWunion;
#endif /* __ASM_LIBGCC_H */

25
u-boot/arch/sh/lib/lshrdi3.c Normal file
View File

@@ -0,0 +1,25 @@
#include "libgcc.h"
long long __lshrdi3(long long u, word_type b)
{
DWunion uu, w;
word_type bm;
if (b == 0)
return u;
uu.ll = u;
bm = 32 - b;
if (bm <= 0) {
w.s.high = 0;
w.s.low = (unsigned int) uu.s.high >> -bm;
} else {
const unsigned int carries = (unsigned int) uu.s.high << bm;
w.s.high = (unsigned int) uu.s.high >> b;
w.s.low = ((unsigned int) uu.s.low >> b) | carries;
}
return w.ll;
}

171
u-boot/arch/sh/lib/lshrsi3.S Normal file
View File

@@ -0,0 +1,171 @@
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
* SPDX-License-Identifier: GPL-2.0+
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
!
! __lshrsi3)
!
! Entry:
!
! r4: Value to shift
! r5: Shifts
!
! Exit:
!
! r0: Result
!
! Destroys:
!
! (none)
!
.global __lshrsi3
.align 2
__lshrsi3:
mov #31,r0
and r0,r5
mova __lshrsi3_table,r0
mov.b @(r0,r5),r5
#ifdef __sh1__
add r5,r0
jmp @r0
#else
braf r5
#endif
mov r4,r0
.align 2
__lshrsi3_table:
.byte __lshrsi3_0-__lshrsi3_table
.byte __lshrsi3_1-__lshrsi3_table
.byte __lshrsi3_2-__lshrsi3_table
.byte __lshrsi3_3-__lshrsi3_table
.byte __lshrsi3_4-__lshrsi3_table
.byte __lshrsi3_5-__lshrsi3_table
.byte __lshrsi3_6-__lshrsi3_table
.byte __lshrsi3_7-__lshrsi3_table
.byte __lshrsi3_8-__lshrsi3_table
.byte __lshrsi3_9-__lshrsi3_table
.byte __lshrsi3_10-__lshrsi3_table
.byte __lshrsi3_11-__lshrsi3_table
.byte __lshrsi3_12-__lshrsi3_table
.byte __lshrsi3_13-__lshrsi3_table
.byte __lshrsi3_14-__lshrsi3_table
.byte __lshrsi3_15-__lshrsi3_table
.byte __lshrsi3_16-__lshrsi3_table
.byte __lshrsi3_17-__lshrsi3_table
.byte __lshrsi3_18-__lshrsi3_table
.byte __lshrsi3_19-__lshrsi3_table
.byte __lshrsi3_20-__lshrsi3_table
.byte __lshrsi3_21-__lshrsi3_table
.byte __lshrsi3_22-__lshrsi3_table
.byte __lshrsi3_23-__lshrsi3_table
.byte __lshrsi3_24-__lshrsi3_table
.byte __lshrsi3_25-__lshrsi3_table
.byte __lshrsi3_26-__lshrsi3_table
.byte __lshrsi3_27-__lshrsi3_table
.byte __lshrsi3_28-__lshrsi3_table
.byte __lshrsi3_29-__lshrsi3_table
.byte __lshrsi3_30-__lshrsi3_table
.byte __lshrsi3_31-__lshrsi3_table
__lshrsi3_6:
shlr2 r0
__lshrsi3_4:
shlr2 r0
__lshrsi3_2:
rts
shlr2 r0
__lshrsi3_7:
shlr2 r0
__lshrsi3_5:
shlr2 r0
__lshrsi3_3:
shlr2 r0
__lshrsi3_1:
rts
shlr r0
__lshrsi3_14:
shlr2 r0
__lshrsi3_12:
shlr2 r0
__lshrsi3_10:
shlr2 r0
__lshrsi3_8:
rts
shlr8 r0
__lshrsi3_15:
shlr2 r0
__lshrsi3_13:
shlr2 r0
__lshrsi3_11:
shlr2 r0
__lshrsi3_9:
shlr8 r0
rts
shlr r0
__lshrsi3_22:
shlr2 r0
__lshrsi3_20:
shlr2 r0
__lshrsi3_18:
shlr2 r0
__lshrsi3_16:
rts
shlr16 r0
__lshrsi3_23:
shlr2 r0
__lshrsi3_21:
shlr2 r0
__lshrsi3_19:
shlr2 r0
__lshrsi3_17:
shlr16 r0
rts
shlr r0
__lshrsi3_30:
shlr2 r0
__lshrsi3_28:
shlr2 r0
__lshrsi3_26:
shlr2 r0
__lshrsi3_24:
shlr16 r0
rts
shlr8 r0
__lshrsi3_31:
shlr2 r0
__lshrsi3_29:
shlr2 r0
__lshrsi3_27:
shlr2 r0
__lshrsi3_25:
shlr16 r0
shlr8 r0
rts
shlr r0
__lshrsi3_0:
rts
nop

217
u-boot/arch/sh/lib/movmem.S Normal file
View File

@@ -0,0 +1,217 @@
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
* SPDX-License-Identifier: GPL-2.0+
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
.text
.balign 4
.global __movmem
.global __movstr
.set __movstr, __movmem
/* This would be a lot simpler if r6 contained the byte count
minus 64, and we wouldn't be called here for a byte count of 64. */
__movmem:
sts.l pr,@-r15
shll2 r6
bsr __movmemSI52+2
mov.l @(48,r5),r0
.balign 4
movmem_loop: /* Reached with rts */
mov.l @(60,r5),r0
add #-64,r6
mov.l r0,@(60,r4)
tst r6,r6
mov.l @(56,r5),r0
bt movmem_done
mov.l r0,@(56,r4)
cmp/pl r6
mov.l @(52,r5),r0
add #64,r5
mov.l r0,@(52,r4)
add #64,r4
bt __movmemSI52
! done all the large groups, do the remainder
! jump to movmem+
mova __movmemSI4+4,r0
add r6,r0
jmp @r0
movmem_done: ! share slot insn, works out aligned.
lds.l @r15+,pr
mov.l r0,@(56,r4)
mov.l @(52,r5),r0
rts
mov.l r0,@(52,r4)
.balign 4
.global __movmemSI64
.global __movstrSI64
.set __movstrSI64, __movmemSI64
__movmemSI64:
mov.l @(60,r5),r0
mov.l r0,@(60,r4)
.global __movmemSI60
.global __movstrSI60
.set __movstrSI60, __movmemSI60
__movmemSI60:
mov.l @(56,r5),r0
mov.l r0,@(56,r4)
.global __movmemSI56
.global __movstrSI56
.set __movstrSI56, __movmemSI56
__movmemSI56:
mov.l @(52,r5),r0
mov.l r0,@(52,r4)
.global __movmemSI52
.global __movstrSI52
.set __movstrSI52, __movmemSI52
__movmemSI52:
mov.l @(48,r5),r0
mov.l r0,@(48,r4)
.global __movmemSI48
.global __movstrSI48
.set __movstrSI48, __movmemSI48
__movmemSI48:
mov.l @(44,r5),r0
mov.l r0,@(44,r4)
.global __movmemSI44
.global __movstrSI44
.set __movstrSI44, __movmemSI44
__movmemSI44:
mov.l @(40,r5),r0
mov.l r0,@(40,r4)
.global __movmemSI40
.global __movstrSI40
.set __movstrSI40, __movmemSI40
__movmemSI40:
mov.l @(36,r5),r0
mov.l r0,@(36,r4)
.global __movmemSI36
.global __movstrSI36
.set __movstrSI36, __movmemSI36
__movmemSI36:
mov.l @(32,r5),r0
mov.l r0,@(32,r4)
.global __movmemSI32
.global __movstrSI32
.set __movstrSI32, __movmemSI32
__movmemSI32:
mov.l @(28,r5),r0
mov.l r0,@(28,r4)
.global __movmemSI28
.global __movstrSI28
.set __movstrSI28, __movmemSI28
__movmemSI28:
mov.l @(24,r5),r0
mov.l r0,@(24,r4)
.global __movmemSI24
.global __movstrSI24
.set __movstrSI24, __movmemSI24
__movmemSI24:
mov.l @(20,r5),r0
mov.l r0,@(20,r4)
.global __movmemSI20
.global __movstrSI20
.set __movstrSI20, __movmemSI20
__movmemSI20:
mov.l @(16,r5),r0
mov.l r0,@(16,r4)
.global __movmemSI16
.global __movstrSI16
.set __movstrSI16, __movmemSI16
__movmemSI16:
mov.l @(12,r5),r0
mov.l r0,@(12,r4)
.global __movmemSI12
.global __movstrSI12
.set __movstrSI12, __movmemSI12
__movmemSI12:
mov.l @(8,r5),r0
mov.l r0,@(8,r4)
.global __movmemSI8
.global __movstrSI8
.set __movstrSI8, __movmemSI8
__movmemSI8:
mov.l @(4,r5),r0
mov.l r0,@(4,r4)
.global __movmemSI4
.global __movstrSI4
.set __movstrSI4, __movmemSI4
__movmemSI4:
mov.l @(0,r5),r0
rts
mov.l r0,@(0,r4)
.global __movmem_i4_even
.global __movstr_i4_even
.set __movstr_i4_even, __movmem_i4_even
.global __movmem_i4_odd
.global __movstr_i4_odd
.set __movstr_i4_odd, __movmem_i4_odd
.global __movmemSI12_i4
.global __movstrSI12_i4
.set __movstrSI12_i4, __movmemSI12_i4
.p2align 5
L_movmem_2mod4_end:
mov.l r0,@(16,r4)
rts
mov.l r1,@(20,r4)
.p2align 2
__movmem_i4_even:
mov.l @r5+,r0
bra L_movmem_start_even
mov.l @r5+,r1
__movmem_i4_odd:
mov.l @r5+,r1
add #-4,r4
mov.l @r5+,r2
mov.l @r5+,r3
mov.l r1,@(4,r4)
mov.l r2,@(8,r4)
L_movmem_loop:
mov.l r3,@(12,r4)
dt r6
mov.l @r5+,r0
bt/s L_movmem_2mod4_end
mov.l @r5+,r1
add #16,r4
L_movmem_start_even:
mov.l @r5+,r2
mov.l @r5+,r3
mov.l r0,@r4
dt r6
mov.l r1,@(4,r4)
bf/s L_movmem_loop
mov.l r2,@(8,r4)
rts
mov.l r3,@(12,r4)
.p2align 4
__movmemSI12_i4:
mov.l @r5,r0
mov.l @(4,r5),r1
mov.l @(8,r5),r2
mov.l r0,@r4
mov.l r1,@(4,r4)
rts
mov.l r2,@(8,r4)

58
u-boot/arch/sh/lib/time.c Normal file
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@@ -0,0 +1,58 @@
/*
* (C) Copyright 2009
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* (C) Copyright 2007-2012
* Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <sh_tmu.h>
#define TCR_TPSC 0x07
static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
unsigned long get_tbclk(void)
{
u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
return get_tmu0_clk_rate() >> ((tmu_bit + 1) * 2);
}
unsigned long timer_read_counter(void)
{
return ~readl(&tmu->tcnt0);
}
static void tmu_timer_start(unsigned int timer)
{
if (timer > 2)
return;
writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr);
}
static void tmu_timer_stop(unsigned int timer)
{
if (timer > 2)
return;
writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr);
}
int timer_init(void)
{
u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
writew((readw(&tmu->tcr0) & ~TCR_TPSC) | tmu_bit, &tmu->tcr0);
tmu_timer_stop(0);
tmu_timer_start(0);
return 0;
}

88
u-boot/arch/sh/lib/time_sh2.c Normal file
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/*
* Copyright (C) 2007,2008 Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
#define CMT_CMCSR_INIT 0x0001 /* PCLK/32 */
#define CMT_CMCSR_CALIB 0x0000
#define CMT_MAX_COUNTER (0xFFFFFFFF)
#define CMT_TIMER_RESET (0xFFFF)
static vu_long cmt0_timer;
static void cmt_timer_start(unsigned int timer)
{
writew(readw(CMSTR) | 0x01, CMSTR);
}
static void cmt_timer_stop(unsigned int timer)
{
writew(readw(CMSTR) & ~0x01, CMSTR);
}
int timer_init(void)
{
cmt0_timer = 0;
/* Divide clock by 32 */
readw(CMCSR_0);
writew(CMT_CMCSR_INIT, CMCSR_0);
/* User Device 0 only */
cmt_timer_stop(0);
writew(CMT_TIMER_RESET, CMCOR_0);
cmt_timer_start(0);
return 0;
}
unsigned long long get_ticks(void)
{
return cmt0_timer;
}
static vu_long cmcnt = 0;
static unsigned long get_usec (void)
{
ulong data = readw(CMCNT_0);
if (data >= cmcnt)
cmcnt = data - cmcnt;
else
cmcnt = (CMT_TIMER_RESET - cmcnt) + data;
if ((cmt0_timer + cmcnt) > CMT_MAX_COUNTER)
cmt0_timer = ((cmt0_timer + cmcnt) - CMT_MAX_COUNTER);
else
cmt0_timer += cmcnt;
cmcnt = data;
return cmt0_timer;
}
/* return msec */
ulong get_timer(ulong base)
{
return (get_usec() / 1000) - base;
}
void __udelay(unsigned long usec)
{
unsigned long end = get_usec() + usec;
while (get_usec() < end)
continue;
}
unsigned long get_tbclk(void)
{
return CONFIG_SH_CMT_CLK_FREQ;
}

60
u-boot/arch/sh/lib/udiv_qrnnd.S Normal file
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/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
* SPDX-License-Identifier: GPL-2.0+
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
/* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */
/* n1 < d, but n1 might be larger than d1. */
.global __udiv_qrnnd_16
.balign 8
__udiv_qrnnd_16:
div0u
cmp/hi r6,r0
bt .Lots
.rept 16
div1 r6,r0
.endr
extu.w r0,r1
bt 0f
add r6,r0
0: rotcl r1
mulu.w r1,r5
xtrct r4,r0
swap.w r0,r0
sts macl,r2
cmp/hs r2,r0
sub r2,r0
bt 0f
addc r5,r0
add #-1,r1
bt 0f
1: add #-1,r1
rts
add r5,r0
.balign 8
.Lots:
sub r5,r0
swap.w r4,r1
xtrct r0,r1
clrt
mov r1,r0
addc r5,r0
mov #-1,r1
bf/s 1b
shlr16 r1
0: rts
nop

66
u-boot/arch/sh/lib/udivsi3.S Normal file
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/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005
Free Software Foundation, Inc.
* SPDX-License-Identifier: GPL-2.0+
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
.balign 4
.global __udivsi3
.type __udivsi3, @function
div8:
div1 r5,r4
div7:
div1 r5,r4; div1 r5,r4; div1 r5,r4
div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
divx4:
div1 r5,r4; rotcl r0
div1 r5,r4; rotcl r0
div1 r5,r4; rotcl r0
rts; div1 r5,r4
__udivsi3:
sts.l pr,@-r15
extu.w r5,r0
cmp/eq r5,r0
bf/s large_divisor
div0u
swap.w r4,r0
shlr16 r4
bsr div8
shll16 r5
bsr div7
div1 r5,r4
xtrct r4,r0
xtrct r0,r4
bsr div8
swap.w r4,r4
bsr div7
div1 r5,r4
lds.l @r15+,pr
xtrct r4,r0
swap.w r0,r0
rotcl r0
rts
shlr16 r5
large_divisor:
mov #0,r0
xtrct r4,r0
xtrct r0,r4
bsr divx4
rotcl r0
bsr divx4
rotcl r0
bsr divx4
rotcl r0
bsr divx4
rotcl r0
lds.l @r15+,pr
rts
rotcl r0

128
u-boot/arch/sh/lib/udivsi3_i4i-Os.S Normal file
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/* Copyright (C) 2006 Free Software Foundation, Inc.
* SPDX-License-Identifier: GPL-2.0+
*/
/* Moderately Space-optimized libgcc routines for the Renesas SH /
STMicroelectronics ST40 CPUs.
Contributed by J"orn Rennecke joern.rennecke@st.com. */
/* Size: 186 bytes jointly for udivsi3_i4i and sdivsi3_i4i
sh4-200 run times:
udiv small divisor: 55 cycles
udiv large divisor: 52 cycles
sdiv small divisor, positive result: 59 cycles
sdiv large divisor, positive result: 56 cycles
sdiv small divisor, negative result: 65 cycles (*)
sdiv large divisor, negative result: 62 cycles (*)
(*): r2 is restored in the rts delay slot and has a lingering latency
of two more cycles. */
.balign 4
.global __udivsi3_i4i
.global __udivsi3_i4
.set __udivsi3_i4, __udivsi3_i4i
.type __udivsi3_i4i, @function
.type __sdivsi3_i4i, @function
__udivsi3_i4i:
sts pr,r1
mov.l r4,@-r15
extu.w r5,r0
cmp/eq r5,r0
swap.w r4,r0
shlr16 r4
bf/s large_divisor
div0u
mov.l r5,@-r15
shll16 r5
sdiv_small_divisor:
div1 r5,r4
bsr div6
div1 r5,r4
div1 r5,r4
bsr div6
div1 r5,r4
xtrct r4,r0
xtrct r0,r4
bsr div7
swap.w r4,r4
div1 r5,r4
bsr div7
div1 r5,r4
xtrct r4,r0
mov.l @r15+,r5
swap.w r0,r0
mov.l @r15+,r4
jmp @r1
rotcl r0
div7:
div1 r5,r4
div6:
div1 r5,r4; div1 r5,r4; div1 r5,r4
div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
divx3:
rotcl r0
div1 r5,r4
rotcl r0
div1 r5,r4
rotcl r0
rts
div1 r5,r4
large_divisor:
mov.l r5,@-r15
sdiv_large_divisor:
xor r4,r0
.rept 4
rotcl r0
bsr divx3
div1 r5,r4
.endr
mov.l @r15+,r5
mov.l @r15+,r4
jmp @r1
rotcl r0
.global __sdivsi3_i4i
.global __sdivsi3_i4
.global __sdivsi3
.set __sdivsi3_i4, __sdivsi3_i4i
.set __sdivsi3, __sdivsi3_i4i
__sdivsi3_i4i:
mov.l r4,@-r15
cmp/pz r5
mov.l r5,@-r15
bt/s pos_divisor
cmp/pz r4
neg r5,r5
extu.w r5,r0
bt/s neg_result
cmp/eq r5,r0
neg r4,r4
pos_result:
swap.w r4,r0
bra sdiv_check_divisor
sts pr,r1
pos_divisor:
extu.w r5,r0
bt/s pos_result
cmp/eq r5,r0
neg r4,r4
neg_result:
mova negate_result,r0
;
mov r0,r1
swap.w r4,r0
lds r2,macl
sts pr,r2
sdiv_check_divisor:
shlr16 r4
bf/s sdiv_large_divisor
div0u
bra sdiv_small_divisor
shll16 r5
.balign 4
negate_result:
neg r0,r0
jmp @r2
sts macl,r2

644
u-boot/arch/sh/lib/udivsi3_i4i.S Normal file
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@@ -0,0 +1,644 @@
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006
Free Software Foundation, Inc.
* SPDX-License-Identifier: GPL-2.0+
*/
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
!! recoded in assembly by Toshiyasu Morita
!! tm@netcom.com
/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
ELF local label prefixes by J"orn Rennecke
amylaar@cygnus.com */
/* This code used shld, thus is not suitable for SH1 / SH2. */
/* Signed / unsigned division without use of FPU, optimized for SH4.
Uses a lookup table for divisors in the range -128 .. +128, and
div1 with case distinction for larger divisors in three more ranges.
The code is lumped together with the table to allow the use of mova. */
#ifdef CONFIG_CPU_LITTLE_ENDIAN
#define L_LSB 0
#define L_LSWMSB 1
#define L_MSWLSB 2
#else
#define L_LSB 3
#define L_LSWMSB 2
#define L_MSWLSB 1
#endif
.balign 4
.global __udivsi3_i4i
.global __udivsi3_i4
.set __udivsi3_i4, __udivsi3_i4i
.type __udivsi3_i4i, @function
__udivsi3_i4i:
mov.w c128_w, r1
div0u
mov r4,r0
shlr8 r0
cmp/hi r1,r5
extu.w r5,r1
bf udiv_le128
cmp/eq r5,r1
bf udiv_ge64k
shlr r0
mov r5,r1
shll16 r5
mov.l r4,@-r15
div1 r5,r0
mov.l r1,@-r15
div1 r5,r0
div1 r5,r0
bra udiv_25
div1 r5,r0
div_le128:
mova div_table_ix,r0
bra div_le128_2
mov.b @(r0,r5),r1
udiv_le128:
mov.l r4,@-r15
mova div_table_ix,r0
mov.b @(r0,r5),r1
mov.l r5,@-r15
div_le128_2:
mova div_table_inv,r0
mov.l @(r0,r1),r1
mov r5,r0
tst #0xfe,r0
mova div_table_clz,r0
dmulu.l r1,r4
mov.b @(r0,r5),r1
bt/s div_by_1
mov r4,r0
mov.l @r15+,r5
sts mach,r0
/* clrt */
addc r4,r0
mov.l @r15+,r4
rotcr r0
rts
shld r1,r0
div_by_1_neg:
neg r4,r0
div_by_1:
mov.l @r15+,r5
rts
mov.l @r15+,r4
div_ge64k:
bt/s div_r8
div0u
shll8 r5
bra div_ge64k_2
div1 r5,r0
udiv_ge64k:
cmp/hi r0,r5
mov r5,r1
bt udiv_r8
shll8 r5
mov.l r4,@-r15
div1 r5,r0
mov.l r1,@-r15
div_ge64k_2:
div1 r5,r0
mov.l zero_l,r1
.rept 4
div1 r5,r0
.endr
mov.l r1,@-r15
div1 r5,r0
mov.w m256_w,r1
div1 r5,r0
mov.b r0,@(L_LSWMSB,r15)
xor r4,r0
and r1,r0
bra div_ge64k_end
xor r4,r0
div_r8:
shll16 r4
bra div_r8_2
shll8 r4
udiv_r8:
mov.l r4,@-r15
shll16 r4
clrt
shll8 r4
mov.l r5,@-r15
div_r8_2:
rotcl r4
mov r0,r1
div1 r5,r1
mov r4,r0
rotcl r0
mov r5,r4
div1 r5,r1
.rept 5
rotcl r0; div1 r5,r1
.endr
rotcl r0
mov.l @r15+,r5
div1 r4,r1
mov.l @r15+,r4
rts
rotcl r0
.global __sdivsi3_i4i
.global __sdivsi3_i4
.global __sdivsi3
.set __sdivsi3_i4, __sdivsi3_i4i
.set __sdivsi3, __sdivsi3_i4i
.type __sdivsi3_i4i, @function
/* This is link-compatible with a __sdivsi3 call,
but we effectively clobber only r1. */
__sdivsi3_i4i:
mov.l r4,@-r15
cmp/pz r5
mov.w c128_w, r1
bt/s pos_divisor
cmp/pz r4
mov.l r5,@-r15
neg r5,r5
bt/s neg_result
cmp/hi r1,r5
neg r4,r4
pos_result:
extu.w r5,r0
bf div_le128
cmp/eq r5,r0
mov r4,r0
shlr8 r0
bf/s div_ge64k
cmp/hi r0,r5
div0u
shll16 r5
div1 r5,r0
div1 r5,r0
div1 r5,r0
udiv_25:
mov.l zero_l,r1
div1 r5,r0
div1 r5,r0
mov.l r1,@-r15
.rept 3
div1 r5,r0
.endr
mov.b r0,@(L_MSWLSB,r15)
xtrct r4,r0
swap.w r0,r0
.rept 8
div1 r5,r0
.endr
mov.b r0,@(L_LSWMSB,r15)
div_ge64k_end:
.rept 8
div1 r5,r0
.endr
mov.l @r15+,r4 ! zero-extension and swap using LS unit.
extu.b r0,r0
mov.l @r15+,r5
or r4,r0
mov.l @r15+,r4
rts
rotcl r0
div_le128_neg:
tst #0xfe,r0
mova div_table_ix,r0
mov.b @(r0,r5),r1
mova div_table_inv,r0
bt/s div_by_1_neg
mov.l @(r0,r1),r1
mova div_table_clz,r0
dmulu.l r1,r4
mov.b @(r0,r5),r1
mov.l @r15+,r5
sts mach,r0
/* clrt */
addc r4,r0
mov.l @r15+,r4
rotcr r0
shld r1,r0
rts
neg r0,r0
pos_divisor:
mov.l r5,@-r15
bt/s pos_result
cmp/hi r1,r5
neg r4,r4
neg_result:
extu.w r5,r0
bf div_le128_neg
cmp/eq r5,r0
mov r4,r0
shlr8 r0
bf/s div_ge64k_neg
cmp/hi r0,r5
div0u
mov.l zero_l,r1
shll16 r5
div1 r5,r0
mov.l r1,@-r15
.rept 7
div1 r5,r0
.endr
mov.b r0,@(L_MSWLSB,r15)
xtrct r4,r0
swap.w r0,r0
.rept 8
div1 r5,r0
.endr
mov.b r0,@(L_LSWMSB,r15)
div_ge64k_neg_end:
.rept 8
div1 r5,r0
.endr
mov.l @r15+,r4 ! zero-extension and swap using LS unit.
extu.b r0,r1
mov.l @r15+,r5
or r4,r1
div_r8_neg_end:
mov.l @r15+,r4
rotcl r1
rts
neg r1,r0
div_ge64k_neg:
bt/s div_r8_neg
div0u
shll8 r5
mov.l zero_l,r1
.rept 6
div1 r5,r0
.endr
mov.l r1,@-r15
div1 r5,r0
mov.w m256_w,r1
div1 r5,r0
mov.b r0,@(L_LSWMSB,r15)
xor r4,r0
and r1,r0
bra div_ge64k_neg_end
xor r4,r0
c128_w:
.word 128
div_r8_neg:
clrt
shll16 r4
mov r4,r1
shll8 r1
mov r5,r4
.rept 7
rotcl r1; div1 r5,r0
.endr
mov.l @r15+,r5
rotcl r1
bra div_r8_neg_end
div1 r4,r0
m256_w:
.word 0xff00
/* This table has been generated by divtab-sh4.c. */
.balign 4
div_table_clz:
.byte 0
.byte 1
.byte 0
.byte -1
.byte -1
.byte -2
.byte -2
.byte -2
.byte -2
.byte -3
.byte -3
.byte -3
.byte -3
.byte -3
.byte -3
.byte -3
.byte -3
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -4
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -5
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
.byte -6
/* Lookup table translating positive divisor to index into table of
normalized inverse. N.B. the '0' entry is also the last entry of the
previous table, and causes an unaligned access for division by zero. */
div_table_ix:
.byte -6
.byte -128
.byte -128
.byte 0
.byte -128
.byte -64
.byte 0
.byte 64
.byte -128
.byte -96
.byte -64
.byte -32
.byte 0
.byte 32
.byte 64
.byte 96
.byte -128
.byte -112
.byte -96
.byte -80
.byte -64
.byte -48
.byte -32
.byte -16
.byte 0
.byte 16
.byte 32
.byte 48
.byte 64
.byte 80
.byte 96
.byte 112
.byte -128
.byte -120
.byte -112
.byte -104
.byte -96
.byte -88
.byte -80
.byte -72
.byte -64
.byte -56
.byte -48
.byte -40
.byte -32
.byte -24
.byte -16
.byte -8
.byte 0
.byte 8
.byte 16
.byte 24
.byte 32
.byte 40
.byte 48
.byte 56
.byte 64
.byte 72
.byte 80
.byte 88
.byte 96
.byte 104
.byte 112
.byte 120
.byte -128
.byte -124
.byte -120
.byte -116
.byte -112
.byte -108
.byte -104
.byte -100
.byte -96
.byte -92
.byte -88
.byte -84
.byte -80
.byte -76
.byte -72
.byte -68
.byte -64
.byte -60
.byte -56
.byte -52
.byte -48
.byte -44
.byte -40
.byte -36
.byte -32
.byte -28
.byte -24
.byte -20
.byte -16
.byte -12
.byte -8
.byte -4
.byte 0
.byte 4
.byte 8
.byte 12
.byte 16
.byte 20
.byte 24
.byte 28
.byte 32
.byte 36
.byte 40
.byte 44
.byte 48
.byte 52
.byte 56
.byte 60
.byte 64
.byte 68
.byte 72
.byte 76
.byte 80
.byte 84
.byte 88
.byte 92
.byte 96
.byte 100
.byte 104
.byte 108
.byte 112
.byte 116
.byte 120
.byte 124
.byte -128
/* 1/64 .. 1/127, normalized. There is an implicit leading 1 in bit 32. */
.balign 4
zero_l:
.long 0x0
.long 0xF81F81F9
.long 0xF07C1F08
.long 0xE9131AC0
.long 0xE1E1E1E2
.long 0xDAE6076C
.long 0xD41D41D5
.long 0xCD856891
.long 0xC71C71C8
.long 0xC0E07039
.long 0xBACF914D
.long 0xB4E81B4F
.long 0xAF286BCB
.long 0xA98EF607
.long 0xA41A41A5
.long 0x9EC8E952
.long 0x9999999A
.long 0x948B0FCE
.long 0x8F9C18FA
.long 0x8ACB90F7
.long 0x86186187
.long 0x81818182
.long 0x7D05F418
.long 0x78A4C818
.long 0x745D1746
.long 0x702E05C1
.long 0x6C16C16D
.long 0x68168169
.long 0x642C8591
.long 0x60581606
.long 0x5C9882BA
.long 0x58ED2309
div_table_inv:
.long 0x55555556
.long 0x51D07EAF
.long 0x4E5E0A73
.long 0x4AFD6A06
.long 0x47AE147B
.long 0x446F8657
.long 0x41414142
.long 0x3E22CBCF
.long 0x3B13B13C
.long 0x38138139
.long 0x3521CFB3
.long 0x323E34A3
.long 0x2F684BDB
.long 0x2C9FB4D9
.long 0x29E4129F
.long 0x27350B89
.long 0x24924925
.long 0x21FB7813
.long 0x1F7047DD
.long 0x1CF06ADB
.long 0x1A7B9612
.long 0x18118119
.long 0x15B1E5F8
.long 0x135C8114
.long 0x11111112
.long 0xECF56BF
.long 0xC9714FC
.long 0xA6810A7
.long 0x8421085
.long 0x624DD30
.long 0x4104105
.long 0x2040811
/* maximum error: 0.987342 scaled: 0.921875*/

65
u-boot/arch/sh/lib/zimageboot.c Normal file
View File

@@ -0,0 +1,65 @@
/*
* (C) Copyright 2010
* Renesas Solutions Corp.
* Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Linux SuperH zImage loading and boot
*/
#include <common.h>
#include <asm/io.h>
#include <asm/zimage.h>
int do_sh_zimageboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong (*zboot_entry)(int, char * const []) = NULL;
char *s0, *s1;
unsigned char *param = NULL;
char *cmdline;
char *bootargs;
disable_interrupts();
if (argc >= 3) {
/* argv[1] holds the address of the zImage */
s0 = argv[1];
/* argv[2] holds the address of zero page */
s1 = argv[2];
} else {
goto exit;
}
if (s0)
zboot_entry = (ulong (*)(int, char * const []))simple_strtoul(s0, NULL, 16);
/* empty_zero_page */
if (s1)
param = (unsigned char*)simple_strtoul(s1, NULL, 16);
/* Linux kernel command line */
cmdline = (char *)param + COMMAND_LINE;
bootargs = getenv("bootargs");
/* Clear zero page */
/* cppcheck-suppress nullPointer */
memset(param, 0, 0x1000);
/* Set commandline */
strcpy(cmdline, bootargs);
/* Boot */
zboot_entry(0, NULL);
exit:
return -1;
}
U_BOOT_CMD(
zimageboot, 3, 0, do_sh_zimageboot,
"Boot zImage for Renesas SH",
""
);