avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
21
u-boot/arch/nds32/cpu/n1213/ag101/Makefile
Normal file
21
u-boot/arch/nds32/cpu/n1213/ag101/Makefile
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@@ -0,0 +1,21 @@
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#
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# Copyright (C) 2011 Andes Technology Corporation
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# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := cpu.o timer.o
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ifndef CONFIG_SKIP_LOWLEVEL_INIT
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obj-y += lowlevel_init.o
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endif
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ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
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obj-y += watchdog.o
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endif
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68
u-boot/arch/nds32/cpu/n1213/ag101/cpu.c
Normal file
68
u-boot/arch/nds32/cpu/n1213/ag101/cpu.c
Normal file
@@ -0,0 +1,68 @@
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* Copyright (C) 2011 Andes Technology Corporation
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* CPU specific code */
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#include <common.h>
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#include <command.h>
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#include <watchdog.h>
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#include <asm/cache.h>
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#include <faraday/ftwdt010_wdt.h>
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/*
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* cleanup_before_linux() is called just before we call linux
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* it prepares the processor for linux
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*
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* we disable interrupt and caches.
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*/
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int cleanup_before_linux(void)
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{
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disable_interrupts();
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#ifdef CONFIG_MMU
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/* turn off I/D-cache */
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icache_disable();
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dcache_disable();
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/* flush I/D-cache */
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invalidate_icac();
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invalidate_dcac();
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#endif
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return 0;
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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disable_interrupts();
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/*
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* reset to the base addr of andesboot.
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* currently no ROM loader at addr 0.
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* do not use reset_cpu(0);
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*/
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#ifdef CONFIG_FTWDT010_WATCHDOG
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/*
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* workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
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* automatic hardware reset when booting Linux.
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* Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
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*/
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ftwdt010_wdt_reset();
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while (1)
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;
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#endif /* CONFIG_FTWDT010_WATCHDOG */
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/*NOTREACHED*/
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}
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336
u-boot/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
Normal file
336
u-boot/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
Normal file
@@ -0,0 +1,336 @@
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/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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.text
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#include <common.h>
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#include <config.h>
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#include <asm/macro.h>
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#include <generated/asm-offsets.h>
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/*
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* parameters for the SDRAM controller
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*/
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#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
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#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
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#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
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#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
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#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
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#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
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#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
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#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
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#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
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#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
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#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
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#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
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/*
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* for Orca and Emerald
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*/
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#define BOARD_ID_REG 0x104
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#define BOARD_ID_FAMILY_MASK 0xfff000
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#define BOARD_ID_FAMILY_V5 0x556000
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#define BOARD_ID_FAMILY_K7 0x74b000
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/*
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* parameters for the static memory controller
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*/
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#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
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#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
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#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
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#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
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/*
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* parameters for the ahbc controller
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*/
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#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
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#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
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/*
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* for Orca and Emerald
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*/
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#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
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#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
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/*
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* parameters for the pmu controoler
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*/
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#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
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/*
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* numeric 7 segment display
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*/
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.macro led, num
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write32 CONFIG_DEBUG_LED, \num
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.endm
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/*
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* Waiting for SDRAM to set up
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*/
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.macro wait_sdram
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li $r0, CONFIG_FTSDMC021_BASE
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1:
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lwi $r1, [$r0+FTSDMC021_CR2]
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bnez $r1, 1b
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.endm
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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.globl lowlevel_init
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lowlevel_init:
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move $r10, $lp
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led 0x0
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jal mem_init
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led 0x10
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jal remap
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#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
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led 0x1f
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jal enable_fpu
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#endif
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led 0x20
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ret $r10
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mem_init:
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move $r11, $lp
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/*
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* mem_init:
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* There are 2 bank connected to FTSMC020 on AG101
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* BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
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* we need to set onboard SDRAM before remap and relocation.
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*/
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led 0x01
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/*
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* for Orca and Emerald
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* disable write protection and reset bank size
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*/
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li $r0, SMC_BANK0_CR_A
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lwi $r1, [$r0+#0x00]
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ori $r1, $r1, 0x8f0
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xori $r1, $r1, 0x8f0
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/*
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* check board
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*/
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li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
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lwi $r3, [$r3]
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li $r4, BOARD_ID_FAMILY_MASK
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and $r3, $r3, $r4
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li $r4, BOARD_ID_FAMILY_K7
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xor $r4, $r3, $r4
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beqz $r4, use_flash_16bit_boot
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/*
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* 32-bit mode
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*/
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use_flash_32bit_boot:
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ori $r1, $r1, 0x50
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li $r2, 0x00151151
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j sdram_b0_cr
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/*
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* 16-bit mode
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*/
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use_flash_16bit_boot:
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ori $r1, $r1, 0x60
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li $r2, 0x00153153
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/*
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* SRAM bank0 config
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*/
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sdram_b0_cr:
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swi $r1, [$r0+#0x00]
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swi $r2, [$r0+#0x04]
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/*
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* config AHB Controller
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*/
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led 0x02
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/*
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* config PMU controller
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*/
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/* ftpmu010_dlldis_disable, must do it in lowleve_init */
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led 0x03
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setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
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/*
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* config SDRAM controller
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*/
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led 0x04
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write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
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led 0x05
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write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
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led 0x06
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write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
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led 0x07
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write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
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wait_sdram
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led 0x08
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write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
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wait_sdram
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led 0x09
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write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
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wait_sdram
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led 0x0a
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move $lp, $r11
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ret
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remap:
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move $r11, $lp
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#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
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bal 2f
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relo_base:
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move $r0, $lp
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#else
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relo_base:
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mfusr $r0, $pc
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#endif /* __NDS32_N1213_43U1H__ */
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|
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/*
|
||||
* Remapping
|
||||
*/
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||||
led 0x1a
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write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800
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write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880
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|
||||
/* clear empty BSR registers */
|
||||
led 0x1b
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||||
li $r4, CONFIG_FTSDMC021_BASE
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||||
li $r5, 0x0
|
||||
swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
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||||
swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
|
||||
|
||||
#ifdef CONFIG_MEM_REMAP
|
||||
/*
|
||||
* Copy ROM code to SDRAM base for memory remap layout.
|
||||
* This is not the real relocation, the real relocation is the function
|
||||
* relocate_code() is start.S which supports the systems is memory
|
||||
* remapped or not.
|
||||
*/
|
||||
/*
|
||||
* Doing memory remap is essential for preparing some non-OS or RTOS
|
||||
* applications.
|
||||
*
|
||||
* This is also a must on ADP-AG101 board.
|
||||
* The reason is because the ROM/FLASH circuit on PCB board.
|
||||
* AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
|
||||
* ROM/FLASH is used to boot.
|
||||
*
|
||||
* When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
|
||||
* and the FLASH is connected to BANK1.
|
||||
* When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
|
||||
* and the FLASH is connected to BANK0.
|
||||
* It will occur problem when doing flash probing if the flash is at
|
||||
* BANK0 (0x00000000) while memory remapping was skipped.
|
||||
*
|
||||
* Other board like ADP-AG101P may not enable this since there is only
|
||||
* a FLASH connected to bank0.
|
||||
*/
|
||||
led 0x11
|
||||
/*
|
||||
* for Orca and Emerald
|
||||
* read sdram base address automatically
|
||||
*/
|
||||
li $r5, AHBC_BSR6_A
|
||||
lwi $r8, [$r5]
|
||||
li $r4, 0xfff00000
|
||||
and $r4, $r4, $r8
|
||||
|
||||
|
||||
li $r5, 0x0
|
||||
la $r1, relo_base /* get $pc or $lp */
|
||||
sub $r2, $r0, $r1
|
||||
sethi $r6, hi20(_end)
|
||||
ori $r6, $r6, lo12(_end)
|
||||
add $r6, $r6, $r2
|
||||
1:
|
||||
lwi.p $r7, [$r5], #4
|
||||
swi.p $r7, [$r4], #4
|
||||
blt $r5, $r6, 1b
|
||||
|
||||
/* set remap bit */
|
||||
/*
|
||||
* MEM remap bit is operational
|
||||
* - use it to map writeable memory at 0x00000000, in place of flash
|
||||
* - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
|
||||
* - after remap: flash/rom 0x80000000, sdram: 0x00000000
|
||||
*/
|
||||
led 0x1c
|
||||
write32 SDMC_B0_BSR_A, 0x00001000
|
||||
write32 SDMC_B1_BSR_A, 0x00001200
|
||||
li $r5, CONFIG_SYS_TEXT_BASE /* flash base address */
|
||||
add $r11, $r11, $r5 /* add flash address offset for ret */
|
||||
add $r10, $r10, $r5
|
||||
move $lp, $r11
|
||||
setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
|
||||
|
||||
/*
|
||||
* for Orca and Emerald
|
||||
* extend sdram size from 256MB to 2GB
|
||||
*/
|
||||
li $r5, AHBC_BSR6_A
|
||||
lwi $r6, [$r5]
|
||||
li $r4, 0xfff0ffff
|
||||
and $r6 ,$r4, $r6
|
||||
li $r4, 0x000b0000
|
||||
or $r6, $r4, $r6
|
||||
swi $r6, [$r5]
|
||||
|
||||
/*
|
||||
* for Orca and Emerald
|
||||
* extend rom base from 256MB to 2GB
|
||||
*/
|
||||
li $r4, AHBC_BSR4_A
|
||||
lwi $r5, [$r4]
|
||||
li $r6, 0xffffff
|
||||
and $r5, $r5, $r6
|
||||
li $r6, 0x80000000
|
||||
or $r5, $r5, $r6
|
||||
swi $r5, [$r4]
|
||||
#endif /* #ifdef CONFIG_MEM_REMAP */
|
||||
move $lp, $r11
|
||||
2:
|
||||
ret
|
||||
|
||||
/*
|
||||
* enable_fpu:
|
||||
* Some of Andes CPU version support FPU coprocessor, if so,
|
||||
* and toolchain support FPU instruction set, we should enable it.
|
||||
*/
|
||||
#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
|
||||
enable_fpu:
|
||||
mfsr $r0, $CPU_VER /* enable FPU if it exists */
|
||||
srli $r0, $r0, 3
|
||||
andi $r0, $r0, 1
|
||||
beqz $r0, 1f /* skip if no COP */
|
||||
mfsr $r0, $FUCOP_EXIST
|
||||
srli $r0, $r0, 31
|
||||
beqz $r0, 1f /* skip if no FPU */
|
||||
mfsr $r0, $FUCOP_CTL
|
||||
ori $r0, $r0, 1
|
||||
mtsr $r0, $FUCOP_CTL
|
||||
1:
|
||||
ret
|
||||
#endif
|
||||
|
||||
.globl show_led
|
||||
show_led:
|
||||
li $r8, (CONFIG_DEBUG_LED)
|
||||
swi $r7, [$r8]
|
||||
ret
|
||||
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
191
u-boot/arch/nds32/cpu/n1213/ag101/timer.c
Normal file
191
u-boot/arch/nds32/cpu/n1213/ag101/timer.c
Normal file
@@ -0,0 +1,191 @@
|
||||
/*
|
||||
* (C) Copyright 2009 Faraday Technology
|
||||
* Po-Yu Chuang <ratbert@faraday-tech.com>
|
||||
*
|
||||
* Copyright (C) 2011 Andes Technology Corporation
|
||||
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
|
||||
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <faraday/fttmr010.h>
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong lastdec;
|
||||
|
||||
int timer_init(void)
|
||||
{
|
||||
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
|
||||
unsigned int cr;
|
||||
|
||||
debug("%s()\n", __func__);
|
||||
|
||||
/* disable timers */
|
||||
writel(0, &tmr->cr);
|
||||
|
||||
#ifdef CONFIG_FTTMR010_EXT_CLK
|
||||
/* use 32768Hz oscillator for RTC, WDT, TIMER */
|
||||
ftpmu010_32768osc_enable();
|
||||
#endif
|
||||
|
||||
/* setup timer */
|
||||
writel(TIMER_LOAD_VAL, &tmr->timer3_load);
|
||||
writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
|
||||
writel(0, &tmr->timer3_match1);
|
||||
writel(0, &tmr->timer3_match2);
|
||||
|
||||
/* we don't want timer to issue interrupts */
|
||||
writel(FTTMR010_TM3_MATCH1 |
|
||||
FTTMR010_TM3_MATCH2 |
|
||||
FTTMR010_TM3_OVERFLOW,
|
||||
&tmr->interrupt_mask);
|
||||
|
||||
cr = readl(&tmr->cr);
|
||||
#ifdef CONFIG_FTTMR010_EXT_CLK
|
||||
cr |= FTTMR010_TM3_CLOCK; /* use external clock */
|
||||
#endif
|
||||
cr |= FTTMR010_TM3_ENABLE;
|
||||
writel(cr, &tmr->cr);
|
||||
|
||||
/* init the timestamp and lastdec value */
|
||||
reset_timer_masked();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* timer without interrupts
|
||||
*/
|
||||
|
||||
/*
|
||||
* reset time
|
||||
*/
|
||||
void reset_timer_masked(void)
|
||||
{
|
||||
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
|
||||
|
||||
/* capure current decrementer value time */
|
||||
#ifdef CONFIG_FTTMR010_EXT_CLK
|
||||
lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
|
||||
#else
|
||||
lastdec = readl(&tmr->timer3_counter) /
|
||||
(CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
|
||||
#endif
|
||||
timestamp = 0; /* start "advancing" time stamp from 0 */
|
||||
|
||||
debug("%s(): lastdec = %lx\n", __func__, lastdec);
|
||||
}
|
||||
|
||||
void reset_timer(void)
|
||||
{
|
||||
debug("%s()\n", __func__);
|
||||
reset_timer_masked();
|
||||
}
|
||||
|
||||
/*
|
||||
* return timer ticks
|
||||
*/
|
||||
ulong get_timer_masked(void)
|
||||
{
|
||||
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
|
||||
|
||||
/* current tick value */
|
||||
#ifdef CONFIG_FTTMR010_EXT_CLK
|
||||
ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
|
||||
#else
|
||||
ulong now = readl(&tmr->timer3_counter) /
|
||||
(CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
|
||||
#endif
|
||||
|
||||
debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
|
||||
|
||||
if (lastdec >= now) {
|
||||
/*
|
||||
* normal mode (non roll)
|
||||
* move stamp fordward with absoulte diff ticks
|
||||
*/
|
||||
timestamp += lastdec - now;
|
||||
} else {
|
||||
/*
|
||||
* we have overflow of the count down timer
|
||||
*
|
||||
* nts = ts + ld + (TLV - now)
|
||||
* ts=old stamp, ld=time that passed before passing through -1
|
||||
* (TLV-now) amount of time after passing though -1
|
||||
* nts = new "advancing time stamp"...it could also roll and
|
||||
* cause problems.
|
||||
*/
|
||||
timestamp += lastdec + TIMER_LOAD_VAL - now;
|
||||
}
|
||||
|
||||
lastdec = now;
|
||||
|
||||
debug("%s() returns %lx\n", __func__, timestamp);
|
||||
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
/*
|
||||
* return difference between timer ticks and base
|
||||
*/
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
debug("%s(%lx)\n", __func__, base);
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
void set_timer(ulong t)
|
||||
{
|
||||
debug("%s(%lx)\n", __func__, t);
|
||||
timestamp = t;
|
||||
}
|
||||
|
||||
/* delay x useconds AND preserve advance timestamp value */
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
|
||||
|
||||
#ifdef CONFIG_FTTMR010_EXT_CLK
|
||||
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
|
||||
#else
|
||||
long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
|
||||
#endif
|
||||
unsigned long now, last = readl(&tmr->timer3_counter);
|
||||
|
||||
debug("%s(%lu)\n", __func__, usec);
|
||||
while (tmo > 0) {
|
||||
now = readl(&tmr->timer3_counter);
|
||||
if (now > last) /* count down timer overflow */
|
||||
tmo -= TIMER_LOAD_VAL + last - now;
|
||||
else
|
||||
tmo -= last - now;
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On ARM it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
debug("%s()\n", __func__);
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk(void)
|
||||
{
|
||||
debug("%s()\n", __func__);
|
||||
#ifdef CONFIG_FTTMR010_EXT_CLK
|
||||
return CONFIG_SYS_HZ;
|
||||
#else
|
||||
return CONFIG_SYS_CLK_FREQ;
|
||||
#endif
|
||||
}
|
||||
33
u-boot/arch/nds32/cpu/n1213/ag101/watchdog.S
Normal file
33
u-boot/arch/nds32/cpu/n1213/ag101/watchdog.S
Normal file
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Andes Technology Corporation
|
||||
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/arch-ag101/ag101.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
.text
|
||||
|
||||
#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
|
||||
ENTRY(turnoff_watchdog)
|
||||
|
||||
#define WD_CR 0xC
|
||||
#define WD_ENABLE 0x1
|
||||
|
||||
! Turn off the watchdog, according to Faraday FTWDT010 spec
|
||||
li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
|
||||
lwi $p1, [$p0] ! Get the config of WD
|
||||
andi $p1, $p1, 0x1f ! Wipe out useless bits
|
||||
li $r0, ~WD_ENABLE
|
||||
and $p1, $p1, $r0 ! Set WD disable
|
||||
sw $p1, [$p0] ! Write back to WD CR
|
||||
|
||||
! Disable Interrupts by clear GIE in $PSW reg
|
||||
setgie.d
|
||||
|
||||
ret
|
||||
|
||||
ENDPROC(turnoff_watchdog)
|
||||
#endif
|
||||
Reference in New Issue
Block a user