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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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18
u-boot/arch/nds32/Kconfig Normal file
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menu "NDS32 architecture"
depends on NDS32
config SYS_ARCH
default "nds32"
choice
prompt "Target select"
optional
config TARGET_ADP_AG101P
bool "Support adp-ag101p"
endchoice
source "board/AndesTech/adp-ag101p/Kconfig"
endmenu

8
u-boot/arch/nds32/Makefile Normal file
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#
# SPDX-License-Identifier: GPL-2.0+
#
head-y := arch/nds32/cpu/$(CPU)/start.o
libs-y += arch/nds32/cpu/$(CPU)/
libs-y += arch/nds32/lib/

22
u-boot/arch/nds32/config.mk Normal file
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#
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2011
# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
#
# SPDX-License-Identifier: GPL-2.0+
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := nds32le-linux-
endif
CONFIG_STANDALONE_LOAD_ADDR = 0x300000 \
-T $(srctree)/examples/standalone/nds32.lds
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -mrelax
PLATFORM_RELFLAGS += -gdwarf-2
PLATFORM_CPPFLAGS += -D__nds32__ -G0 -ffixed-10 -fpie
LDFLAGS_u-boot = --gc-sections --relax

14
u-boot/arch/nds32/cpu/n1213/Makefile Normal file
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2011 Andes Technology Corporation
# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
extra-y = start.o
obj-$(if $(filter ag101,$(SOC)),y) += ag101/

21
u-boot/arch/nds32/cpu/n1213/ag101/Makefile Normal file
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#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# Copyright (C) 2011 Andes Technology Corporation
# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := cpu.o timer.o
ifndef CONFIG_SKIP_LOWLEVEL_INIT
obj-y += lowlevel_init.o
endif
ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
obj-y += watchdog.o
endif

68
u-boot/arch/nds32/cpu/n1213/ag101/cpu.c Normal file
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/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* CPU specific code */
#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
#include <faraday/ftwdt010_wdt.h>
/*
* cleanup_before_linux() is called just before we call linux
* it prepares the processor for linux
*
* we disable interrupt and caches.
*/
int cleanup_before_linux(void)
{
disable_interrupts();
#ifdef CONFIG_MMU
/* turn off I/D-cache */
icache_disable();
dcache_disable();
/* flush I/D-cache */
invalidate_icac();
invalidate_dcac();
#endif
return 0;
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
/*
* reset to the base addr of andesboot.
* currently no ROM loader at addr 0.
* do not use reset_cpu(0);
*/
#ifdef CONFIG_FTWDT010_WATCHDOG
/*
* workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
* automatic hardware reset when booting Linux.
* Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
*/
ftwdt010_wdt_reset();
while (1)
;
#endif /* CONFIG_FTWDT010_WATCHDOG */
/*NOTREACHED*/
}

336
u-boot/arch/nds32/cpu/n1213/ag101/lowlevel_init.S Normal file
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/*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
.text
#include <common.h>
#include <config.h>
#include <asm/macro.h>
#include <generated/asm-offsets.h>
/*
* parameters for the SDRAM controller
*/
#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
/*
* for Orca and Emerald
*/
#define BOARD_ID_REG 0x104
#define BOARD_ID_FAMILY_MASK 0xfff000
#define BOARD_ID_FAMILY_V5 0x556000
#define BOARD_ID_FAMILY_K7 0x74b000
/*
* parameters for the static memory controller
*/
#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
/*
* parameters for the ahbc controller
*/
#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
/*
* for Orca and Emerald
*/
#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
/*
* parameters for the pmu controoler
*/
#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
/*
* numeric 7 segment display
*/
.macro led, num
write32 CONFIG_DEBUG_LED, \num
.endm
/*
* Waiting for SDRAM to set up
*/
.macro wait_sdram
li $r0, CONFIG_FTSDMC021_BASE
1:
lwi $r1, [$r0+FTSDMC021_CR2]
bnez $r1, 1b
.endm
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
.globl lowlevel_init
lowlevel_init:
move $r10, $lp
led 0x0
jal mem_init
led 0x10
jal remap
#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
led 0x1f
jal enable_fpu
#endif
led 0x20
ret $r10
mem_init:
move $r11, $lp
/*
* mem_init:
* There are 2 bank connected to FTSMC020 on AG101
* BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
* we need to set onboard SDRAM before remap and relocation.
*/
led 0x01
/*
* for Orca and Emerald
* disable write protection and reset bank size
*/
li $r0, SMC_BANK0_CR_A
lwi $r1, [$r0+#0x00]
ori $r1, $r1, 0x8f0
xori $r1, $r1, 0x8f0
/*
* check board
*/
li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
lwi $r3, [$r3]
li $r4, BOARD_ID_FAMILY_MASK
and $r3, $r3, $r4
li $r4, BOARD_ID_FAMILY_K7
xor $r4, $r3, $r4
beqz $r4, use_flash_16bit_boot
/*
* 32-bit mode
*/
use_flash_32bit_boot:
ori $r1, $r1, 0x50
li $r2, 0x00151151
j sdram_b0_cr
/*
* 16-bit mode
*/
use_flash_16bit_boot:
ori $r1, $r1, 0x60
li $r2, 0x00153153
/*
* SRAM bank0 config
*/
sdram_b0_cr:
swi $r1, [$r0+#0x00]
swi $r2, [$r0+#0x04]
/*
* config AHB Controller
*/
led 0x02
/*
* config PMU controller
*/
/* ftpmu010_dlldis_disable, must do it in lowleve_init */
led 0x03
setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
/*
* config SDRAM controller
*/
led 0x04
write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
led 0x05
write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
led 0x06
write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
led 0x07
write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
wait_sdram
led 0x08
write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
wait_sdram
led 0x09
write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
wait_sdram
led 0x0a
move $lp, $r11
ret
remap:
move $r11, $lp
#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
bal 2f
relo_base:
move $r0, $lp
#else
relo_base:
mfusr $r0, $pc
#endif /* __NDS32_N1213_43U1H__ */
/*
* Remapping
*/
led 0x1a
write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800
write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880
/* clear empty BSR registers */
led 0x1b
li $r4, CONFIG_FTSDMC021_BASE
li $r5, 0x0
swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
#ifdef CONFIG_MEM_REMAP
/*
* Copy ROM code to SDRAM base for memory remap layout.
* This is not the real relocation, the real relocation is the function
* relocate_code() is start.S which supports the systems is memory
* remapped or not.
*/
/*
* Doing memory remap is essential for preparing some non-OS or RTOS
* applications.
*
* This is also a must on ADP-AG101 board.
* The reason is because the ROM/FLASH circuit on PCB board.
* AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
* ROM/FLASH is used to boot.
*
* When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
* and the FLASH is connected to BANK1.
* When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
* and the FLASH is connected to BANK0.
* It will occur problem when doing flash probing if the flash is at
* BANK0 (0x00000000) while memory remapping was skipped.
*
* Other board like ADP-AG101P may not enable this since there is only
* a FLASH connected to bank0.
*/
led 0x11
/*
* for Orca and Emerald
* read sdram base address automatically
*/
li $r5, AHBC_BSR6_A
lwi $r8, [$r5]
li $r4, 0xfff00000
and $r4, $r4, $r8
li $r5, 0x0
la $r1, relo_base /* get $pc or $lp */
sub $r2, $r0, $r1
sethi $r6, hi20(_end)
ori $r6, $r6, lo12(_end)
add $r6, $r6, $r2
1:
lwi.p $r7, [$r5], #4
swi.p $r7, [$r4], #4
blt $r5, $r6, 1b
/* set remap bit */
/*
* MEM remap bit is operational
* - use it to map writeable memory at 0x00000000, in place of flash
* - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
* - after remap: flash/rom 0x80000000, sdram: 0x00000000
*/
led 0x1c
write32 SDMC_B0_BSR_A, 0x00001000
write32 SDMC_B1_BSR_A, 0x00001200
li $r5, CONFIG_SYS_TEXT_BASE /* flash base address */
add $r11, $r11, $r5 /* add flash address offset for ret */
add $r10, $r10, $r5
move $lp, $r11
setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
/*
* for Orca and Emerald
* extend sdram size from 256MB to 2GB
*/
li $r5, AHBC_BSR6_A
lwi $r6, [$r5]
li $r4, 0xfff0ffff
and $r6 ,$r4, $r6
li $r4, 0x000b0000
or $r6, $r4, $r6
swi $r6, [$r5]
/*
* for Orca and Emerald
* extend rom base from 256MB to 2GB
*/
li $r4, AHBC_BSR4_A
lwi $r5, [$r4]
li $r6, 0xffffff
and $r5, $r5, $r6
li $r6, 0x80000000
or $r5, $r5, $r6
swi $r5, [$r4]
#endif /* #ifdef CONFIG_MEM_REMAP */
move $lp, $r11
2:
ret
/*
* enable_fpu:
* Some of Andes CPU version support FPU coprocessor, if so,
* and toolchain support FPU instruction set, we should enable it.
*/
#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
enable_fpu:
mfsr $r0, $CPU_VER /* enable FPU if it exists */
srli $r0, $r0, 3
andi $r0, $r0, 1
beqz $r0, 1f /* skip if no COP */
mfsr $r0, $FUCOP_EXIST
srli $r0, $r0, 31
beqz $r0, 1f /* skip if no FPU */
mfsr $r0, $FUCOP_CTL
ori $r0, $r0, 1
mtsr $r0, $FUCOP_CTL
1:
ret
#endif
.globl show_led
show_led:
li $r8, (CONFIG_DEBUG_LED)
swi $r7, [$r8]
ret
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */

191
u-boot/arch/nds32/cpu/n1213/ag101/timer.c Normal file
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/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <faraday/fttmr010.h>
static ulong timestamp;
static ulong lastdec;
int timer_init(void)
{
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
unsigned int cr;
debug("%s()\n", __func__);
/* disable timers */
writel(0, &tmr->cr);
#ifdef CONFIG_FTTMR010_EXT_CLK
/* use 32768Hz oscillator for RTC, WDT, TIMER */
ftpmu010_32768osc_enable();
#endif
/* setup timer */
writel(TIMER_LOAD_VAL, &tmr->timer3_load);
writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
writel(0, &tmr->timer3_match1);
writel(0, &tmr->timer3_match2);
/* we don't want timer to issue interrupts */
writel(FTTMR010_TM3_MATCH1 |
FTTMR010_TM3_MATCH2 |
FTTMR010_TM3_OVERFLOW,
&tmr->interrupt_mask);
cr = readl(&tmr->cr);
#ifdef CONFIG_FTTMR010_EXT_CLK
cr |= FTTMR010_TM3_CLOCK; /* use external clock */
#endif
cr |= FTTMR010_TM3_ENABLE;
writel(cr, &tmr->cr);
/* init the timestamp and lastdec value */
reset_timer_masked();
return 0;
}
/*
* timer without interrupts
*/
/*
* reset time
*/
void reset_timer_masked(void)
{
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
/* capure current decrementer value time */
#ifdef CONFIG_FTTMR010_EXT_CLK
lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
#else
lastdec = readl(&tmr->timer3_counter) /
(CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
#endif
timestamp = 0; /* start "advancing" time stamp from 0 */
debug("%s(): lastdec = %lx\n", __func__, lastdec);
}
void reset_timer(void)
{
debug("%s()\n", __func__);
reset_timer_masked();
}
/*
* return timer ticks
*/
ulong get_timer_masked(void)
{
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
/* current tick value */
#ifdef CONFIG_FTTMR010_EXT_CLK
ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
#else
ulong now = readl(&tmr->timer3_counter) /
(CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
#endif
debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
if (lastdec >= now) {
/*
* normal mode (non roll)
* move stamp fordward with absoulte diff ticks
*/
timestamp += lastdec - now;
} else {
/*
* we have overflow of the count down timer
*
* nts = ts + ld + (TLV - now)
* ts=old stamp, ld=time that passed before passing through -1
* (TLV-now) amount of time after passing though -1
* nts = new "advancing time stamp"...it could also roll and
* cause problems.
*/
timestamp += lastdec + TIMER_LOAD_VAL - now;
}
lastdec = now;
debug("%s() returns %lx\n", __func__, timestamp);
return timestamp;
}
/*
* return difference between timer ticks and base
*/
ulong get_timer(ulong base)
{
debug("%s(%lx)\n", __func__, base);
return get_timer_masked() - base;
}
void set_timer(ulong t)
{
debug("%s(%lx)\n", __func__, t);
timestamp = t;
}
/* delay x useconds AND preserve advance timestamp value */
void __udelay(unsigned long usec)
{
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
#ifdef CONFIG_FTTMR010_EXT_CLK
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
#else
long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
#endif
unsigned long now, last = readl(&tmr->timer3_counter);
debug("%s(%lu)\n", __func__, usec);
while (tmo > 0) {
now = readl(&tmr->timer3_counter);
if (now > last) /* count down timer overflow */
tmo -= TIMER_LOAD_VAL + last - now;
else
tmo -= last - now;
last = now;
}
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
debug("%s()\n", __func__);
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
debug("%s()\n", __func__);
#ifdef CONFIG_FTTMR010_EXT_CLK
return CONFIG_SYS_HZ;
#else
return CONFIG_SYS_CLK_FREQ;
#endif
}

33
u-boot/arch/nds32/cpu/n1213/ag101/watchdog.S Normal file
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/*
* Copyright (C) 2011 Andes Technology Corporation
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch-ag101/ag101.h>
#include <linux/linkage.h>
.text
#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
ENTRY(turnoff_watchdog)
#define WD_CR 0xC
#define WD_ENABLE 0x1
! Turn off the watchdog, according to Faraday FTWDT010 spec
li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
lwi $p1, [$p0] ! Get the config of WD
andi $p1, $p1, 0x1f ! Wipe out useless bits
li $r0, ~WD_ENABLE
and $p1, $p1, $r0 ! Set WD disable
sw $p1, [$p0] ! Write back to WD CR
! Disable Interrupts by clear GIE in $PSW reg
setgie.d
ret
ENDPROC(turnoff_watchdog)
#endif

531
u-boot/arch/nds32/cpu/n1213/start.S Normal file
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/*
* Andesboot - Startup Code for Whitiger core
*
* Copyright (C) 2006 Andes Technology Corporation
* Copyright (C) 2006 Shawn Lin <nobuhiro@andestech.com>
* Copyright (C) 2011 Macpaul Lin <macpaul@andestech.com>
* Greentime Hu <greentime@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
#include <asm/macro.h>
/*
* Jump vector table for EVIC mode
*/
#define ENA_DCAC 2UL
#define DIS_DCAC ~ENA_DCAC
#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
#define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
#define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
#define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
#define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
#define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
#define PSW $ir0
#define EIT_INTR_PSW $ir1 ! interruption $PSW
#define EIT_PREV_IPSW $ir2 ! previous $IPSW
#define EIT_IVB $ir3 ! intr vector base address
#define EIT_EVA $ir4 ! MMU related Exception VA reg
#define EIT_PREV_EVA $ir5 ! previous $eva
#define EIT_ITYPE $ir6 ! interruption type
#define EIT_PREV_ITYPE $ir7 ! prev intr type
#define EIT_MACH_ERR $ir8 ! machine error log
#define EIT_INTR_PC $ir9 ! Interruption PC
#define EIT_PREV_IPC $ir10 ! previous $IPC
#define EIT_OVL_INTR_PC $ir11 ! overflow interruption PC
#define EIT_PREV_P0 $ir12 ! prev $P0
#define EIT_PREV_P1 $ir13 ! prev $p1
#define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
#define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
#define MR_CAC_CTL $mr8
.globl _start
_start: j reset
j tlb_fill
j tlb_not_present
j tlb_misc
j tlb_vlpt_miss
j machine_error
j debug
j general_exception
j syscall
j internal_interrupt ! H0I
j internal_interrupt ! H1I
j internal_interrupt ! H2I
j internal_interrupt ! H3I
j internal_interrupt ! H4I
j internal_interrupt ! H5I
j software_interrupt ! S0I
.balign 16
/*
* Andesboot Startup Code (reset vector)
*
* 1. bootstrap
* 1.1 reset - start of u-boot
* 1.2 to superuser mode - as is when reset
* 1.4 Do lowlevel_init
* - (this will jump out to lowlevel_init.S in SoC)
* - (lowlevel_init)
* 1.3 Turn off watchdog timer
* - (this will jump out to watchdog.S in SoC)
* - (turnoff_watchdog)
* 2. Do critical init when reboot (not from mem)
* 3. Relocate andesboot to ram
* 4. Setup stack
* 5. Jump to second stage (board_init_r)
*/
/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
.globl _TEXT_BASE
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
* Subtracting _start from them lets the linker put their
* relative position in the executable instead of leaving
* them null.
*/
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* The bootstrap code of nds32 core
*/
reset:
set_ivb:
li $r0, 0x0
/* turn on BTB */
mtsr $r0, $misc_ctl
/* set IVIC, vector size: 4 bytes, base: 0x0 */
mtsr $r0, $ivb
load_lli:
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
jal load_lowlevel_init
jral $p0
#endif
/*
* Set the N1213 (Whitiger) core to superuser mode
* According to spec, it is already when reset
*/
turnoff_wtdog:
#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
jal load_turnoff_watchdog
jral $p0
#endif
/*
* Do CPU critical regs init only at reboot,
* not when booting from ram
*/
#ifdef CONFIG_INIT_CRITICAL
bal cpu_init_crit ! Do CPU critical regs init
#endif
/*
* Set stackpointer in internal RAM to call board_init_f
* $sp must be 8-byte alignment for ABI compliance.
*/
call_board_init_f:
li $sp, CONFIG_SYS_INIT_SP_ADDR
li $r10, GD_SIZE /* get GD size */
sub $sp, $sp, $r10 /* GD start addr */
move $r10, $sp
li $r0, 0x00000000
#ifdef __PIC__
#ifdef __NDS32_N1213_43U1H__
/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
la $r15, board_init_f ! store function address into $r15
#endif
#endif
j board_init_f ! jump to board_init_f() in lib/board.c
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
*/
.globl relocate_code
relocate_code:
move $r4, $r0 /* save addr_sp */
move $r5, $r1 /* save addr of gd */
move $r6, $r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
move $sp, $r4
la $r0, _start
beq $r0, $r6, clear_bss /* skip relocation */
move $r1, $r6 /* r1 <- scratch for copy_loop */
la $r3, __bss_start
sub $r3, $r3, $r0 /* r3 <- __bss_start_ofs */
add $r2, $r0, $r3 /* r2 <- source end address */
copy_loop:
lwi.p $r7, [$r0], #4
swi.p $r7, [$r1], #4
blt $r0, $r2, copy_loop
/*
* fix relocations related issues
*/
fix_relocations:
l.w $r0, _TEXT_BASE /* r0 <- Text base */
sub $r9, $r6, $r0 /* r9 <- relocation offset */
fix_got:
/*
* Now we want to update GOT.
*
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation.
*/
la $r2, __got_start /* r2 <- rel __got_start in FLASH */
add $r2, $r2, $r9 /* r2 <- rel __got_start in RAM */
la $r3, __got_end /* r3 <- rel __got_end in FLASH */
add $r3, $r3, $r9 /* r3 <- rel __got_end in RAM */
addi $r2, $r2, #8 /* skipping first two entries */
fix_got_loop:
lwi $r0, [$r2] /* r0 <- location in FLASH to fix up */
add $r0, $r0, $r9 /* r0 <- location fix up to RAM */
swi.p $r0, [$r2], #4 /* r0 <- store fix into .got in RAM */
blt $r2, $r3, fix_got_loop
clear_bss:
la $r0, __bss_start /* r0 <- rel __bss_start in FLASH */
add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */
la $r1, __bss_end /* r1 <- rel __bss_end in RAM */
add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */
li $r2, 0x00000000 /* clear */
clbss_l:
sw $r2, [$r0] /* clear loop... */
addi $r0, $r0, #4
bne $r0, $r1, clbss_l
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
call_board_init_r:
la $r0, board_init_r
move $lp, $r0 /* offset of board_init_r() */
add $lp, $lp, $r9 /* real address of board_init_r() */
/* setup parameters for board_init_r */
move $r0, $r5 /* gd_t */
move $r1, $r6 /* dest_addr */
#ifdef __PIC__
#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA */
move $r15, $lp /* store function address into $r15 */
#endif
#endif
/* jump to it ... */
jr $lp /* jump to board_init_r() */
/*
* Initialize CPU critical registers
*
* 1. Setup control registers
* 1.1 Mask all IRQs
* 1.2 Flush cache and TLB
* 1.3 Disable MMU and cache
* 2. Setup memory timing
*/
cpu_init_crit:
move $r0, $lp /* push ra */
/* Disable Interrupts by clear GIE in $PSW reg */
setgie.d
/* Flush caches and TLB */
/* Invalidate caches */
bal invalidate_icac
bal invalidate_dcac
/* Flush TLB */
mfsr $p0, $MMU_CFG
andi $p0, $p0, 0x3 ! MMPS
li $p1, 0x2 ! TLB MMU
bne $p0, $p1, 1f
tlbop flushall ! Flush TLB
1:
! Disable MMU, Dcache
! Whitiger is MMU disabled when reset
! Disable the D$
mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
li $p1, DIS_DCAC
and $p0, $p0, $p1 ! Set DC_EN bit
mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg
isb
move $lp, $r0
2:
ret
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
load_lowlevel_init:
la $r6, lowlevel_init
la $r7, load_lli + 4
sub $p0, $r6, $r7
add $p0, $p0, $lp
ret
#endif
#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
load_turnoff_watchdog:
la $r6, turnoff_watchdog
la $r7, turnoff_wtdog + 4
sub $p0, $r6, $r7
add $p0, $p0, $lp
ret
#endif
/*
* Invalidate I$
*/
invalidate_icac:
! read $cr1(I CAC/MEM cfg. reg.) configuration
mfsr $t0, CR_ICAC_MEM
! Get the ISZ field
andi $p0, $t0, ICAC_MEM_KBF_ISZ
! if $p0=0, then no I CAC existed
beqz $p0, end_flush_icache
! get $p0 the index of I$ block
srli $p0, $p0, 6
! $t1= bit width of I cache line size(ISZ)
addi $t1, $p0, 2
li $t4, 1
sll $t5, $t4, $t1 ! get $t5 cache line size
andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
addi $t2, $p1, 6 ! $t2= bit width of ISET
andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
srli $p1, $p1, 3
addi $p1, $p1, 1 ! then $p1 is I way number
add $t3, $t2, $t1 ! SHIFT
sll $p1, $p1, $t3 ! GET the total cache size
ICAC_LOOP:
sub $p1, $p1, $t5
cctl $p1, L1I_IX_INVAL
bnez $p1, ICAC_LOOP
end_flush_icache:
ret
/*
* Invalidate D$
*/
invalidate_dcac:
! read $cr2(D CAC/MEM cfg. reg.) configuration
mfsr $t0, CR_DCAC_MEM
! Get the DSZ field
andi $p0, $t0, DCAC_MEM_KBF_DSZ
! if $p0=0, then no D CAC existed
beqz $p0, end_flush_dcache
! get $p0 the index of D$ block
srli $p0, $p0, 6
! $t1= bit width of D cache line size(DSZ)
addi $t1, $p0, 2
li $t4, 1
sll $t5, $t4, $t1 ! get $t5 cache line size
andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
addi $t2, $p1, 6 ! $t2= bit width of DSET
andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
srli $p1, $p1, 3
addi $p1, $p1, 1 ! then $p1 is D way number
add $t3, $t2, $t1 ! SHIFT
sll $p1, $p1, $t3 ! GET the total cache size
DCAC_LOOP:
sub $p1, $p1, $t5
cctl $p1, L1D_IX_INVAL
bnez $p1, DCAC_LOOP
end_flush_dcache:
ret
/*
* Interrupt handling
*/
/*
* exception handlers
*/
.align 5
.macro SAVE_ALL
! FIXME: Other way to get PC?
! FIXME: Update according to the newest spec!!
1:
li $r28, 1
push $r28
mfsr $r28, PSW ! $PSW
push $r28
mfsr $r28, EIT_EVA ! $ir1 $EVA
push $r28
mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE
push $r28
mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error
push $r28
mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW
push $r28
mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW
push $r28
mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA
push $r28
mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE
push $r28
mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC
push $r28
mfsr $r28, EIT_PREV_IPC ! $ir10 prev INTR_PC
push $r28
mfsr $r28, EIT_OVL_INTR_PC ! $ir11 Overflowed INTR_PC
push $r28
mfusr $r28, $d1.lo
push $r28
mfusr $r28, $d1.hi
push $r28
mfusr $r28, $d0.lo
push $r28
mfusr $r28, $d0.hi
push $r28
pushm $r0, $r30 ! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
addi $sp, $sp, -4 ! make room for implicit pt_regs parameters
.endm
.align 5
tlb_fill:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 1 ! Determine interruption type
bal do_interruption
.align 5
tlb_not_present:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 2 ! Determine interruption type
bal do_interruption
.align 5
tlb_misc:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 3 ! Determine interruption type
bal do_interruption
.align 5
tlb_vlpt_miss:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 4 ! Determine interruption type
bal do_interruption
.align 5
machine_error:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 5 ! Determine interruption type
bal do_interruption
.align 5
debug:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 6 ! Determine interruption type
bal do_interruption
.align 5
general_exception:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 7 ! Determine interruption type
bal do_interruption
.align 5
syscall:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 8 ! Determine interruption type
bal do_interruption
.align 5
internal_interrupt:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 9 ! Determine interruption type
bal do_interruption
.align 5
software_interrupt:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 10 ! Determine interruption type
bal do_interruption
.align 5
/*
* void reset_cpu(ulong addr);
* $r0: input address to jump to
*/
.globl reset_cpu
reset_cpu:
/* No need to disable MMU because we never enable it */
bal invalidate_icac
bal invalidate_dcac
mfsr $p0, $MMU_CFG
andi $p0, $p0, 0x3 ! MMPS
li $p1, 0x2 ! TLB MMU
bne $p0, $p1, 1f
tlbop flushall ! Flush TLB
1:
mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
li $p1, DIS_DCAC
and $p0, $p0, $p1 ! Clear the DC_EN bit
mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg
br $r0 ! Jump to the input address

56
u-boot/arch/nds32/cpu/n1213/u-boot.lds Normal file
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
OUTPUT_ARCH(nds32)
ENTRY(_start)
SECTIONS
{
. = ALIGN(4);
.text :
{
arch/nds32/cpu/n1213/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data*) }
. = ALIGN(4);
.got : {
__got_start = .;
*(.got.plt) *(.got)
__got_end = .;
}
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
_end = .;
.bss : {
__bss_start = .;
*(.bss)
. = ALIGN(4);
__bss_end = .;
}
}

91
u-boot/arch/nds32/include/asm/arch-ag101/ag101.h Normal file
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/*
* Copyright (C) 2011 Andes Technology Corporation
* Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __AG101_H
#define __AG101_H
/* Hardware register bases */
/* AHB Controller */
#define CONFIG_FTAHBC020S_BASE 0x90100000
/* Static Memory Controller (SRAM) */
#define CONFIG_FTSMC020_BASE 0x90200000
/* FTSDMC021 SDRAM Controller */
#define CONFIG_FTSDMC021_BASE 0x90300000
/* DMA Controller */
#define CONFIG_FTDMAC020_BASE 0x90400000
/* AHB-to-APB Bridge */
#define CONFIG_FTAPBBRG020S_01_BASE 0x90500000
/* LCD Controller */
#define CONFIG_FTLCDC100_BASE 0x90600000
/* Reserved */
#define CONFIG_RESERVED_01_BASE 0x90700000
/* Reserved */
#define CONFIG_RESERVED_02_BASE 0x90800000
/* Ethernet */
#define CONFIG_FTMAC100_BASE 0x90900000
/* External USB host */
#define CONFIG_EXT_USB_HOST_BASE 0x90A00000
/* USB Device */
#define CONFIG_USB_DEV_BASE 0x90B00000
/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
#define CONFIG_EXT_AHBPCIBRG_BASE 0x90C00000
/* Reserved */
#define CONFIG_RESERVED_03_BASE 0x90D00000
/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
#define CONFIG_EXT_AHBAPBBRG_BASE 0x90E00000
/* External AHB slave1 (LCD) */
#define CONFIG_EXT_AHBSLAVE01_BASE 0x90F00000
/* External AHB slave2 (FUSBH200) */
#define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000
/* DEBUG LED */
#define CONFIG_DEBUG_LED 0x902FFFFC
/* APB Device definitions */
/* Power Management Unit */
#define CONFIG_FTPMU010_BASE 0x98100000
/* BT UART 2/IrDA (UART 01 in Linux) */
#define CONFIG_FTUART010_01_BASE 0x98300000
/* Counter/Timers */
#define CONFIG_FTTMR010_BASE 0x98400000
/* Watchdog Timer */
#define CONFIG_FTWDT010_BASE 0x98500000
/* Real Time Clock */
#define CONFIG_FTRTC010_BASE 0x98600000
/* GPIO */
#define CONFIG_FTGPIO010_BASE 0x98700000
/* Interrupt Controller */
#define CONFIG_FTINTC010_BASE 0x98800000
/* I2C */
#define CONFIG_FTIIC010_BASE 0x98A00000
/* Reserved */
#define CONFIG_RESERVED_04_BASE 0x98C00000
/* Compat Flash Controller */
#define CONFIG_FTCFC010_BASE 0x98D00000
/* SD Controller */
#define CONFIG_FTSDC010_BASE 0x98E00000
/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
#define CONFIG_FTSSP010_02_BASE 0x99400000
/* ST UART ? SSP 02 (UART 02 in Linux) */
#define CONFIG_FTUART010_02_BASE 0x99600000
/* The following address was not defined in Linux */
/* FF UART 3 */
#define CONFIG_FTUART010_03_BASE 0x98200000
/* Synchronous Serial Port Controller (SSP) 01 */
#define CONFIG_FTSSP010_01_BASE 0x98B00000
/* IrDA */
#define CONFIG_IRDA_BASE 0x98900000
/* PWM - Pulse Width Modulator Controller */
#define CONFIG_PMW_BASE 0x99100000
#endif /* __AG101_H */

85
u-boot/arch/nds32/include/asm/arch-ag102/ag102.h Normal file
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/*
* Copyright (C) 2011 Andes Technology Corporation
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __AG102_H
#define __AG102_H
/*
* Hardware register bases
*/
/* PCI Controller */
#define CONFIG_FTPCI100_BASE 0x90000000
/* LPC Controller */
#define CONFIG_LPC_IO_BASE 0x90100000
/* LPC Controller */
#define CONFIG_LPC_BASE 0x90200000
/* NDS32 Data Local Memory 01 */
#define CONFIG_NDS_DLM1_BASE 0x90300000
/* NDS32 Data Local Memory 02 */
#define CONFIG_NDS_DLM2_BASE 0x90400000
/* Synopsys DWC DDR2/1 Controller */
#define CONFIG_DWCDDR21MCTL_BASE 0x90500000
/* DMA Controller */
#define CONFIG_FTDMAC020_BASE 0x90600000
/* FTIDE020_S IDE (ATA) Controller */
#define CONFIG_FTIDE020S_BASE 0x90700000
/* USB OTG Controller */
#define CONFIG_FZOTG266HD0A_BASE 0x90800000
/* Andes L2 Cache Controller */
#define CONFIG_NCEL2C100_BASE 0x90900000
/* XGI XG22 GPU */
#define CONFIG_XGI_XG22_BASE 0x90A00000
/* GMAC Ethernet Controller */
#define CONFIG_FTGMAC100_BASE 0x90B00000
/* AHB Controller */
#define CONFIG_FTAHBC020S_BASE 0x90C00000
/* AHB-to-APB Bridge Controller */
#define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000
/* External AHB2AHB Controller */
#define CONFIG_EXT_AHB2AHB_BASE 0x90E00000
/* Andes Multi-core Interrupt Controller */
#define CONFIG_NCEMIC100_BASE 0x90F00000
/*
* APB Device definitions
*/
/* Compat Flash Controller */
#define CONFIG_FTCFC010_BASE 0x94000000
/* APB - SSP (SPI) (without AC97) Controller */
#define CONFIG_FTSSP010_01_BASE 0x94100000
/* UART1 - APB STUART Controller (UART0 in Linux) */
#define CONFIG_FTUART010_01_BASE 0x94200000
/* FTSDC010 SD Controller */
#define CONFIG_FTSDC010_BASE 0x94400000
/* APB - SSP with HDA/AC97 Controller */
#define CONFIG_FTSSP010_02_BASE 0x94500000
/* UART2 - APB STUART Controller (UART1 in Linux) */
#define CONFIG_FTUART010_02_BASE 0x94600000
/* PCU Controller */
#define CONFIG_ANDES_PCU_BASE 0x94800000
/* FTTMR010 Timer */
#define CONFIG_FTTMR010_BASE 0x94900000
/* Watch Dog Controller */
#define CONFIG_FTWDT010_BASE 0x94A00000
/* FTRTC010 Real Time Clock */
#define CONFIG_FTRTC010_BASE 0x98B00000
/* GPIO Controller */
#define CONFIG_FTGPIO010_BASE 0x94C00000
/* I2C Controller */
#define CONFIG_FTIIC010_BASE 0x94E00000
/* PWM - Pulse Width Modulator Controller */
#define CONFIG_FTPWM010_BASE 0x94F00000
/* Debug LED */
#define CONFIG_DEBUG_LED 0x902FFFFC
/* Power Management Unit */
#define CONFIG_FTPMU010_BASE 0x98100000
#endif /* __AG102_H */

190
u-boot/arch/nds32/include/asm/bitops.h Normal file
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/*
* Copyright 1995, Russell King.
* Various bits and pieces copyrights include:
* Linus Torvalds (test_bit).
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
*
* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
*
* Please note that the code in this file should never be included
* from user space. Many of these are not implemented in assembler
* since they would be too costly. Also, they require priviledged
* instructions (which are not available from user mode) to ensure
* that they are atomic.
*/
#ifndef __ASM_NDS_BITOPS_H
#define __ASM_NDS_BITOPS_H
#ifdef __KERNEL__
#include <asm/system.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/__ffs.h>
#define smp_mb__before_clear_bit() do { } while (0)
#define smp_mb__after_clear_bit() do { } while (0)
/*
* Function prototypes to keep gcc -Wall happy.
*/
extern void set_bit(int nr, void *addr);
static inline void __set_bit(int nr, void *addr)
{
int *a = (int *)addr;
int mask;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
*a |= mask;
}
extern void clear_bit(int nr, void *addr);
static inline void __clear_bit(int nr, void *addr)
{
int *a = (int *)addr;
int mask;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a &= ~mask;
local_irq_restore(flags);
}
extern void change_bit(int nr, void *addr);
static inline void __change_bit(int nr, void *addr)
{
int mask;
unsigned long *ADDR = (unsigned long *)addr;
ADDR += nr >> 5;
mask = 1 << (nr & 31);
*ADDR ^= mask;
}
extern int test_and_set_bit(int nr, void *addr);
static inline int __test_and_set_bit(int nr, void *addr)
{
int mask, retval;
unsigned int *a = (unsigned int *)addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
retval = (mask & *a) != 0;
*a |= mask;
return retval;
}
extern int test_and_clear_bit(int nr, void *addr);
static inline int __test_and_clear_bit(int nr, void *addr)
{
int mask, retval;
unsigned int *a = (unsigned int *)addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
retval = (mask & *a) != 0;
*a &= ~mask;
return retval;
}
extern int test_and_change_bit(int nr, void *addr);
static inline int __test_and_change_bit(int nr, void *addr)
{
int mask, retval;
unsigned int *a = (unsigned int *)addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
retval = (mask & *a) != 0;
*a ^= mask;
return retval;
}
extern int find_first_zero_bit(void *addr, unsigned size);
extern int find_next_zero_bit(void *addr, int size, int offset);
/*
* This routine doesn't need to be atomic.
*/
static inline int test_bit(int nr, const void *addr)
{
return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
}
/*
* ffz = Find First Zero in word. Undefined if no zero exists,
* so code should check against ~0UL first..
*/
static inline unsigned long ffz(unsigned long word)
{
int k;
word = ~word;
k = 31;
if (word & 0x0000ffff) {
k -= 16; word <<= 16;
}
if (word & 0x00ff0000) {
k -= 8; word <<= 8;
}
if (word & 0x0f000000) {
k -= 4; word <<= 4;
}
if (word & 0x30000000) {
k -= 2; word <<= 2;
}
if (word & 0x40000000)
k -= 1;
return k;
}
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
/*
* redefined in include/linux/bitops.h
* #define ffs(x) generic_ffs(x)
*/
/*
* hweightN: returns the hamming weight (i.e. the number
* of bits set) of a N-bit word
*/
#define hweight32(x) generic_hweight32(x)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
#define ext2_set_bit test_and_set_bit
#define ext2_clear_bit test_and_clear_bit
#define ext2_test_bit test_bit
#define ext2_find_first_zero_bit find_first_zero_bit
#define ext2_find_next_zero_bit find_next_zero_bit
/* Bitmap functions for the minix filesystem. */
#define minix_test_and_set_bit(nr, addr) test_and_set_bit(nr, addr)
#define minix_set_bit(nr, addr) set_bit(nr, addr)
#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr)
#define minix_test_bit(nr, addr) test_bit(nr, addr)
#define minix_find_first_zero_bit(addr, size) find_first_zero_bit(addr, size)
#endif /* __KERNEL__ */
#endif /* __ASM_NDS_BITOPS_H */

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/*
* linux/include/asm-arm/byteorder.h
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* ARM Endian-ness. In little endian mode, the data bus is connected such
* that byte accesses appear as:
* 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
* and word accesses (data or instruction) appear as:
* d0...d31
*
* When in big endian mode, byte accesses appear as:
* 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
* and word accesses (data or instruction) appear as:
* d0...d31
*/
#ifndef __ASM_NDS_BYTEORDER_H
#define __ASM_NDS_BYTEORDER_H
#include <asm/types.h>
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
#endif
#ifdef __NDSEB__
#include <linux/byteorder/big_endian.h>
#else
#include <linux/byteorder/little_endian.h>
#endif
#endif

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/*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CACHE_H
#define _ASM_CACHE_H
/* cache */
int icache_status(void);
void icache_enable(void);
void icache_disable(void);
int dcache_status(void);
void dcache_enable(void);
void dcache_disable(void);
#define DEFINE_GET_SYS_REG(reg) \
static inline unsigned long GET_##reg(void) \
{ \
unsigned long val; \
__asm__ volatile ( \
"mfsr %0, $"#reg : "=&r" (val) : : "memory" \
); \
return val; \
}
enum cache_t {ICACHE, DCACHE};
DEFINE_GET_SYS_REG(ICM_CFG);
DEFINE_GET_SYS_REG(DCM_CFG);
#define ICM_CFG_OFF_ISZ 6 /* I-cache line size */
#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ)
#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */
#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ)
/*
* The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
* We use that value for aligning DMA buffers unless the board config has
* specified an alternate cache line size.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 32
#endif
#endif /* _ASM_CACHE_H */

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/*
* Copyright (C) 2011 Andes Technology Corporation
* Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
* Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_NEEDS_MANUAL_RELOC
#endif

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/*
* Copyright (C) 2013 Andes Technology Corporation
* Ken Kuo, Andes Technology Corporation <ken_kuo@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_NDS_DMA_MAPPING_H
#define __ASM_NDS_DMA_MAPPING_H
enum dma_data_direction {
DMA_BIDIRECTIONAL = 0,
DMA_TO_DEVICE = 1,
DMA_FROM_DEVICE = 2,
};
static void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
return (void *)*handle;
}
static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
enum dma_data_direction dir)
{
return (unsigned long)vaddr;
}
static inline void dma_unmap_single(volatile void *vaddr, size_t len,
unsigned long paddr)
{
}
#endif /* __ASM_NDS_DMA_MAPPING_H */

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#include <asm-generic/errno.h>

34
u-boot/arch/nds32/include/asm/global_data.h Normal file
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/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/**************************************************************
* CAUTION:
* - do not implement for NDS32 Arch yet.
* - so far no one uses the macros defined in this head file.
**************************************************************/
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
/* Architecture-specific global data */
struct arch_global_data {
};
#include <asm-generic/global_data.h>
#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
extern volatile gd_t g_gd;
#define DECLARE_GLOBAL_DATA_PTR static volatile gd_t *gd = &g_gd
#else
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("$r10")
#endif
#endif /* __ASM_GBL_DATA_H */

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/*
* linux/include/asm-nds/io.h
*
* Copyright (C) 1996-2000 Russell King
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0
*
* Modifications:
* 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
* constant addresses and variable addresses.
* 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
* specific IO header files.
* 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
* 04-Apr-1999 PJB Added check_signature.
* 12-Dec-1999 RMK More cleanups
* 18-Jun-2000 RMK Removed virt_to_* and friends definitions
*/
#ifndef __ASM_NDS_IO_H
#define __ASM_NDS_IO_H
/*
* CAUTION:
* - do not implement for NDS32 Arch yet.
* - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
* iinclude asm/io.h
*/
#ifdef __KERNEL__
#include <linux/types.h>
#include <asm/byteorder.h>
static inline void sync(void)
{
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
static inline phys_addr_t virt_to_phys(void *vaddr)
{
return (phys_addr_t)(vaddr);
}
/*
* Generic virtual read/write. Note that we don't support half-word
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
* to the architecture specific code.
*/
#define __arch_getb(a) (*(unsigned char *)(a))
#define __arch_getw(a) (*(unsigned short *)(a))
#define __arch_getl(a) (*(unsigned int *)(a))
#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
extern void __raw_readsl(unsigned int addr, void *data, int longlen);
#define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a)
#define __raw_writel(v, a) __arch_putl(v, a)
#define __raw_readb(a) __arch_getb(a)
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
/*
* TODO: The kernel offers some more advanced versions of barriers, it might
* have some advantages to use them instead of the simple one here.
*/
#define dmb() __asm__ __volatile__ ("" : : : "memory")
#define __iormb() dmb()
#define __iowmb() dmb()
static inline void writeb(unsigned char val, unsigned char *addr)
{
__iowmb();
__arch_putb(val, addr);
}
static inline void writew(unsigned short val, unsigned short *addr)
{
__iowmb();
__arch_putw(val, addr);
}
static inline void writel(unsigned int val, unsigned int *addr)
{
__iowmb();
__arch_putl(val, addr);
}
static inline unsigned char readb(unsigned char *addr)
{
u8 val;
val = __arch_getb(addr);
__iormb();
return val;
}
static inline unsigned short readw(unsigned short *addr)
{
u16 val;
val = __arch_getw(addr);
__iormb();
return val;
}
static inline unsigned int readl(unsigned int *addr)
{
u32 val;
val = __arch_getl(addr);
__iormb();
return val;
}
/*
* The compiler seems to be incapable of optimising constants
* properly. Spell it out to the compiler in some cases.
* These are only valid for small values of "off" (< 1<<12)
*/
#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off)
#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off)
#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off)
#define __raw_base_readb(base, off) __arch_base_getb(base, off)
#define __raw_base_readw(base, off) __arch_base_getw(base, off)
#define __raw_base_readl(base, off) __arch_base_getl(base, off)
#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
#define out_le32(a, v) out_arch(l, le32, a, v)
#define out_le16(a, v) out_arch(w, le16, a, v)
#define in_le32(a) in_arch(l, le32, a)
#define in_le16(a) in_arch(w, le16, a)
#define out_be32(a, v) out_arch(l, be32, a, v)
#define out_be16(a, v) out_arch(w, be16, a, v)
#define in_be32(a) in_arch(l, be32, a)
#define in_be16(a) in_arch(w, be16, a)
#define out_8(a, v) __raw_writeb(v, a)
#define in_8(a) __raw_readb(a)
/*
* Clear and set bits in one shot. These macros can be used to clear and
* set multiple bits in a register using a single call. These macros can
* also be used to set a multiple-bit bit pattern using a mask, by
* specifying the mask in the 'clear' parameter and the new bit pattern
* in the 'set' parameter.
*/
#define clrbits(type, addr, clear) \
out_##type((addr), in_##type(addr) & ~(clear))
#define setbits(type, addr, set) \
out_##type((addr), in_##type(addr) | (set))
#define clrsetbits(type, addr, clear, set) \
out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
#define setbits_be32(addr, set) setbits(be32, addr, set)
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
#define setbits_le32(addr, set) setbits(le32, addr, set)
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
#define setbits_be16(addr, set) setbits(be16, addr, set)
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
#define setbits_le16(addr, set) setbits(le16, addr, set)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrbits_8(addr, clear) clrbits(8, addr, clear)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
/*
* Now, pick up the machine-defined IO definitions
* #include <asm/arch/io.h>
*/
/*
* IO port access primitives
* -------------------------
*
* The NDS32 doesn't have special IO access instructions just like ARM;
* all IO is memory mapped.
* Note that these are defined to perform little endian accesses
* only. Their primary purpose is to access PCI and ISA peripherals.
*
* Note that for a big endian machine, this implies that the following
* big endian mode connectivity is in place, as described by numerious
* ARM documents:
*
* PCI: D0-D7 D8-D15 D16-D23 D24-D31
* ARM: D24-D31 D16-D23 D8-D15 D0-D7
*
* The machine specific io.h include defines __io to translate an "IO"
* address to a memory address.
*
* Note that we prevent GCC re-ordering or caching values in expressions
* by introducing sequence points into the in*() definitions. Note that
* __raw_* do not guarantee this behaviour.
*
* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
*/
#ifdef __io
#define outb(v, p) __raw_writeb(v, __io(p))
#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
#define outsb(p, d, l) writesb(__io(p), d, l)
#define outsw(p, d, l) writesw(__io(p), d, l)
#define outsl(p, d, l) writesl(__io(p), d, l)
#define insb(p, d, l) readsb(__io(p), d, l)
#define insw(p, d, l) readsw(__io(p), d, l)
#define insl(p, d, l) readsl(__io(p), d, l)
static inline void readsb(unsigned int *addr, void * data, int bytelen)
{
unsigned char *ptr = (unsigned char *)addr;
unsigned char *ptr2 = (unsigned char *)data;
while (bytelen) {
*ptr2 = *ptr;
ptr2++;
bytelen--;
}
}
static inline void readsw(unsigned int *addr, void * data, int wordlen)
{
unsigned short *ptr = (unsigned short *)addr;
unsigned short *ptr2 = (unsigned short *)data;
while (wordlen) {
*ptr2 = *ptr;
ptr2++;
wordlen--;
}
}
static inline void readsl(unsigned int *addr, void * data, int longlen)
{
unsigned int *ptr = (unsigned int *)addr;
unsigned int *ptr2 = (unsigned int *)data;
while (longlen) {
*ptr2 = *ptr;
ptr2++;
longlen--;
}
}
static inline void writesb(unsigned int *addr, const void * data, int bytelen)
{
unsigned char *ptr = (unsigned char *)addr;
unsigned char *ptr2 = (unsigned char *)data;
while (bytelen) {
*ptr = *ptr2;
ptr2++;
bytelen--;
}
}
static inline void writesw(unsigned int *addr, const void * data, int wordlen)
{
unsigned short *ptr = (unsigned short *)addr;
unsigned short *ptr2 = (unsigned short *)data;
while (wordlen) {
*ptr = *ptr2;
ptr2++;
wordlen--;
}
}
static inline void writesl(unsigned int *addr, const void * data, int longlen)
{
unsigned int *ptr = (unsigned int *)addr;
unsigned int *ptr2 = (unsigned int *)data;
while (longlen) {
*ptr = *ptr2;
ptr2++;
longlen--;
}
}
#endif
#define outb_p(val, port) outb((val), (port))
#define outw_p(val, port) outw((val), (port))
#define outl_p(val, port) outl((val), (port))
#define inb_p(port) inb((port))
#define inw_p(port) inw((port))
#define inl_p(port) inl((port))
#define outsb_p(port, from, len) outsb(port, from, len)
#define outsw_p(port, from, len) outsw(port, from, len)
#define outsl_p(port, from, len) outsl(port, from, len)
#define insb_p(port, to, len) insb(port, to, len)
#define insw_p(port, to, len) insw(port, to, len)
#define insl_p(port, to, len) insl(port, to, len)
/*
* ioremap and friends.
*
* ioremap takes a PCI memory address, as specified in
* linux/Documentation/IO-mapping.txt. If you want a
* physical address, use __ioremap instead.
*/
extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
extern void __iounmap(void *addr);
/*
* Generic ioremap support.
*
* Define:
* iomem_valid_addr(off,size)
* iomem_to_phys(off)
*/
#ifdef iomem_valid_addr
#define __arch_ioremap(off, sz, nocache) \
({ \
unsigned long _off = (off), _size = (sz); \
void *_ret = (void *)0; \
if (iomem_valid_addr(_off, _size)) \
_ret = __ioremap(iomem_to_phys(_off), _size, 0); \
_ret; \
})
#define __arch_iounmap __iounmap
#endif
#define ioremap(off, sz) __arch_ioremap((off), (sz), 0)
#define ioremap_nocache(off, sz) __arch_ioremap((off), (sz), 1)
#define iounmap(_addr) __arch_iounmap(_addr)
/*
* DMA-consistent mapping functions. These allocate/free a region of
* uncached, unwrite-buffered mapped memory space for use with DMA
* devices. This is the "generic" version. The PCI specific version
* is in pci.h
*/
extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
extern void consistent_sync(void *vaddr, size_t size, int rw);
/*
* String version of IO memory access ops:
*/
extern void _memcpy_fromio(void *, unsigned long, size_t);
extern void _memcpy_toio(unsigned long, const void *, size_t);
extern void _memset_io(unsigned long, int, size_t);
extern void __readwrite_bug(const char *fn);
/*
* If this architecture has PCI memory IO, then define the read/write
* macros. These should only be used with the cookie passed from
* ioremap.
*/
#ifdef __mem_pci
#define readb(c) ({ unsigned int __v = \
__raw_readb(__mem_pci(c)); __v; })
#define readw(c) ({ unsigned int __v = \
le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
#define readl(c) ({ unsigned int __v = \
le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
#define writeb(v, c) __raw_writeb(v, __mem_pci(c))
#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
#define eth_io_copy_and_sum(s, c, l, b) \
eth_copy_and_sum((s), __mem_pci(c), (l), (b))
static inline int
check_signature(unsigned long io_addr, const unsigned char *signature,
int length)
{
int retval = 0;
do {
if (readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
#endif /* __mem_pci */
/*
* If this architecture has ISA IO, then define the isa_read/isa_write
* macros.
*/
#ifdef __mem_isa
#define isa_readb(addr) __raw_readb(__mem_isa(addr))
#define isa_readw(addr) __raw_readw(__mem_isa(addr))
#define isa_readl(addr) __raw_readl(__mem_isa(addr))
#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr))
#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr))
#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr))
#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c))
#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c))
#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c))
#define isa_eth_io_copy_and_sum(a, b, c, d) \
eth_copy_and_sum((a), __mem_isa(b), (c), (d))
static inline int
isa_check_signature(unsigned long io_addr, const unsigned char *signature,
int length)
{
int retval = 0;
do {
if (isa_readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
#else /* __mem_isa */
#define isa_readb(addr) (__readwrite_bug("isa_readb"), 0)
#define isa_readw(addr) (__readwrite_bug("isa_readw"), 0)
#define isa_readl(addr) (__readwrite_bug("isa_readl"), 0)
#define isa_writeb(val, addr) __readwrite_bug("isa_writeb")
#define isa_writew(val, addr) __readwrite_bug("isa_writew")
#define isa_writel(val, addr) __readwrite_bug("isa_writel")
#define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io")
#define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio")
#define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio")
#define isa_eth_io_copy_and_sum(a, b, c, d) \
__readwrite_bug("isa_eth_io_copy_and_sum")
#define isa_check_signature(io, sig, len) (0)
#endif /* __mem_isa */
#endif /* __KERNEL__ */
#endif /* __ASM_NDS_IO_H */

12
u-boot/arch/nds32/include/asm/linkage.h Normal file
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/*
* U-Boot - linkage.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_LINKAGE_H
#define __ASM_LINKAGE_H
#endif

29
u-boot/arch/nds32/include/asm/mach-types.h Normal file
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/*
* This was automagically generated from arch/nds/tools/mach-types!
* Do NOT edit
*/
#ifndef __ASM_NDS32_MACH_TYPE_H
#define __ASM_NDS32_MACH_TYPE_H
#ifndef __ASSEMBLY__
/* The type of machine we're running on */
extern unsigned int __machine_arch_type;
#endif
/* see arch/arm/kernel/arch.c for a description of these */
#define MACH_TYPE_ADPAG101P 1
#ifdef CONFIG_ARCH_ADPAG101P
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_ADPAG101P
# endif
# define machine_is_adpag101p() (machine_arch_type == MACH_TYPE_ADPAG101P)
#else
# define machine_is_adpag101p() (1)
#endif
#endif /* __ASM_NDS32_MACH_TYPE_H */

80
u-boot/arch/nds32/include/asm/macro.h Normal file
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/*
* include/asm-nds32/macro.h
*
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Copyright (C) 2011 Andes Technology Corporation
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_NDS_MACRO_H
#define __ASM_NDS_MACRO_H
#ifdef __ASSEMBLY__
/*
* These macros provide a convenient way to write 8, 16 and 32 bit data
* to an "immediate address (address used by periphal)" only.
* Registers r4 and r5 are used, any data in these registers are
* overwritten by the macros.
* The macros are valid for any NDS32 architecture, they do not implement
* any memory barriers so caution is recommended when using these when the
* caches are enabled or on a multi-core system.
*/
.macro write32, addr, data
li $r4, \addr
li $r5, \data
swi $r5, [$r4]
.endm
.macro write16, addr, data
li $r4, \addr
li $r5, \data
shi $r5, [$r4]
.endm
.macro write8, addr, data
li $r4, \addr
li $r5, \data
sbi $r5, [$r4]
.endm
/*
* This macro read a value from a register, then do OR operation
* (set bit fields) to the value, and then store it back to the register.
* Note: Instruction 'ori' supports immediate value up to 15 bits.
*/
.macro setbf32, addr, data
li $r4, \addr
lwi $r5, [$r4]
li $r6, \data
or $r5, $r5, $r6
swi $r5, [$r4]
.endm
.macro setbf15, addr, data
li $r4, \addr
lwi $r5, [$r4]
ori $r5, $r5, \data
swi $r5, [$r4]
.endm
/*
* This macro generates a loop that can be used for delays in the code.
* Register r4 is used, any data in this register is overwritten by the
* macro.
* The macro is valid for any NDS32 architeture. The actual time spent in the
* loop will vary from CPU to CPU though.
*/
.macro wait_timer, time
li $r4, \time
1:
nop
addi $r4, $r4, -1
bnez $r4, 1b
.endm
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARM_MACRO_H */

88
u-boot/arch/nds32/include/asm/posix_types.h Normal file
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/*
* linux/include/asm-arm/posix_types.h
*
* Copyright (C) 1996-1998 Russell King.
*
* Copyright (C) 2011 Andes Technology Corporation
* Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
* Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 27-06-1996 RMK Created
* 05-03-2010 Modified for arch NDS32
*/
#ifndef __ARCH_NDS_POSIX_TYPES_H
#define __ARCH_NDS_POSIX_TYPES_H
/*
* This file is generally used by user-level software, so you need to
* be a little careful about namespace pollution etc. Also, we cannot
* assume GCC is being used.
*/
typedef unsigned short __kernel_dev_t;
typedef unsigned long __kernel_ino_t;
typedef unsigned short __kernel_mode_t;
typedef unsigned short __kernel_nlink_t;
typedef long __kernel_off_t;
typedef int __kernel_pid_t;
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
#ifdef __GNUC__
typedef __SIZE_TYPE__ __kernel_size_t;
#else
typedef unsigned int __kernel_size_t;
#endif
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
typedef int __kernel_daddr_t;
typedef char *__kernel_caddr_t;
typedef unsigned short __kernel_uid16_t;
typedef unsigned short __kernel_gid16_t;
typedef unsigned int __kernel_uid32_t;
typedef unsigned int __kernel_gid32_t;
typedef unsigned short __kernel_old_uid_t;
typedef unsigned short __kernel_old_gid_t;
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
typedef struct {
#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
int __val[2];
#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
#undef __FD_SET
#define __FD_SET(fd, fdsetp) \
(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
#undef __FD_CLR
#define __FD_CLR(fd, fdsetp) \
(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
#undef __FD_ISSET
#define __FD_ISSET(fd, fdsetp) \
((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
#undef __FD_ZERO
#define __FD_ZERO(fdsetp) \
(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
#endif
#endif /* __ARCH_NDS_POSIX_TYPES_H */

25
u-boot/arch/nds32/include/asm/processor.h Normal file
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/*
* linux/include/asm-arm/processor.h
*
* Copyright (C) 1995-2002 Russell King
*
* Copyright (C) 2011 Andes Technology Corporation
* Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
* Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_NDS_PROCESSOR_H
#define __ASM_NDS_PROCESSOR_H
/**************************************************************
* CAUTION:
* - do not implement for NDS32 Arch yet.
* - so far some files include /asm/processor.h, but
* no one uses the macros defined in this head file.
**************************************************************/
#endif /* __ASM_ARM_PROCESSOR_H */

90
u-boot/arch/nds32/include/asm/ptrace.h Normal file
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/*
* Copyright (C) 2011 Andes Technology Corporation
* Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
* Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_NDS_PTRACE_H
#define __ASM_NDS_PTRACE_H
#define USR_MODE 0x00
#define SU_MODE 0x01
#define HV_MODE 0x10
#define MODE_MASK (0x03<<3)
#define GIE_BIT 0x01
#ifndef __ASSEMBLY__
/* this struct defines the way the registers are stored on the
stack during a system call. */
#define NDS32_REG long
struct pt_regs {
NDS32_REG ir0;
NDS32_REG ipsw;
NDS32_REG ipc;
NDS32_REG sp;
NDS32_REG orig_r0;
NDS32_REG pipsw;
NDS32_REG pipc;
NDS32_REG pp0;
NDS32_REG pp1;
NDS32_REG d0hi;
NDS32_REG d0lo;
NDS32_REG d1hi;
NDS32_REG d1lo;
NDS32_REG r[26]; /* r0 - r25 */
NDS32_REG p0; /* r26 - used by OS */
NDS32_REG p1; /* r27 - used by OS */
NDS32_REG fp; /* r28 */
NDS32_REG gp; /* r29 */
NDS32_REG lp; /* r30 */
NDS32_REG fucop_ctl;
NDS32_REG osp;
};
#define processor_mode(regs) \
(((regs)->ipsw & MODE_MASK) >> 3)
#define interrupts_enabled(regs) \
((regs)->ipsw & GIE_BIT)
/*
* Offsets used by 'ptrace' system call interface.
* These can't be changed without breaking binary compatibility
* with MkLinux, etc.
*/
#define PT_R0 0
#define PT_R1 1
#define PT_R2 2
#define PT_R3 3
#define PT_R4 4
#define PT_R5 5
#define PT_R6 6
#define PT_R7 7
#define PT_R8 8
#define PT_R9 9
#define PT_R10 10
#define PT_R11 11
#define PT_R12 12
#define PT_R13 13
#define PT_R14 14
#define PT_R15 15
#define PT_R16 16
#define PT_R17 17
#define PT_R18 18
#define PT_R19 19
#define PT_R20 20
#define PT_R21 21
#define PT_R22 22
#define PT_R23 23
#define PT_R24 24
#define PT_R25 25
#endif /* __ASSEMBLY__ */
#endif /* __ASM_NDS_PTRACE_H */

11
u-boot/arch/nds32/include/asm/sections.h Normal file
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/*
* Copyright (c) 2012 The Chromium OS Authors.
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_NDS32_SECTIONS_H
#define __ASM_NDS32_SECTIONS_H
#include <asm-generic/sections.h>
#endif

190
u-boot/arch/nds32/include/asm/setup.h Normal file
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/*
* linux/arch/nds32/include/asm/setup.h
*
* Copyright (C) 1997-1999 Russell King
* Copyright (C) 2008 Andes Technology Corporation
* Copyright (C) 2013 Ken Kuo (ken_kuo@andestech.com)
*
* SPDX-License-Identifier: GPL-2.0
*
* Structure passed to kernel to tell it about the
* hardware it's running on. See Documentation/arm/Setup
* for more info.
*/
#ifndef __ASMNDS32_SETUP_H
#define __ASMNDS32_SETUP_H
#define COMMAND_LINE_SIZE 256
/* The list ends with an ATAG_NONE node. */
#define ATAG_NONE 0x00000000
struct tag_header {
u32 size;
u32 tag;
};
/* The list must start with an ATAG_CORE node */
#define ATAG_CORE 0x54410001
struct tag_core {
u32 flags; /* bit 0 = read-only */
u32 pagesize;
u32 rootdev;
};
/* it is allowed to have multiple ATAG_MEM nodes */
#define ATAG_MEM 0x54410002
struct tag_mem32 {
u32 size;
u32 start; /* physical start address */
};
/* VGA text type displays */
#define ATAG_VIDEOTEXT 0x54410003
struct tag_videotext {
u8 x;
u8 y;
u16 video_page;
u8 video_mode;
u8 video_cols;
u16 video_ega_bx;
u8 video_lines;
u8 video_isvga;
u16 video_points;
};
/* describes how the ramdisk will be used in kernel */
#define ATAG_RAMDISK 0x54410004
struct tag_ramdisk {
u32 flags; /* bit 0 = load, bit 1 = prompt */
u32 size; /* decompressed ramdisk size in _kilo_ bytes */
u32 start; /* starting block of floppy-based RAM disk image */
};
/*
* this one accidentally used virtual addresses - as such,
* it's deprecated.
* describes where the compressed ramdisk image lives (virtual address)
*/
#define ATAG_INITRD 0x54410005
/* describes where the compressed ramdisk image lives (physical address) */
#define ATAG_INITRD2 0x54420005
struct tag_initrd {
u32 start; /* physical start address */
u32 size; /* size of compressed ramdisk image in bytes */
};
/* board serial number. "64 bits should be enough for everybody" */
#define ATAG_SERIAL 0x54410006
struct tag_serialnr {
u32 low;
u32 high;
};
/* board revision */
#define ATAG_REVISION 0x54410007
struct tag_revision {
u32 rev;
};
/* initial values for vesafb-type framebuffers. see struct screen_info
* in include/linux/tty.h
*/
#define ATAG_VIDEOLFB 0x54410008
struct tag_videolfb {
u16 lfb_width;
u16 lfb_height;
u16 lfb_depth;
u16 lfb_linelength;
u32 lfb_base;
u32 lfb_size;
u8 red_size;
u8 red_pos;
u8 green_size;
u8 green_pos;
u8 blue_size;
u8 blue_pos;
u8 rsvd_size;
u8 rsvd_pos;
};
/* command line: \0 terminated string */
#define ATAG_CMDLINE 0x54410009
struct tag_cmdline {
char cmdline[COMMAND_LINE_SIZE];
};
struct tag {
struct tag_header hdr;
union {
struct tag_core core;
struct tag_mem32 mem;
struct tag_videotext videotext;
struct tag_ramdisk ramdisk;
struct tag_initrd initrd;
struct tag_serialnr serialnr;
struct tag_revision revision;
struct tag_videolfb videolfb;
struct tag_cmdline cmdline;
} u;
};
struct tagtable {
u32 tag;
int (*parse)(const struct tag *);
};
#define tag_member_present(tag, member) \
((unsigned long)(&((struct tag *)0L)->member + 1) \
<= (tag)->hdr.size * 4)
#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size))
#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
#define for_each_tag(t, base) \
for (t = base; t->hdr.size; t = tag_next(t))
#ifdef __KERNEL__
#define __tag __used __attribute__((__section__(".taglist")))
#define __tagtable(tag, fn) \
static struct tagtable __tagtable_##fn __tag = { tag, fn }
/*
* Memory map description
*/
#define NR_BANKS 8
struct meminfo {
int nr_banks;
struct {
unsigned long start;
unsigned long size;
int node;
} bank[NR_BANKS];
};
/*
* Early command line parameters.
*/
struct early_params {
const char *arg;
void (*fn)(char **p);
};
#define __early_param(name, fn) \
static struct early_params __early_##fn __used \
__attribute__((__section__("__early_param"))) = { name, fn }
#endif
#endif

57
u-boot/arch/nds32/include/asm/string.h Normal file
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/*
* Copyright (C) 2011 Andes Technology Corporation
* Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
* Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_NDS_STRING_H
#define __ASM_NDS_STRING_H
/*
* We don't do inline string functions, since the
* optimised inline asm versions are not small.
*/
#undef __HAVE_ARCH_STRRCHR
extern char *strrchr(const char *s, int c);
#undef __HAVE_ARCH_STRCHR
extern char *strchr(const char *s, int c);
#undef __HAVE_ARCH_MEMCPY
extern void *memcpy(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMMOVE
extern void *memmove(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMCHR
extern void *memchr(const void *, int, __kernel_size_t);
#undef __HAVE_ARCH_MEMZERO
#undef __HAVE_ARCH_MEMSET
extern void *memset(void *, int, __kernel_size_t);
#ifdef CONFIG_MARCO_MEMSET
extern void __memzero(void *ptr, __kernel_size_t n);
#define memset(p, v, n) \
({ \
if ((n) != 0) { \
if (__builtin_constant_p((v)) && (v) == 0) \
__memzero((p), (n)); \
else \
memset((p), (v), (n)); \
} \
(p); \
})
#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
#else
extern void memzero(void *ptr, __kernel_size_t n);
#endif
#endif /* __ASM_NDS_STRING_H */

72
u-boot/arch/nds32/include/asm/system.h Normal file
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/*
* Copyright (C) 2011 Andes Technology Corporation
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_NDS_SYSTEM_H
#define __ASM_NDS_SYSTEM_H
/*
* Interrupt configuring macros.
*/
extern int irq_flags;
#define local_irq_enable() \
__asm__ __volatile__ ( \
"mfsr %0, $psw\n\t" \
"andi %0, %0, 0x1\n\t" \
"setgie.e\n\t" \
: \
: "r" (irq_flags) \
)
#define local_irq_disable() \
do { \
int __tmp_dummy; \
__asm__ __volatile__ ( \
"mfsr %0, $psw\n\t" \
"andi %0, %0, 0x1\n\t" \
"setgie.d\n\t" \
"dsb\n\t" \
: "=r" (__tmp_dummy) \
); \
} while (0)
#define local_irq_save(x) \
__asm__ __volatile__ ( \
"mfsr %0, $psw\n\t" \
"andi %0, %0, 0x1\n\t" \
"setgie.d\n\t" \
"dsb\n\t" \
: "=&r" (x) \
)
#define local_save_flags(x) \
__asm__ __volatile__ ( \
"mfsr %0, $psw\n\t" \
"andi %0, %0, 0x1\n\t" \
"setgie.e\n\t" \
"setgie.d\n\t" \
: "=r" (x) \
)
#define irqs_enabled_from_flags(x) ((x) != 0x1f)
#define local_irq_restore(x) \
do { \
if (irqs_enabled_from_flags(x)) \
local_irq_enable(); \
} while (0)
/*
* Force strict CPU ordering.
*/
#define nop() asm volatile ("nop;\n\t" : : )
#define mb() asm volatile ("" : : : "memory")
#define rmb() asm volatile ("" : : : "memory")
#define wmb() asm volatile ("" : : : "memory")
#endif /* __ASM_NDS_SYSTEM_H */

63
u-boot/arch/nds32/include/asm/types.h Normal file
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/*
* Copyright (C) 2011 Andes Technology Corporation
* Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
* Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_NDS_TYPES_H
#define __ASM_NDS_TYPES_H
typedef unsigned short umode_t;
/*
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
* header files exported to user space
*/
typedef __signed__ char __s8;
typedef unsigned char __u8;
typedef __signed__ short __s16;
typedef unsigned short __u16;
typedef __signed__ int __s32;
typedef unsigned int __u32;
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
typedef __signed__ long long __s64;
typedef unsigned long long __u64;
#endif
/*
* These aren't exported outside the kernel to avoid name space clashes
*/
#ifdef __KERNEL__
typedef signed char s8;
typedef unsigned char u8;
typedef signed short s16;
typedef unsigned short u16;
typedef signed int s32;
typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
#define BITS_PER_LONG 32
#include <stddef.h>
typedef u32 dma_addr_t;
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
#endif /* __KERNEL__ */
#endif

29
u-boot/arch/nds32/include/asm/u-boot-nds32.h Normal file
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/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _U_BOOT_NDS32_H_
#define _U_BOOT_NDS32_H_ 1
/* for the following variables, see start.S */
extern ulong IRQ_STACK_START; /* top of IRQ stack */
extern ulong FIQ_STACK_START; /* top of FIQ stack */
/* cpu/.../cpu.c */
int cleanup_before_linux(void);
/* board/.../... */
int board_init(void);
/* cpu/.../interrupt.c */
void reset_timer_masked(void);
#endif /* _U_BOOT_NDS32_H_ */

45
u-boot/arch/nds32/include/asm/u-boot.h Normal file
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/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* Copyright (C) 2011 Andes Technology Corporation
* Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
* Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
*
* SPDX-License-Identifier: GPL-2.0+
*
********************************************************************
* NOTE: This header file defines an interface to U-Boot. Including
* this (unmodified) header file in another file is considered normal
* use of U-Boot, and does *not* fall under the heading of "derived
* work".
********************************************************************
*/
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
#include <environment.h>
typedef struct bd_info {
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
unsigned long bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned char bi_enetaddr[6];
struct /* RAM configuration */
{
unsigned long start;
unsigned long size;
} bi_dram[CONFIG_NR_DRAM_BANKS];
} bd_t;
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_NDS32
#endif /* _U_BOOT_H_ */

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u-boot/arch/nds32/include/asm/unaligned.h Normal file
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#include <asm-generic/unaligned.h>

14
u-boot/arch/nds32/lib/Makefile Normal file
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2011 Andes Technology Corporation
# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += cache.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += interrupts.o

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u-boot/arch/nds32/lib/asm-offsets.c Normal file
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/*
* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
*
* Generate definitions needed by assembly language modules.
* This code generates raw asm output which is post-processed to extract
* and format the required data.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <linux/kbuild.h>
int main(void)
{
/*
* TODO : Check if each entry in this file is really necessary.
* - struct ftahbc02s
* - struct ftsdmc021
* - struct andes_pcu
* - struct dwcddr21mctl
* are used only for generating asm-offsets.h.
* It means their offset addresses are referenced only from assembly
* code. Is it better to define the macros directly in headers?
*/
#ifdef CONFIG_FTSMC020
OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
#endif
BLANK();
#ifdef CONFIG_FTAHBC020S
OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]);
OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
#endif
BLANK();
#ifdef CONFIG_FTPMU010
OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0);
#endif
BLANK();
#ifdef CONFIG_FTSDMC021
OFFSET(FTSDMC021_TP1, ftsdmc021, tp1);
OFFSET(FTSDMC021_TP2, ftsdmc021, tp2);
OFFSET(FTSDMC021_CR1, ftsdmc021, cr1);
OFFSET(FTSDMC021_CR2, ftsdmc021, cr2);
OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr);
OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr);
OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr);
OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr);
#endif
BLANK();
#ifdef CONFIG_ANDES_PCU
OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
#endif
BLANK();
#ifdef CONFIG_DWCDDR21MCTL
OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */
OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */
OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */
OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */
OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */
OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */
OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */
OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */
OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */
OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
#endif
return 0;
}

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u-boot/arch/nds32/lib/bootm.c Normal file
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/*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \
defined(CONFIG_SERIAL_TAG) || \
defined(CONFIG_REVISION_TAG)
static void setup_start_tag(bd_t *bd);
# ifdef CONFIG_SETUP_MEMORY_TAGS
static void setup_memory_tags(bd_t *bd);
# endif
static void setup_commandline_tag(bd_t *bd, char *commandline);
# ifdef CONFIG_INITRD_TAG
static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
# endif
static void setup_end_tag(bd_t *bd);
static struct tag *params;
#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
bd_t *bd = gd->bd;
char *s;
int machid = bd->bi_arch_number;
void (*theKernel)(int zero, int arch, uint params);
#ifdef CONFIG_CMDLINE_TAG
char *commandline = getenv("bootargs");
#endif
/*
* allow the PREP bootm subcommand, it is required for bootm to work
*/
if (flag & BOOTM_STATE_OS_PREP)
return 0;
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
return 1;
theKernel = (void (*)(int, int, uint))images->ep;
s = getenv("machid");
if (s) {
machid = simple_strtoul(s, NULL, 16);
printf("Using machid 0x%x from environment\n", machid);
}
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
debug("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)theKernel);
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \
defined(CONFIG_SERIAL_TAG) || \
defined(CONFIG_REVISION_TAG)
setup_start_tag(bd);
#ifdef CONFIG_SERIAL_TAG
setup_serial_tag(&params);
#endif
#ifdef CONFIG_REVISION_TAG
setup_revision_tag(&params);
#endif
#ifdef CONFIG_SETUP_MEMORY_TAGS
setup_memory_tags(bd);
#endif
#ifdef CONFIG_CMDLINE_TAG
setup_commandline_tag(bd, commandline);
#endif
#ifdef CONFIG_INITRD_TAG
if (images->rd_start && images->rd_end)
setup_initrd_tag(bd, images->rd_start, images->rd_end);
#endif
setup_end_tag(bd);
#endif
/* we assume that the kernel is in place */
printf("\nStarting kernel ...\n\n");
#ifdef CONFIG_USB_DEVICE
{
extern void udc_disconnect(void);
udc_disconnect();
}
#endif
cleanup_before_linux();
theKernel(0, machid, bd->bi_boot_params);
/* does not return */
return 1;
}
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \
defined(CONFIG_SERIAL_TAG) || \
defined(CONFIG_REVISION_TAG)
static void setup_start_tag(bd_t *bd)
{
params = (struct tag *)bd->bi_boot_params;
params->hdr.tag = ATAG_CORE;
params->hdr.size = tag_size(tag_core);
params->u.core.flags = 0;
params->u.core.pagesize = 0;
params->u.core.rootdev = 0;
params = tag_next(params);
}
#ifdef CONFIG_SETUP_MEMORY_TAGS
static void setup_memory_tags(bd_t *bd)
{
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
params->hdr.tag = ATAG_MEM;
params->hdr.size = tag_size(tag_mem32);
params->u.mem.start = bd->bi_dram[i].start;
params->u.mem.size = bd->bi_dram[i].size;
params = tag_next(params);
}
}
#endif /* CONFIG_SETUP_MEMORY_TAGS */
static void setup_commandline_tag(bd_t *bd, char *commandline)
{
char *p;
if (!commandline)
return;
/* eat leading white space */
for (p = commandline; *p == ' '; p++)
;
/* skip non-existent command lines so the kernel will still
* use its default command line.
*/
if (*p == '\0')
return;
params->hdr.tag = ATAG_CMDLINE;
params->hdr.size =
(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
strcpy(params->u.cmdline.cmdline, p)
;
params = tag_next(params);
}
#ifdef CONFIG_INITRD_TAG
static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
{
/* an ATAG_INITRD node tells the kernel where the compressed
* ramdisk can be found. ATAG_RDIMG is a better name, actually.
*/
params->hdr.tag = ATAG_INITRD2;
params->hdr.size = tag_size(tag_initrd);
params->u.initrd.start = initrd_start;
params->u.initrd.size = initrd_end - initrd_start;
params = tag_next(params);
}
#endif /* CONFIG_INITRD_TAG */
#ifdef CONFIG_SERIAL_TAG
void setup_serial_tag(struct tag **tmp)
{
struct tag *params = *tmp;
struct tag_serialnr serialnr;
void get_board_serial(struct tag_serialnr *serialnr);
get_board_serial(&serialnr);
params->hdr.tag = ATAG_SERIAL;
params->hdr.size = tag_size(tag_serialnr);
params->u.serialnr.low = serialnr.low;
params->u.serialnr.high = serialnr.high;
params = tag_next(params);
*tmp = params;
}
#endif
#ifdef CONFIG_REVISION_TAG
void setup_revision_tag(struct tag **in_params)
{
u32 rev = 0;
u32 get_board_rev(void);
rev = get_board_rev();
params->hdr.tag = ATAG_REVISION;
params->hdr.size = tag_size(tag_revision);
params->u.revision.rev = rev;
params = tag_next(params);
}
#endif /* CONFIG_REVISION_TAG */
static void setup_end_tag(bd_t *bd)
{
params->hdr.tag = ATAG_NONE;
params->hdr.size = 0;
}
#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */

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u-boot/arch/nds32/lib/cache.c Normal file
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/*
* Copyright (C) 2012 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
{
if (cache == ICACHE)
return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
>> ICM_CFG_OFF_ISZ) - 1);
else
return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
>> DCM_CFG_OFF_DSZ) - 1);
}
void flush_dcache_range(unsigned long start, unsigned long end)
{
unsigned long line_size;
line_size = CACHE_LINE_SIZE(DCACHE);
while (end > start) {
asm volatile (
"\n\tcctl %0, L1D_VA_WB"
"\n\tcctl %0, L1D_VA_INVAL"
:
: "r" (start)
);
start += line_size;
}
}
void invalidate_icache_range(unsigned long start, unsigned long end)
{
unsigned long line_size;
line_size = CACHE_LINE_SIZE(ICACHE);
while (end > start) {
asm volatile (
"\n\tcctl %0, L1I_VA_INVAL"
:
: "r"(start)
);
start += line_size;
}
}
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
unsigned long line_size;
line_size = CACHE_LINE_SIZE(DCACHE);
while (end > start) {
asm volatile (
"\n\tcctl %0, L1D_VA_INVAL"
:
: "r"(start)
);
start += line_size;
}
}
void flush_cache(unsigned long addr, unsigned long size)
{
flush_dcache_range(addr, addr + size);
invalidate_icache_range(addr, addr + size);
}
void icache_enable(void)
{
asm volatile (
"mfsr $p0, $mr8\n\t"
"ori $p0, $p0, 0x01\n\t"
"mtsr $p0, $mr8\n\t"
"isb\n\t"
);
}
void icache_disable(void)
{
asm volatile (
"mfsr $p0, $mr8\n\t"
"li $p1, ~0x01\n\t"
"and $p0, $p0, $p1\n\t"
"mtsr $p0, $mr8\n\t"
"isb\n\t"
);
}
int icache_status(void)
{
int ret;
asm volatile (
"mfsr $p0, $mr8\n\t"
"andi %0, $p0, 0x01\n\t"
: "=r" (ret)
:
: "memory"
);
return ret;
}
void dcache_enable(void)
{
asm volatile (
"mfsr $p0, $mr8\n\t"
"ori $p0, $p0, 0x02\n\t"
"mtsr $p0, $mr8\n\t"
"isb\n\t"
);
}
void dcache_disable(void)
{
asm volatile (
"mfsr $p0, $mr8\n\t"
"li $p1, ~0x02\n\t"
"and $p0, $p0, $p1\n\t"
"mtsr $p0, $mr8\n\t"
"isb\n\t"
);
}
int dcache_status(void)
{
int ret;
asm volatile (
"mfsr $p0, $mr8\n\t"
"andi %0, $p0, 0x02\n\t"
: "=r" (ret)
:
: "memory"
);
return ret;
}

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u-boot/arch/nds32/lib/interrupts.c Normal file
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/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#undef INTERRUPT_MODE
static int int_flag;
int irq_flags; /* needed by asm-nds32/system.h */
int GIE_STATUS(void)
{
int ret;
__asm__ __volatile__ (
"mfsr $p0, $psw\n\t"
"andi %0, %0, 0x1\n\t"
: "=r" (ret)
:
: "memory"
);
return ret;
}
#ifdef CONFIG_USE_INTERRUPT
int interrupt_init(void)
{
return 0;
}
/* enable interrupts */
void enable_interrupts(void)
{
local_irq_restore(int_flag);
}
/*
* disable interrupts
* Return true if GIE is enabled before we disable it.
*/
int disable_interrupts(void)
{
int gie_ori_status;
gie_ori_status = GIE_STATUS();
local_irq_save(int_flag);
return gie_ori_status;
}
#endif
void bad_mode(void)
{
panic("Resetting CPU ...\n");
reset_cpu(0);
}
void show_regs(struct pt_regs *regs)
{
const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
printf("\n");
printf("pc : [<%08lx>] sp: [<%08lx>]\n"
"lp : %08lx gp : %08lx fp : %08lx\n",
regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
printf("D1H: %08lx D1L: %08lx D0H: %08lx D0L: %08lx\n",
regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
printf("r27: %08lx r26: %08lx r25: %08lx r24: %08lx\n",
regs->p1, regs->p0, regs->r[25], regs->r[24]);
printf("r23: %08lx r22: %08lx r21: %08lx r20: %08lx\n",
regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
printf("r19: %08lx r18: %08lx r17: %08lx r16: %08lx\n",
regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
printf("r15: %08lx r14: %08lx r13: %08lx r12: %08lx\n",
regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
printf("r11: %08lx r10: %08lx r9 : %08lx r8 : %08lx\n",
regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
printf(" Interrupts %s Mode %s\n",
interrupts_enabled(regs) ? "on" : "off",
processor_modes[processor_mode(regs)]);
}
void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
{
const char *interruption_type[] = {
"Reset",
"TLB Fill",
"TLB Not Present",
"TLB Misc",
"VLPT Miss",
"Cache Parity Error",
"Debug",
"General Exception",
"External Interrupt"
};
printf("%s\n", interruption_type[EVIC_num]);
show_regs(pt_regs);
bad_mode();
}