avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/arch/mips/mach-au1x00/Makefile

@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2011
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o

u-boot/arch/mips/mach-au1x00/au1x00_eth.c

@@ -0,0 +1,304 @@
+/* Only eth0 supported for now
+ *
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <config.h>
+
+#if defined(CONFIG_SYS_DISCOVER_PHY)
+#error "PHY not supported yet"
+/* We just assume that we are running 100FD for now */
+/* We all use switches, right? ;-) */
+#endif
+
+/* I assume ethernet behaves like au1000 */
+
+#ifdef CONFIG_SOC_AU1000
+/* Base address differ between cpu:s */
+#define ETH0_BASE AU1000_ETH0_BASE
+#define MAC0_ENABLE AU1000_MAC0_ENABLE
+#else
+#ifdef CONFIG_SOC_AU1100
+#define ETH0_BASE AU1100_ETH0_BASE
+#define MAC0_ENABLE AU1100_MAC0_ENABLE
+#else
+#ifdef CONFIG_SOC_AU1500
+#define ETH0_BASE AU1500_ETH0_BASE
+#define MAC0_ENABLE AU1500_MAC0_ENABLE
+#else
+#ifdef CONFIG_SOC_AU1550
+#define ETH0_BASE AU1550_ETH0_BASE
+#define MAC0_ENABLE AU1550_MAC0_ENABLE
+#else
+#error "No valid cpu set"
+#endif
+#endif
+#endif
+#endif
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <command.h>
+#include <asm/io.h>
+#include <mach/au1x00.h>
+
+#if defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+#endif
+
+/* Ethernet Transmit and Receive Buffers */
+#define DBUF_LENGTH  1520
+#define PKT_MAXBUF_SIZE		1518
+
+static char txbuf[DBUF_LENGTH];
+
+static int next_tx;
+static int next_rx;
+
+/* 4 rx and 4 tx fifos */
+#define NO_OF_FIFOS 4
+
+typedef struct{
+	u32 status;
+	u32 addr;
+	u32 len; /* Only used for tx */
+	u32 not_used;
+} mac_fifo_t;
+
+mac_fifo_t mac_fifo[NO_OF_FIFOS];
+
+#define MAX_WAIT 1000
+
+#if defined(CONFIG_CMD_MII)
+int  au1x00_miiphy_read(const char *devname, unsigned char addr,
+		unsigned char reg, unsigned short * value)
+{
+	volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+	volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+	u32 mii_control;
+	unsigned int timedout = 20;
+
+	while (*mii_control_reg & MAC_MII_BUSY) {
+		udelay(1000);
+		if (--timedout == 0) {
+			printf("au1x00_eth: miiphy_read busy timeout!!\n");
+			return -1;
+		}
+	}
+
+	mii_control = MAC_SET_MII_SELECT_REG(reg) |
+		MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
+
+	*mii_control_reg = mii_control;
+
+	timedout = 20;
+	while (*mii_control_reg & MAC_MII_BUSY) {
+		udelay(1000);
+		if (--timedout == 0) {
+			printf("au1x00_eth: miiphy_read busy timeout!!\n");
+			return -1;
+		}
+	}
+	*value = *mii_data_reg;
+	return 0;
+}
+
+int  au1x00_miiphy_write(const char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value)
+{
+	volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+	volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+	u32 mii_control;
+	unsigned int timedout = 20;
+
+	while (*mii_control_reg & MAC_MII_BUSY) {
+		udelay(1000);
+		if (--timedout == 0) {
+			printf("au1x00_eth: miiphy_write busy timeout!!\n");
+			return -1;
+		}
+	}
+
+	mii_control = MAC_SET_MII_SELECT_REG(reg) |
+		MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
+
+	*mii_data_reg = value;
+	*mii_control_reg = mii_control;
+	return 0;
+}
+#endif
+
+static int au1x00_send(struct eth_device *dev, void *packet, int length)
+{
+	volatile mac_fifo_t *fifo_tx =
+		(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
+	int i;
+	int res;
+
+	/* tx fifo should always be idle */
+	fifo_tx[next_tx].len = length;
+	fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
+	au_sync();
+
+	udelay(1);
+	i=0;
+	while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
+		if(i>MAX_WAIT){
+			printf("TX timeout\n");
+			break;
+		}
+		udelay(1);
+		i++;
+	}
+
+	/* Clear done bit */
+	fifo_tx[next_tx].addr = 0;
+	fifo_tx[next_tx].len = 0;
+	au_sync();
+
+	res = fifo_tx[next_tx].status;
+
+	next_tx++;
+	if(next_tx>=NO_OF_FIFOS){
+		next_tx=0;
+	}
+	return(res);
+}
+
+static int au1x00_recv(struct eth_device* dev){
+	volatile mac_fifo_t *fifo_rx =
+		(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
+
+	int length;
+	u32 status;
+
+	for(;;){
+		if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
+			/* Nothing has been received */
+			return(-1);
+		}
+
+		status = fifo_rx[next_rx].status;
+
+		length = status&0x3FFF;
+
+		if(status&RX_ERROR){
+			printf("Rx error 0x%x\n", status);
+		} else {
+			/* Pass the packet up to the protocol layers. */
+			net_process_received_packet(net_rx_packets[next_rx],
+						    length - 4);
+		}
+
+		fifo_rx[next_rx].addr =
+			(virt_to_phys(net_rx_packets[next_rx])) | RX_DMA_ENABLE;
+
+		next_rx++;
+		if(next_rx>=NO_OF_FIFOS){
+			next_rx=0;
+		}
+	} /* for */
+
+	return(0); /* Does anyone use this? */
+}
+
+static int au1x00_init(struct eth_device* dev, bd_t * bd){
+
+	volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
+	volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
+	volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
+	volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
+	volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
+	volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
+	volatile mac_fifo_t *fifo_tx =
+		(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
+	volatile mac_fifo_t *fifo_rx =
+		(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
+	int i;
+
+	next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
+	next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
+
+	/* We have to enable clocks before releasing reset */
+	*macen = MAC_EN_CLOCK_ENABLE;
+	udelay(10);
+
+	/* Enable MAC0 */
+	/* We have to release reset before accessing registers */
+	*macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
+		MAC_EN_RESET1|MAC_EN_RESET2;
+	udelay(10);
+
+	for(i=0;i<NO_OF_FIFOS;i++){
+		fifo_tx[i].len = 0;
+		fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
+		fifo_rx[i].addr = (virt_to_phys(net_rx_packets[i])) |
+			RX_DMA_ENABLE;
+	}
+
+	/* Put mac addr in little endian */
+#define ea eth_get_ethaddr()
+	*mac_addr_high	=	(ea[5] <<  8) | (ea[4]	    ) ;
+	*mac_addr_low	=	(ea[3] << 24) | (ea[2] << 16) |
+		(ea[1] <<  8) | (ea[0]	    ) ;
+#undef ea
+	*mac_mcast_low = 0;
+	*mac_mcast_high = 0;
+
+	/* Make sure the MAC buffer is in the correct endian mode */
+#ifdef __LITTLE_ENDIAN
+	*mac_ctrl = MAC_FULL_DUPLEX;
+	udelay(1);
+	*mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
+#else
+	*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
+	udelay(1);
+	*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
+#endif
+
+	return(1);
+}
+
+static void au1x00_halt(struct eth_device* dev){
+	volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
+
+	/* Put MAC0 in reset */
+	*macen = 0;
+}
+
+int au1x00_enet_initialize(bd_t *bis){
+	struct eth_device* dev;
+
+	if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
+		puts ("malloc failed\n");
+		return -1;
+	}
+
+	memset(dev, 0, sizeof *dev);
+
+	strcpy(dev->name, "Au1X00 ethernet");
+	dev->iobase = 0;
+	dev->priv   = 0;
+	dev->init   = au1x00_init;
+	dev->halt   = au1x00_halt;
+	dev->send   = au1x00_send;
+	dev->recv   = au1x00_recv;
+
+	eth_register(dev);
+
+#if defined(CONFIG_CMD_MII)
+	miiphy_register(dev->name,
+		au1x00_miiphy_read, au1x00_miiphy_write);
+#endif
+
+	return 1;
+}
+
+int cpu_eth_init(bd_t *bis)
+{
+	au1x00_enet_initialize(bis);
+	return 0;
+}

u-boot/arch/mips/mach-au1x00/au1x00_ide.c

@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ide.h>
+
+/* AU1X00 swaps data in big-endian mode, enforce little-endian function */
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+	ide_input_data(dev, sect_buf, words);
+}

u-boot/arch/mips/mach-au1x00/au1x00_serial.c

@@ -0,0 +1,131 @@
+/*
+ * AU1X00 UART support
+ *
+ * Hardcoded to UART 0 for now
+ * Speed and options also hardcoded to 115200 8N1
+ *
+ *  Copyright (c) 2003	Thomas.Lange@corelatus.se
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <mach/au1x00.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
+/******************************************************************************
+*
+* serial_init - initialize a channel
+*
+* This routine initializes the number of data bits, parity
+* and set the selected baud rate. Interrupts are disabled.
+* Set the modem control signals if the option is selected.
+*
+* RETURNS: N/A
+*/
+
+static int au1x00_serial_init(void)
+{
+	volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
+	volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
+
+	/* Enable clocks first */
+	*uart_enable = UART_EN_CE;
+
+	/* Then release reset */
+	/* Must release reset before setting other regs */
+	*uart_enable = UART_EN_CE|UART_EN_E;
+
+	/* Activate fifos, reset tx and rx */
+	/* Set tx trigger level to 12 */
+	*uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
+		UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
+
+	serial_setbrg();
+
+	return 0;
+}
+
+
+static void au1x00_serial_setbrg(void)
+{
+	volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
+	volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
+	volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
+	int sd;
+	int divisorx2;
+
+	/* sd is system clock divisor			*/
+	/* see section 10.4.5 in au1550 datasheet	*/
+	sd = (*sys_powerctrl & 0x03) + 2;
+
+	/* calulate 2x baudrate and round */
+	divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
+
+	if (divisorx2 & 0x01)
+		divisorx2 = divisorx2 + 1;
+
+	*uart_clk = divisorx2 / 2;
+
+	/* Set parity, stop bits and word length to 8N1 */
+	*uart_lcr = UART_LCR_WLEN8;
+}
+
+static void au1x00_serial_putc(const char c)
+{
+	volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
+	volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
+
+	if (c == '\n')
+		au1x00_serial_putc('\r');
+
+	/* Wait for fifo to shift out some bytes */
+	while((*uart_lsr&UART_LSR_THRE)==0);
+
+	*uart_tx = (u32)c;
+}
+
+static int au1x00_serial_getc(void)
+{
+	volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
+	char c;
+
+	while (!serial_tstc());
+
+	c = (*uart_rx&0xFF);
+	return c;
+}
+
+static int au1x00_serial_tstc(void)
+{
+	volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
+
+	if(*uart_lsr&UART_LSR_DR){
+		/* Data in rfifo */
+		return(1);
+	}
+	return 0;
+}
+
+static struct serial_device au1x00_serial_drv = {
+	.name	= "au1x00_serial",
+	.start	= au1x00_serial_init,
+	.stop	= NULL,
+	.setbrg	= au1x00_serial_setbrg,
+	.putc	= au1x00_serial_putc,
+	.puts	= default_serial_puts,
+	.getc	= au1x00_serial_getc,
+	.tstc	= au1x00_serial_tstc,
+};
+
+void au1x00_serial_initialize(void)
+{
+	serial_register(&au1x00_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+	return &au1x00_serial_drv;
+}

u-boot/arch/mips/mach-au1x00/au1x00_usb_ohci.h

@@ -0,0 +1,416 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+	/* No  Error  */	0,
+	/* CRC Error  */	USB_ST_CRC_ERR,
+	/* Bit Stuff  */	USB_ST_BIT_ERR,
+	/* Data Togg  */	USB_ST_CRC_ERR,
+	/* Stall      */	USB_ST_STALLED,
+	/* DevNotResp */	-1,
+	/* PIDCheck   */	USB_ST_BIT_ERR,
+	/* UnExpPID   */	USB_ST_BIT_ERR,
+	/* DataOver   */	USB_ST_BUF_ERR,
+	/* DataUnder  */	USB_ST_BUF_ERR,
+	/* reservd    */	-1,
+	/* reservd    */	-1,
+	/* BufferOver */	USB_ST_BUF_ERR,
+	/* BuffUnder  */	USB_ST_BUF_ERR,
+	/* Not Access */	-1,
+	/* Not Access */	-1
+};
+
+/* ED States */
+
+#define ED_NEW		0x00
+#define ED_UNLINK	0x01
+#define ED_OPER		0x02
+#define ED_DEL		0x04
+#define ED_URB_DEL	0x08
+
+/* usb_ohci_ed */
+struct ed {
+	__u32 hwINFO;
+	__u32 hwTailP;
+	__u32 hwHeadP;
+	__u32 hwNextED;
+
+	struct ed *ed_prev;
+	__u8 int_period;
+	__u8 int_branch;
+	__u8 int_load;
+	__u8 int_interval;
+	__u8 state;
+	__u8 type;
+	__u16 last_iso;
+	struct ed *ed_rm_list;
+
+	struct usb_device *usb_dev;
+	__u32 unused[3];
+} __attribute__((aligned(16)));
+typedef struct ed ed_t;
+
+
+/* TD info field */
+#define TD_CC			0xf0000000
+#define TD_CC_GET(td_p)		((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc)	(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC			0x0C000000
+#define TD_T			0x03000000
+#define TD_T_DATA0		0x02000000
+#define TD_T_DATA1		0x03000000
+#define TD_T_TOGGLE		0x00000000
+#define TD_R			0x00040000
+#define TD_DI			0x00E00000
+#define TD_DI_SET(X)		(((X) & 0x07)<< 21)
+#define TD_DP			0x00180000
+#define TD_DP_SETUP		0x00000000
+#define TD_DP_IN		0x00100000
+#define TD_DP_OUT		0x00080000
+
+#define TD_ISO			0x00010000
+#define TD_DEL			0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR		0x00
+#define TD_CC_CRC		0x01
+#define TD_CC_BITSTUFFING	0x02
+#define TD_CC_DATATOGGLEM	0x03
+#define TD_CC_STALL		0x04
+#define TD_DEVNOTRESP		0x05
+#define TD_PIDCHECKFAIL		0x06
+#define TD_UNEXPECTEDPID	0x07
+#define TD_DATAOVERRUN		0x08
+#define TD_DATAUNDERRUN		0x09
+#define TD_BUFFEROVERRUN	0x0C
+#define TD_BUFFERUNDERRUN	0x0D
+#define TD_NOTACCESSED		0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+	__u32 hwINFO;
+	__u32 hwCBP;		/* Current Buffer Pointer */
+	__u32 hwNextTD;		/* Next TD Pointer */
+	__u32 hwBE;		/* Memory Buffer End Pointer */
+
+	__u16 hwPSW[MAXPSW];
+	__u8 unused;
+	__u8 index;
+	struct ed *ed;
+	struct td *next_dl_td;
+	struct usb_device *usb_dev;
+	int transfer_len;
+	__u32 data;
+
+	__u32 unused2[2];
+} __attribute__((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP	(1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of.  It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32	/* part of the OHCI standard */
+struct ohci_hcca {
+	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
+	__u16	frame_no;		/* current frame number */
+	__u16	pad1;			/* set to 0 on each frame_no change */
+	__u32	done_head;		/* info returned for an interrupt */
+	u8		reserved_for_hc[116];
+} __attribute__((aligned(256)));
+
+
+/*
+ * Maximum number of root hub ports.
+ */
+#define MAX_ROOT_PORTS	15	/* maximum OHCI root hub ports */
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region.  This is Memory Mapped I/O.	You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+	/* control and status registers */
+	__u32	revision;
+	__u32	control;
+	__u32	cmdstatus;
+	__u32	intrstatus;
+	__u32	intrenable;
+	__u32	intrdisable;
+	/* memory pointers */
+	__u32	hcca;
+	__u32	ed_periodcurrent;
+	__u32	ed_controlhead;
+	__u32	ed_controlcurrent;
+	__u32	ed_bulkhead;
+	__u32	ed_bulkcurrent;
+	__u32	donehead;
+	/* frame counters */
+	__u32	fminterval;
+	__u32	fmremaining;
+	__u32	fmnumber;
+	__u32	periodicstart;
+	__u32	lsthresh;
+	/* Root hub ports */
+	struct	ohci_roothub_regs {
+		__u32	a;
+		__u32	b;
+		__u32	status;
+		__u32	portstatus[MAX_ROOT_PORTS];
+	} roothub;
+} __attribute__((aligned(32)));
+
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
+#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
+#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
+#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
+#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
+#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
+#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
+#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
+#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+#	define OHCI_USB_RESET	(0 << 6)
+#	define OHCI_USB_RESUME	(1 << 6)
+#	define OHCI_USB_OPER	(2 << 6)
+#	define OHCI_USB_SUSPEND	(3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR	(1 << 0)	/* host controller reset */
+#define OHCI_CLF	(1 << 1)	/* control list filled */
+#define OHCI_BLF	(1 << 2)	/* bulk list filled */
+#define OHCI_OCR	(1 << 3)	/* ownership change request */
+#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
+#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
+#define OHCI_INTR_SF	(1 << 2)	/* start frame */
+#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
+#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
+#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
+#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
+#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
+#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */
+
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+	int devnum; /* Address of Root Hub endpoint */
+	void *dev;  /* was urb */
+	void *int_addr;
+	int send;
+	int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE		0x01
+#define RH_ENDPOINT		0x02
+#define RH_OTHER		0x03
+
+#define RH_CLASS		0x20
+#define RH_VENDOR		0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS		0x0080
+#define RH_CLEAR_FEATURE	0x0100
+#define RH_SET_FEATURE		0x0300
+#define RH_SET_ADDRESS		0x0500
+#define RH_GET_DESCRIPTOR	0x0680
+#define RH_SET_DESCRIPTOR	0x0700
+#define RH_GET_CONFIGURATION	0x0880
+#define RH_SET_CONFIGURATION	0x0900
+#define RH_GET_STATE		0x0280
+#define RH_GET_INTERFACE	0x0A80
+#define RH_SET_INTERFACE	0x0B00
+#define RH_SYNC_FRAME		0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP		0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION	0x00
+#define RH_PORT_ENABLE		0x01
+#define RH_PORT_SUSPEND		0x02
+#define RH_PORT_OVER_CURRENT	0x03
+#define RH_PORT_RESET		0x04
+#define RH_PORT_POWER		0x08
+#define RH_PORT_LOW_SPEED	0x09
+
+#define RH_C_PORT_CONNECTION	0x10
+#define RH_C_PORT_ENABLE	0x11
+#define RH_C_PORT_SUSPEND	0x12
+#define RH_C_PORT_OVER_CURRENT	0x13
+#define RH_C_PORT_RESET		0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER	0x00
+#define RH_C_HUB_OVER_CURRENT	0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL	0x01
+
+#define RH_ACK			0x01
+#define RH_REQ_ERR		-1
+#define RH_NACK			0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS		0x00000001	/* current connect status */
+#define RH_PS_PES		0x00000002	/* port enable status*/
+#define RH_PS_PSS		0x00000004	/* port suspend status */
+#define RH_PS_POCI		0x00000008	/* port over current indicator */
+#define RH_PS_PRS		0x00000010	/* port reset status */
+#define RH_PS_PPS		0x00000100	/* port power status */
+#define RH_PS_LSDA		0x00000200	/* low speed device attached */
+#define RH_PS_CSC		0x00010000	/* connect status change */
+#define RH_PS_PESC		0x00020000	/* port enable status change */
+#define RH_PS_PSSC		0x00040000	/* port suspend status change */
+#define RH_PS_OCIC		0x00080000	/* over current indicator change */
+#define RH_PS_PRSC		0x00100000	/* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS		0x00000001	/* local power status */
+#define RH_HS_OCI		0x00000002	/* over current indicator */
+#define RH_HS_DRWE		0x00008000	/* device remote wakeup enable */
+#define RH_HS_LPSC		0x00010000	/* local power status change */
+#define RH_HS_OCIC		0x00020000	/* over current indicator change */
+#define RH_HS_CRWE		0x80000000	/* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR			0x0000ffff	/* device removable flags */
+#define RH_B_PPCM		0xffff0000	/* port power control mask */
+
+/* roothub.a masks */
+#define	RH_A_NDP		(0xff << 0)	/* number of downstream ports */
+#define	RH_A_PSM		(1 << 8)	/* power switching mode */
+#define	RH_A_NPS		(1 << 9)	/* no power switching */
+#define	RH_A_DT			(1 << 10)	/* device type (mbz) */
+#define	RH_A_OCPM		(1 << 11)	/* over current protection mode */
+#define	RH_A_NOCP		(1 << 12)	/* no over current protection */
+#define	RH_A_POTPGT		(0xff << 24)	/* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct
+{
+	ed_t *ed;
+	__u16 length;		/* number of tds associated with this request */
+	__u16 td_cnt;		/* number of tds already serviced */
+	int   state;
+	unsigned long pipe;
+	int actual_length;
+	td_t *td[N_URB_TD];	/* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+
+typedef struct ohci {
+	struct ohci_hcca *hcca;		/* hcca */
+	/*dma_addr_t hcca_dma;*/
+
+	int irq;
+	int disabled;			/* e.g. got a UE, we're hung */
+	int sleeping;
+	unsigned long flags;		/* for HC bugs */
+
+	struct ohci_regs *regs;		/* OHCI controller's memory */
+
+	ed_t *ed_rm_list[2];		/* lists of all endpoints to be removed */
+	ed_t *ed_bulktail;		/* last endpoint of bulk list */
+	ed_t *ed_controltail;		/* last endpoint of control list */
+	int intrstatus;
+	__u32 hc_control;		/* copy of the hc control reg */
+	struct usb_device *dev[32];
+	struct virt_root_hub rh;
+
+	const char	*slot_name;
+} ohci_t;
+
+#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+	ed_t	ed[NUM_EDS];
+	int ed_cnt;
+};
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* +1 so we can align the storage */
+td_t gtd[NUM_TD+1];
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *
+td_alloc (struct usb_device *usb_dev)
+{
+	int i;
+	struct td	*td;
+
+	td = NULL;
+	for (i = 0; i < NUM_TD; i++) {
+		if (ptd[i].usb_dev == NULL) {
+			td = &ptd[i];
+			td->usb_dev = usb_dev;
+			break;
+		}
+	}
+	return td;
+}
+
+static inline void
+ed_free (struct ed *ed)
+{
+	ed->usb_dev = NULL;
+}