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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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55
u-boot/arch/m68k/include/asm/bitops.h Normal file
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/*
* bitops.h: Bit string operations on the m68k
*/
#ifndef _M68K_BITOPS_H
#define _M68K_BITOPS_H
#include <asm/byteorder.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/__ffs.h>
extern void set_bit(int nr, volatile void *addr);
extern void clear_bit(int nr, volatile void *addr);
extern void change_bit(int nr, volatile void *addr);
extern int test_and_clear_bit(int nr, volatile void *addr);
extern int test_and_change_bit(int nr, volatile void *addr);
#ifdef __KERNEL__
static inline int test_bit(int nr, __const__ volatile void *addr)
{
__const__ unsigned int *p = (__const__ unsigned int *) addr;
return (p[nr >> 5] & (1UL << (nr & 31))) != 0;
}
static inline int test_and_set_bit(int nr, volatile void *vaddr)
{
char retval;
volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
__asm__ __volatile__ ("bset %2,(%4); sne %0"
: "=d" (retval), "=m" (*p)
: "di" (nr & 7), "m" (*p), "a" (p));
return retval;
}
#define __ffs(x) (ffs(x) - 1)
/*
* * hweightN: returns the hamming weight (i.e. the number
* * of bits set) of a N-bit word
* */
#define hweight32(x) generic_hweight32(x)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
#endif /* __KERNEL__ */
#endif /* _M68K_BITOPS_H */

91
u-boot/arch/m68k/include/asm/byteorder.h Normal file
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/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _M68K_BYTEORDER_H
#define _M68K_BYTEORDER_H
#include <asm/types.h>
#ifdef __GNUC__
#define __sw16(x) \
((__u16)( \
(((__u16)(x) & (__u16)0x00ffU) << 8) | \
(((__u16)(x) & (__u16)0xff00U) >> 8) ))
#define __sw32(x) \
((__u32)( \
(((__u32)(x)) << 24) | \
(((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
(((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
(((__u32)(x)) >> 24) ))
static __inline__ unsigned ld_le16(const volatile unsigned short *addr)
{
unsigned result = *addr;
return __sw16(result);
}
static __inline__ void st_le16(volatile unsigned short *addr,
const unsigned val)
{
*addr = __sw16(val);
}
static __inline__ unsigned ld_le32(const volatile unsigned *addr)
{
unsigned result = *addr;
return __sw32(result);
}
static __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
{
*addr = __sw32(val);
}
#if 0
/* alas, egcs sounds like it has a bug in this code that doesn't use the
inline asm correctly, and can cause file corruption. Until I hear that
it's fixed, I can live without the extra speed. I hope. */
#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
#if 0
# define __arch_swab16(x) ld_le16(&x)
# define __arch_swab32(x) ld_le32(&x)
#else
static __inline__ __attribute__ ((const))
__u16 ___arch__swab16(__u16 value)
{
return __sw16(value);
}
static __inline__ __attribute__ ((const))
__u32 ___arch__swab32(__u32 value)
{
return __sw32(value);
}
#define __arch__swab32(x) ___arch__swab32(x)
#define __arch__swab16(x) ___arch__swab16(x)
#endif /* 0 */
#endif
/* The same, but returns converted value from the location pointer by addr. */
#define __arch__swab16p(addr) ld_le16(addr)
#define __arch__swab32p(addr) ld_le32(addr)
/* The same, but do the conversion in situ, ie. put the value back to addr. */
#define __arch__swab16s(addr) st_le16(addr,*addr)
#define __arch__swab32s(addr) st_le32(addr,*addr)
#endif
#endif /* __GNUC__ */
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
#define __BYTEORDER_HAS_U64__
#endif
#include <linux/byteorder/big_endian.h>
#endif /* _M68K_BYTEORDER_H */

204
u-boot/arch/m68k/include/asm/cache.h Normal file
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/*
* ColdFire cache
*
* Copyright 2004-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CACHE_H
#define __CACHE_H
#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x)
#define CONFIG_CF_V2
#endif
#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
defined(CONFIG_MCF5301x)
#define CONFIG_CF_V3
#endif
#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
#define CONFIG_CF_V4
#elif defined(CONFIG_MCF5441x)
#define CONFIG_CF_V4E /* Four Extra ACRn */
#endif
/* ***** CACR ***** */
/* V2 Core */
#ifdef CONFIG_CF_V2
#define CF_CACR_CENB (1 << 31)
#define CF_CACR_CPD (1 << 28)
#define CF_CACR_CFRZ (1 << 27)
#define CF_CACR_CEIB (1 << 10)
#define CF_CACR_DCM (1 << 9)
#define CF_CACR_DBWE (1 << 8)
#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253)
#define CF_CACR_DWP (1 << 6)
#else
#define CF_CACR_CINV (1 << 24)
#define CF_CACR_DISI (1 << 23)
#define CF_CACR_DISD (1 << 22)
#define CF_CACR_INVI (1 << 21)
#define CF_CACR_INVD (1 << 20)
#define CF_CACR_DWP (1 << 5)
#define CF_CACR_EUSP (1 << 4)
#endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */
#endif /* CONFIG_CF_V2 */
/* V3 Core */
#ifdef CONFIG_CF_V3
#define CF_CACR_EC (1 << 31)
#define CF_CACR_ESB (1 << 29)
#define CF_CACR_DPI (1 << 28)
#define CF_CACR_HLCK (1 << 27)
#define CF_CACR_CINVA (1 << 24)
#define CF_CACR_DNFB (1 << 10)
#define CF_CACR_DCM_UNMASK 0xFFFFFCFF
#define CF_CACR_DCM_WT (0 << 8)
#define CF_CACR_DCM_CB (1 << 8)
#define CF_CACR_DCM_P (2 << 8)
#define CF_CACR_DCM_IP (3 << 8)
#define CF_CACR_DW (1 << 5)
#define CF_CACR_EUSP (1 << 4)
#endif /* CONFIG_CF_V3 */
/* V4 Core */
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
#define CF_CACR_DEC (1 << 31)
#define CF_CACR_DW (1 << 30)
#define CF_CACR_DESB (1 << 29)
#define CF_CACR_DDPI (1 << 28)
#define CF_CACR_DHLCK (1 << 27)
#define CF_CACR_DDCM_UNMASK (0xF9FFFFFF)
#define CF_CACR_DDCM_WT (0 << 25)
#define CF_CACR_DDCM_CB (1 << 25)
#define CF_CACR_DDCM_P (2 << 25)
#define CF_CACR_DDCM_IP (3 << 25)
#define CF_CACR_DCINVA (1 << 24)
#define CF_CACR_DDSP (1 << 23)
#define CF_CACR_BEC (1 << 19)
#define CF_CACR_BCINVA (1 << 18)
#define CF_CACR_IEC (1 << 15)
#define CF_CACR_DNFB (1 << 13)
#define CF_CACR_IDPI (1 << 12)
#define CF_CACR_IHLCK (1 << 11)
#define CF_CACR_IDCM (1 << 10)
#define CF_CACR_ICINVA (1 << 8)
#define CF_CACR_IDSP (1 << 7)
#define CF_CACR_EUSP (1 << 5)
#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
#define CF_CACR_IVO (1 << 20)
#define CF_CACR_SPA (1 << 14)
#else
#define CF_CACR_DF (1 << 4)
#endif
#endif /* CONFIG_CF_V4 */
/* ***** ACR ***** */
#define CF_ACR_ADR_UNMASK (0x00FFFFFF)
#define CF_ACR_ADR(x) ((x & 0xFF) << 24)
#define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF)
#define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16)
#define CF_ACR_EN (1 << 15)
#define CF_ACR_SM_UNMASK (0xFFFF9FFF)
#define CF_ACR_SM_UM (0 << 13)
#define CF_ACR_SM_SM (1 << 13)
#define CF_ACR_SM_ALL (3 << 13)
#define CF_ACR_WP (1 << 2)
/* V2 Core */
#ifdef CONFIG_CF_V2
#define CF_ACR_CM (1 << 6)
#define CF_ACR_BWE (1 << 5)
#else
/* V3 & V4 */
#define CF_ACR_CM_UNMASK (0xFFFFFF9F)
#define CF_ACR_CM_WT (0 << 5)
#define CF_ACR_CM_CB (1 << 5)
#define CF_ACR_CM_P (2 << 5)
#define CF_ACR_CM_IP (3 << 5)
#endif /* CONFIG_CF_V2 */
/* V4 Core */
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
#define CF_ACR_AMM (1 << 10)
#define CF_ACR_SP (1 << 3)
#endif /* CONFIG_CF_V4 */
#ifndef CONFIG_SYS_CACHE_ICACR
#define CONFIG_SYS_CACHE_ICACR 0
#endif
#ifndef CONFIG_SYS_CACHE_DCACR
#ifdef CONFIG_SYS_CACHE_ICACR
#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR
#else
#define CONFIG_SYS_CACHE_DCACR 0
#endif
#endif
#ifndef CONFIG_SYS_CACHE_ACR0
#define CONFIG_SYS_CACHE_ACR0 0
#endif
#ifndef CONFIG_SYS_CACHE_ACR1
#define CONFIG_SYS_CACHE_ACR1 0
#endif
#ifndef CONFIG_SYS_CACHE_ACR2
#define CONFIG_SYS_CACHE_ACR2 0
#endif
#ifndef CONFIG_SYS_CACHE_ACR3
#define CONFIG_SYS_CACHE_ACR3 0
#endif
#ifndef CONFIG_SYS_CACHE_ACR4
#define CONFIG_SYS_CACHE_ACR4 0
#endif
#ifndef CONFIG_SYS_CACHE_ACR5
#define CONFIG_SYS_CACHE_ACR5 0
#endif
#ifndef CONFIG_SYS_CACHE_ACR6
#define CONFIG_SYS_CACHE_ACR6 0
#endif
#ifndef CONFIG_SYS_CACHE_ACR7
#define CONFIG_SYS_CACHE_ACR7 0
#endif
#define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
void icache_invalid(void);
void dcache_invalid(void);
#endif
/*
* m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer
* alignment unless the board configuration has specified a new value.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 16
#endif
#endif /* __CACHE_H */

63
u-boot/arch/m68k/include/asm/coldfire/ata.h Normal file
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/*
* ATA Internal Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ATA_H__
#define __ATA_H__
/* ATA */
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
u8 rsvd6[106];
} atac_t;
#endif /* __ATA_H__ */

63
u-boot/arch/m68k/include/asm/coldfire/crossbar.h Normal file
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/*
* Cross Bar Switch Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CROSSBAR_H__
#define __CROSSBAR_H__
/*********************************************************************
* Cross-bar switch (XBS)
*********************************************************************/
typedef struct xbs {
u32 prs1; /* 0x100 Priority Register Slave 1 */
u32 res1[3]; /* 0x104 - 0F */
u32 crs1; /* 0x110 Control Register Slave 1 */
u32 res2[187]; /* 0x114 - 0x3FF */
u32 prs4; /* 0x400 Priority Register Slave 4 */
u32 res3[3]; /* 0x404 - 0F */
u32 crs4; /* 0x410 Control Register Slave 4 */
u32 res4[123]; /* 0x414 - 0x5FF */
u32 prs6; /* 0x600 Priority Register Slave 6 */
u32 res5[3]; /* 0x604 - 0F */
u32 crs6; /* 0x610 Control Register Slave 6 */
u32 res6[59]; /* 0x614 - 0x6FF */
u32 prs7; /* 0x700 Priority Register Slave 7 */
u32 res7[3]; /* 0x704 - 0F */
u32 crs7; /* 0x710 Control Register Slave 7 */
} xbs_t;
/* Bit definitions and macros for PRS group */
#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */
#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */
#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */
#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */
#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */
#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */
#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */
/* Bit definitions and macros for CRS group */
#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */
#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */
#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */
#define XBS_CRS_RO (0x80000000) /* Read Only */
#define XBS_CRS_PCTL_PARK_FIELD (0)
#define XBS_CRS_PCTL_PARK_ON_LAST (1)
#define XBS_CRS_PCTL_PARK_NONE (2)
#define XBS_CRS_PCTL_PARK_CORE (0)
#define XBS_CRS_PCTL_PARK_EDMA (1)
#define XBS_CRS_PCTL_PARK_FEC0 (2)
#define XBS_CRS_PCTL_PARK_FEC1 (3)
#define XBS_CRS_PCTL_PARK_PCI (5)
#define XBS_CRS_PCTL_PARK_USB (6)
#define XBS_CRS_PCTL_PARK_SBF (7)
#endif /* __CROSSBAR_H__ */

142
u-boot/arch/m68k/include/asm/coldfire/dspi.h Normal file
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/*
* MCF5227x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DSPI_H__
#define __DSPI_H__
/* DMA Serial Peripheral Interface (DSPI) */
typedef struct dspi {
u32 mcr; /* 0x00 */
u32 resv0; /* 0x04 */
u32 tcr; /* 0x08 */
u32 ctar[8]; /* 0x0C - 0x28 */
u32 sr; /* 0x2C */
u32 irsr; /* 0x30 */
u32 tfr; /* 0x34 - PUSHR */
u16 resv1; /* 0x38 */
u16 rfr; /* 0x3A - POPR */
#ifdef CONFIG_MCF547x_8x
u32 tfdr[4]; /* 0x3C */
u8 resv2[0x30]; /* 0x40 */
u32 rfdr[4]; /* 0x7C */
#else
u32 tfdr[16]; /* 0x3C */
u32 rfdr[16]; /* 0x7C */
#endif
} dspi_t;
/* Module configuration */
#define DSPI_MCR_MSTR (0x80000000)
#define DSPI_MCR_CSCK (0x40000000)
#define DSPI_MCR_DCONF(x) (((x)&0x03)<<28)
#define DSPI_MCR_FRZ (0x08000000)
#define DSPI_MCR_MTFE (0x04000000)
#define DSPI_MCR_PCSSE (0x02000000)
#define DSPI_MCR_ROOE (0x01000000)
#define DSPI_MCR_CSIS7 (0x00800000)
#define DSPI_MCR_CSIS6 (0x00400000)
#define DSPI_MCR_CSIS5 (0x00200000)
#define DSPI_MCR_CSIS4 (0x00100000)
#define DSPI_MCR_CSIS3 (0x00080000)
#define DSPI_MCR_CSIS2 (0x00040000)
#define DSPI_MCR_CSIS1 (0x00020000)
#define DSPI_MCR_CSIS0 (0x00010000)
#define DSPI_MCR_MDIS (0x00004000)
#define DSPI_MCR_DTXF (0x00002000)
#define DSPI_MCR_DRXF (0x00001000)
#define DSPI_MCR_CTXF (0x00000800)
#define DSPI_MCR_CRXF (0x00000400)
#define DSPI_MCR_SMPL_PT(x) (((x)&0x03)<<8)
#define DSPI_MCR_HALT (0x00000001)
/* Transfer count */
#define DSPI_TCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
/* Clock and transfer attributes */
#define DSPI_CTAR_DBR (0x80000000)
#define DSPI_CTAR_TRSZ(x) (((x)&0x0F)<<27)
#define DSPI_CTAR_CPOL (0x04000000)
#define DSPI_CTAR_CPHA (0x02000000)
#define DSPI_CTAR_LSBFE (0x01000000)
#define DSPI_CTAR_PCSSCK(x) (((x)&0x03)<<22)
#define DSPI_CTAR_PCSSCK_7CLK (0x00A00000)
#define DSPI_CTAR_PCSSCK_5CLK (0x00800000)
#define DSPI_CTAR_PCSSCK_3CLK (0x00400000)
#define DSPI_CTAR_PCSSCK_1CLK (0x00000000)
#define DSPI_CTAR_PASC(x) (((x)&0x03)<<20)
#define DSPI_CTAR_PASC_7CLK (0x00300000)
#define DSPI_CTAR_PASC_5CLK (0x00200000)
#define DSPI_CTAR_PASC_3CLK (0x00100000)
#define DSPI_CTAR_PASC_1CLK (0x00000000)
#define DSPI_CTAR_PDT(x) (((x)&0x03)<<18)
#define DSPI_CTAR_PDT_7CLK (0x000A0000)
#define DSPI_CTAR_PDT_5CLK (0x00080000)
#define DSPI_CTAR_PDT_3CLK (0x00040000)
#define DSPI_CTAR_PDT_1CLK (0x00000000)
#define DSPI_CTAR_PBR(x) (((x)&0x03)<<16)
#define DSPI_CTAR_PBR_7CLK (0x00030000)
#define DSPI_CTAR_PBR_5CLK (0x00020000)
#define DSPI_CTAR_PBR_3CLK (0x00010000)
#define DSPI_CTAR_PBR_1CLK (0x00000000)
#define DSPI_CTAR_CSSCK(x) (((x)&0x0F)<<12)
#define DSPI_CTAR_ASC(x) (((x)&0x0F)<<8)
#define DSPI_CTAR_DT(x) (((x)&0x0F)<<4)
#define DSPI_CTAR_BR(x) (((x)&0x0F))
/* Status */
#define DSPI_SR_TCF (0x80000000)
#define DSPI_SR_TXRXS (0x40000000)
#define DSPI_SR_EOQF (0x10000000)
#define DSPI_SR_TFUF (0x08000000)
#define DSPI_SR_TFFF (0x02000000)
#define DSPI_SR_RFOF (0x00080000)
#define DSPI_SR_RFDF (0x00020000)
#define DSPI_SR_TXCTR(x) (((x)&0x0F)<<12)
#define DSPI_SR_TXPTR(x) (((x)&0x0F)<<8)
#define DSPI_SR_RXCTR(x) (((x)&0x0F)<<4)
#define DSPI_SR_RXPTR(x) (((x)&0x0F))
/* DMA/interrupt request selct and enable */
#define DSPI_IRSR_TCFE (0x80000000)
#define DSPI_IRSR_EOQFE (0x10000000)
#define DSPI_IRSR_TFUFE (0x08000000)
#define DSPI_IRSR_TFFFE (0x02000000)
#define DSPI_IRSR_TFFFS (0x01000000)
#define DSPI_IRSR_RFOFE (0x00080000)
#define DSPI_IRSR_RFDFE (0x00020000)
#define DSPI_IRSR_RFDFS (0x00010000)
/* Transfer control - 32-bit access */
#define DSPI_TFR_CONT (0x80000000)
#define DSPI_TFR_CTAS(x) (((x)&0x07)<<12)
#define DSPI_TFR_EOQ (0x08000000)
#define DSPI_TFR_CTCNT (0x04000000)
#define DSPI_TFR_CS7 (0x00800000)
#define DSPI_TFR_CS6 (0x00400000)
#define DSPI_TFR_CS5 (0x00200000)
#define DSPI_TFR_CS4 (0x00100000)
#define DSPI_TFR_CS3 (0x00080000)
#define DSPI_TFR_CS2 (0x00040000)
#define DSPI_TFR_CS1 (0x00020000)
#define DSPI_TFR_CS0 (0x00010000)
/* Transfer Fifo */
#define DSPI_TFR_TXDATA(x) (((x)&0xFFFF))
/* Bit definitions and macros for DRFR */
#define DSPI_RFR_RXDATA(x) (((x)&0xFFFF))
/* Bit definitions and macros for DTFDR group */
#define DSPI_TFDR_TXDATA(x) (((x)&0x0000FFFF))
#define DSPI_TFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for DRFDR group */
#define DSPI_RFDR_RXDATA(x) (((x)&0x0000FFFF))
#endif /* __DSPI_H__ */

161
u-boot/arch/m68k/include/asm/coldfire/edma.h Normal file
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/*
* EDMA Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EDMA_H__
#define __EDMA_H__
/*********************************************************************
* Enhanced DMA (EDMA)
*********************************************************************/
/* eDMA module registers */
typedef struct edma_ctrl {
u32 cr; /* 0x00 Control Register */
u32 es; /* 0x04 Error Status Register */
u16 res1[3]; /* 0x08 - 0x0D */
u16 erq; /* 0x0E Enable Request Register */
u16 res2[3]; /* 0x10 - 0x15 */
u16 eei; /* 0x16 Enable Error Interrupt Request */
u8 serq; /* 0x18 Set Enable Request */
u8 cerq; /* 0x19 Clear Enable Request */
u8 seei; /* 0x1A Set En Error Interrupt Request */
u8 ceei; /* 0x1B Clear En Error Interrupt Request */
u8 cint; /* 0x1C Clear Interrupt Enable */
u8 cerr; /* 0x1D Clear Error */
u8 ssrt; /* 0x1E Set START Bit */
u8 cdne; /* 0x1F Clear DONE Status Bit */
u16 res3[3]; /* 0x20 - 0x25 */
u16 intr; /* 0x26 Interrupt Request */
u16 res4[3]; /* 0x28 - 0x2D */
u16 err; /* 0x2E Error Register */
u32 res5[52]; /* 0x30 - 0xFF */
u8 dchpri0; /* 0x100 Channel 0 Priority */
u8 dchpri1; /* 0x101 Channel 1 Priority */
u8 dchpri2; /* 0x102 Channel 2 Priority */
u8 dchpri3; /* 0x103 Channel 3 Priority */
u8 dchpri4; /* 0x104 Channel 4 Priority */
u8 dchpri5; /* 0x105 Channel 5 Priority */
u8 dchpri6; /* 0x106 Channel 6 Priority */
u8 dchpri7; /* 0x107 Channel 7 Priority */
u8 dchpri8; /* 0x108 Channel 8 Priority */
u8 dchpri9; /* 0x109 Channel 9 Priority */
u8 dchpri10; /* 0x110 Channel 10 Priority */
u8 dchpri11; /* 0x111 Channel 11 Priority */
u8 dchpri12; /* 0x112 Channel 12 Priority */
u8 dchpri13; /* 0x113 Channel 13 Priority */
u8 dchpri14; /* 0x114 Channel 14 Priority */
u8 dchpri15; /* 0x115 Channel 15 Priority */
} edma_t;
/* TCD - eDMA*/
typedef struct tcd_ctrl {
u32 saddr; /* 0x00 Source Address */
u16 attr; /* 0x04 Transfer Attributes */
u16 soff; /* 0x06 Signed Source Address Offset */
u32 nbytes; /* 0x08 Minor Byte Count */
u32 slast; /* 0x0C Last Source Address Adjustment */
u32 daddr; /* 0x10 Destination address */
u16 citer; /* 0x14 Cur Minor Loop Link, Major Loop Cnt */
u16 doff; /* 0x16 Signed Destination Address Offset */
u32 dlast_sga; /* 0x18 Last Dest Adr Adj/Scatter Gather Adr */
u16 biter; /* 0x1C Minor Loop Lnk, Major Loop Cnt */
u16 csr; /* 0x1E Control and Status */
} tcd_st;
typedef struct tcd_multiple {
tcd_st tcd[16];
} tcd_t;
/* Bit definitions and macros for EPPAR */
#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
#define EPORT_EPPAR_LEVEL (0)
#define EPORT_EPPAR_RISING (1)
#define EPORT_EPPAR_FALLING (2)
#define EPORT_EPPAR_BOTH (3)
#define EPORT_EPPAR_EPPA7_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA7_RISING (0x4000)
#define EPORT_EPPAR_EPPA7_FALLING (0x8000)
#define EPORT_EPPAR_EPPA7_BOTH (0xC000)
#define EPORT_EPPAR_EPPA6_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA6_RISING (0x1000)
#define EPORT_EPPAR_EPPA6_FALLING (0x2000)
#define EPORT_EPPAR_EPPA6_BOTH (0x3000)
#define EPORT_EPPAR_EPPA5_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA5_RISING (0x0400)
#define EPORT_EPPAR_EPPA5_FALLING (0x0800)
#define EPORT_EPPAR_EPPA5_BOTH (0x0C00)
#define EPORT_EPPAR_EPPA4_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA4_RISING (0x0100)
#define EPORT_EPPAR_EPPA4_FALLING (0x0200)
#define EPORT_EPPAR_EPPA4_BOTH (0x0300)
#define EPORT_EPPAR_EPPA3_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA3_RISING (0x0040)
#define EPORT_EPPAR_EPPA3_FALLING (0x0080)
#define EPORT_EPPAR_EPPA3_BOTH (0x00C0)
#define EPORT_EPPAR_EPPA2_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA2_RISING (0x0010)
#define EPORT_EPPAR_EPPA2_FALLING (0x0020)
#define EPORT_EPPAR_EPPA2_BOTH (0x0030)
#define EPORT_EPPAR_EPPA1_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA1_RISING (0x0004)
#define EPORT_EPPAR_EPPA1_FALLING (0x0008)
#define EPORT_EPPAR_EPPA1_BOTH (0x000C)
/* Bit definitions and macros for EPDDR */
#define EPORT_EPDDR_EPDD1 (0x02)
#define EPORT_EPDDR_EPDD2 (0x04)
#define EPORT_EPDDR_EPDD3 (0x08)
#define EPORT_EPDDR_EPDD4 (0x10)
#define EPORT_EPDDR_EPDD5 (0x20)
#define EPORT_EPDDR_EPDD6 (0x40)
#define EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for EPIER */
#define EPORT_EPIER_EPIE1 (0x02)
#define EPORT_EPIER_EPIE2 (0x04)
#define EPORT_EPIER_EPIE3 (0x08)
#define EPORT_EPIER_EPIE4 (0x10)
#define EPORT_EPIER_EPIE5 (0x20)
#define EPORT_EPIER_EPIE6 (0x40)
#define EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for EPDR */
#define EPORT_EPDR_EPD1 (0x02)
#define EPORT_EPDR_EPD2 (0x04)
#define EPORT_EPDR_EPD3 (0x08)
#define EPORT_EPDR_EPD4 (0x10)
#define EPORT_EPDR_EPD5 (0x20)
#define EPORT_EPDR_EPD6 (0x40)
#define EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for EPPDR */
#define EPORT_EPPDR_EPPD1 (0x02)
#define EPORT_EPPDR_EPPD2 (0x04)
#define EPORT_EPPDR_EPPD3 (0x08)
#define EPORT_EPPDR_EPPD4 (0x10)
#define EPORT_EPPDR_EPPD5 (0x20)
#define EPORT_EPPDR_EPPD6 (0x40)
#define EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for EPFR */
#define EPORT_EPFR_EPF1 (0x02)
#define EPORT_EPFR_EPF2 (0x04)
#define EPORT_EPFR_EPF3 (0x08)
#define EPORT_EPFR_EPF4 (0x10)
#define EPORT_EPFR_EPF5 (0x20)
#define EPORT_EPFR_EPF6 (0x40)
#define EPORT_EPFR_EPF7 (0x80)
#endif /* __EDMA_H__ */

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/*
* Edge Port Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EPORT_H__
#define __EPORT_H__
/* Edge Port Module (EPORT) */
typedef struct eport {
#ifdef CONFIG_MCF547x_8x
u16 par; /* 0x00 */
u16 res0; /* 0x02 */
u8 ddr; /* 0x04 */
u8 ier; /* 0x05 */
u16 res1; /* 0x06 */
u8 dr; /* 0x08 */
u8 pdr; /* 0x09 */
u16 res2; /* 0x0A */
u8 fr; /* 0x0C */
u8 res3[3]; /* 0x0D */
#else
u16 par; /* 0x00 Pin Assignment */
u8 ddr; /* 0x02 Data Direction */
u8 ier; /* 0x03 Interrupt Enable */
u8 dr; /* 0x04 Data */
u8 pdr; /* 0x05 Pin Data */
u8 fr; /* 0x06 Flag */
u8 res0;
#endif
} eport_t;
/* EPPAR */
#define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2)
#define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4)
#define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6)
#define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8)
#define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10)
#define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12)
#define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14)
#define EPORT_PAR_LEVEL (0)
#define EPORT_PAR_RISING (1)
#define EPORT_PAR_FALLING (2)
#define EPORT_PAR_BOTH (3)
#define EPORT_PAR_EPPA7_LEVEL (0x0000)
#define EPORT_PAR_EPPA7_RISING (0x4000)
#define EPORT_PAR_EPPA7_FALLING (0x8000)
#define EPORT_PAR_EPPA7_BOTH (0xC000)
#define EPORT_PAR_EPPA6_LEVEL (0x0000)
#define EPORT_PAR_EPPA6_RISING (0x1000)
#define EPORT_PAR_EPPA6_FALLING (0x2000)
#define EPORT_PAR_EPPA6_BOTH (0x3000)
#define EPORT_PAR_EPPA5_LEVEL (0x0000)
#define EPORT_PAR_EPPA5_RISING (0x0400)
#define EPORT_PAR_EPPA5_FALLING (0x0800)
#define EPORT_PAR_EPPA5_BOTH (0x0C00)
#define EPORT_PAR_EPPA4_LEVEL (0x0000)
#define EPORT_PAR_EPPA4_RISING (0x0100)
#define EPORT_PAR_EPPA4_FALLING (0x0200)
#define EPORT_PAR_EPPA4_BOTH (0x0300)
#define EPORT_PAR_EPPA3_LEVEL (0x0000)
#define EPORT_PAR_EPPA3_RISING (0x0040)
#define EPORT_PAR_EPPA3_FALLING (0x0080)
#define EPORT_PAR_EPPA3_BOTH (0x00C0)
#define EPORT_PAR_EPPA2_LEVEL (0x0000)
#define EPORT_PAR_EPPA2_RISING (0x0010)
#define EPORT_PAR_EPPA2_FALLING (0x0020)
#define EPORT_PAR_EPPA2_BOTH (0x0030)
#define EPORT_PAR_EPPA1_LEVEL (0x0000)
#define EPORT_PAR_EPPA1_RISING (0x0004)
#define EPORT_PAR_EPPA1_FALLING (0x0008)
#define EPORT_PAR_EPPA1_BOTH (0x000C)
/* EPDDR */
#define EPORT_DDR_EPDD1 (0x02)
#define EPORT_DDR_EPDD2 (0x04)
#define EPORT_DDR_EPDD3 (0x08)
#define EPORT_DDR_EPDD4 (0x10)
#define EPORT_DDR_EPDD5 (0x20)
#define EPORT_DDR_EPDD6 (0x40)
#define EPORT_DDR_EPDD7 (0x80)
/* EPIER */
#define EPORT_IER_EPIE1 (0x02)
#define EPORT_IER_EPIE2 (0x04)
#define EPORT_IER_EPIE3 (0x08)
#define EPORT_IER_EPIE4 (0x10)
#define EPORT_IER_EPIE5 (0x20)
#define EPORT_IER_EPIE6 (0x40)
#define EPORT_IER_EPIE7 (0x80)
/* EPDR */
#define EPORT_DR_EPD1 (0x02)
#define EPORT_DR_EPD2 (0x04)
#define EPORT_DR_EPD3 (0x08)
#define EPORT_DR_EPD4 (0x10)
#define EPORT_DR_EPD5 (0x20)
#define EPORT_DR_EPD6 (0x40)
#define EPORT_DR_EPD7 (0x80)
/* EPPDR */
#define EPORT_PDR_EPPD1 (0x02)
#define EPORT_PDR_EPPD2 (0x04)
#define EPORT_PDR_EPPD3 (0x08)
#define EPORT_PDR_EPPD4 (0x10)
#define EPORT_PDR_EPPD5 (0x20)
#define EPORT_PDR_EPPD6 (0x40)
#define EPORT_PDR_EPPD7 (0x80)
/* EPFR */
#define EPORT_FR_EPF1 (0x02)
#define EPORT_FR_EPF2 (0x04)
#define EPORT_FR_EPF3 (0x08)
#define EPORT_FR_EPF4 (0x10)
#define EPORT_FR_EPF5 (0x20)
#define EPORT_FR_EPF6 (0x40)
#define EPORT_FR_EPF7 (0x80)
#endif /* __EPORT_H__ */

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/*
* FlexBus Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FLEXBUS_H
#define __FLEXBUS_H
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
#ifdef CONFIG_M5235
typedef struct fbcs {
u16 csar0; /* Chip-select Address */
u16 res1;
u32 csmr0; /* Chip-select Mask */
u16 res2;
u16 cscr0; /* Chip-select Control */
u16 csar1;
u16 res3;
u32 csmr1;
u16 res4;
u16 cscr1;
u16 csar2;
u16 res5;
u32 csmr2;
u16 res6;
u16 cscr2;
u16 csar3;
u16 res7;
u32 csmr3;
u16 res8;
u16 cscr3;
u16 csar4;
u16 res9;
u32 csmr4;
u16 res10;
u16 cscr4;
u16 csar5;
u16 res11;
u32 csmr5;
u16 res12;
u16 cscr5;
u16 csar6;
u16 res13;
u32 csmr6;
u16 res14;
u16 cscr6;
u16 csar7;
u16 res15;
u32 csmr7;
u16 res16;
u16 cscr7;
} fbcs_t;
#else
typedef struct fbcs {
u32 csar0; /* Chip-select Address */
u32 csmr0; /* Chip-select Mask */
u32 cscr0; /* Chip-select Control */
u32 csar1;
u32 csmr1;
u32 cscr1;
u32 csar2;
u32 csmr2;
u32 cscr2;
u32 csar3;
u32 csmr3;
u32 cscr3;
u32 csar4;
u32 csmr4;
u32 cscr4;
u32 csar5;
u32 csmr5;
u32 cscr5;
u32 csar6;
u32 csmr6;
u32 cscr6;
u32 csar7;
u32 csmr7;
u32 cscr7;
} fbcs_t;
#endif
#define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000)
#define FBCS_CSMR_BAM(x) (((x) & 0xFFFF) << 16)
#define FBCS_CSMR_BAM_MASK (0x0000FFFF)
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define FBCS_CSMR_BAM_512M (0x1FFF0000)
#define FBCS_CSMR_BAM_256M (0x0FFF0000)
#define FBCS_CSMR_BAM_128M (0x07FF0000)
#define FBCS_CSMR_BAM_64M (0x03FF0000)
#define FBCS_CSMR_BAM_32M (0x01FF0000)
#define FBCS_CSMR_BAM_16M (0x00FF0000)
#define FBCS_CSMR_BAM_8M (0x007F0000)
#define FBCS_CSMR_BAM_4M (0x003F0000)
#define FBCS_CSMR_BAM_2M (0x001F0000)
#define FBCS_CSMR_BAM_1M (0x000F0000)
#define FBCS_CSMR_BAM_1024K (0x000F0000)
#define FBCS_CSMR_BAM_512K (0x00070000)
#define FBCS_CSMR_BAM_256K (0x00030000)
#define FBCS_CSMR_BAM_128K (0x00010000)
#define FBCS_CSMR_BAM_64K (0x00000000)
#ifdef CONFIG_M5249
#define FBCS_CSMR_WP (0x00000080)
#define FBCS_CSMR_AM (0x00000040)
#define FBCS_CSMR_CI (0x00000020)
#define FBCS_CSMR_SC (0x00000010)
#define FBCS_CSMR_SD (0x00000008)
#define FBCS_CSMR_UC (0x00000004)
#define FBCS_CSMR_UD (0x00000002)
#else
#define FBCS_CSMR_WP (0x00000100)
#endif
#define FBCS_CSMR_V (0x00000001) /* Valid bit */
#ifdef CONFIG_M5235
#define FBCS_CSCR_SRWS(x) (((x) & 0x3) << 14)
#define FBCS_CSCR_IWS(x) (((x) & 0xF) << 10)
#define FBCS_CSCR_AA_ON (1 << 8)
#define FBCS_CSCR_AA_OFF (0 << 8)
#define FBCS_CSCR_PS_32 (0 << 6)
#define FBCS_CSCR_PS_16 (2 << 6)
#define FBCS_CSCR_PS_8 (1 << 6)
#define FBCS_CSCR_BEM_ON (1 << 5)
#define FBCS_CSCR_BEM_OFF (0 << 5)
#define FBCS_CSCR_BSTR_ON (1 << 4)
#define FBCS_CSCR_BSTR_OFF (0 << 4)
#define FBCS_CSCR_BSTW_ON (1 << 3)
#define FBCS_CSCR_BSTW_OFF (0 << 3)
#define FBCS_CSCR_SWWS(x) (((x) & 0x7) << 0)
#else
#define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26)
#define FBCS_CSCR_SWS_MASK (0x03FFFFFF)
#define FBCS_CSCR_SWSEN (0x00800000)
#define FBCS_CSCR_ASET(x) (((x) & 0x03) << 20)
#define FBCS_CSCR_ASET_MASK (0xFFCFFFFF)
#define FBCS_CSCR_RDAH(x) (((x) & 0x03) << 18)
#define FBCS_CSCR_RDAH_MASK (0xFFF3FFFF)
#define FBCS_CSCR_WRAH(x) (((x) & 0x03) << 16)
#define FBCS_CSCR_WRAH_MASK (0xFFFCFFFF)
#define FBCS_CSCR_WS(x) (((x) & 0x3F) << 10)
#define FBCS_CSCR_WS_MASK (0xFFFF03FF)
#define FBCS_CSCR_SBM (0x00000200)
#define FBCS_CSCR_AA (0x00000100)
#define FBCS_CSCR_PS(x) (((x) & 0x03) << 6)
#define FBCS_CSCR_PS_MASK (0xFFFFFF3F)
#define FBCS_CSCR_BEM (0x00000020)
#define FBCS_CSCR_BSTR (0x00000010)
#define FBCS_CSCR_BSTW (0x00000008)
#define FBCS_CSCR_PS_16 (0x00000080)
#define FBCS_CSCR_PS_8 (0x00000040)
#define FBCS_CSCR_PS_32 (0x00000000)
#endif
#endif /* __FLEXBUS_H */

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/*
* Flex CAN Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FLEXCAN_H__
#define __FLEXCAN_H__
/* FlexCan Message Buffer */
typedef struct can_msgbuf_ctrl {
#ifdef CONFIG_M5282
u8 tmstamp; /* 0x00 Timestamp */
u8 ctrl; /* 0x01 Control */
u16 idh; /* 0x02 ID High */
u16 idl; /* 0x04 ID High */
u8 data[8]; /* 0x06 8 Byte Data Field */
u16 res; /* 0x0E */
#else
u16 ctrl; /* 0x00 Control/Status */
u16 tmstamp; /* 0x02 Timestamp */
u32 id; /* 0x04 Identifier */
u8 data[8]; /* 0x08 8 Byte Data Field */
#endif
} can_msg_t;
#ifdef CONFIG_M5282
/* MSGBUF CTRL */
#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x0F) << 4)
#define CAN_MSGBUF_CTRL_CODE_MASK (0x0F)
#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x0F)
#define CAN_MSGBUF_CTRL_LEN_MASK (0xF0)
/* MSGBUF ID */
#define CAN_MSGBUF_IDH_STD(x) (((x) & 0x07FF) << 5)
#define CAN_MSGBUF_IDH_STD_MASK (0xE003FFFF)
#define CAN_MSGBUF_IDH_SRR (0x0010)
#define CAN_MSGBUF_IDH_IDE (0x0080)
#define CAN_MSGBUF_IDH_EXTH(x) ((x) & 0x07)
#define CAN_MSGBUF_IDH_EXTH_MASK (0xFFF8)
#define CAN_MSGBUF_IDL_EXTL(x) (((x) & 0x7FFF) << 1)
#define CAN_MSGBUF_IDL_EXTL_MASK (0xFFFE)
#define CAN_MSGBUF_IDL_RTR (0x0001)
#else
/* MSGBUF CTRL */
#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x000F) << 8)
#define CAN_MSGBUF_CTRL_CODE_MASK (0xF0FF)
#define CAN_MSGBUF_CTRL_SRR (0x0040)
#define CAN_MSGBUF_CTRL_IDE (0x0020)
#define CAN_MSGBUF_CTRL_RTR (0x0010)
#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x000F)
#define CAN_MSGBUF_CTRL_LEN_MASK (0xFFF0)
/* MSGBUF ID */
#define CAN_MSGBUF_ID_STD(x) (((x) & 0x000007FF) << 18)
#define CAN_MSGBUF_ID_STD_MASK (0xE003FFFF)
#define CAN_MSGBUF_ID_EXT(x) ((x) & 0x0003FFFF)
#define CAN_MSGBUF_ID_EXT_MASK (0xFFFC0000)
#endif
/* FlexCan module */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration */
u32 ctrl; /* 0x04 Control */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmsk; /* 0x10 Rx Global Mask */
u32 rx14msk; /* 0x14 RxBuffer 14 Mask */
u32 rx15msk; /* 0x18 RxBuffer 15 Mask */
#ifdef CONFIG_M5282
u32 res2; /* 0x1C */
u16 errstat; /* 0x20 Error and status */
u16 imsk; /* 0x22 Interrupt Mask */
u16 iflag; /* 0x24 Interrupt Flag */
u16 errcnt; /* 0x26 Error Counter */
u32 res3[3]; /* 0x28 - 0x33 */
#else
u16 res2; /* 0x1C */
u16 errcnt; /* 0x1E Error Counter */
u16 res3; /* 0x20 */
u16 errstat; /* 0x22 Error and status */
u32 res4; /* 0x24 */
u32 imsk; /* 0x28 Interrupt Mask */
u32 res5; /* 0x2C */
u16 iflag; /* 0x30 Interrupt Flag */
#endif
u32 res6[19]; /* 0x34 - 0x7F */
void *msgbuf; /* 0x80 Message Buffer 0-15 */
} can_t;
/* MCR */
#define CAN_MCR_MDIS (0x80000000)
#define CAN_MCR_FRZ (0x40000000)
#define CAN_MCR_HALT (0x10000000)
#define CAN_MCR_NORDY (0x08000000)
#define CAN_MCF_WAKEMSK (0x04000000) /* 5282 */
#define CAN_MCR_SOFTRST (0x02000000)
#define CAN_MCR_FRZACK (0x01000000)
#define CAN_MCR_SUPV (0x00800000)
#define CAN_MCR_SELFWAKE (0x00400000) /* 5282 */
#define CAN_MCR_APS (0x00200000) /* 5282 */
#define CAN_MCR_LPMACK (0x00100000)
#define CAN_MCF_BCC (0x00010000)
#define CAN_MCR_MAXMB(x) ((x) & 0x0F)
#define CAN_MCR_MAXMB_MASK (0xFFFFFFF0)
/* CTRL */
#define CAN_CTRL_PRESDIV(x) (((x) & 0xFF) << 24)
#define CAN_CTRL_PRESDIV_MASK (0x00FFFFFF)
#define CAN_CTRL_RJW(x) (((x) & 0x03) << 22)
#define CAN_CTRL_RJW_MASK (0xFF3FFFFF)
#define CAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
#define CAN_CTRL_PSEG1_MASK (0xFFC7FFFF)
#define CAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
#define CAN_CTRL_PSEG2_MASK (0xFFF8FFFF)
#define CAN_CTRL_BOFFMSK (0x00008000)
#define CAN_CTRL_ERRMSK (0x00004000)
#define CAN_CTRL_CLKSRC (0x00002000)
#define CAN_CTRL_LPB (0x00001000)
#define CAN_CTRL_RXMODE (0x00000400) /* 5282 */
#define CAN_CTRL_TXMODE(x) (((x) & 0x03) << 8) /* 5282 */
#define CAN_CTRL_TXMODE_MASK (0xFFFFFCFF) /* 5282 */
#define CAN_CTRL_TXMODE_CAN0 (0x00000000) /* 5282 */
#define CAN_CTRL_TXMODE_CAN1 (0x00000100) /* 5282 */
#define CAN_CTRL_TXMODE_OPEN (0x00000200) /* 5282 */
#define CAN_CTRL_SMP (0x00000080)
#define CAN_CTRL_BOFFREC (0x00000040)
#define CAN_CTRL_TSYNC (0x00000020)
#define CAN_CTRL_LBUF (0x00000010)
#define CAN_CTRL_LOM (0x00000008)
#define CAN_CTRL_PROPSEG(x) ((x) & 0x07)
#define CAN_CTRL_PROPSEG_MASK (0xFFFFFFF8)
/* TIMER */
/* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */
#define CAN_TIMER(x) ((x) & 0xFFFF)
#define CAN_TIMER_MASK (0xFFFF0000)
/* RXGMASK */
#ifdef CONFIG_M5282
#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 21)
#define CAN_RXGMSK_MI_STD_MASK (0x001FFFFF)
#define CAN_RXGMSK_MI_EXT(x) (((x) & 0x0003FFFF) << 1)
#define CAN_RXGMSK_MI_EXT_MASK (0xFFF80001)
#else
#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 18)
#define CAN_RXGMSK_MI_STD_MASK (0xE003FFFF)
#define CAN_RXGMSK_MI_EXT(x) ((x) & 0x0003FFFF)
#define CAN_RXGMSK_MI_EXT_MASK (0xFFFC0000)
#endif
/* ERRCNT */
#define CAN_ERRCNT_RXECTR(x) (((x) & 0xFF) << 8)
#define CAN_ERRCNT_RXECTR_MASK (0x00FF)
#define CAN_ERRCNT_TXECTR(x) ((x) & 0xFF)
#define CAN_ERRCNT_TXECTR_MASK (0xFF00)
/* ERRSTAT */
#define CAN_ERRSTAT_BITERR1 (0x8000)
#define CAN_ERRSTAT_BITERR0 (0x4000)
#define CAN_ERRSTAT_ACKERR (0x2000)
#define CAN_ERRSTAT_CRCERR (0x1000)
#define CAN_ERRSTAT_FRMERR (0x0800)
#define CAN_ERRSTAT_STFERR (0x0400)
#define CAN_ERRSTAT_TXWRN (0x0200)
#define CAN_ERRSTAT_RXWRN (0x0100)
#define CAN_ERRSTAT_IDLE (0x0080)
#define CAN_ERRSTAT_TXRX (0x0040)
#define CAN_ERRSTAT_FLT_MASK (0xFFCF)
#define CAN_ERRSTAT_FLT_BUSOFF (0x0020)
#define CAN_ERRSTAT_FLT_PASSIVE (0x0010)
#define CAN_ERRSTAT_FLT_ACTIVE (0x0000)
#ifdef CONFIG_M5282
#define CAN_ERRSTAT_BOFFINT (0x0004)
#define CAN_ERRSTAT_ERRINT (0x0002)
#else
#define CAN_ERRSTAT_ERRINT (0x0004)
#define CAN_ERRSTAT_BOFFINT (0x0002)
#define CAN_ERRSTAT_WAKEINT (0x0001)
#endif
/* IMASK */
#ifdef CONFIG_M5253
#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFFFFFF))
#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
#else
#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFF))
#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
#endif
/* IFLAG */
#ifdef CONFIG_M5253
#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFFFFFF))
#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
#else
#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFF))
#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
#endif
#endif /* __FLEXCAN_H__ */

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/*
* Interrupt Controller Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __INTCTRL_H__
#define __INTCTRL_H__
#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
defined(CONFIG_M547x) || defined(CONFIG_M548x)
# define CONFIG_SYS_CF_INTC_REG1
#endif
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending High */
u32 iprl0; /* 0x04 Pending Low */
u32 imrh0; /* 0x08 Mask High */
u32 imrl0; /* 0x0C Mask Low */
u32 frch0; /* 0x10 Force High */
u32 frcl0; /* 0x14 Force Low */
#if defined(CONFIG_SYS_CF_INTC_REG1)
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
#else
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
#endif
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt ack */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 L1iack0; /* 0xE4 Level n interrupt ack */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 L2iack0; /* 0xE8 Level n interrupt ack */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 L3iack0; /* 0xEC Level n interrupt ack */
u8 res7[3]; /* 0xED - 0xEF */
u8 L4iack0; /* 0xF0 Level n interrupt ack */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 L5iack0; /* 0xF4 Level n interrupt ack */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 L6iack0; /* 0xF8 Level n interrupt ack */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 L7iack0; /* 0xFC Level n interrupt ack */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending High */
u32 iprl1; /* 0x04 Pending Low */
u32 imrh1; /* 0x08 Mask High */
u32 imrl1; /* 0x0C Mask Low */
u32 frch1; /* 0x10 Force High */
u32 frcl1; /* 0x14 Force Low */
#if defined(CONFIG_SYS_CF_INTC_REG1)
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
#else
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
#endif
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt ack */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 L1iack1; /* 0xE4 Level n interrupt ack */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 L2iack1; /* 0xE8 Level n interrupt ack */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 L3iack1; /* 0xEC Level n interrupt ack */
u8 res8[3]; /* 0xED - 0xEF */
u8 L4iack1; /* 0xF0 Level n interrupt ack */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 L5iack1; /* 0xF4 Level n interrupt ack */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 L6iack1; /* 0xF8 Level n interrupt ack */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 L7iack1; /* 0xFC Level n interrupt ack */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0x00 Global Software Interrupt ack */
u8 res0[0x3];
u8 gl1iack; /* 0x04 */
u8 resv1[0x3];
u8 gl2iack; /* 0x08 */
u8 res2[0x3];
u8 gl3iack; /* 0x0C */
u8 res3[0x3];
u8 gl4iack; /* 0x10 */
u8 res4[0x3];
u8 gl5iack; /* 0x14 */
u8 res5[0x3];
u8 gl6iack; /* 0x18 */
u8 res6[0x3];
u8 gl7iack; /* 0x1C */
u8 res7[0x3];
} intgack_t;
#define INTC_IPRH_INT63 (0x80000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT32 (0x00000001)
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
#define INTC_IMRLn_MASKALL (0x00000001)
#define INTC_IRLR(x) (((x) & 0x7F) << 1)
#define INTC_IRLR_MASK (0x01)
#define INTC_IACKLPR_LVL(x) (((x) & 0x07) << 4)
#define INTC_IACKLPR_LVL_MASK (0x8F)
#define INTC_IACKLPR_PRI(x) ((x) & 0x0F)
#define INTC_IACKLPR_PRI_MASK (0xF0)
#if defined(CONFIG_SYS_CF_INTC_REG1)
#define INTC_ICR_IL(x) (((x) & 0x07) << 3)
#define INTC_ICR_IL_MASK (0xC7)
#define INTC_ICR_IP(x) ((x) & 0x07)
#define INTC_ICR_IP_MASK (0xF8)
#else
#define INTC_ICR_IL(x) ((x) & 0x07)
#define INTC_ICR_IL_MASK (0xF8)
#endif
#define INTC_ICONFIG_ELVLPRI_MASK (0x01FF)
#define INTC_ICONFIG_ELVLPRI7 (0x8000)
#define INTC_ICONFIG_ELVLPRI6 (0x4000)
#define INTC_ICONFIG_ELVLPRI5 (0x2000)
#define INTC_ICONFIG_ELVLPRI4 (0x1000)
#define INTC_ICONFIG_ELVLPRI3 (0x0800)
#define INTC_ICONFIG_ELVLPRI2 (0x0400)
#define INTC_ICONFIG_ELVLPRI1 (0x0200)
#define INTC_ICONFIG_EMASK (0x0020)
#define INTC_SIMR_ALL (0x40)
#define INTC_SIMR(x) ((x) & 0x3F)
#define INTC_SIMR_MASK (0x80)
#define INTC_CIMR_ALL (0x40)
#define INTC_CIMR(x) ((x) & 0x3F)
#define INTC_CIMR_MASK (0x80)
#define INTC_CLMASK(x) ((x) & 0x0F)
#define INTC_CLMASK_MASK (0xF0)
#define INTC_SLMASK(x) ((x) & 0x0F)
#define INTC_SLMASK_MASK (0xF0)
#endif /* __INTCTRL_H__ */

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/*
* LCD controller Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LCDC_H__
#define __LCDC_H__
/* LCD module registers */
typedef struct lcd_ctrl {
u32 ssar; /* 0x00 Screen Start Address Register */
u32 sr; /* 0x04 LCD Size Register */
u32 vpw; /* 0x08 Virtual Page Width Register */
u32 cpr; /* 0x0C Cursor Position Register */
u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
u32 ccmr; /* 0x14 Color Cursor Mapping Register */
u32 pcr; /* 0x18 Panel Configuration Register */
u32 hcr; /* 0x1C Horizontal Configuration Register */
u32 vcr; /* 0x20 Vertical Configuration Register */
u32 por; /* 0x24 Panning Offset Register */
u32 scr; /* 0x28 Sharp Configuration Register */
u32 pccr; /* 0x2C PWM Contrast Control Register */
u32 dcr; /* 0x30 DMA Control Register */
u32 rmcr; /* 0x34 Refresh Mode Control Register */
u32 icr; /* 0x38 Refresh Mode Control Register */
u32 ier; /* 0x3C Interrupt Enable Register */
u32 isr; /* 0x40 Interrupt Status Register */
u32 res[4];
u32 gwsar; /* 0x50 Graphic Window Start Address Register */
u32 gwsr; /* 0x54 Graphic Window Size Register */
u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */
u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */
u32 gwpr; /* 0x60 Graphic Window Position Register */
u32 gwcr; /* 0x64 Graphic Window Control Register */
u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */
} lcd_t;
typedef struct lcdbg_ctrl {
u32 bglut[255];
} lcdbg_t;
typedef struct lcdgw_ctrl {
u32 gwlut[255];
} lcdgw_t;
/* Bit definitions and macros for LCDC_LSSAR */
#define LCDC_SSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for LCDC_LSR */
#define LCDC_SR_XMAX(x) (((x)&0x0000003F)<<20)
#define LCDC_SR_YMAX(x) ((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LVPWR */
#define LCDC_VPWR_VPW(x) (((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LCPR */
#define LCDC_CPR_CC(x) (((x)&0x00000003)<<30)
#define LCDC_CPR_CC_AND (0xC0000000)
#define LCDC_CPR_CC_XOR (0x80000000)
#define LCDC_CPR_CC_OR (0x40000000)
#define LCDC_CPR_CC_TRANSPARENT (0x00000000)
#define LCDC_CPR_OP (0x10000000)
#define LCDC_CPR_CXP(x) (((x)&0x000003FF)<<16)
#define LCDC_CPR_CYP(x) ((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LCWHBR */
#define LCDC_CWHBR_BK_EN (0x80000000)
#define LCDC_CWHBR_CW(x) (((x)&0x0000001F)<<24)
#define LCDC_CWHBR_CH(x) (((x)&0x0000001F)<<16)
#define LCDC_CWHBR_BD(x) ((x)&0x000000FF)
/* Bit definitions and macros for LCDC_LCCMR */
#define LCDC_CCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
#define LCDC_CCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
#define LCDC_CCMR_CUR_COL_B(x) ((x)&0x0000003F)
/* Bit definitions and macros for LCDC_LPCR */
#define LCDC_PCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
#define LCDC_PCR_MODE_TFT (0xC0000000)
#define LCDC_PCR_MODE_CSTN (0x40000000)
#define LCDC_PCR_MODE_MONOCHROME (0x00000000)
#define LCDC_PCR_TFT (0x80000000)
#define LCDC_PCR_COLOR (0x40000000)
#define LCDC_PCR_PBSIZ(x) (((x)&0x00000003)<<28)
#define LCDC_PCR_PBSIZ_8 (0x30000000)
#define LCDC_PCR_PBSIZ_4 (0x20000000)
#define LCDC_PCR_PBSIZ_2 (0x10000000)
#define LCDC_PCR_PBSIZ_1 (0x00000000)
#define LCDC_PCR_BPIX(x) (((x)&0x00000007)<<25)
#define LCDC_PCR_BPIX_18bpp (0x0C000000)
#define LCDC_PCR_BPIX_16bpp (0x0A000000)
#define LCDC_PCR_BPIX_12bpp (0x08000000)
#define LCDC_PCR_BPIX_8bpp (0x06000000)
#define LCDC_PCR_BPIX_4bpp (0x04000000)
#define LCDC_PCR_BPIX_2bpp (0x02000000)
#define LCDC_PCR_BPIX_1bpp (0x00000000)
#define LCDC_PCR_PIXPOL (0x01000000)
#define LCDC_PCR_FLM (0x00800000)
#define LCDC_PCR_LPPOL (0x00400000)
#define LCDC_PCR_CLKPOL (0x00200000)
#define LCDC_PCR_OEPOL (0x00100000)
#define LCDC_PCR_SCLKIDLE (0x00080000)
#define LCDC_PCR_ENDSEL (0x00040000)
#define LCDC_PCR_SWAP_SEL (0x00020000)
#define LCDC_PCR_REV_VS (0x00010000)
#define LCDC_PCR_ACDSEL (0x00008000)
#define LCDC_PCR_ACD(x) (((x)&0x0000007F)<<8)
#define LCDC_PCR_SCLKSEL (0x00000080)
#define LCDC_PCR_SHARP (0x00000040)
#define LCDC_PCR_PCD(x) ((x)&0x0000003F)
/* Bit definitions and macros for LCDC_LHCR */
#define LCDC_HCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
#define LCDC_HCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
#define LCDC_HCR_H_WAIT_2(x) ((x)&0x000000FF)
/* Bit definitions and macros for LCDC_LVCR */
#define LCDC_VCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
#define LCDC_VCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
#define LCDC_VCR_V_WAIT_2(x) ((x)&0x000000FF)
/* Bit definitions and macros for LCDC_SCR */
#define LCDC_SCR_PS_R_DELAY(x) (((x)&0x0000003F) << 26)
#define LCDC_SCR_CLS_R_DELAY(x) (((x)&0x000000FF) << 16)
#define LCDC_SCR_RTG_DELAY(x) (((x)&0x0000000F) << 8)
#define LCDC_SCR_GRAY2(x) (((x)&0x0000000F) << 4)
#define LCDC_SCR_GRAY1(x) ((x)&&0x0000000F)
/* Bit definitions and macros for LCDC_LPCCR */
#define LCDC_PCCR_CLS_HI_WID(x) (((x)&0x000001FF)<<16)
#define LCDC_PCCR_LDMSK (0x00008000)
#define LCDC_PCCR_SCR(x) (((x)&0x00000003)<<9)
#define LCDC_PCCR_SCR_LCDCLK (0x00000400)
#define LCDC_PCCR_SCR_PIXCLK (0x00000200)
#define LCDC_PCCR_SCR_LNPULSE (0x00000000)
#define LCDC_PCCR_CC_EN (0x00000100)
#define LCDC_PCCR_PW(x) ((x)&0x000000FF)
/* Bit definitions and macros for LCDC_LDCR */
#define LCDC_DCR_BURST (0x80000000)
#define LCDC_DCR_HM(x) (((x)&0x0000001F)<<16)
#define LCDC_DCR_TM(x) ((x)&0x0000001F)
/* Bit definitions and macros for LCDC_LRMCR */
#define LCDC_RMCR_SEL_REF (0x00000001)
/* Bit definitions and macros for LCDC_LICR */
#define LCDC_ICR_GW_INT_CON (0x00000010)
#define LCDC_ICR_INTSYN (0x00000004)
#define LCDC_ICR_INTCON (0x00000001)
/* Bit definitions and macros for LCDC_LIER */
#define LCDC_IER_GW_UDR (0x00000080)
#define LCDC_IER_GW_ERR (0x00000040)
#define LCDC_IER_GW_EOF (0x00000020)
#define LCDC_IER_GW_BOF (0x00000010)
#define LCDC_IER_UDR (0x00000008)
#define LCDC_IER_ERR (0x00000004)
#define LCDC_IER_EOF (0x00000002)
#define LCDC_IER_BOF (0x00000001)
/* Bit definitions and macros for LCDC_LGWSAR */
#define LCDC_GWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for LCDC_LGWSR */
#define LCDC_GWSR_GWW(x) (((x)&0x0000003F)<<20)
#define LCDC_GWSR_GWH(x) ((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LGWVPWR */
#define LCDC_GWVPWR_GWVPW(x) ((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LGWPOR */
#define LCDC_GWPOR_GWPO(x) ((x)&0x0000001F)
/* Bit definitions and macros for LCDC_LGWPR */
#define LCDC_GWPR_GWXP(x) (((x)&0x000003FF)<<16)
#define LCDC_GWPR_GWYP(x) ((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LGWCR */
#define LCDC_GWCR_GWAV(x) (((x)&0x000000FF)<<24)
#define LCDC_GWCR_GWCKE (0x00800000)
#define LCDC_LGWCR_GWE (0x00400000)
#define LCDC_LGWCR_GW_RVS (0x00200000)
#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
#define LCDC_LGWCR_GWCKB(x) ((x)&0x0000003F)
/* Bit definitions and macros for LCDC_LGWDCR */
#define LCDC_LGWDCR_GWBT (0x80000000)
#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
#define LCDC_LGWDCR_GWTM(x) ((x)&0x0000001F)
#endif /* __LCDC_H__ */

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u-boot/arch/m68k/include/asm/coldfire/mdha.h Normal file
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/*
* Message Digest Hardware Accelerator Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MDHA_H__
#define __MDHA_H__
/* Message Digest Hardware Accelerator */
typedef struct mdha_ctrl {
u32 mr; /* 0x00 MDHA Mode */
u32 cr; /* 0x04 Control */
u32 cmd; /* 0x08 Command */
u32 sr; /* 0x0C Status */
u32 isr; /* 0x10 Interrupt Status */
u32 imr; /* 0x14 Interrupt Mask */
u32 dsz; /* 0x1C Data Size */
u32 inp; /* 0x20 Input FIFO */
u32 res1[3]; /* 0x24 - 0x2F */
u32 mda0; /* 0x30 Message Digest AO */
u32 mdb0; /* 0x34 Message Digest BO */
u32 mdc0; /* 0x38 Message Digest CO */
u32 mdd0; /* 0x3C Message Digest DO */
u32 mde0; /* 0x40 Message Digest EO */
u32 mdsz; /* 0x44 Message Data Size */
u32 res[10]; /* 0x48 - 0x6F */
u32 mda1; /* 0x70 Message Digest A1 */
u32 mdb1; /* 0x74 Message Digest B1 */
u32 mdc1; /* 0x78 Message Digest C1 */
u32 mdd1; /* 0x7C Message Digest D1 */
u32 mde1; /* 0x80 Message Digest E1 */
} mdha_t;
#define MDHA_MR_SSL (0x00000400)
#define MDHA_MR_MACFUL (0x00000200)
#define MDHA_MR_SWAP (0x00000100)
#define MDHA_MR_OPAD (0x00000080)
#define MDHA_MR_IPAD (0x00000040)
#define MDHA_MR_INIT (0x00000020)
#define MDHA_MR_MAC(x) (((x) & 0x03) << 3)
#define MDHA_MR_MAC_MASK (0xFFFFFFE7)
#define MDHA_MR_MAC_EHMAC (0x00000010)
#define MDHA_MR_MAC_HMAC (0x00000008)
#define MDHA_MR_MAC_NONE (0x00000000)
#define MDHA_MR_PDATA (0x00000004)
#define MDHA_MR_ALG (0x00000001)
#define MDHA_CR_DMAL(x) (((x) & 0x1F) << 16) /* 532x */
#define MDHA_CR_DMAL_MASK (0xFFE0FFFF) /* 532x */
#define MDHA_CR_END (0x00000004) /* 532x */
#define MDHA_CR_DMA (0x00000002) /* 532x */
#define MDHA_CR_IE (0x00000001)
#define MDHA_CMD_GO (0x00000008)
#define MDHA_CMD_CI (0x00000004)
#define MDHA_CMD_RI (0x00000001)
#define MDHA_CMD_SWR (0x00000001)
#define MDHA_SR_IFL(x) (((x) & 0xFF) << 16)
#define MDHA_SR_IFL_MASK (0xFF00FFFF)
#define MDHA_SR_APD(x) (((x) & 0x7) << 13)
#define MDHA_SR_APD_MASK (0xFFFF1FFF)
#define MDHA_SR_FS(x) (((x) & 0x7) << 8)
#define MDHA_SR_FS_MASK (0xFFFFF8FF)
#define MDHA_SR_GNW (0x00000080)
#define MDHA_SR_HSH (0x00000040)
#define MDHA_SR_BUSY (0x00000010)
#define MDHA_SR_RD (0x00000008)
#define MDHA_SR_ERR (0x00000004)
#define MDHA_SR_DONE (0x00000002)
#define MDHA_SR_INT (0x00000001)
#define MDHA_ISR_DRL (0x00000400) /* 532x */
#define MDHA_ISR_GTDS (0x00000200)
#define MDHA_ISR_ERE (0x00000100)
#define MDHA_ISR_RMDP (0x00000080)
#define MDHA_ISR_DSE (0x00000020)
#define MDHA_ISR_IME (0x00000010)
#define MDHA_ISR_NEIF (0x00000004)
#define MDHA_ISR_IFO (0x00000001)
#endif /* __MDHA_H__ */

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u-boot/arch/m68k/include/asm/coldfire/pwm.h Normal file
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/*
* Pulse Width Modulation Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ATA_H__
#define __ATA_H__
/* Pulse Width Modulation (PWM) */
typedef struct pwm_ctrl {
#ifdef CONFIG_M5272
u8 cr0;
u8 res1[3];
u8 cr1;
u8 res2[3];
u8 cr2;
u8 res3[7];
u8 pwr0;
u8 res4[3];
u8 pwr1;
u8 res5[3];
u8 pwr2;
u8 res6[7];
#else
u8 en; /* 0x00 PWM Enable */
u8 pol; /* 0x01 Polarity */
u8 clk; /* 0x02 Clock Select */
u8 prclk; /* 0x03 Prescale Clock Select */
u8 cae; /* 0x04 Center Align Enable */
u8 ctl; /* 0x05 Control */
u16 res1; /* 0x06 - 0x07 */
u8 scla; /* 0x08 Scale A */
u8 sclb; /* 0x09 Scale B */
u16 res2; /* 0x0A - 0x0B */
#ifdef CONFIG_M5275
u8 cnt[4]; /* 0x0C Channel n Counter */
u16 res3; /* 0x10 - 0x11 */
u8 per[4]; /* 0x14 Channel n Period */
u16 res4; /* 0x16 - 0x17 */
u8 dty[4]; /* 0x18 Channel n Duty */
#else
u8 cnt[8]; /* 0x0C Channel n Counter */
u8 per[8]; /* 0x14 Channel n Period */
u8 dty[8]; /* 0x1C Channel n Duty */
u8 sdn; /* 0x24 Shutdown */
u8 res3[3]; /* 0x25 - 0x27 */
#endif /* CONFIG_M5275 */
#endif /* CONFIG_M5272 */
} pwm_t;
#ifdef CONFIG_M5272
#define PWM_CR_EN (0x80)
#define PWM_CR_FRC1 (0x40)
#define PWM_CR_LVL (0x20)
#define PWM_CR_CLKSEL(x) ((x) & 0x0F)
#define PWM_CR_CLKSEL_MASK (0xF0)
#else
#define PWM_EN_PWMEn(x) (1 << ((x) & 0x07))
#define PWM_EN_PWMEn_MASK (0xF0)
#define PWM_POL_PPOLn(x) (1 << ((x) & 0x07))
#define PWM_POL_PPOLn_MASK (0xF0)
#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
#define PWM_CLK_PCLKn_MASK (0xF0)
#define PWM_PRCLK_PCKB(x) (((x) & 0x07) << 4)
#define PWM_PRCLK_PCKB_MASK (0x8F)
#define PWM_PRCLK_PCKA(x) ((x) & 0x07)
#define PWM_PRCLK_PCKA_MASK (0xF8)
#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
#define PWM_CLK_PCLKn_MASK (0xF0)
#define PWM_CTL_CON67 (0x80)
#define PWM_CTL_CON45 (0x40)
#define PWM_CTL_CON23 (0x20)
#define PWM_CTL_CON01 (0x10)
#define PWM_CTL_PSWAR (0x08)
#define PWM_CTL_PFRZ (0x04)
#define PWM_SDN_IF (0x80)
#define PWM_SDN_IE (0x40)
#define PWM_SDN_RESTART (0x20)
#define PWM_SDN_LVL (0x10)
#define PWM_SDN_PWM7IN (0x04)
#define PWM_SDN_PWM7IL (0x02)
#define PWM_SDN_SDNEN (0x01)
#endif /* CONFIG_M5272 */
#endif /* __ATA_H__ */

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u-boot/arch/m68k/include/asm/coldfire/qspi.h Normal file
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/*
* Queue Serial Peripheral Interface Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __QSPI_H__
#define __QSPI_H__
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 mr; /* 0x00 Mode */
u16 res1;
u16 dlyr; /* 0x04 Delay */
u16 res2;
u16 wr; /* 0x08 Wrap */
u16 res3;
u16 ir; /* 0x0C Interrupt */
u16 res4;
u16 ar; /* 0x10 Address */
u16 res5;
u16 dr; /* 0x14 Data */
u16 res6;
} qspi_t;
/* MR */
#define QSPI_QMR_MSTR (0x8000)
#define QSPI_QMR_DOHIE (0x4000)
#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define QSPI_QMR_BITS_MASK (0xC3FF)
#define QSPI_QMR_BITS_8 (0x2000)
#define QSPI_QMR_BITS_9 (0x2400)
#define QSPI_QMR_BITS_10 (0x2800)
#define QSPI_QMR_BITS_11 (0x2C00)
#define QSPI_QMR_BITS_12 (0x3000)
#define QSPI_QMR_BITS_13 (0x3400)
#define QSPI_QMR_BITS_14 (0x3800)
#define QSPI_QMR_BITS_15 (0x3C00)
#define QSPI_QMR_BITS_16 (0x0000)
#define QSPI_QMR_CPOL (0x0200)
#define QSPI_QMR_CPHA (0x0100)
#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
#define QSPI_QMR_BAUD_MASK (0xFF00)
/* DLYR */
#define QSPI_QDLYR_SPE (0x8000)
#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define QSPI_QDLYR_QCD_MASK (0x80FF)
#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
#define QSPI_QDLYR_DTL_MASK (0xFF00)
/* WR */
#define QSPI_QWR_HALT (0x8000)
#define QSPI_QWR_WREN (0x4000)
#define QSPI_QWR_WRTO (0x2000)
#define QSPI_QWR_CSIV (0x1000)
#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define QSPI_QWR_ENDQP_MASK (0xF0FF)
#define QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
#define QSPI_QWR_CPTQP_MASK (0xFF0F)
#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
#define QSPI_QWR_NEWQP_MASK (0xFFF0)
/* IR */
#define QSPI_QIR_WCEFB (0x8000)
#define QSPI_QIR_ABRTB (0x4000)
#define QSPI_QIR_ABRTL (0x1000)
#define QSPI_QIR_WCEFE (0x0800)
#define QSPI_QIR_ABRTE (0x0400)
#define QSPI_QIR_SPIFE (0x0100)
#define QSPI_QIR_WCEF (0x0008)
#define QSPI_QIR_ABRT (0x0004)
#define QSPI_QIR_SPIF (0x0001)
/* AR */
#define QSPI_QAR_ADDR(x) ((x)&0x003F)
#define QSPI_QAR_ADDR_MASK (0xFFC0)
#define QSPI_QAR_TRANS (0x0000)
#define QSPI_QAR_RECV (0x0010)
#define QSPI_QAR_CMD (0x0020)
/* DR with RAM command word definitions */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
#define QSPI_QDR_DSCK (0x1000)
#define QSPI_QDR_QSPI_CS3 (0x0800)
#define QSPI_QDR_QSPI_CS2 (0x0400)
#define QSPI_QDR_QSPI_CS1 (0x0200)
#define QSPI_QDR_QSPI_CS0 (0x0100)
#endif /* __QSPI_H__ */

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u-boot/arch/m68k/include/asm/coldfire/rng.h Normal file
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/*
* RNG Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __RNG_H__
#define __RNG_H__
/* Random Number Generator */
typedef struct rng_ctrl {
u32 cr; /* 0x00 Control */
u32 sr; /* 0x04 Status */
u32 er; /* 0x08 Entropy */
u32 out; /* 0x0C Output FIFO */
} rng_t;
#define RNG_CR_SLM (0x00000010) /* Sleep mode - 5445x */
#define RNG_CR_CI (0x00000008) /* Clear interrupt */
#define RNG_CR_IM (0x00000004) /* Interrupt mask */
#define RNG_CR_HA (0x00000002) /* High assurance */
#define RNG_CR_GO (0x00000001) /* Go bit */
#define RNG_SR_OFS(x) (((x) & 0x000000FF) << 16)
#define RNG_SR_OFS_MASK (0xFF00FFFF)
#define RNG_SR_OFL(x) (((x) & 0x000000FF) << 8)
#define RNG_SR_OFL_MASK (0xFFFF00FF)
#define RNG_SR_EI (0x00000008)
#define RNG_SR_FUF (0x00000004)
#define RNG_SR_LRS (0x00000002)
#define RNG_SR_SV (0x00000001)
#endif /* __RNG_H__ */

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u-boot/arch/m68k/include/asm/coldfire/skha.h Normal file
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/*
* Symmetric Key Hardware Accelerator Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SKHA_H__
#define __SKHA_H__
typedef struct skha_ctrl {
u32 mr; /* 0x00 Mode */
u32 cr; /* 0x04 Control */
u32 cmr; /* 0x08 Command */
u32 sr; /* 0x0C Status */
u32 esr; /* 0x10 Error Status */
u32 emr; /* 0x14 Error Status Mask Register) */
u32 ksr; /* 0x18 Key Size */
u32 dsr; /* 0x1C Data Size */
u32 in; /* 0x20 Input FIFO */
u32 out; /* 0x24 Output FIFO */
u32 res1[2]; /* 0x28 - 0x2F */
u32 kdr1; /* 0x30 Key Data 1 */
u32 kdr2; /* 0x34 Key Data 2 */
u32 kdr3; /* 0x38 Key Data 3 */
u32 kdr4; /* 0x3C Key Data 4 */
u32 kdr5; /* 0x40 Key Data 5 */
u32 kdr6; /* 0x44 Key Data 6 */
u32 res2[10]; /* 0x48 - 0x6F */
u32 c1; /* 0x70 Context 1 */
u32 c2; /* 0x74 Context 2 */
u32 c3; /* 0x78 Context 3 */
u32 c4; /* 0x7C Context 4 */
u32 c5; /* 0x80 Context 5 */
u32 c6; /* 0x84 Context 6 */
u32 c7; /* 0x88 Context 7 */
u32 c8; /* 0x8C Context 8 */
u32 c9; /* 0x90 Context 9 */
u32 c10; /* 0x94 Context 10 */
u32 c11; /* 0x98 Context 11 */
u32 c12; /* 0x9C Context 12 - 5235, 5271, 5272 */
} skha_t;
#ifdef CONFIG_MCF532x
#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 9)
#define SKHA_MODE_CTRM_MASK (0xFFFFE1FF)
#define SKHA_MODE_DKP (0x00000100)
#else
#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 8)
#define SKHA_MODE_CTRM_MASK (0xFFFFF0FF)
#define SKHA_MODE_DKP (0x00000080)
#endif
#define SKHA_MODE_CM(x) (((x) & 0x03) << 3)
#define SKHA_MODE_CM_MASK (0xFFFFFFE7)
#define SKHA_MODE_DIR (0x00000004)
#define SKHA_MODE_ALG(x) ((x) & 0x03)
#define SKHA_MODE_ALG_MASK (0xFFFFFFFC)
#define SHKA_CR_ODMAL(x) (((x) & 0x3F) << 24)
#define SHKA_CR_ODMAL_MASK (0xC0FFFFFF)
#define SHKA_CR_IDMAL(x) (((x) & 0x3F) << 16)
#define SHKA_CR_IDMAL_MASK (0xFFC0FFFF)
#define SHKA_CR_END (0x00000008)
#define SHKA_CR_ODMA (0x00000004)
#define SHKA_CR_IDMA (0x00000002)
#define SKHA_CR_IE (0x00000001)
#define SKHA_CMR_GO (0x00000008)
#define SKHA_CMR_CI (0x00000004)
#define SKHA_CMR_RI (0x00000002)
#define SKHA_CMR_SWR (0x00000001)
#define SKHA_SR_OFL(x) (((x) & 0xFF) << 24)
#define SKHA_SR_OFL_MASK (0x00FFFFFF)
#define SKHA_SR_IFL(x) (((x) & 0xFF) << 16)
#define SKHA_SR_IFL_MASK (0xFF00FFFF)
#define SKHA_SR_AESES(x) (((x) & 0x1F) << 11)
#define SKHA_SR_AESES_MASK (0xFFFF07FF)
#define SKHA_SR_DESES(x) (((x) & 0x7) << 8)
#define SKHA_SR_DESES_MASK (0xFFFFF8FF)
#define SKHA_SR_BUSY (0x00000010)
#define SKHA_SR_RD (0x00000008)
#define SKHA_SR_ERR (0x00000004)
#define SKHA_SR_DONE (0x00000002)
#define SKHA_SR_INT (0x00000001)
#define SHKA_ESE_DRL (0x00000800)
#define SKHA_ESR_KRE (0x00000400)
#define SKHA_ESR_KPE (0x00000200)
#define SKHA_ESR_ERE (0x00000100)
#define SKHA_ESR_RMDP (0x00000080)
#define SKHA_ESR_KSE (0x00000040)
#define SKHA_ESR_DSE (0x00000020)
#define SKHA_ESR_IME (0x00000010)
#define SKHA_ESR_NEOF (0x00000008)
#define SKHA_ESR_NEIF (0x00000004)
#define SKHA_ESR_OFU (0x00000002)
#define SKHA_ESR_IFO (0x00000001)
#define SKHA_KSR_SZ(x) ((x) & 0x3F)
#define SKHA_KSR_SZ_MASK (0xFFFFFFC0)
#endif /* __SKHA_H__ */

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/*
* SSI Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SSI_H__
#define __SSI_H__
typedef struct ssi {
u32 tx0;
u32 tx1;
u32 rx0;
u32 rx1;
u32 cr;
u32 isr;
u32 ier;
u32 tcr;
u32 rcr;
u32 ccr;
u8 resv0[0x4];
u32 fcsr;
u8 resv1[0x8];
u32 acr;
u32 acadd;
u32 acdat;
u32 atag;
u32 tmask;
u32 rmask;
} ssi_t;
#define SSI_CR_CIS (0x00000200)
#define SSI_CR_TCH (0x00000100)
#define SSI_CR_MCE (0x00000080)
#define SSI_CR_I2S_MASK (0xFFFFFF9F)
#define SSI_CR_I2S_SLAVE (0x00000040)
#define SSI_CR_I2S_MASTER (0x00000020)
#define SSI_CR_I2S_NORMAL (0x00000000)
#define SSI_CR_SYN (0x00000010)
#define SSI_CR_NET (0x00000008)
#define SSI_CR_RE (0x00000004)
#define SSI_CR_TE (0x00000002)
#define SSI_CR_SSI_EN (0x00000001)
#define SSI_ISR_CMDAU (0x00040000)
#define SSI_ISR_CMDDU (0x00020000)
#define SSI_ISR_RXT (0x00010000)
#define SSI_ISR_RDR1 (0x00008000)
#define SSI_ISR_RDR0 (0x00004000)
#define SSI_ISR_TDE1 (0x00002000)
#define SSI_ISR_TDE0 (0x00001000)
#define SSI_ISR_ROE1 (0x00000800)
#define SSI_ISR_ROE0 (0x00000400)
#define SSI_ISR_TUE1 (0x00000200)
#define SSI_ISR_TUE0 (0x00000100)
#define SSI_ISR_TFS (0x00000080)
#define SSI_ISR_RFS (0x00000040)
#define SSI_ISR_TLS (0x00000020)
#define SSI_ISR_RLS (0x00000010)
#define SSI_ISR_RFF1 (0x00000008)
#define SSI_ISR_RFF0 (0x00000004)
#define SSI_ISR_TFE1 (0x00000002)
#define SSI_ISR_TFE0 (0x00000001)
#define SSI_IER_RDMAE (0x00400000)
#define SSI_IER_RIE (0x00200000)
#define SSI_IER_TDMAE (0x00100000)
#define SSI_IER_TIE (0x00080000)
#define SSI_IER_CMDAU (0x00040000)
#define SSI_IER_CMDU (0x00020000)
#define SSI_IER_RXT (0x00010000)
#define SSI_IER_RDR1 (0x00008000)
#define SSI_IER_RDR0 (0x00004000)
#define SSI_IER_TDE1 (0x00002000)
#define SSI_IER_TDE0 (0x00001000)
#define SSI_IER_ROE1 (0x00000800)
#define SSI_IER_ROE0 (0x00000400)
#define SSI_IER_TUE1 (0x00000200)
#define SSI_IER_TUE0 (0x00000100)
#define SSI_IER_TFS (0x00000080)
#define SSI_IER_RFS (0x00000040)
#define SSI_IER_TLS (0x00000020)
#define SSI_IER_RLS (0x00000010)
#define SSI_IER_RFF1 (0x00000008)
#define SSI_IER_RFF0 (0x00000004)
#define SSI_IER_TFE1 (0x00000002)
#define SSI_IER_TFE0 (0x00000001)
#define SSI_TCR_TXBIT0 (0x00000200)
#define SSI_TCR_TFEN1 (0x00000100)
#define SSI_TCR_TFEN0 (0x00000080)
#define SSI_TCR_TFDIR (0x00000040)
#define SSI_TCR_TXDIR (0x00000020)
#define SSI_TCR_TSHFD (0x00000010)
#define SSI_TCR_TSCKP (0x00000008)
#define SSI_TCR_TFSI (0x00000004)
#define SSI_TCR_TFSL (0x00000002)
#define SSI_TCR_TEFS (0x00000001)
#define SSI_RCR_RXEXT (0x00000400)
#define SSI_RCR_RXBIT0 (0x00000200)
#define SSI_RCR_RFEN1 (0x00000100)
#define SSI_RCR_RFEN0 (0x00000080)
#define SSI_RCR_RSHFD (0x00000010)
#define SSI_RCR_RSCKP (0x00000008)
#define SSI_RCR_RFSI (0x00000004)
#define SSI_RCR_RFSL (0x00000002)
#define SSI_RCR_REFS (0x00000001)
#define SSI_CCR_DIV2 (0x00040000)
#define SSI_CCR_PSR (0x00020000)
#define SSI_CCR_WL(x) (((x) & 0x0F) << 13)
#define SSI_CCR_WL_MASK (0xFFFE1FFF)
#define SSI_CCR_DC(x) (((x)& 0x1F) << 8)
#define SSI_CCR_DC_MASK (0xFFFFE0FF)
#define SSI_CCR_PM(x) ((x) & 0xFF)
#define SSI_CCR_PM_MASK (0xFFFFFF00)
#define SSI_FCSR_RFCNT1(x) (((x) & 0x0F) << 28)
#define SSI_FCSR_RFCNT1_MASK (0x0FFFFFFF)
#define SSI_FCSR_TFCNT1(x) (((x) & 0x0F) << 24)
#define SSI_FCSR_TFCNT1_MASK (0xF0FFFFFF)
#define SSI_FCSR_RFWM1(x) (((x) & 0x0F) << 20)
#define SSI_FCSR_RFWM1_MASK (0xFF0FFFFF)
#define SSI_FCSR_TFWM1(x) (((x) & 0x0F) << 16)
#define SSI_FCSR_TFWM1_MASK (0xFFF0FFFF)
#define SSI_FCSR_RFCNT0(x) (((x) & 0x0F) << 12)
#define SSI_FCSR_RFCNT0_MASK (0xFFFF0FFF)
#define SSI_FCSR_TFCNT0(x) (((x) & 0x0F) << 8)
#define SSI_FCSR_TFCNT0_MASK (0xFFFFF0FF)
#define SSI_FCSR_RFWM0(x) (((x) & 0x0F) << 4)
#define SSI_FCSR_RFWM0_MASK (0xFFFFFF0F)
#define SSI_FCSR_TFWM0(x) ((x) & 0x0F)
#define SSI_FCSR_TFWM0_MASK (0xFFFFFFF0)
#define SSI_ACR_FRDIV(x) (((x) & 0x3F) << 5)
#define SSI_ACR_FRDIV_MASK (0xFFFFF81F)
#define SSI_ACR_WR (0x00000010)
#define SSI_ACR_RD (0x00000008)
#define SSI_ACR_TIF (0x00000004)
#define SSI_ACR_FV (0x00000002)
#define SSI_ACR_AC97EN (0x00000001)
#define SSI_ACADD_SSI_ACADD(x) ((x) & 0x0007FFFF)
#define SSI_ACDAT_SSI_ACDAT(x) ((x) & 0x0007FFFF)
#define SSI_ATAG_DDI_ATAG(x) ((x) & 0x0000FFFF)
#endif /* __SSI_H__ */

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/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_NEEDS_MANUAL_RELOC
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#define CONFIG_SYS_BOOT_GET_CMDLINE
#define CONFIG_SYS_BOOT_GET_KBD
#endif

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#include <asm-generic/errno.h>

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/*
* fec.h -- Fast Ethernet Controller definitions
*
* Some definitions copied from commproc.h for MPC8xx:
* MPC8xx Communication Processor Module.
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
* Add FEC Structure and definitions
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef fec_h
#define fec_h
/* Buffer descriptors used FEC.
*/
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
#define BD_ENET_RX_RO1 ((ushort)0x4000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
#define BD_ENET_RX_BC ((ushort)0x0080)
#define BD_ENET_RX_MC ((ushort)0x0040)
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
#define BD_ENET_RX_TR BD_ENET_RX_CL
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
#define BD_ENET_TX_ABC BD_ENET_TX_DEF
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
#define BD_ENET_TX_RCMASK ((ushort)0x003c)
#define BD_ENET_TX_UN ((ushort)0x0002)
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
/*********************************************************************
* Fast Ethernet Controller (FEC)
*********************************************************************/
/* FEC private information */
struct fec_info_s {
int index;
u32 iobase;
u32 pinmux;
u32 miibase;
int phy_addr;
int dup_spd;
char *phy_name;
int phyname_init;
cbd_t *rxbd; /* Rx BD */
cbd_t *txbd; /* Tx BD */
uint rxIdx;
uint txIdx;
char *txbuf;
int initialized;
struct fec_info_s *next;
};
#ifdef CONFIG_MCFFEC
/* Register read/write struct */
typedef struct fec {
#ifdef CONFIG_M5272
u32 ecr; /* 0x00 */
u32 eir; /* 0x04 */
u32 eimr; /* 0x08 */
u32 ivsr; /* 0x0C */
u32 rdar; /* 0x10 */
u32 tdar; /* 0x14 */
u8 resv1[0x28]; /* 0x18 */
u32 mmfr; /* 0x40 */
u32 mscr; /* 0x44 */
u8 resv2[0x44]; /* 0x48 */
u32 frbr; /* 0x8C */
u32 frsr; /* 0x90 */
u8 resv3[0x10]; /* 0x94 */
u32 tfwr; /* 0xA4 */
u32 res4; /* 0xA8 */
u32 tfsr; /* 0xAC */
u8 resv4[0x50]; /* 0xB0 */
u32 opd; /* 0x100 - dummy */
u32 rcr; /* 0x104 */
u32 mibc; /* 0x108 */
u8 resv5[0x38]; /* 0x10C */
u32 tcr; /* 0x144 */
u8 resv6[0x270]; /* 0x148 */
u32 iaur; /* 0x3B8 - dummy */
u32 ialr; /* 0x3BC - dummy */
u32 palr; /* 0x3C0 */
u32 paur; /* 0x3C4 */
u32 gaur; /* 0x3C8 */
u32 galr; /* 0x3CC */
u32 erdsr; /* 0x3D0 */
u32 etdsr; /* 0x3D4 */
u32 emrbr; /* 0x3D8 */
u8 resv12[0x74]; /* 0x18C */
#else
u8 resv0[0x4];
u32 eir;
u32 eimr;
u8 resv1[0x4];
u32 rdar;
u32 tdar;
u8 resv2[0xC];
u32 ecr;
u8 resv3[0x18];
u32 mmfr;
u32 mscr;
u8 resv4[0x1C];
u32 mibc;
u8 resv5[0x1C];
u32 rcr;
u8 resv6[0x3C];
u32 tcr;
u8 resv7[0x1C];
u32 palr;
u32 paur;
u32 opd;
u8 resv8[0x28];
u32 iaur;
u32 ialr;
u32 gaur;
u32 galr;
u8 resv9[0x1C];
u32 tfwr;
u8 resv10[0x4];
u32 frbr;
u32 frsr;
u8 resv11[0x2C];
u32 erdsr;
u32 etdsr;
u32 emrbr;
u8 resv12[0x74];
#endif
u32 rmon_t_drop;
u32 rmon_t_packets;
u32 rmon_t_bc_pkt;
u32 rmon_t_mc_pkt;
u32 rmon_t_crc_align;
u32 rmon_t_undersize;
u32 rmon_t_oversize;
u32 rmon_t_frag;
u32 rmon_t_jab;
u32 rmon_t_col;
u32 rmon_t_p64;
u32 rmon_t_p65to127;
u32 rmon_t_p128to255;
u32 rmon_t_p256to511;
u32 rmon_t_p512to1023;
u32 rmon_t_p1024to2047;
u32 rmon_t_p_gte2048;
u32 rmon_t_octets;
u32 ieee_t_drop;
u32 ieee_t_frame_ok;
u32 ieee_t_1col;
u32 ieee_t_mcol;
u32 ieee_t_def;
u32 ieee_t_lcol;
u32 ieee_t_excol;
u32 ieee_t_macerr;
u32 ieee_t_cserr;
u32 ieee_t_sqe;
u32 ieee_t_fdxfc;
u32 ieee_t_octets_ok;
u8 resv13[0x8];
u32 rmon_r_drop;
u32 rmon_r_packets;
u32 rmon_r_bc_pkt;
u32 rmon_r_mc_pkt;
u32 rmon_r_crc_align;
u32 rmon_r_undersize;
u32 rmon_r_oversize;
u32 rmon_r_frag;
u32 rmon_r_jab;
u32 rmon_r_resvd_0;
u32 rmon_r_p64;
u32 rmon_r_p65to127;
u32 rmon_r_p128to255;
u32 rmon_r_p256to511;
u32 rmon_r_p512to1023;
u32 rmon_r_p1024to2047;
u32 rmon_r_p_gte2048;
u32 rmon_r_octets;
u32 ieee_r_drop;
u32 ieee_r_frame_ok;
u32 ieee_r_crc;
u32 ieee_r_align;
u32 ieee_r_macerr;
u32 ieee_r_fdxfc;
u32 ieee_r_octets_ok;
} fec_t;
#endif /* CONFIG_MCFFEC */
/*********************************************************************
* Fast Ethernet Controller (FEC)
*********************************************************************/
/* Bit definitions and macros for FEC_EIR */
#define FEC_EIR_CLEAR_ALL (0xFFF80000)
#define FEC_EIR_HBERR (0x80000000)
#define FEC_EIR_BABR (0x40000000)
#define FEC_EIR_BABT (0x20000000)
#define FEC_EIR_GRA (0x10000000)
#define FEC_EIR_TXF (0x08000000)
#define FEC_EIR_TXB (0x04000000)
#define FEC_EIR_RXF (0x02000000)
#define FEC_EIR_RXB (0x01000000)
#define FEC_EIR_MII (0x00800000)
#define FEC_EIR_EBERR (0x00400000)
#define FEC_EIR_LC (0x00200000)
#define FEC_EIR_RL (0x00100000)
#define FEC_EIR_UN (0x00080000)
/* Bit definitions and macros for FEC_RDAR */
#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
/* Bit definitions and macros for FEC_TDAR */
#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
/* Bit definitions and macros for FEC_ECR */
#define FEC_ECR_ETHER_EN (0x00000002)
#define FEC_ECR_RESET (0x00000001)
/* Bit definitions and macros for FEC_MMFR */
#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
#define FEC_MMFR_ST_01 (0x40000000)
#define FEC_MMFR_OP_RD (0x20000000)
#define FEC_MMFR_OP_WR (0x10000000)
#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
#define FEC_MMFR_TA_10 (0x00020000)
/* Bit definitions and macros for FEC_MSCR */
#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
/* Bit definitions and macros for FEC_MIBC */
#define FEC_MIBC_MIB_DISABLE (0x80000000)
#define FEC_MIBC_MIB_IDLE (0x40000000)
/* Bit definitions and macros for FEC_RCR */
#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
#define FEC_RCR_FCE (0x00000020)
#define FEC_RCR_BC_REJ (0x00000010)
#define FEC_RCR_PROM (0x00000008)
#define FEC_RCR_MII_MODE (0x00000004)
#define FEC_RCR_DRT (0x00000002)
#define FEC_RCR_LOOP (0x00000001)
/* Bit definitions and macros for FEC_TCR */
#define FEC_TCR_RFC_PAUSE (0x00000010)
#define FEC_TCR_TFC_PAUSE (0x00000008)
#define FEC_TCR_FDEN (0x00000004)
#define FEC_TCR_HBC (0x00000002)
#define FEC_TCR_GTS (0x00000001)
/* Bit definitions and macros for FEC_PAUR */
#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
/* Bit definitions and macros for FEC_OPD */
#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for FEC_TFWR */
#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
#define FEC_TFWR_X_WMRK_64 (0x01)
#define FEC_TFWR_X_WMRK_128 (0x02)
#define FEC_TFWR_X_WMRK_192 (0x03)
/* Bit definitions and macros for FEC_FRBR */
#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
/* Bit definitions and macros for FEC_FRSR */
#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
/* Bit definitions and macros for FEC_ERDSR */
#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for FEC_ETDSR */
#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for FEC_EMRBR */
#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
#define FEC_RESET_DELAY 100
#define FEC_RX_TOUT 100
int fecpin_setclear(struct eth_device *dev, int setclear);
#ifdef CONFIG_SYS_DISCOVER_PHY
void __mii_init(void);
uint mii_send(uint mii_cmd);
int mii_discover_phy(struct eth_device *dev);
int mcffec_miiphy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int mcffec_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
#endif
#endif /* fec_h */

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/*
* Freescale I2C Controller
*
* Copyright 2006 Freescale Semiconductor, Inc.
*
* Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
* Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
* and Jeff Brown.
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_FSL_I2C_H_
#define _ASM_FSL_I2C_H_
#include <asm/types.h>
typedef struct fsl_i2c_base {
u8 adr; /* I2C slave address */
u8 res0[3];
#define I2C_ADR 0xFE
#define I2C_ADR_SHIFT 1
#define I2C_ADR_RES ~(I2C_ADR)
u8 fdr; /* I2C frequency divider register */
u8 res1[3];
#define IC2_FDR 0x3F
#define IC2_FDR_SHIFT 0
#define IC2_FDR_RES ~(IC2_FDR)
u8 cr; /* I2C control redister */
u8 res2[3];
#define I2C_CR_MEN 0x80
#define I2C_CR_MIEN 0x40
#define I2C_CR_MSTA 0x20
#define I2C_CR_MTX 0x10
#define I2C_CR_TXAK 0x08
#define I2C_CR_RSTA 0x04
#define I2C_CR_BCST 0x01
u8 sr; /* I2C status register */
u8 res3[3];
#define I2C_SR_MCF 0x80
#define I2C_SR_MAAS 0x40
#define I2C_SR_MBB 0x20
#define I2C_SR_MAL 0x10
#define I2C_SR_BCSTM 0x08
#define I2C_SR_SRW 0x04
#define I2C_SR_MIF 0x02
#define I2C_SR_RXAK 0x01
u8 dr; /* I2C data register */
u8 res4[3];
#define I2C_DR 0xFF
#define I2C_DR_SHIFT 0
#define I2C_DR_RES ~(I2C_DR)
} fsl_i2c_t;
#endif /* _ASM_I2C_H_ */

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/*
* fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef fsl_mcdmafec_h
#define fsl_mcdmafec_h
/* Re-use of the definitions */
#include <asm/fec.h>
typedef struct fecdma {
u32 rsvd0; /* 0x000 */
u32 eir; /* 0x004 */
u32 eimr; /* 0x008 */
u32 rsvd1[6]; /* 0x00C - 0x023 */
u32 ecr; /* 0x024 */
u32 rsvd2[6]; /* 0x028 - 0x03F */
u32 mmfr; /* 0x040 */
u32 mscr; /* 0x044 */
u32 rsvd3[7]; /* 0x048 - 0x063 */
u32 mibc; /* 0x064 */
u32 rsvd4[7]; /* 0x068 - 0x083 */
u32 rcr; /* 0x084 */
u32 rhr; /* 0x088 */
u32 rsvd5[14]; /* 0x08C - 0x0C3 */
u32 tcr; /* 0x0C4 */
u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */
u32 palr; /* 0x0E4 */
u32 paur; /* 0x0E8 */
u32 opd; /* 0x0EC */
u32 rsvd7[10]; /* 0x0F0 - 0x117 */
u32 iaur; /* 0x118 */
u32 ialr; /* 0x11C */
u32 gaur; /* 0x120 */
u32 galr; /* 0x124 */
u32 rsvd8[7]; /* 0x128 - 0x143 */
u32 tfwr; /* 0x144 */
u32 rsvd9[14]; /* 0x148 - 0x17F */
u32 fmc; /* 0x180 */
u32 rfdr; /* 0x184 */
u32 rfsr; /* 0x188 */
u32 rfcr; /* 0x18C */
u32 rlrfp; /* 0x190 */
u32 rlwfp; /* 0x194 */
u32 rfar; /* 0x198 */
u32 rfrp; /* 0x19C */
u32 rfwp; /* 0x1A0 */
u32 tfdr; /* 0x1A4 */
u32 tfsr; /* 0x1A8 */
u32 tfcr; /* 0x1AC */
u32 tlrfp; /* 0x1B0 */
u32 tlwfp; /* 0x1B4 */
u32 tfar; /* 0x1B8 */
u32 tfrp; /* 0x1BC */
u32 tfwp; /* 0x1C0 */
u32 frst; /* 0x1C4 */
u32 ctcwr; /* 0x1C8 */
} fecdma_t;
struct fec_info_dma {
int index;
u32 iobase;
u32 pinmux;
u32 miibase;
int phy_addr;
int dup_spd;
char *phy_name;
int phyname_init;
cbd_t *rxbd; /* Rx BD */
cbd_t *txbd; /* Tx BD */
uint rxIdx;
uint txIdx;
char *txbuf;
int initialized;
struct fec_info_dma *next;
u16 rxTask; /* DMA receive Task Number */
u16 txTask; /* DMA Transmit Task Number */
u16 rxPri; /* DMA Receive Priority */
u16 txPri; /* DMA Transmit Priority */
u16 rxInit; /* DMA Receive Initiator */
u16 txInit; /* DMA Transmit Initiator */
u16 usedTbdIdx; /* next transmit BD to clean */
u16 cleanTbdNum; /* the number of available transmit BDs */
};
/* Bit definitions and macros for IEVENT */
#define FEC_EIR_TXERR (0x00040000)
#define FEC_EIR_RXERR (0x00020000)
#undef FEC_EIR_CLEAR_ALL
#define FEC_EIR_CLEAR_ALL (0xFFFE0000)
/* Bit definitions and macros for R_HASH */
#define FEC_RHASH_FCE_DC (0x80000000)
#define FEC_RHASH_MULTCAST (0x40000000)
#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24)
/* Bit definitions and macros for FEC_TFWR */
#undef FEC_TFWR_X_WMRK
#undef FEC_TFWR_X_WMRK_64
#undef FEC_TFWR_X_WMRK_128
#undef FEC_TFWR_X_WMRK_192
#define FEC_TFWR_X_WMRK(x) ((x)&0x0F)
#define FEC_TFWR_X_WMRK_64 (0x00)
#define FEC_TFWR_X_WMRK_128 (0x01)
#define FEC_TFWR_X_WMRK_192 (0x02)
#define FEC_TFWR_X_WMRK_256 (0x03)
#define FEC_TFWR_X_WMRK_320 (0x04)
#define FEC_TFWR_X_WMRK_384 (0x05)
#define FEC_TFWR_X_WMRK_448 (0x06)
#define FEC_TFWR_X_WMRK_512 (0x07)
#define FEC_TFWR_X_WMRK_576 (0x08)
#define FEC_TFWR_X_WMRK_640 (0x09)
#define FEC_TFWR_X_WMRK_704 (0x0A)
#define FEC_TFWR_X_WMRK_768 (0x0B)
#define FEC_TFWR_X_WMRK_832 (0x0C)
#define FEC_TFWR_X_WMRK_896 (0x0D)
#define FEC_TFWR_X_WMRK_960 (0x0E)
#define FEC_TFWR_X_WMRK_1024 (0x0F)
/* FIFO definitions */
/* Bit definitions and macros for FSTAT */
#define FIFO_STAT_IP (0x80000000)
#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24)
#define FIFO_STAT_FAE (0x00800000)
#define FIFO_STAT_RXW (0x00400000)
#define FIFO_STAT_UF (0x00200000)
#define FIFO_STAT_OF (0x00100000)
#define FIFO_STAT_FR (0x00080000)
#define FIFO_STAT_FULL (0x00040000)
#define FIFO_STAT_ALARM (0x00020000)
#define FIFO_STAT_EMPTY (0x00010000)
/* Bit definitions and macros for FCTRL */
#define FIFO_CTRL_WCTL (0x40000000)
#define FIFO_CTRL_WFR (0x20000000)
#define FIFO_CTRL_FRAME (0x08000000)
#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24)
#define FIFO_CTRL_IPMASK (0x00800000)
#define FIFO_CTRL_FAEMASK (0x00400000)
#define FIFO_CTRL_RXWMASK (0x00200000)
#define FIFO_CTRL_UFMASK (0x00100000)
#define FIFO_CTRL_OFMASK (0x00080000)
#endif /* fsl_mcdmafec_h */

33
u-boot/arch/m68k/include/asm/global_data.h Normal file
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@@ -0,0 +1,33 @@
/*
* (C) Copyright 2002 - 2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
/* Architecture-specific global data */
struct arch_global_data {
#ifdef CONFIG_SYS_I2C_FSL
unsigned long i2c1_clk;
unsigned long i2c2_clk;
#endif
#ifdef CONFIG_EXTRA_CLOCK
unsigned long inp_clk;
unsigned long vco_clk;
unsigned long flb_clk;
#endif
};
#include <asm-generic/global_data.h>
#if 0
extern gd_t *global_data;
#define DECLARE_GLOBAL_DATA_PTR gd_t *gd = global_data
#else
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("d7")
#endif
#endif /* __ASM_GBL_DATA_H */

505
u-boot/arch/m68k/include/asm/immap.h Normal file
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/*
* ColdFire Internal Memory Map and Defines
*
* Copyright 2004-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_H
#define __IMMAP_H
#if defined(CONFIG_MCF520x)
#include <asm/immap_520x.h>
#include <asm/m520x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (6)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE (6)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M520x */
#ifdef CONFIG_M52277
#include <asm/immap_5227x.h>
#include <asm/m5227x.h>
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
#ifdef CONFIG_LCD
#define CONFIG_SYS_LCD_BASE (MMAP_LCD)
#endif
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (6)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE (6)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M52277 */
#ifdef CONFIG_M5235
#include <asm/immap_5235.h>
#include <asm/m5235.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE (6)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5235 */
#ifdef CONFIG_M5249
#include <asm/immap_5249.h>
#include <asm/m5249.h>
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
#define CONFIG_SYS_TMRINTR_NO (31)
#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
#endif
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
#include <asm/immap_5253.h>
#include <asm/m5249.h>
#include <asm/m5253.h>
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
#define CONFIG_SYS_TMRINTR_NO (27)
#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
#endif
#endif /* CONFIG_M5253 */
#ifdef CONFIG_M5271
#include <asm/immap_5271.h>
#include <asm/m5271.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5271 */
#ifdef CONFIG_M5272
#include <asm/immap_5272.h>
#include <asm/m5272.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_TMR3)
#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
#define CONFIG_SYS_TMRINTR_NO (INT_TMR3)
#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24)
#define CONFIG_SYS_TMRINTR_PEND (0)
#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5272 */
#ifdef CONFIG_M5275
#include <asm/immap_5275.h>
#include <asm/m5275.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (192)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (0x1E)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5275 */
#ifdef CONFIG_M5282
#include <asm/immap_5282.h>
#include <asm/m5282.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5282 */
#ifdef CONFIG_M5307
#include <asm/immap_5307.h>
#include <asm/m5307.h>
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
(CONFIG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \
(CONFIG_SYS_INTR_BASE))->ipr)
#define CONFIG_SYS_TMRINTR_NO (31)
#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5307 */
#if defined(CONFIG_MCF5301x)
#include <asm/immap_5301x.h>
#include <asm/m5301x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (6)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE (6)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5301x */
#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
#include <asm/immap_5329.h>
#include <asm/m5329.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (6)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE (6)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5329 && CONFIG_M5373 */
#if defined(CONFIG_M54418)
#include <asm/immap_5441x.h>
#include <asm/m5441x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#if (CONFIG_SYS_UART_PORT < 4)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
(CONFIG_SYS_UART_PORT * 0x4000))
#else
#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
((CONFIG_SYS_UART_PORT - 4) * 0x4000))
#endif
#define MMAP_DSPI MMAP_DSPI0
#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (6)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE (6)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M54418 */
#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
#include <asm/immap_5445x.h>
#include <asm/m5445x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#if defined(CONFIG_M54455EVB)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#endif
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (6)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE (6)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE)
#endif
#endif /* CONFIG_M54451 || CONFIG_M54455 */
#ifdef CONFIG_M547x
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>
#ifdef CONFIG_FSLDMAFEC
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#define FEC0_RX_TASK 0
#define FEC0_TX_TASK 1
#define FEC0_RX_PRIORITY 6
#define FEC0_TX_PRIORITY 7
#define FEC0_RX_INIT 16
#define FEC0_TX_INIT 17
#define FEC1_RX_TASK 2
#define FEC1_TX_TASK 3
#define FEC1_RX_PRIORITY 6
#define FEC1_TX_PRIORITY 7
#define FEC1_RX_INIT 30
#define FEC1_TX_INIT 31
#endif
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
#ifdef CONFIG_SLTTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (0x1E)
#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CONFIG_SYS_PCI_BAR0 (0x40000000)
#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
#endif
#endif /* CONFIG_M547x */
#ifdef CONFIG_M548x
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>
#ifdef CONFIG_FSLDMAFEC
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#define FEC0_RX_TASK 0
#define FEC0_TX_TASK 1
#define FEC0_RX_PRIORITY 6
#define FEC0_TX_PRIORITY 7
#define FEC0_RX_INIT 16
#define FEC0_TX_INIT 17
#define FEC1_RX_TASK 2
#define FEC1_TX_TASK 3
#define FEC1_RX_PRIORITY 6
#define FEC1_TX_PRIORITY 7
#define FEC1_RX_INIT 30
#define FEC1_TX_INIT 31
#endif
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
/* Timer */
#ifdef CONFIG_SLTTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (0x1E)
#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
#endif
#endif /* CONFIG_M548x */
#endif /* __IMMAP_H */

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/*
* MCF520x Internal Memory Map
*
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_520X__
#define __IMMAP_520X__
#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000)
#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000)
#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000)
#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000)
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/qspi.h>
/* System Controller Module */
typedef struct scm1 {
u32 mpr; /* 0x00 Master Privilege */
u32 rsvd1[7];
u32 pacra; /* 0x20 Peripheral Access Ctrl A */
u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
u32 rsvd2[4];
u32 pacre; /* 0x40 Peripheral Access Ctrl E */
u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
u32 rsvd3[3];
u32 bmt; /* 0x50 bus monitor */
} scm1_t;
typedef struct scm2 {
u8 rsvd1[19]; /* 0x00 - 0x12 */
u8 wcr; /* 0x13 */
u16 rsvd2; /* 0x14 - 0x15 */
u16 cwcr; /* 0x16 */
u8 rsvd3[3]; /* 0x18 - 0x1A */
u8 cwsr; /* 0x1B */
u8 rsvd4[3]; /* 0x1C - 0x1E */
u8 scmisr; /* 0x1F */
u8 rsvd5[79]; /* 0x20 - 0x6F */
u32 cfadr; /* 0x70 */
u8 rsvd7; /* 0x74 */
u8 cfier; /* 0x75 */
u8 cfloc; /* 0x76 */
u8 cfatr; /* 0x77 */
u32 rsvd8; /* 0x78 - 0x7B */
u32 cfdtr; /* 0x7C */
} scm2_t;
/* Chip configuration module */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
typedef struct ccm_ctrl {
u16 ccr; /* 0x00 Chip Cfg */
u16 res1; /* 0x02 */
u16 rcon; /* 0x04 Reset Cfg */
u16 cir; /* 0x06 Chip ID */
} ccm_t;
/* GPIO port */
typedef struct gpio_ctrl {
/* Port Output Data */
u8 podr_busctl; /* 0x00 */
u8 podr_be; /* 0x01 */
u8 podr_cs; /* 0x02 */
u8 podr_feci2c; /* 0x03 */
u8 podr_qspi; /* 0x04 */
u8 podr_timer; /* 0x05 */
u8 podr_uart; /* 0x06 */
u8 podr_fech; /* 0x07 */
u8 podr_fecl; /* 0x08 */
u8 res01[3]; /* 0x9 - 0x0B */
/* Port Data Direction */
u8 pddr_busctl; /* 0x0C */
u8 pddr_be; /* 0x0D */
u8 pddr_cs; /* 0x0E */
u8 pddr_feci2c; /* 0x0F */
u8 pddr_qspi; /* 0x10*/
u8 pddr_timer; /* 0x11 */
u8 pddr_uart; /* 0x12 */
u8 pddr_fech; /* 0x13 */
u8 pddr_fecl; /* 0x14 */
u8 res02[5]; /* 0x15 - 0x19 */
/* Port Data Direction */
u8 ppdr_cs; /* 0x1A */
u8 ppdr_feci2c; /* 0x1B */
u8 ppdr_qspi; /* 0x1C */
u8 ppdr_timer; /* 0x1D */
u8 ppdr_uart; /* 0x1E */
u8 ppdr_fech; /* 0x1F */
u8 ppdr_fecl; /* 0x20 */
u8 res03[3]; /* 0x21 - 0x23 */
/* Port Clear Output Data */
u8 pclrr_busctl; /* 0x24 */
u8 pclrr_be; /* 0x25 */
u8 pclrr_cs; /* 0x26 */
u8 pclrr_feci2c; /* 0x27 */
u8 pclrr_qspi; /* 0x28 */
u8 pclrr_timer; /* 0x29 */
u8 pclrr_uart; /* 0x2A */
u8 pclrr_fech; /* 0x2B */
u8 pclrr_fecl; /* 0x2C */
u8 res04[3]; /* 0x2D - 0x2F */
/* Pin Assignment */
u8 par_busctl; /* 0x30 */
u8 par_be; /* 0x31 */
u8 par_cs; /* 0x32 */
u8 par_feci2c; /* 0x33 */
u8 par_qspi; /* 0x34 */
u8 par_timer; /* 0x35 */
u16 par_uart; /* 0x36 */
u8 par_fec; /* 0x38 */
u8 par_irq; /* 0x39 */
/* Mode Select Control */
/* Drive Strength Control */
u8 mscr_fb; /* 0x3A */
u8 mscr_sdram; /* 0x3B */
u8 dscr_i2c; /* 0x3C */
u8 dscr_misc; /* 0x3D */
u8 dscr_fec; /* 0x3E */
u8 dscr_uart; /* 0x3F */
u8 dscr_qspi; /* 0x40 */
} gpio_t;
/* SDRAM controller */
typedef struct sdram_ctrl {
u32 mode; /* 0x00 Mode/Extended Mode */
u32 ctrl; /* 0x04 Ctrl */
u32 cfg1; /* 0x08 Cfg 1 */
u32 cfg2; /* 0x0C Cfg 2 */
u32 res1[64]; /* 0x10 - 0x10F */
u32 cs0; /* 0x110 Chip Select 0 Cfg */
u32 cs1; /* 0x114 Chip Select 1 Cfg */
} sdram_t;
/* Clock Module */
typedef struct pll_ctrl {
u8 odr; /* 0x00 Output divider */
u8 rsvd1;
u8 cr; /* 0x02 Control */
u8 rsvd2;
u8 mdr; /* 0x04 Modulation Divider */
u8 rsvd3;
u8 fdr; /* 0x06 Feedback Divider */
u8 rsvd4;
} pll_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
u16 cr; /* 0x00 Control */
u16 mr; /* 0x02 Modulus */
u16 cntr; /* 0x04 Count */
u16 sr; /* 0x06 Service */
} wdog_t;
#endif /* __IMMAP_520X__ */

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/*
* MCF5227x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5227X__
#define __IMMAP_5227X__
/* Module Base Addresses */
#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
#define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000)
#define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000)
#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010)
#define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070)
#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
#define MMAP_IACK (CONFIG_SYS_MBAR + 0x00054000)
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
#define MMAP_PWM (CONFIG_SYS_MBAR + 0x00090000)
#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00094000)
#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
#define MMAP_ADC (CONFIG_SYS_MBAR + 0x000A8000)
#define MMAP_LCD (CONFIG_SYS_MBAR + 0x000AC000)
#define MMAP_LCD_BGLUT (CONFIG_SYS_MBAR + 0x000AC800)
#define MMAP_LCD_GWLUT (CONFIG_SYS_MBAR + 0x000ACC00)
#define MMAP_USBHW (CONFIG_SYS_MBAR + 0x000B0000)
#define MMAP_USBCAPS (CONFIG_SYS_MBAR + 0x000B0100)
#define MMAP_USBEHCI (CONFIG_SYS_MBAR + 0x000B0140)
#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B01A0)
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/ssi.h>
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/* Chip Configuration Module (CCM) */
typedef struct ccm {
u16 ccr; /* Chip Configuration (Rd-only) */
u16 resv1;
u16 rcon; /* Reset Configuration (Rd-only) */
u16 cir; /* Chip Identification (Rd-only) */
u32 resv2;
u16 misccr; /* Miscellaneous Control */
u16 cdr; /* Clock Divider */
u16 uocsr; /* USB On-the-Go Controller Status */
u16 resv4;
u16 sbfsr; /* Serial Boot Status */
u16 sbfcr; /* Serial Boot Control */
} ccm_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
u32 res0[0x700]; /* 0x100 */
can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */
} canex_t;
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
/* Port Output Data Registers */
u8 podr_be; /* 0x00 */
u8 podr_cs; /* 0x01 */
u8 podr_fbctl; /* 0x02 */
u8 podr_i2c; /* 0x03 */
u8 rsvd1; /* 0x04 */
u8 podr_uart; /* 0x05 */
u8 podr_dspi; /* 0x06 */
u8 podr_timer; /* 0x07 */
u8 podr_lcdctl; /* 0x08 */
u8 podr_lcddatah; /* 0x09 */
u8 podr_lcddatam; /* 0x0A */
u8 podr_lcddatal; /* 0x0B */
/* Port Data Direction Registers */
u8 pddr_be; /* 0x0C */
u8 pddr_cs; /* 0x0D */
u8 pddr_fbctl; /* 0x0E */
u8 pddr_i2c; /* 0x0F */
u8 rsvd2; /* 0x10 */
u8 pddr_uart; /* 0x11 */
u8 pddr_dspi; /* 0x12 */
u8 pddr_timer; /* 0x13 */
u8 pddr_lcdctl; /* 0x14 */
u8 pddr_lcddatah; /* 0x15 */
u8 pddr_lcddatam; /* 0x16 */
u8 pddr_lcddatal; /* 0x17 */
/* Port Pin Data/Set Data Registers */
u8 ppdsdr_be; /* 0x18 */
u8 ppdsdr_cs; /* 0x19 */
u8 ppdsdr_fbctl; /* 0x1A */
u8 ppdsdr_i2c; /* 0x1B */
u8 rsvd3; /* 0x1C */
u8 ppdsdr_uart; /* 0x1D */
u8 ppdsdr_dspi; /* 0x1E */
u8 ppdsdr_timer; /* 0x1F */
u8 ppdsdr_lcdctl; /* 0x20 */
u8 ppdsdr_lcddatah; /* 0x21 */
u8 ppdsdr_lcddatam; /* 0x22 */
u8 ppdsdr_lcddatal; /* 0x23 */
/* Port Clear Output Data Registers */
u8 pclrr_be; /* 0x24 */
u8 pclrr_cs; /* 0x25 */
u8 pclrr_fbctl; /* 0x26 */
u8 pclrr_i2c; /* 0x27 */
u8 rsvd4; /* 0x28 */
u8 pclrr_uart; /* 0x29 */
u8 pclrr_dspi; /* 0x2A */
u8 pclrr_timer; /* 0x2B */
u8 pclrr_lcdctl; /* 0x2C */
u8 pclrr_lcddatah; /* 0x2D */
u8 pclrr_lcddatam; /* 0x2E */
u8 pclrr_lcddatal; /* 0x2F */
/* Pin Assignment Registers */
u8 par_be; /* 0x30 */
u8 par_cs; /* 0x31 */
u8 par_fbctl; /* 0x32 */
u8 par_i2c; /* 0x33 */
u16 par_uart; /* 0x34 */
u8 par_dspi; /* 0x36 */
u8 par_timer; /* 0x37 */
u8 par_lcdctl; /* 0x38 */
u8 par_irq; /* 0x39 */
u16 rsvd6; /* 0x3A - 0x3B */
u32 par_lcdh; /* 0x3C */
u32 par_lcdl; /* 0x40 */
/* Mode select control registers */
u8 mscr_fb; /* 0x44 */
u8 mscr_sdram; /* 0x45 */
u16 rsvd7; /* 0x46 - 0x47 */
u8 dscr_dspi; /* 0x48 */
u8 dscr_timer; /* 0x49 */
u8 dscr_i2c; /* 0x4A */
u8 dscr_lcd; /* 0x4B */
u8 dscr_debug; /* 0x4C */
u8 dscr_clkrst; /* 0x4D */
u8 dscr_irq; /* 0x4E */
u8 dscr_uart; /* 0x4F */
} gpio_t;
/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 sdmr; /* Mode/Extended Mode */
u32 sdcr; /* Control */
u32 sdcfg1; /* Configuration 1 */
u32 sdcfg2; /* Chip Select */
u8 resv0[0x100];
u32 sdcs0; /* Mode/Extended Mode */
u32 sdcs1; /* Mode/Extended Mode */
} sdramc_t;
/* Phase Locked Loop (PLL) */
typedef struct pll {
u32 pcr; /* PLL Control */
u32 psr; /* PLL Status */
} pll_t;
/* System Control Module register */
typedef struct scm1 {
u32 mpr; /* 0x00 Master Privilege */
u32 rsvd1[7];
u32 pacra; /* 0x20 */
u32 pacrb; /* 0x24 */
u32 pacrc; /* 0x28 */
u32 pacrd; /* 0x2C */
u32 rsvd2[4];
u32 pacre; /* 0x40 */
u32 pacrf; /* 0x44 */
u32 pacrg; /* 0x48 */
u32 rsvd3;
u32 pacri; /* 0x50 */
} scm1_t;
typedef struct scm2_ctrl {
u8 res1[3]; /* 0x00 - 0x02 */
u8 wcr; /* 0x03 wakeup control */
u16 res2; /* 0x04 - 0x05 */
u16 cwcr; /* 0x06 Core Watchdog Control */
u8 res3[3]; /* 0x08 - 0x0A */
u8 cwsr; /* 0x0B Core Watchdog Service */
u8 res4[2]; /* 0x0C - 0x0D */
u8 scmisr; /* 0x0F Interrupt Status */
u32 res5; /* 0x20 */
u32 bcr; /* 0x24 Burst Configuration */
} scm2_t;
typedef struct scm3_ctrl {
u32 cfadr; /* 0x00 Core Fault Address */
u8 res7; /* 0x04 */
u8 cfier; /* 0x05 Core Fault Interrupt Enable */
u8 cfloc; /* 0x06 Core Fault Location */
u8 cfatr; /* 0x07 Core Fault Attributes */
u32 cfdtr; /* 0x08 Core Fault Data */
} scm3_t;
typedef struct rtcex {
u32 rsvd1[3];
u32 gocu;
u32 gocl;
} rtcex_t;
#endif /* __IMMAP_5227X__ */

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/*
* MCF5329 Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5235__
#define __IMMAP_5235__
#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000)
#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000)
#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000)
#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/rng.h>
#include <asm/coldfire/skha.h>
/* System Control Module register */
typedef struct scm_ctrl {
u32 ipsbar; /* 0x00 - MBAR */
u32 res1; /* 0x04 */
u32 rambar; /* 0x08 - RAMBAR */
u32 res2; /* 0x0C */
u8 crsr; /* 0x10 Core Reset Status Register */
u8 cwcr; /* 0x11 Core Watchdog Control Register */
u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */
u8 cwsr; /* 0x13 Core Watchdog Service Register */
u32 dmareqc; /* 0x14 */
u32 res3; /* 0x18 */
u32 mpark; /* 0x1C */
u8 mpr; /* 0x20 */
u8 res4[3]; /* 0x21 - 0x23 */
u8 pacr0; /* 0x24 */
u8 pacr1; /* 0x25 */
u8 pacr2; /* 0x26 */
u8 pacr3; /* 0x27 */
u8 pacr4; /* 0x28 */
u32 res5; /* 0x29 */
u8 pacr5; /* 0x2a */
u8 pacr6; /* 0x2b */
u8 pacr7; /* 0x2c */
u32 res6; /* 0x2d */
u8 pacr8; /* 0x2e */
u32 res7; /* 0x2f */
u8 gpacr; /* 0x30 */
u8 res8[3]; /* 0x31 - 0x33 */
} scm_t;
/* SDRAM controller registers */
typedef struct sdram_ctrl {
u16 dcr; /* 0x00 Control register */
u16 res1[3]; /* 0x02 - 0x07 */
u32 dacr0; /* 0x08 address and control register 0 */
u32 dmr0; /* 0x0C mask register block 0 */
u32 dacr1; /* 0x10 address and control register 1 */
u32 dmr1; /* 0x14 mask register block 1 */
} sdram_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */
u8 podr_addr; /* 0x00 */
u8 podr_datah; /* 0x01 */
u8 podr_datal; /* 0x02 */
u8 podr_busctl; /* 0x03 */
u8 podr_bs; /* 0x04 */
u8 podr_cs; /* 0x05 */
u8 podr_sdram; /* 0x06 */
u8 podr_feci2c; /* 0x07 */
u8 podr_uarth; /* 0x08 */
u8 podr_uartl; /* 0x09 */
u8 podr_qspi; /* 0x0A */
u8 podr_timer; /* 0x0B */
u8 podr_etpu; /* 0x0C */
u8 res1[3]; /* 0x0D - 0x0F */
/* Port Data Direction Registers */
u8 pddr_addr; /* 0x10 */
u8 pddr_datah; /* 0x11 */
u8 pddr_datal; /* 0x12 */
u8 pddr_busctl; /* 0x13 */
u8 pddr_bs; /* 0x14 */
u8 pddr_cs; /* 0x15 */
u8 pddr_sdram; /* 0x16 */
u8 pddr_feci2c; /* 0x17 */
u8 pddr_uarth; /* 0x18 */
u8 pddr_uartl; /* 0x19 */
u8 pddr_qspi; /* 0x1A */
u8 pddr_timer; /* 0x1B */
u8 pddr_etpu; /* 0x1C */
u8 res2[3]; /* 0x1D - 0x1F */
/* Port Data Direction Registers */
u8 ppdsdr_addr; /* 0x20 */
u8 ppdsdr_datah; /* 0x21 */
u8 ppdsdr_datal; /* 0x22 */
u8 ppdsdr_busctl; /* 0x23 */
u8 ppdsdr_bs; /* 0x24 */
u8 ppdsdr_cs; /* 0x25 */
u8 ppdsdr_sdram; /* 0x26 */
u8 ppdsdr_feci2c; /* 0x27 */
u8 ppdsdr_uarth; /* 0x28 */
u8 ppdsdr_uartl; /* 0x29 */
u8 ppdsdr_qspi; /* 0x2A */
u8 ppdsdr_timer; /* 0x2B */
u8 ppdsdr_etpu; /* 0x2C */
u8 res3[3]; /* 0x2D - 0x2F */
/* Port Clear Output Data Registers */
u8 pclrr_addr; /* 0x30 */
u8 pclrr_datah; /* 0x31 */
u8 pclrr_datal; /* 0x32 */
u8 pclrr_busctl; /* 0x33 */
u8 pclrr_bs; /* 0x34 */
u8 pclrr_cs; /* 0x35 */
u8 pclrr_sdram; /* 0x36 */
u8 pclrr_feci2c; /* 0x37 */
u8 pclrr_uarth; /* 0x38 */
u8 pclrr_uartl; /* 0x39 */
u8 pclrr_qspi; /* 0x3A */
u8 pclrr_timer; /* 0x3B */
u8 pclrr_etpu; /* 0x3C */
u8 res4[3]; /* 0x3D - 0x3F */
/* Pin Assignment Registers */
u8 par_ad; /* 0x40 */
u8 res5; /* 0x41 */
u16 par_busctl; /* 0x42 */
u8 par_bs; /* 0x44 */
u8 par_cs; /* 0x45 */
u8 par_sdram; /* 0x46 */
u8 par_feci2c; /* 0x47 */
u16 par_uart; /* 0x48 */
u8 par_qspi; /* 0x4A */
u8 res6; /* 0x4B */
u16 par_timer; /* 0x4C */
u8 par_etpu; /* 0x4E */
u8 res7; /* 0x4F */
/* Drive Strength Control Registers */
u8 dscr_eim; /* 0x50 */
u8 dscr_etpu; /* 0x51 */
u8 dscr_feci2c; /* 0x52 */
u8 dscr_uart; /* 0x53 */
u8 dscr_qspi; /* 0x54 */
u8 dscr_timer; /* 0x55 */
u16 res8; /* 0x56 */
} gpio_t;
/*Chip configuration module registers */
typedef struct ccm_ctrl {
u8 rcr; /* 0x01 */
u8 rsr; /* 0x02 */
u16 res1; /* 0x03 */
u16 ccr; /* 0x04 Chip configuration register */
u16 lpcr; /* 0x06 Low-power Control register */
u16 rcon; /* 0x08 Rreset configuration register */
u16 cir; /* 0x0a Chip identification register */
} ccm_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u32 syncr; /* 0x00 synthesizer control register */
u32 synsr; /* 0x04 synthesizer status register */
} pll_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
u16 cr; /* 0x00 Control register */
u16 mr; /* 0x02 Modulus register */
u16 cntr; /* 0x04 Count register */
u16 sr; /* 0x06 Service register */
} wdog_t;
#endif /* __IMMAP_5235__ */

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u-boot/arch/m68k/include/asm/immap_5249.h Normal file
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/*
* MCF5249 Internal Memory Map
*
* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5249__
#define __IMMAP_5249__
#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400)
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/qspi.h>
#endif /* __IMMAP_5249__ */

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u-boot/arch/m68k/include/asm/immap_5253.h Normal file
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/*
* MCF5253 Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5253__
#define __IMMAP_5253__
#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_I2C0 (CONFIG_SYS_MBAR + 0x00000280)
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400)
#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000)
#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000)
#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C)
#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440)
#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00)
#include <asm/coldfire/ata.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/qspi.h>
typedef struct canex_ctrl {
can_msg_t msg[32]; /* 0x80 Message Buffer 0-31 */
} canex_t;
#endif /* __IMMAP_5253__ */

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u-boot/arch/m68k/include/asm/immap_5271.h Normal file
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/*
* MCF5272 Internal Memory Map
*
* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* 2006 Zachary P. Landau <zachary.landau@labxtechnologies.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5271__
#define __IMMAP_5271__
#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000)
#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000)
#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000)
#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/rng.h>
#include <asm/coldfire/skha.h>
#endif /* __IMMAP_5271__ */

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u-boot/arch/m68k/include/asm/immap_5272.h Normal file
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/*
* MCF5272 Internal Memory Map
*
* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5272__
#define __IMMAP_5272__
#define MMAP_CFG (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000020)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x000000A0)
#define MMAP_PWM (CONFIG_SYS_MBAR + 0x000000C0)
#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x000000E0)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000100)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000140)
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000180)
#define MMAP_TMR0 (CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_TMR1 (CONFIG_SYS_MBAR + 0x00000220)
#define MMAP_TMR2 (CONFIG_SYS_MBAR + 0x00000240)
#define MMAP_TMR3 (CONFIG_SYS_MBAR + 0x00000260)
#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00000280)
#define MMAP_PLIC (CONFIG_SYS_MBAR + 0x00000300)
#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840)
#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000)
#include <asm/coldfire/pwm.h>
/* System configuration registers */
typedef struct sys_ctrl {
uint sc_mbar;
ushort sc_scr;
ushort sc_spr;
uint sc_pmr;
char res1[2];
ushort sc_alpr;
uint sc_dir;
char res2[12];
} sysctrl_t;
/* Interrupt module registers */
typedef struct int_ctrl {
uint int_icr1;
uint int_icr2;
uint int_icr3;
uint int_icr4;
uint int_isr;
uint int_pitr;
uint int_piwr;
uchar res1[3];
uchar int_pivr;
} intctrl_t;
/* Chip select module registers */
typedef struct cs_ctlr {
uint cs_br0;
uint cs_or0;
uint cs_br1;
uint cs_or1;
uint cs_br2;
uint cs_or2;
uint cs_br3;
uint cs_or3;
uint cs_br4;
uint cs_or4;
uint cs_br5;
uint cs_or5;
uint cs_br6;
uint cs_or6;
uint cs_br7;
uint cs_or7;
} csctrl_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
uint gpio_pacnt;
ushort gpio_paddr;
ushort gpio_padat;
uint gpio_pbcnt;
ushort gpio_pbddr;
ushort gpio_pbdat;
uchar res1[4];
ushort gpio_pcddr;
ushort gpio_pcdat;
uint gpio_pdcnt;
uchar res2[4];
} gpio_t;
/* DMA module registers */
typedef struct dma_ctrl {
ulong dma_dmr;
uchar res1[2];
ushort dma_dir;
ulong dma_dbcr;
ulong dma_dsar;
ulong dma_ddar;
uchar res2[12];
} dma_t;
/* SDRAM controller registers, offset: 0x180 */
typedef struct sdram_ctrl {
uchar res1[2];
ushort sdram_sdcr;
uchar res2[2];
ushort sdram_sdtr;
uchar res3[120];
} sdramctrl_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
ushort wdog_wrrr;
ushort res1;
ushort wdog_wirr;
ushort res2;
ushort wdog_wcr;
ushort res3;
ushort wdog_wer;
uchar res4[114];
} wdog_t;
/* PLIC module registers */
typedef struct plic_ctrl {
ulong plic_p0b1rr;
ulong plic_p1b1rr;
ulong plic_p2b1rr;
ulong plic_p3b1rr;
ulong plic_p0b2rr;
ulong plic_p1b2rr;
ulong plic_p2b2rr;
ulong plic_p3b2rr;
uchar plic_p0drr;
uchar plic_p1drr;
uchar plic_p2drr;
uchar plic_p3drr;
uchar res1[4];
ulong plic_p0b1tr;
ulong plic_p1b1tr;
ulong plic_p2b1tr;
ulong plic_p3b1tr;
ulong plic_p0b2tr;
ulong plic_p1b2tr;
ulong plic_p2b2tr;
ulong plic_p3b2tr;
uchar plic_p0dtr;
uchar plic_p1dtr;
uchar plic_p2dtr;
uchar plic_p3dtr;
uchar res2[4];
ushort plic_p0cr;
ushort plic_p1cr;
ushort plic_p2cr;
ushort plic_p3cr;
ushort plic_p0icr;
ushort plic_p1icr;
ushort plic_p2icr;
ushort plic_p3icr;
ushort plic_p0gmr;
ushort plic_p1gmr;
ushort plic_p2gmr;
ushort plic_p3gmr;
ushort plic_p0gmt;
ushort plic_p1gmt;
ushort plic_p2gmt;
ushort plic_p3gmt;
uchar res3;
uchar plic_pgmts;
uchar plic_pgmta;
uchar res4;
uchar plic_p0gcir;
uchar plic_p1gcir;
uchar plic_p2gcir;
uchar plic_p3gcir;
uchar plic_p0gcit;
uchar plic_p1gcit;
uchar plic_p2gcit;
uchar plic_p3gcit;
uchar res5[3];
uchar plic_pgcitsr;
uchar res6[3];
uchar plic_pdcsr;
ushort plic_p0psr;
ushort plic_p1psr;
ushort plic_p2psr;
ushort plic_p3psr;
ushort plic_pasr;
uchar res7;
uchar plic_plcr;
ushort res8;
ushort plic_pdrqr;
ushort plic_p0sdr;
ushort plic_p1sdr;
ushort plic_p2sdr;
ushort plic_p3sdr;
ushort res9;
ushort plic_pcsr;
uchar res10[1184];
} plic_t;
/* USB module registers */
typedef struct usb {
ushort res1;
ushort usb_fnr;
ushort res2;
ushort usb_fnmr;
ushort res3;
ushort usb_rfmr;
ushort res4;
ushort usb_rfmmr;
uchar res5[3];
uchar usb_far;
ulong usb_asr;
ulong usb_drr1;
ulong usb_drr2;
ushort res6;
ushort usb_specr;
ushort res7;
ushort usb_ep0sr;
ulong usb_iep0cfg;
ulong usb_oep0cfg;
ulong usb_ep1cfg;
ulong usb_ep2cfg;
ulong usb_ep3cfg;
ulong usb_ep4cfg;
ulong usb_ep5cfg;
ulong usb_ep6cfg;
ulong usb_ep7cfg;
ulong usb_ep0ctl;
ushort res8;
ushort usb_ep1ctl;
ushort res9;
ushort usb_ep2ctl;
ushort res10;
ushort usb_ep3ctl;
ushort res11;
ushort usb_ep4ctl;
ushort res12;
ushort usb_ep5ctl;
ushort res13;
ushort usb_ep6ctl;
ushort res14;
ushort usb_ep7ctl;
ulong usb_ep0isr;
ushort res15;
ushort usb_ep1isr;
ushort res16;
ushort usb_ep2isr;
ushort res17;
ushort usb_ep3isr;
ushort res18;
ushort usb_ep4isr;
ushort res19;
ushort usb_ep5isr;
ushort res20;
ushort usb_ep6isr;
ushort res21;
ushort usb_ep7isr;
ulong usb_ep0imr;
ushort res22;
ushort usb_ep1imr;
ushort res23;
ushort usb_ep2imr;
ushort res24;
ushort usb_ep3imr;
ushort res25;
ushort usb_ep4imr;
ushort res26;
ushort usb_ep5imr;
ushort res27;
ushort usb_ep6imr;
ushort res28;
ushort usb_ep7imr;
ulong usb_ep0dr;
ulong usb_ep1dr;
ulong usb_ep2dr;
ulong usb_ep3dr;
ulong usb_ep4dr;
ulong usb_ep5dr;
ulong usb_ep6dr;
ulong usb_ep7dr;
ushort res29;
ushort usb_ep0dpr;
ushort res30;
ushort usb_ep1dpr;
ushort res31;
ushort usb_ep2dpr;
ushort res32;
ushort usb_ep3dpr;
ushort res33;
ushort usb_ep4dpr;
ushort res34;
ushort usb_ep5dpr;
ushort res35;
ushort usb_ep6dpr;
ushort res36;
ushort usb_ep7dpr;
uchar res37[788];
uchar usb_cfgram[1024];
} usb_t;
#endif /* __IMMAP_5272__ */

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u-boot/arch/m68k/include/asm/immap_5275.h Normal file
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/*
* MCF5274/5 Internal Memory Map
*
* Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
* Based on work Copyright (c) 2003 Josef Baumgartner
* <josef.baumgartner@telex.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5275__
#define __IMMAP_5275__
#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000)
#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400)
#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800)
#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000)
#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004)
#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000)
#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/rng.h>
#include <asm/coldfire/skha.h>
/* System configuration registers
*/
typedef struct sys_ctrl {
u32 ipsbar;
u32 res1;
u32 rambar;
u32 res2;
u8 crsr;
u8 cwcr;
u8 lpicr;
u8 cwsr;
u8 res3[8];
u32 mpark;
u8 mpr;
u8 res4[3];
u8 pacr0;
u8 pacr1;
u8 pacr2;
u8 pacr3;
u8 pacr4;
u8 res5;
u8 pacr5;
u8 pacr6;
u8 pacr7;
u8 res6;
u8 pacr8;
u8 res7;
u8 gpacr;
u8 res8[3];
} sysctrl_t;
/* SDRAM controller registers, offset: 0x040
*/
typedef struct sdram_ctrl {
u32 sdmr;
u32 sdcr;
u32 sdcfg1;
u32 sdcfg2;
u32 sdbar0;
u32 sdbmr0;
u32 sdbar1;
u32 sdbmr1;
} sdramctrl_t;
/* DMA module registers, offset 0x100
*/
typedef struct dma_ctrl {
u32 sar;
u32 dar;
u32 dsrbcr;
u32 dcr;
} dma_t;
/* GPIO port registers
*/
typedef struct gpio_ctrl {
/* Port Output Data Registers */
u8 podr_res1[4];
u8 podr_busctl;
u8 podr_addr;
u8 podr_res2[2];
u8 podr_cs;
u8 podr_res3;
u8 podr_fec0h;
u8 podr_fec0l;
u8 podr_feci2c;
u8 podr_qspi;
u8 podr_sdram;
u8 podr_timerh;
u8 podr_timerl;
u8 podr_uartl;
u8 podr_fec1h;
u8 podr_fec1l;
u8 podr_bs;
u8 podr_res4;
u8 podr_usbh;
u8 podr_usbl;
u8 podr_uarth;
u8 podr_res5[3];
/* Port Data Direction Registers */
u8 pddr_res1[4];
u8 pddr_busctl;
u8 pddr_addr;
u8 pddr_res2[2];
u8 pddr_cs;
u8 pddr_res3;
u8 pddr_fec0h;
u8 pddr_fec0l;
u8 pddr_feci2c;
u8 pddr_qspi;
u8 pddr_sdram;
u8 pddr_timerh;
u8 pddr_timerl;
u8 pddr_uartl;
u8 pddr_fec1h;
u8 pddr_fec1l;
u8 pddr_bs;
u8 pddr_res4;
u8 pddr_usbh;
u8 pddr_usbl;
u8 pddr_uarth;
u8 pddr_res5[3];
/* Port Pin Data/Set Registers */
u8 ppdsdr_res1[4];
u8 ppdsdr_busctl;
u8 ppdsdr_addr;
u8 ppdsdr_res2[2];
u8 ppdsdr_cs;
u8 ppdsdr_res3;
u8 ppdsdr_fec0h;
u8 ppdsdr_fec0l;
u8 ppdsdr_feci2c;
u8 ppdsdr_qspi;
u8 ppdsdr_sdram;
u8 ppdsdr_timerh;
u8 ppdsdr_timerl;
u8 ppdsdr_uartl;
u8 ppdsdr_fec1h;
u8 ppdsdr_fec1l;
u8 ppdsdr_bs;
u8 ppdsdr_res4;
u8 ppdsdr_usbh;
u8 ppdsdr_usbl;
u8 ppdsdr_uarth;
u8 ppdsdr_res5[3];
/* Port Clear Output Data Registers */
u8 pclrr_res1[4];
u8 pclrr_busctl;
u8 pclrr_addr;
u8 pclrr_res2[2];
u8 pclrr_cs;
u8 pclrr_res3;
u8 pclrr_fec0h;
u8 pclrr_fec0l;
u8 pclrr_feci2c;
u8 pclrr_qspi;
u8 pclrr_sdram;
u8 pclrr_timerh;
u8 pclrr_timerl;
u8 pclrr_uartl;
u8 pclrr_fec1h;
u8 pclrr_fec1l;
u8 pclrr_bs;
u8 pclrr_res4;
u8 pclrr_usbh;
u8 pclrr_usbl;
u8 pclrr_uarth;
u8 pclrr_res5[3];
/* Pin Assignment Registers */
u8 par_addr;
u8 par_cs;
u16 par_busctl;
u8 par_res1[2];
u16 par_usb;
u8 par_fec0hl;
u8 par_fec1hl;
u16 par_timer;
u16 par_uart;
u16 par_qspi;
u16 par_sdram;
u16 par_feci2c;
u8 par_bs;
u8 par_res2[3];
} gpio_t;
/* Watchdog registers
*/
typedef struct wdog_ctrl {
u16 wcr;
u16 wmr;
u16 wcntr;
u16 wsr;
u8 res4[114];
} wdog_t;
/* USB module registers
*/
typedef struct usb {
u16 res1;
u16 fnr;
u16 res2;
u16 fnmr;
u16 res3;
u16 rfmr;
u16 res4;
u16 rfmmr;
u8 res5[3];
u8 far;
u32 asr;
u32 drr1;
u32 drr2;
u16 res6;
u16 specr;
u16 res7;
u16 ep0sr;
u32 iep0cfg;
u32 oep0cfg;
u32 ep1cfg;
u32 ep2cfg;
u32 ep3cfg;
u32 ep4cfg;
u32 ep5cfg;
u32 ep6cfg;
u32 ep7cfg;
u32 ep0ctl;
u16 res8;
u16 ep1ctl;
u16 res9;
u16 ep2ctl;
u16 res10;
u16 ep3ctl;
u16 res11;
u16 ep4ctl;
u16 res12;
u16 ep5ctl;
u16 res13;
u16 ep6ctl;
u16 res14;
u16 ep7ctl;
u32 ep0isr;
u16 res15;
u16 ep1isr;
u16 res16;
u16 ep2isr;
u16 res17;
u16 ep3isr;
u16 res18;
u16 ep4isr;
u16 res19;
u16 ep5isr;
u16 res20;
u16 ep6isr;
u16 res21;
u16 ep7isr;
u32 ep0imr;
u16 res22;
u16 ep1imr;
u16 res23;
u16 ep2imr;
u16 res24;
u16 ep3imr;
u16 res25;
u16 ep4imr;
u16 res26;
u16 ep5imr;
u16 res27;
u16 ep6imr;
u16 res28;
u16 ep7imr;
u32 ep0dr;
u32 ep1dr;
u32 ep2dr;
u32 ep3dr;
u32 ep4dr;
u32 ep5dr;
u32 ep6dr;
u32 ep7dr;
u16 res29;
u16 ep0dpr;
u16 res30;
u16 ep1dpr;
u16 res31;
u16 ep2dpr;
u16 res32;
u16 ep3dpr;
u16 res33;
u16 ep4dpr;
u16 res34;
u16 ep5dpr;
u16 res35;
u16 ep6dpr;
u16 res36;
u16 ep7dpr;
u8 res37[788];
u8 cfgram[1024];
} usb_t;
/* PLL module registers
*/
typedef struct pll_ctrl {
u32 syncr;
u32 synsr;
} pll_t;
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
#endif /* __IMMAP_5275__ */

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/*
* MCF5282 Internal Memory Map
*
* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5282__
#define __IMMAP_5282__
#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140)
#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180)
#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000)
#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000)
#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
#define MMAP_QADC (CONFIG_SYS_MBAR + 0x00190000)
#define MMAP_GPTMRA (CONFIG_SYS_MBAR + 0x001A0000)
#define MMAP_GPTMRB (CONFIG_SYS_MBAR + 0x001B0000)
#define MMAP_CAN (CONFIG_SYS_MBAR + 0x001C0000)
#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/qspi.h>
/* System Control Module */
typedef struct scm_ctrl {
u32 ipsbar;
u32 res1;
u32 rambar;
u32 res2;
u8 crsr;
u8 cwcr;
u8 lpicr;
u8 cwsr;
u32 res3;
u8 mpark;
u8 res4[3];
u8 pacr0;
u8 pacr1;
u8 pacr2;
u8 pacr3;
u8 pacr4;
u8 res5;
u8 pacr5;
u8 pacr6;
u8 pacr7;
u8 res6;
u8 pacr8;
u8 res7;
u8 gpacr0;
u8 gpacr1;
u16 res8;
} scm_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u16 syncr; /* 0x00 synthesizer control register */
u16 synsr; /* 0x02 synthesizer status register */
} pll_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
ushort wcr;
ushort wmr;
ushort wcntr;
ushort wsr;
} wdog_t;
#endif /* __IMMAP_5282__ */

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/*
* MCF5301x Internal Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5301X__
#define __IMMAP_5301X__
#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000)
#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000)
#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000)
#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000)
#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000)
#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000)
#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000)
#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000)
#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000)
#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000)
#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000)
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000)
#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000)
#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000)
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/ssi.h>
#include <asm/coldfire/rng.h>
#include <asm/rtc.h>
/* System Controller Module */
typedef struct scm1 {
u32 mpr; /* 0x00 Master Privilege */
u32 rsvd1[7];
u32 pacra; /* 0x20 Peripheral Access Ctrl A */
u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
u32 rsvd2[4];
u32 pacre; /* 0x40 Peripheral Access Ctrl E */
u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
u32 pacrg; /* 0x48 Peripheral Access Ctrl G */
} scm1_t;
typedef struct scm2 {
u8 rsvd1[19]; /* 0x00 - 0x12 */
u8 wcr; /* 0x13 */
u16 rsvd2; /* 0x14 - 0x15 */
u16 cwcr; /* 0x16 */
u8 rsvd3[3]; /* 0x18 - 0x1A */
u8 cwsr; /* 0x1B */
u8 rsvd4[3]; /* 0x1C - 0x1E */
u8 scmisr; /* 0x1F */
u32 rsvd5; /* 0x20 - 0x23 */
u8 bcr; /* 0x24 */
u8 rsvd6[74]; /* 0x25 - 0x6F */
u32 cfadr; /* 0x70 */
u8 rsvd7; /* 0x74 */
u8 cfier; /* 0x75 */
u8 cfloc; /* 0x76 */
u8 cfatr; /* 0x77 */
u32 rsvd8; /* 0x78 - 0x7B */
u32 cfdtr; /* 0x7C */
} scm2_t;
/* PWM module */
typedef struct pwm_ctrl {
u8 en; /* 0x00 PWM Enable */
u8 pol; /* 0x01 Polarity */
u8 clk; /* 0x02 Clock Select */
u8 prclk; /* 0x03 Prescale Clock Select */
u8 cae; /* 0x04 Center Align Enable */
u8 ctl; /* 0x05 Ctrl */
u8 res1[2]; /* 0x06 - 0x07 */
u8 scla; /* 0x08 Scale A */
u8 sclb; /* 0x09 Scale B */
u8 res2[2]; /* 0x0A - 0x0B */
u8 cnt0; /* 0x0C Channel 0 Counter */
u8 cnt1; /* 0x0D Channel 1 Counter */
u8 cnt2; /* 0x0E Channel 2 Counter */
u8 cnt3; /* 0x0F Channel 3 Counter */
u8 cnt4; /* 0x10 Channel 4 Counter */
u8 cnt5; /* 0x11 Channel 5 Counter */
u8 cnt6; /* 0x12 Channel 6 Counter */
u8 cnt7; /* 0x13 Channel 7 Counter */
u8 per0; /* 0x14 Channel 0 Period */
u8 per1; /* 0x15 Channel 1 Period */
u8 per2; /* 0x16 Channel 2 Period */
u8 per3; /* 0x17 Channel 3 Period */
u8 per4; /* 0x18 Channel 4 Period */
u8 per5; /* 0x19 Channel 5 Period */
u8 per6; /* 0x1A Channel 6 Period */
u8 per7; /* 0x1B Channel 7 Period */
u8 dty0; /* 0x1C Channel 0 Duty */
u8 dty1; /* 0x1D Channel 1 Duty */
u8 dty2; /* 0x1E Channel 2 Duty */
u8 dty3; /* 0x1F Channel 3 Duty */
u8 dty4; /* 0x20 Channel 4 Duty */
u8 dty5; /* 0x21 Channel 5 Duty */
u8 dty6; /* 0x22 Channel 6 Duty */
u8 dty7; /* 0x23 Channel 7 Duty */
u8 sdn; /* 0x24 Shutdown */
u8 res3[3]; /* 0x25 - 0x27 */
} pwm_t;
/* Chip configuration module */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
typedef struct ccm_ctrl {
u16 ccr; /* 0x00 Chip Cfg */
u16 res1; /* 0x02 */
u16 rcon; /* 0x04 Reset Cfg */
u16 cir; /* 0x06 Chip ID */
u32 res2; /* 0x08 */
u16 misccr; /* 0x0A Misc Ctrl */
u16 cdr; /* 0x0C Clock divider */
u16 uhcsr; /* 0x10 USB Host status */
u16 uocsr; /* 0x12 USB On-the-Go Status */
u16 res3; /* 0x14 */
u16 codeccr; /* 0x16 Codec Control */
u16 misccr2; /* 0x18 Misc2 Ctrl */
} ccm_t;
/* GPIO port */
typedef struct gpio_ctrl {
/* Port Output Data */
u8 podr_fbctl; /* 0x00 */
u8 podr_be; /* 0x01 */
u8 podr_cs; /* 0x02 */
u8 podr_dspi; /* 0x03 */
u8 res01; /* 0x04 */
u8 podr_fec0; /* 0x05 */
u8 podr_feci2c; /* 0x06 */
u8 res02[2]; /* 0x07 - 0x08 */
u8 podr_simp1; /* 0x09 */
u8 podr_simp0; /* 0x0A */
u8 podr_timer; /* 0x0B */
u8 podr_uart; /* 0x0C */
u8 podr_debug; /* 0x0D */
u8 res03; /* 0x0E */
u8 podr_sdhc; /* 0x0F */
u8 podr_ssi; /* 0x10 */
u8 res04[3]; /* 0x11 - 0x13 */
/* Port Data Direction */
u8 pddr_fbctl; /* 0x14 */
u8 pddr_be; /* 0x15 */
u8 pddr_cs; /* 0x16 */
u8 pddr_dspi; /* 0x17 */
u8 res05; /* 0x18 */
u8 pddr_fec0; /* 0x19 */
u8 pddr_feci2c; /* 0x1A */
u8 res06[2]; /* 0x1B - 0x1C */
u8 pddr_simp1; /* 0x1D */
u8 pddr_simp0; /* 0x1E */
u8 pddr_timer; /* 0x1F */
u8 pddr_uart; /* 0x20 */
u8 pddr_debug; /* 0x21 */
u8 res07; /* 0x22 */
u8 pddr_sdhc; /* 0x23 */
u8 pddr_ssi; /* 0x24 */
u8 res08[3]; /* 0x25 - 0x27 */
/* Port Data Direction */
u8 ppdr_fbctl; /* 0x28 */
u8 ppdr_be; /* 0x29 */
u8 ppdr_cs; /* 0x2A */
u8 ppdr_dspi; /* 0x2B */
u8 res09; /* 0x2C */
u8 ppdr_fec0; /* 0x2D */
u8 ppdr_feci2c; /* 0x2E */
u8 res10[2]; /* 0x2F - 0x30 */
u8 ppdr_simp1; /* 0x31 */
u8 ppdr_simp0; /* 0x32 */
u8 ppdr_timer; /* 0x33 */
u8 ppdr_uart; /* 0x34 */
u8 ppdr_debug; /* 0x35 */
u8 res11; /* 0x36 */
u8 ppdr_sdhc; /* 0x37 */
u8 ppdr_ssi; /* 0x38 */
u8 res12[3]; /* 0x39 - 0x3B */
/* Port Clear Output Data */
u8 pclrr_fbctl; /* 0x3C */
u8 pclrr_be; /* 0x3D */
u8 pclrr_cs; /* 0x3E */
u8 pclrr_dspi; /* 0x3F */
u8 res13; /* 0x40 */
u8 pclrr_fec0; /* 0x41 */
u8 pclrr_feci2c; /* 0x42 */
u8 res14[2]; /* 0x43 - 0x44 */
u8 pclrr_simp1; /* 0x45 */
u8 pclrr_simp0; /* 0x46 */
u8 pclrr_timer; /* 0x47 */
u8 pclrr_uart; /* 0x48 */
u8 pclrr_debug; /* 0x49 */
u8 res15; /* 0x4A */
u8 pclrr_sdhc; /* 0x4B */
u8 pclrr_ssi; /* 0x4C */
u8 res16[3]; /* 0x4D - 0x4F */
/* Pin Assignment */
u8 par_fbctl; /* 0x50 */
u8 par_be; /* 0x51 */
u8 par_cs; /* 0x52 */
u8 res17; /* 0x53 */
u8 par_dspih; /* 0x54 */
u8 par_dspil; /* 0x55 */
u8 par_fec; /* 0x56 */
u8 par_feci2c; /* 0x57 */
u8 par_irq0h; /* 0x58 */
u8 par_irq0l; /* 0x59 */
u8 par_irq1h; /* 0x5A */
u8 par_irq1l; /* 0x5B */
u8 par_simp1h; /* 0x5C */
u8 par_simp1l; /* 0x5D */
u8 par_simp0; /* 0x5E */
u8 par_timer; /* 0x5F */
u8 par_uart; /* 0x60 */
u8 res18; /* 0x61 */
u8 par_debug; /* 0x62 */
u8 par_sdhc; /* 0x63 */
u8 par_ssih; /* 0x64 */
u8 par_ssil; /* 0x65 */
u8 res19[2]; /* 0x66 - 0x67 */
/* Mode Select Control */
/* Drive Strength Control */
u8 mscr_mscr1; /* 0x68 */
u8 mscr_mscr2; /* 0x69 */
u8 mscr_mscr3; /* 0x6A */
u8 mscr_mscr45; /* 0x6B */
u8 srcr_dspi; /* 0x6C */
u8 dscr_fec; /* 0x6D */
u8 srcr_i2c; /* 0x6E */
u8 srcr_irq; /* 0x6F */
u8 srcr_sim; /* 0x70 */
u8 srcr_timer; /* 0x71 */
u8 srcr_uart; /* 0x72 */
u8 res20; /* 0x73 */
u8 srcr_sdhc; /* 0x74 */
u8 srcr_ssi; /* 0x75 */
u8 res21[2]; /* 0x76 - 0x77 */
u8 pcr_pcrh; /* 0x78 */
u8 pcr_pcrl; /* 0x79 */
} gpio_t;
/* SDRAM controller */
typedef struct sdram_ctrl {
u32 mode; /* 0x00 Mode/Extended Mode */
u32 ctrl; /* 0x04 Ctrl */
u32 cfg1; /* 0x08 Cfg 1 */
u32 cfg2; /* 0x0C Cfg 2 */
u32 res1[64]; /* 0x10 - 0x10F */
u32 cs0; /* 0x110 Chip Select 0 Cfg */
u32 cs1; /* 0x114 Chip Select 1 Cfg */
} sdram_t;
/* Clock Module */
typedef struct pll_ctrl {
u32 pcr; /* 0x00 Ctrl */
u32 pdr; /* 0x04 Divider */
u32 psr; /* 0x08 Status */
} pll_t;
typedef struct rtcex {
u32 rsvd1[3];
u32 gocu;
u32 gocl;
} rtcex_t;
#endif /* __IMMAP_5301X__ */

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/*
* (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
#ifndef __IMMAP_5307__
#define __IMMAP_5307__
#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244)
typedef struct sim {
u8 rsr;
u8 sypcr;
u8 swivr;
u8 swsr;
u16 par;
u8 irqpar;
u8 res1;
u8 pllcr;
u8 res2;
u16 res3;
u8 mpark;
u8 res4;
u16 res5;
u32 res6;
} sim_t;
typedef struct intctrl {
u32 ipr;
u32 imr;
u16 res7;
u8 res8;
u8 avr;
u8 icr0;
u8 icr1;
u8 icr2;
u8 icr3;
u8 icr4;
u8 icr5;
u8 icr6;
u8 icr7;
u8 icr8;
u8 icr9;
u16 res9;
} intctrl_t;
typedef struct csm {
u16 csar0; /* Chip-select Address */
u16 res1;
u32 csmr0; /* Chip-select Mask */
u16 res2;
u16 cscr0; /* Chip-select Control */
u16 csar1;
u16 res3;
u32 csmr1;
u16 res4;
u16 cscr1;
u16 csar2;
u16 res5;
u32 csmr2;
u16 res6;
u16 cscr2;
u16 csar3;
u16 res7;
u32 csmr3;
u16 res8;
u16 cscr3;
u16 csar4;
u16 res9;
u32 csmr4;
u16 res10;
u16 cscr4;
u16 csar5;
u16 res11;
u32 csmr5;
u16 res12;
u16 cscr5;
u16 csar6;
u16 res13;
u32 csmr6;
u16 res14;
u16 cscr6;
u16 csar7;
u16 res15;
u32 csmr7;
u16 res16;
u16 cscr7;
} csm_t;
typedef struct sdramctrl {
u16 dcr;
u16 res1;
u32 res2;
u32 dacr0;
u32 dmr0;
u32 dacr1;
u32 dmr1;
} sdramctrl_t;
typedef struct gpio {
u16 paddr;
u16 res1;
u16 padat;
u16 res2;
} gpio_t;
#endif /* __IMMAP_5307__ */

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/*
* MCF5329 Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5329__
#define __IMMAP_5329__
#define MMAP_SCM1 0xEC000000
#define MMAP_MDHA 0xEC080000
#define MMAP_SKHA 0xEC084000
#define MMAP_RNG 0xEC088000
#define MMAP_SCM2 0xFC000000
#define MMAP_XBS 0xFC004000
#define MMAP_FBCS 0xFC008000
#define MMAP_CAN 0xFC020000
#define MMAP_FEC 0xFC030000
#define MMAP_SCM3 0xFC040000
#define MMAP_EDMA 0xFC044000
#define MMAP_TCD 0xFC045000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
#define MMAP_INTCACK 0xFC054000
#define MMAP_I2C 0xFC058000
#define MMAP_QSPI 0xFC05C000
#define MMAP_UART0 0xFC060000
#define MMAP_UART1 0xFC064000
#define MMAP_UART2 0xFC068000
#define MMAP_DTMR0 0xFC070000
#define MMAP_DTMR1 0xFC074000
#define MMAP_DTMR2 0xFC078000
#define MMAP_DTMR3 0xFC07C000
#define MMAP_PIT0 0xFC080000
#define MMAP_PIT1 0xFC084000
#define MMAP_PIT2 0xFC088000
#define MMAP_PIT3 0xFC08C000
#define MMAP_PWM 0xFC090000
#define MMAP_EPORT 0xFC094000
#define MMAP_WDOG 0xFC098000
#define MMAP_RCM 0xFC0A0000
#define MMAP_CCM 0xFC0A0004
#define MMAP_GPIO 0xFC0A4000
#define MMAP_RTC 0xFC0A8000
#define MMAP_LCDC 0xFC0AC000
#define MMAP_USBOTG 0xFC0B0000
#define MMAP_USBH 0xFC0B4000
#define MMAP_SDRAM 0xFC0B8000
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C0000
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/ssi.h>
#include <asm/coldfire/skha.h>
/* System control module registers */
typedef struct scm1_ctrl {
u32 mpr0; /* 0x00 Master Privilege Register 0 */
u32 res1[15]; /* 0x04 - 0x3F */
u32 pacrh; /* 0x40 Peripheral Access Control Register H */
u32 res2[3]; /* 0x44 - 0x53 */
u32 bmt0; /*0x54 Bus Monitor Timeout 0 */
} scm1_t;
/* System control module registers 2 */
typedef struct scm2_ctrl {
u32 mpr1; /* 0x00 Master Privilege Register */
u32 res1[7]; /* 0x04 - 0x1F */
u32 pacra; /* 0x20 Peripheral Access Control Register A */
u32 pacrb; /* 0x24 Peripheral Access Control Register B */
u32 pacrc; /* 0x28 Peripheral Access Control Register C */
u32 pacrd; /* 0x2C Peripheral Access Control Register D */
u32 res2[4]; /* 0x30 - 0x3F */
u32 pacre; /* 0x40 Peripheral Access Control Register E */
u32 pacrf; /* 0x44 Peripheral Access Control Register F */
u32 pacrg; /* 0x48 Peripheral Access Control Register G */
u32 res3[2]; /* 0x4C - 0x53 */
u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
} scm2_t;
/* System Control Module register 3 */
typedef struct scm3_ctrl {
u8 res1[19]; /* 0x00 - 0x12 */
u8 wcr; /* 0x13 wakeup control register */
u16 res2; /* 0x14 - 0x15 */
u16 cwcr; /* 0x16 Core Watchdog Control Register */
u8 res3[3]; /* 0x18 - 0x1A */
u8 cwsr; /* 0x1B Core Watchdog Service Register */
u8 res4[2]; /* 0x1C - 0x1D */
u8 scmisr; /* 0x1F Interrupt Status Register */
u32 res5; /* 0x20 */
u32 bcr; /* 0x24 Burst Configuration Register */
u32 res6[18]; /* 0x28 - 0x6F */
u32 cfadr; /* 0x70 Core Fault Address Register */
u8 res7[4]; /* 0x71 - 0x74 */
u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */
u8 cfloc; /* 0x76 Core Fault Location Register */
u8 cfatr; /* 0x77 Core Fault Attributes Register */
u32 res8; /* 0x78 */
u32 cfdtr; /* 0x7C Core Fault Data Register */
} scm3_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
u16 cr; /* 0x00 Control register */
u16 mr; /* 0x02 Modulus register */
u16 cntr; /* 0x04 Count register */
u16 sr; /* 0x06 Service register */
} wdog_t;
/*Chip configuration module registers */
typedef struct ccm_ctrl {
u16 ccr; /* 0x00 Chip configuration register */
u16 res2; /* 0x02 */
u16 rcon; /* 0x04 Rreset configuration register */
u16 cir; /* 0x06 Chip identification register */
u32 res3; /* 0x08 */
u16 misccr; /* 0x0A Miscellaneous control register */
u16 cdr; /* 0x0C Clock divider register */
u16 uhcsr; /* 0x10 USB Host controller status register */
u16 uocsr; /* 0x12 USB On-the-Go Controller Status Reg */
} ccm_t;
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */
#ifdef CONFIG_M5329
u8 podr_fech; /* 0x00 */
u8 podr_fecl; /* 0x01 */
#else
u16 res00; /* 0x00 - 0x01 */
#endif
u8 podr_ssi; /* 0x02 */
u8 podr_busctl; /* 0x03 */
u8 podr_be; /* 0x04 */
u8 podr_cs; /* 0x05 */
u8 podr_pwm; /* 0x06 */
u8 podr_feci2c; /* 0x07 */
u8 res08; /* 0x08 */
u8 podr_uart; /* 0x09 */
u8 podr_qspi; /* 0x0A */
u8 podr_timer; /* 0x0B */
#ifdef CONFIG_M5329
u8 res0C; /* 0x0C */
u8 podr_lcddatah; /* 0x0D */
u8 podr_lcddatam; /* 0x0E */
u8 podr_lcddatal; /* 0x0F */
u8 podr_lcdctlh; /* 0x10 */
u8 podr_lcdctll; /* 0x11 */
#else
u16 res0C; /* 0x0C - 0x0D */
u8 podr_fech; /* 0x0E */
u8 podr_fecl; /* 0x0F */
u16 res10[3]; /* 0x10 - 0x15 */
#endif
/* Port Data Direction Registers */
#ifdef CONFIG_M5329
u16 res12; /* 0x12 - 0x13 */
u8 pddr_fech; /* 0x14 */
u8 pddr_fecl; /* 0x15 */
#endif
u8 pddr_ssi; /* 0x16 */
u8 pddr_busctl; /* 0x17 */
u8 pddr_be; /* 0x18 */
u8 pddr_cs; /* 0x19 */
u8 pddr_pwm; /* 0x1A */
u8 pddr_feci2c; /* 0x1B */
u8 res1C; /* 0x1C */
u8 pddr_uart; /* 0x1D */
u8 pddr_qspi; /* 0x1E */
u8 pddr_timer; /* 0x1F */
#ifdef CONFIG_M5329
u8 res20; /* 0x20 */
u8 pddr_lcddatah; /* 0x21 */
u8 pddr_lcddatam; /* 0x22 */
u8 pddr_lcddatal; /* 0x23 */
u8 pddr_lcdctlh; /* 0x24 */
u8 pddr_lcdctll; /* 0x25 */
u16 res26; /* 0x26 - 0x27 */
#else
u16 res20; /* 0x20 - 0x21 */
u8 pddr_fech; /* 0x22 */
u8 pddr_fecl; /* 0x23 */
u16 res24[3]; /* 0x24 - 0x29 */
#endif
/* Port Data Direction Registers */
#ifdef CONFIG_M5329
u8 ppd_fech; /* 0x28 */
u8 ppd_fecl; /* 0x29 */
#endif
u8 ppd_ssi; /* 0x2A */
u8 ppd_busctl; /* 0x2B */
u8 ppd_be; /* 0x2C */
u8 ppd_cs; /* 0x2D */
u8 ppd_pwm; /* 0x2E */
u8 ppd_feci2c; /* 0x2F */
u8 res30; /* 0x30 */
u8 ppd_uart; /* 0x31 */
u8 ppd_qspi; /* 0x32 */
u8 ppd_timer; /* 0x33 */
#ifdef CONFIG_M5329
u8 res34; /* 0x34 */
u8 ppd_lcddatah; /* 0x35 */
u8 ppd_lcddatam; /* 0x36 */
u8 ppd_lcddatal; /* 0x37 */
u8 ppd_lcdctlh; /* 0x38 */
u8 ppd_lcdctll; /* 0x39 */
u16 res3A; /* 0x3A - 0x3B */
#else
u16 res34; /* 0x34 - 0x35 */
u8 ppd_fech; /* 0x36 */
u8 ppd_fecl; /* 0x37 */
u16 res38[3]; /* 0x38 - 0x3D */
#endif
/* Port Clear Output Data Registers */
#ifdef CONFIG_M5329
u8 res3C; /* 0x3C */
u8 pclrr_fech; /* 0x3D */
u8 pclrr_fecl; /* 0x3E */
#else
u8 pclrr_ssi; /* 0x3E */
#endif
u8 pclrr_busctl; /* 0x3F */
u8 pclrr_be; /* 0x40 */
u8 pclrr_cs; /* 0x41 */
u8 pclrr_pwm; /* 0x42 */
u8 pclrr_feci2c; /* 0x43 */
u8 res44; /* 0x44 */
u8 pclrr_uart; /* 0x45 */
u8 pclrr_qspi; /* 0x46 */
u8 pclrr_timer; /* 0x47 */
#ifdef CONFIG_M5329
u8 pclrr_lcddatah; /* 0x48 */
u8 pclrr_lcddatam; /* 0x49 */
u8 pclrr_lcddatal; /* 0x4A */
u8 pclrr_ssi; /* 0x4B */
u8 pclrr_lcdctlh; /* 0x4C */
u8 pclrr_lcdctll; /* 0x4D */
u16 res4E; /* 0x4E - 0x4F */
#else
u16 res48; /* 0x48 - 0x49 */
u8 pclrr_fech; /* 0x4A */
u8 pclrr_fecl; /* 0x4B */
u8 res4C[5]; /* 0x4C - 0x50 */
#endif
/* Pin Assignment Registers */
#ifdef CONFIG_M5329
u8 par_fec; /* 0x50 */
#endif
u8 par_pwm; /* 0x51 */
u8 par_busctl; /* 0x52 */
u8 par_feci2c; /* 0x53 */
u8 par_be; /* 0x54 */
u8 par_cs; /* 0x55 */
u16 par_ssi; /* 0x56 */
u16 par_uart; /* 0x58 */
u16 par_qspi; /* 0x5A */
u8 par_timer; /* 0x5C */
#ifdef CONFIG_M5329
u8 par_lcddata; /* 0x5D */
u16 par_lcdctl; /* 0x5E */
#else
u8 par_fec; /* 0x5D */
u16 res5E; /* 0x5E - 0x5F */
#endif
u16 par_irq; /* 0x60 */
u16 res62; /* 0x62 - 0x63 */
/* Mode Select Control Registers */
u8 mscr_flexbus; /* 0x64 */
u8 mscr_sdram; /* 0x65 */
u16 res66; /* 0x66 - 0x67 */
/* Drive Strength Control Registers */
u8 dscr_i2c; /* 0x68 */
u8 dscr_pwm; /* 0x69 */
u8 dscr_fec; /* 0x6A */
u8 dscr_uart; /* 0x6B */
u8 dscr_qspi; /* 0x6C */
u8 dscr_timer; /* 0x6D */
u8 dscr_ssi; /* 0x6E */
#ifdef CONFIG_M5329
u8 dscr_lcd; /* 0x6F */
#else
u8 res6F; /* 0x6F */
#endif
u8 dscr_debug; /* 0x70 */
u8 dscr_clkrst; /* 0x71 */
u8 dscr_irq; /* 0x72 */
} gpio_t;
/* USB OTG module registers */
typedef struct usb_otg {
u32 id; /* 0x000 Identification Register */
u32 hwgeneral; /* 0x004 General HW Parameters */
u32 hwhost; /* 0x008 Host HW Parameters */
u32 hwdev; /* 0x00C Device HW parameters */
u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
u32 res1[58]; /* 0x18 - 0xFF */
u8 caplength; /* 0x100 Capability Register Length */
u8 res2; /* 0x101 */
u16 hciver; /* 0x102 Host Interface Version Number */
u32 hcsparams; /* 0x104 Host Structural Parameters */
u32 hccparams; /* 0x108 Host Capability Parameters */
u32 res3[5]; /* 0x10C - 0x11F */
u16 dciver; /* 0x120 Device Interface Version Number */
u16 res4; /* 0x122 */
u32 dccparams; /* 0x124 Device Capability Parameters */
u32 res5[6]; /* 0x128 - 0x13F */
u32 cmd; /* 0x140 USB Command */
u32 sts; /* 0x144 USB Status */
u32 intr; /* 0x148 USB Interrupt Enable */
u32 frindex; /* 0x14C USB Frame Index */
u32 res6; /* 0x150 */
u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */
u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */
u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */
u32 burstsize; /* 0x160 Master Interface Data Burst Size */
u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */
u32 res7[6]; /* 0x168 - 0x17F */
u32 cfgflag; /* 0x180 Configure Flag Register */
u32 portsc1; /* 0x184 Port Status/Control */
u32 res8[7]; /* 0x188 - 0x1A3 */
u32 otgsc; /* 0x1A4 On The Go Status and Control */
u32 mode; /* 0x1A8 USB mode register */
u32 eptsetstat; /* 0x1AC Endpoint Setup status */
u32 eptprime; /* 0x1B0 Endpoint initialization */
u32 eptflush; /* 0x1B4 Endpoint de-initialize */
u32 eptstat; /* 0x1B8 Endpoint status */
u32 eptcomplete; /* 0x1BC Endpoint Complete */
u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
u32 eptctrl3; /* 0x1CC Endpoint control 3 */
} usbotg_t;
/* SDRAM controller registers */
typedef struct sdram_ctrl {
u32 mode; /* 0x00 Mode/Extended Mode register */
u32 ctrl; /* 0x04 Control register */
u32 cfg1; /* 0x08 Configuration register 1 */
u32 cfg2; /* 0x0C Configuration register 2 */
u32 res1[64]; /* 0x10 - 0x10F */
u32 cs0; /* 0x110 Chip Select 0 Configuration */
u32 cs1; /* 0x114 Chip Select 1 Configuration */
} sdram_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u8 podr; /* 0x00 Output Divider Register */
u8 res1[3];
u8 pcr; /* 0x04 Control Register */
u8 res2[3];
u8 pmdr; /* 0x08 Modulation Divider Register */
u8 res3[3];
u8 pfdr; /* 0x0C Feedback Divider Register */
u8 res4[3];
} pll_t;
#endif /* __IMMAP_5329__ */

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/*
* MCF5441x Internal Memory Map
*
* Copyright 2010-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5441X__
#define __IMMAP_5441X__
/* Module Base Addresses */
#define MMAP_XBS 0xFC004000
#define MMAP_FBCS 0xFC008000
#define MMAP_CAN0 0xFC020000
#define MMAP_CAN1 0xFC024000
#define MMAP_I2C1 0xFC038000
#define MMAP_DSPI1 0xFC03C000
#define MMAP_SCM 0xFC040000
#define MMAP_PM 0xFC04002C
#define MMAP_EDMA 0xFC044000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
#define MMAP_INTC2 0xFC050000
#define MMAP_IACK 0xFC054000
#define MMAP_I2C0 0xFC058000
#define MMAP_DSPI0 0xFC05C000
#define MMAP_UART0 0xFC060000
#define MMAP_UART1 0xFC064000
#define MMAP_UART2 0xFC068000
#define MMAP_UART3 0xFC06C000
#define MMAP_DTMR0 0xFC070000
#define MMAP_DTMR1 0xFC074000
#define MMAP_DTMR2 0xFC078000
#define MMAP_DTMR3 0xFC07C000
#define MMAP_PIT0 0xFC080000
#define MMAP_PIT1 0xFC084000
#define MMAP_PIT2 0xFC088000
#define MMAP_PIT3 0xFC08C000
#define MMAP_EPORT0 0xFC090000
#define MMAP_ADC 0xFC094000
#define MMAP_DAC0 0xFC098000
#define MMAP_DAC1 0xFC09C000
#define MMAP_RRTC 0xFC0A8000
#define MMAP_SIM 0xFC0AC000
#define MMAP_USBOTG 0xFC0B0000
#define MMAP_USBEHCI 0xFC0B4000
#define MMAP_SDRAM 0xFC0B8000
#define MMAP_SSI0 0xFC0BC000
#define MMAP_PLL 0xFC0C0000
#define MMAP_RNG 0xFC0C4000
#define MMAP_SSI1 0xFC0C8000
#define MMAP_ESDHC 0xFC0CC000
#define MMAP_FEC0 0xFC0D4000
#define MMAP_FEC1 0xFC0D8000
#define MMAP_L2_SW0 0xFC0DC000
#define MMAP_L2_SW1 0xFC0E0000
#define MMAP_NFC_RAM 0xFC0FC000
#define MMAP_NFC 0xFC0FF000
#define MMAP_1WIRE 0xEC008000
#define MMAP_I2C2 0xEC010000
#define MMAP_I2C3 0xEC014000
#define MMAP_I2C4 0xEC018000
#define MMAP_I2C5 0xEC01C000
#define MMAP_DSPI2 0xEC038000
#define MMAP_DSPI3 0xEC03C000
#define MMAP_UART4 0xEC060000
#define MMAP_UART5 0xEC064000
#define MMAP_UART6 0xEC068000
#define MMAP_UART7 0xEC06C000
#define MMAP_UART8 0xEC070000
#define MMAP_UART9 0xEC074000
#define MMAP_RCM 0xEC090000
#define MMAP_CCM 0xEC090000
#define MMAP_GPIO 0xEC094000
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/ssi.h>
/* Serial Boot Facility (SBF) */
typedef struct sbf {
u8 resv0[0x18];
u16 sbfsr; /* Serial Boot Facility Status */
u8 resv1[0x6];
u16 sbfcr; /* Serial Boot Facility Control */
} sbf_t;
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/* Chip Configuration Module (CCM) */
typedef struct ccm {
u8 ccm_resv0[0x4]; /* 0x00 */
u16 ccr; /* 0x04 Chip Configuration */
u8 resv1[0x2]; /* 0x06 */
u16 rcon; /* 0x08 Reset Configuration */
u16 cir; /* 0x0A Chip Identification */
u8 resv2[0x2]; /* 0x0C */
u16 misccr; /* 0x0E Miscellaneous Control */
u16 cdrh; /* 0x10 Clock Divider */
u16 cdrl; /* 0x12 Clock Divider */
u16 uocsr; /* 0x14 USB On-the-Go Controller Status */
u16 uhcsr; /* 0x16 */
u16 misccr3; /* 0x18 */
u16 misccr2; /* 0x1A */
u16 adctsr; /* 0x1C */
u16 dactsr; /* 0x1E */
u16 sbfsr; /* 0x20 */
u16 sbfcr; /* 0x22 */
u32 fnacr; /* 0x24 */
} ccm_t;
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
u8 podr_a; /* 0x00 */
u8 podr_b; /* 0x01 */
u8 podr_c; /* 0x02 */
u8 podr_d; /* 0x03 */
u8 podr_e; /* 0x04 */
u8 podr_f; /* 0x05 */
u8 podr_g; /* 0x06 */
u8 podr_h; /* 0x07 */
u8 podr_i; /* 0x08 */
u8 podr_j; /* 0x09 */
u8 podr_k; /* 0x0A */
u8 rsvd0; /* 0x0B */
u8 pddr_a; /* 0x0C */
u8 pddr_b; /* 0x0D */
u8 pddr_c; /* 0x0E */
u8 pddr_d; /* 0x0F */
u8 pddr_e; /* 0x10 */
u8 pddr_f; /* 0x11 */
u8 pddr_g; /* 0x12 */
u8 pddr_h; /* 0x13 */
u8 pddr_i; /* 0x14 */
u8 pddr_j; /* 0x15 */
u8 pddr_k; /* 0x16 */
u8 rsvd1; /* 0x17 */
u8 ppdsdr_a; /* 0x18 */
u8 ppdsdr_b; /* 0x19 */
u8 ppdsdr_c; /* 0x1A */
u8 ppdsdr_d; /* 0x1B */
u8 ppdsdr_e; /* 0x1C */
u8 ppdsdr_f; /* 0x1D */
u8 ppdsdr_g; /* 0x1E */
u8 ppdsdr_h; /* 0x1F */
u8 ppdsdr_i; /* 0x20 */
u8 ppdsdr_j; /* 0x21 */
u8 ppdsdr_k; /* 0x22 */
u8 rsvd2; /* 0x23 */
u8 pclrr_a; /* 0x24 */
u8 pclrr_b; /* 0x25 */
u8 pclrr_c; /* 0x26 */
u8 pclrr_d; /* 0x27 */
u8 pclrr_e; /* 0x28 */
u8 pclrr_f; /* 0x29 */
u8 pclrr_g; /* 0x2A */
u8 pclrr_h; /* 0x2B */
u8 pclrr_i; /* 0x2C */
u8 pclrr_j; /* 0x2D */
u8 pclrr_k; /* 0x2E */
u8 rsvd3; /* 0x2F */
u16 pcr_a; /* 0x30 */
u16 pcr_b; /* 0x32 */
u16 pcr_c; /* 0x34 */
u16 pcr_d; /* 0x36 */
u16 pcr_e; /* 0x38 */
u16 pcr_f; /* 0x3A */
u16 pcr_g; /* 0x3C */
u16 pcr_h; /* 0x3E */
u16 pcr_i; /* 0x40 */
u16 pcr_j; /* 0x42 */
u16 pcr_k; /* 0x44 */
u16 rsvd4; /* 0x46 */
u8 par_fbctl; /* 0x48 */
u8 par_be; /* 0x49 */
u8 par_cs; /* 0x4A */
u8 par_cani2c; /* 0x4B */
u8 par_irqh; /* 0x4C */
u8 par_irql; /* 0x4D */
u8 par_dspi0; /* 0x4E */
u8 par_dspiow; /* 0x4F */
u8 par_timer; /* 0x50 */
u8 par_uart2; /* 0x51 */
u8 par_uart1; /* 0x52 */
u8 par_uart0; /* 0x53 */
u8 par_sdhch; /* 0x54 */
u8 par_sdhcl; /* 0x55 */
u8 par_simp0h; /* 0x56 */
u8 par_simp1h; /* 0x57 */
u8 par_ssi0h; /* 0x58 */
u8 par_ssi0l; /* 0x59 */
u8 par_dbg1h; /* 0x5A */
u8 par_dbg0h; /* 0x5B */
u8 par_dbgl; /* 0x5C */
u8 rsvd5; /* 0x5D */
u8 par_fec; /* 0x5E */
u8 rsvd6; /* 0x5F */
u8 mscr_sdram; /* 0x60 */
u8 rsvd7[3]; /* 0x61-0x63 */
u8 srcr_fb1; /* 0x64 */
u8 srcr_fb2; /* 0x65 */
u8 srcr_fb3; /* 0x66 */
u8 srcr_fb4; /* 0x67 */
u8 srcr_dspiow; /* 0x68 */
u8 srcr_cani2c; /* 0x69 */
u8 srcr_irq; /* 0x6A */
u8 srcr_timer; /* 0x6B */
u8 srcr_uart; /* 0x6C */
u8 srcr_fec; /* 0x6D */
u8 srcr_sdhc; /* 0x6E */
u8 srcr_simp0; /* 0x6F */
u8 srcr_ssi0; /* 0x70 */
u8 rsvd8[3]; /* 0x71-0x73 */
u16 urts_pol; /* 0x74 */
u16 ucts_pol; /* 0x76 */
u16 utxd_wom; /* 0x78 */
u32 urxd_wom; /* 0x7c */
u32 hcr1; /* 0x80 */
u32 hcr0; /* 0x84 */
} gpio_t;
/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 cr00; /* 0x00 */
u32 cr01; /* 0x04 */
u32 cr02; /* 0x08 */
u32 cr03; /* 0x0C */
u32 cr04; /* 0x10 */
u32 cr05; /* 0x14 */
u32 cr06; /* 0x18 */
u32 cr07; /* 0x1C */
u32 cr08; /* 0x20 */
u32 cr09; /* 0x24 */
u32 cr10; /* 0x28 */
u32 cr11; /* 0x2C */
u32 cr12; /* 0x30 */
u32 cr13; /* 0x34 */
u32 cr14; /* 0x38 */
u32 cr15; /* 0x3C */
u32 cr16; /* 0x40 */
u32 cr17; /* 0x44 */
u32 cr18; /* 0x48 */
u32 cr19; /* 0x4C */
u32 cr20; /* 0x50 */
u32 cr21; /* 0x54 */
u32 cr22; /* 0x58 */
u32 cr23; /* 0x5C */
u32 cr24; /* 0x60 */
u32 cr25; /* 0x64 */
u32 cr26; /* 0x68 */
u32 cr27; /* 0x6C */
u32 cr28; /* 0x70 */
u32 cr29; /* 0x74 */
u32 cr30; /* 0x78 */
u32 cr31; /* 0x7C */
u32 cr32; /* 0x80 */
u32 cr33; /* 0x84 */
u32 cr34; /* 0x88 */
u32 cr35; /* 0x8C */
u32 cr36; /* 0x90 */
u32 cr37; /* 0x94 */
u32 cr38; /* 0x98 */
u32 cr39; /* 0x9C */
u32 cr40; /* 0xA0 */
u32 cr41; /* 0xA4 */
u32 cr42; /* 0xA8 */
u32 cr43; /* 0xAC */
u32 cr44; /* 0xB0 */
u32 cr45; /* 0xB4 */
u32 cr46; /* 0xB8 */
u32 cr47; /* 0xBC */
u32 cr48; /* 0xC0 */
u32 cr49; /* 0xC4 */
u32 cr50; /* 0xC8 */
u32 cr51; /* 0xCC */
u32 cr52; /* 0xD0 */
u32 cr53; /* 0xD4 */
u32 cr54; /* 0xD8 */
u32 cr55; /* 0xDC */
u32 cr56; /* 0xE0 */
u32 cr57; /* 0xE4 */
u32 cr58; /* 0xE8 */
u32 cr59; /* 0xEC */
u32 cr60; /* 0xF0 */
u32 cr61; /* 0xF4 */
u32 cr62; /* 0xF8 */
u32 cr63; /* 0xFC */
u32 rsvd3[32]; /* 0xF4-0x1A8 */
u32 rcrcr; /* 0x180 */
u32 swrcr; /* 0x184 */
u32 rcr; /* 0x188 */
u32 msovr; /* 0x18C */
u32 rcrdbg; /* 0x190 */
u32 sl0adj; /* 0x194 */
u32 sl1adj; /* 0x198 */
u32 sl2adj; /* 0x19C */
u32 sl3adj; /* 0x1A0 */
u32 sl4adj; /* 0x1A4 */
u32 flight_tm; /* 0x1A8 */
u32 padcr; /* 0x1AC */
} sdramc_t;
/* Phase Locked Loop (PLL) */
typedef struct pll {
u32 pcr; /* Control */
u32 pdr; /* Divider */
u32 psr; /* Status */
} pll_t;
typedef struct scm {
u8 rsvd1[19]; /* 0x00 - 0x12 */
u8 wcr; /* 0x13 */
u16 rsvd2; /* 0x14 - 0x15 */
u16 cwcr; /* 0x16 */
u8 rsvd3[3]; /* 0x18 - 0x1A */
u8 cwsr; /* 0x1B */
u8 rsvd4[3]; /* 0x1C - 0x1E */
u8 scmisr; /* 0x1F */
u32 rsvd5; /* 0x20 - 0x23 */
u32 bcr; /* 0x24 */
u8 rsvd6[72]; /* 0x28 - 0x6F */
u32 cfadr; /* 0x70 */
u8 rsvd7; /* 0x74 */
u8 cfier; /* 0x75 */
u8 cfloc; /* 0x76 */
u8 cfatr; /* 0x77 */
u32 rsvd8; /* 0x78 - 0x7B */
u32 cfdtr; /* 0x7C */
} scm_t;
typedef struct pm {
u8 pmsr0; /* */
u8 pmcr0;
u8 pmsr1;
u8 pmcr1;
u32 pmhr0;
u32 pmlr0;
u32 pmhr1;
u32 pmlr1;
} pm_t;
#endif /* __IMMAP_5441X__ */

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/*
* MCF5445x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_5445X__
#define __IMMAP_5445X__
/* Module Base Addresses */
#define MMAP_SCM1 0xFC000000
#define MMAP_XBS 0xFC004000
#define MMAP_FBCS 0xFC008000
#define MMAP_FEC0 0xFC030000
#define MMAP_FEC1 0xFC034000
#define MMAP_RTC 0xFC03C000
#define MMAP_SCM2 0xFC040000
#define MMAP_EDMA 0xFC044000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
#define MMAP_IACK 0xFC054000
#define MMAP_I2C 0xFC058000
#define MMAP_DSPI 0xFC05C000
#define MMAP_UART0 0xFC060000
#define MMAP_UART1 0xFC064000
#define MMAP_UART2 0xFC068000
#define MMAP_DTMR0 0xFC070000
#define MMAP_DTMR1 0xFC074000
#define MMAP_DTMR2 0xFC078000
#define MMAP_DTMR3 0xFC07C000
#define MMAP_PIT0 0xFC080000
#define MMAP_PIT1 0xFC084000
#define MMAP_PIT2 0xFC088000
#define MMAP_PIT3 0xFC08C000
#define MMAP_EPORT 0xFC094000
#define MMAP_WTM 0xFC098000
#define MMAP_SBF 0xFC0A0000
#define MMAP_RCM 0xFC0A0000
#define MMAP_CCM 0xFC0A0000
#define MMAP_GPIO 0xFC0A4000
#define MMAP_PCI 0xFC0A8000
#define MMAP_PCIARB 0xFC0AC000
#define MMAP_RNG 0xFC0B4000
#define MMAP_SDRAM 0xFC0B8000
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C4000
#define MMAP_ATA 0x90000000
#define MMAP_USBHW 0xFC0B0000
#define MMAP_USBCAPS 0xFC0B0100
#define MMAP_USBEHCI 0xFC0B0140
#define MMAP_USBOTG 0xFC0B01A0
#include <asm/coldfire/ata.h>
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/ssi.h>
/* Watchdog Timer Modules (WTM) */
typedef struct wtm {
u16 wcr;
u16 wmr;
u16 wcntr;
u16 wsr;
} wtm_t;
/* Serial Boot Facility (SBF) */
typedef struct sbf {
u8 resv0[0x18];
u16 sbfsr; /* Serial Boot Facility Status Register */
u8 resv1[0x6];
u16 sbfcr; /* Serial Boot Facility Control Register */
} sbf_t;
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/* Chip Configuration Module (CCM) */
typedef struct ccm {
u8 ccm_resv0[0x4];
u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
u8 resv1[0x2];
u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
u16 cir; /* Chip Identification Register (Read-only) */
u8 resv2[0x4];
u16 misccr; /* Miscellaneous Control Register */
u16 cdr; /* Clock Divider Register */
u16 uocsr; /* USB On-the-Go Controller Status Register */
} ccm_t;
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
u8 podr_fec0h; /* FEC0 High Port Output Data Register */
u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
u8 podr_ssi; /* SSI Port Output Data Register */
u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
u8 podr_dma; /* DMA Port Output Data Register */
u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
u8 resv0[0x1];
u8 podr_uart; /* UART Port Output Data Register */
u8 podr_dspi; /* DSPI Port Output Data Register */
u8 podr_timer; /* Timer Port Output Data Register */
u8 podr_pci; /* PCI Port Output Data Register */
u8 podr_usb; /* USB Port Output Data Register */
u8 podr_atah; /* ATA High Port Output Data Register */
u8 podr_atal; /* ATA Low Port Output Data Register */
u8 podr_fec1h; /* FEC1 High Port Output Data Register */
u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
u8 resv1[0x2];
u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
u8 pddr_ssi; /* SSI Port Data Direction Register */
u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
u8 pddr_dma; /* DMA Port Data Direction Register */
u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
u8 resv2[0x1];
u8 pddr_uart; /* UART Port Data Direction Register */
u8 pddr_dspi; /* DSPI Port Data Direction Register */
u8 pddr_timer; /* Timer Port Data Direction Register */
u8 pddr_pci; /* PCI Port Data Direction Register */
u8 pddr_usb; /* USB Port Data Direction Register */
u8 pddr_atah; /* ATA High Port Data Direction Register */
u8 pddr_atal; /* ATA Low Port Data Direction Register */
u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
u8 resv3[0x2];
u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
u8 resv4[0x1];
u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
u8 resv5[0x2];
u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
u8 pclrr_dma; /* DMA Port Clear Output Data Register */
u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
u8 resv6[0x1];
u8 pclrr_uart; /* UART Port Clear Output Data Register */
u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
u8 pclrr_timer; /* Timer Port Clear Output Data Register */
u8 pclrr_pci; /* PCI Port Clear Output Data Register */
u8 pclrr_usb; /* USB Port Clear Output Data Register */
u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
u8 resv7[0x2];
u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
u8 par_fec; /* FEC Pin Assignment Register */
u8 par_dma; /* DMA Pin Assignment Register */
u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
u8 par_dspi; /* DSPI Pin Assignment Register */
u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
u8 par_timer; /* Time Pin Assignment Register */
u8 par_usb; /* USB Pin Assignment Register */
u8 resv8[0x1];
u8 par_uart; /* UART Pin Assignment Register */
u16 par_feci2c; /* FEC / I2C Pin Assignment Register */
u16 par_ssi; /* SSI Pin Assignment Register */
u16 par_ata; /* ATA Pin Assignment Register */
u8 par_irq; /* IRQ Pin Assignment Register */
u8 resv9[0x1];
u16 par_pci; /* PCI Pin Assignment Register */
u8 mscr_sdram; /* SDRAM Mode Select Control Register */
u8 mscr_pci; /* PCI Mode Select Control Register */
u8 resv10[0x2];
u8 dscr_i2c; /* I2C Drive Strength Control Register */
u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
u8 dscr_fec; /* FEC Drive Strength Control Register */
u8 dscr_uart; /* UART Drive Strength Control Register */
u8 dscr_dspi; /* DSPI Drive Strength Control Register */
u8 dscr_timer; /* TIMER Drive Strength Control Register */
u8 dscr_ssi; /* SSI Drive Strength Control Register */
u8 dscr_dma; /* DMA Drive Strength Control Register */
u8 dscr_debug; /* DEBUG Drive Strength Control Register */
u8 dscr_reset; /* RESET Drive Strength Control Register */
u8 dscr_irq; /* IRQ Drive Strength Control Register */
u8 dscr_usb; /* USB Drive Strength Control Register */
u8 dscr_ata; /* ATA Drive Strength Control Register */
} gpio_t;
/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 sdmr; /* SDRAM Mode/Extended Mode Register */
u32 sdcr; /* SDRAM Control Register */
u32 sdcfg1; /* SDRAM Configuration Register 1 */
u32 sdcfg2; /* SDRAM Chip Select Register */
u8 resv0[0x100];
u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
} sdramc_t;
/* Phase Locked Loop (PLL) */
typedef struct pll {
u32 pcr; /* PLL Control Register */
u32 psr; /* PLL Status Register */
} pll_t;
typedef struct pci {
u32 idr; /* 0x00 Device Id / Vendor Id Register */
u32 scr; /* 0x04 Status / command Register */
u32 ccrir; /* 0x08 Class Code / Revision Id Register */
u32 cr1; /* 0x0c Configuration 1 Register */
u32 bar0; /* 0x10 Base address register 0 Register */
u32 bar1; /* 0x14 Base address register 1 Register */
u32 bar2; /* 0x18 Base address register 2 Register */
u32 bar3; /* 0x1c Base address register 3 Register */
u32 bar4; /* 0x20 Base address register 4 Register */
u32 bar5; /* 0x24 Base address register 5 Register */
u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
u32 erbar; /* 0x30 Expansion ROM Base Address Register */
u32 cpr; /* 0x34 Capabilities Pointer Register */
u32 rsvd1; /* 0x38 */
u32 cr2; /* 0x3c Configuration Register 2 */
u32 rsvd2[8]; /* 0x40 - 0x5f */
/* General control / status registers */
u32 gscr; /* 0x60 Global Status / Control Register */
u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
u32 tcr1; /* 0x6c Target Control 1 Register */
u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
u32 rsvd3; /* 0x7c */
u32 iwcr; /* 0x80 Initiator Window Configuration Register */
u32 icr; /* 0x84 Initiator Control Register */
u32 isr; /* 0x88 Initiator Status Register */
u32 tcr2; /* 0x8c Target Control 2 Register */
u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
u32 intr; /* 0xa8 Interrupt Register */
u32 rsvd4[19]; /* 0xac - 0xf7 */
u32 car; /* 0xf8 Configuration Address Register */
} pci_t;
typedef struct pci_arbiter {
/* Pci Arbiter Registers */
union {
u32 acr; /* Arbiter Control Register */
u32 asr; /* Arbiter Status Register */
};
} pciarb_t;
/* Register read/write struct */
typedef struct scm1 {
u32 mpr; /* 0x00 Master Privilege Register */
u32 rsvd1[7];
u32 pacra; /* 0x20 Peripheral Access Control Register A */
u32 pacrb; /* 0x24 Peripheral Access Control Register B */
u32 pacrc; /* 0x28 Peripheral Access Control Register C */
u32 pacrd; /* 0x2C Peripheral Access Control Register D */
u32 rsvd2[4];
u32 pacre; /* 0x40 Peripheral Access Control Register E */
u32 pacrf; /* 0x44 Peripheral Access Control Register F */
u32 pacrg; /* 0x48 Peripheral Access Control Register G */
} scm1_t;
typedef struct scm2 {
u8 rsvd1[19]; /* 0x00 - 0x12 */
u8 wcr; /* 0x13 */
u16 rsvd2; /* 0x14 - 0x15 */
u16 cwcr; /* 0x16 */
u8 rsvd3[3]; /* 0x18 - 0x1A */
u8 cwsr; /* 0x1B */
u8 rsvd4[3]; /* 0x1C - 0x1E */
u8 scmisr; /* 0x1F */
u32 rsvd5; /* 0x20 - 0x23 */
u8 bcr; /* 0x24 */
u8 rsvd6[74]; /* 0x25 - 0x6F */
u32 cfadr; /* 0x70 */
u8 rsvd7; /* 0x74 */
u8 cfier; /* 0x75 */
u8 cfloc; /* 0x76 */
u8 cfatr; /* 0x77 */
u32 rsvd8; /* 0x78 - 0x7B */
u32 cfdtr; /* 0x7C */
} scm2_t;
typedef struct rtcex {
u32 rsvd1[3];
u32 gocu;
u32 gocl;
} rtcex_t;
#endif /* __IMMAP_5445X__ */

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/*
* MCF547x_8x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_547x_8x__
#define __IMMAP_547x_8x__
#define MMAP_SIU (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000100)
#define MMAP_XARB (CONFIG_SYS_MBAR + 0x00000240)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000500)
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000700)
#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800)
#define MMAP_SLT0 (CONFIG_SYS_MBAR + 0x00000900)
#define MMAP_SLT1 (CONFIG_SYS_MBAR + 0x00000910)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00)
#define MMAP_PCI (CONFIG_SYS_MBAR + 0x00000B00)
#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00)
#define MMAP_EXTDMA (CONFIG_SYS_MBAR + 0x00000D00)
#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00000F00)
#define MMAP_CTM (CONFIG_SYS_MBAR + 0x00007F00)
#define MMAP_MCDMA (CONFIG_SYS_MBAR + 0x00008000)
#define MMAP_SCPCI (CONFIG_SYS_MBAR + 0x00008400)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00008600)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00008700)
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00008800)
#define MMAP_UART3 (CONFIG_SYS_MBAR + 0x00008900)
#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x00008A00)
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008F00)
#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00009000)
#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009800)
#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x0000A000)
#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x0000A800)
#define MMAP_USBD (CONFIG_SYS_MBAR + 0x0000B000)
#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00010000)
#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00)
#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000)
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
typedef struct siu {
u32 mbar; /* 0x00 */
u32 drv; /* 0x04 */
u32 rsvd1[2]; /* 0x08 - 0x1F */
u32 sbcr; /* 0x10 */
u32 rsvd2[3]; /* 0x14 - 0x1F */
u32 cs0cfg; /* 0x20 */
u32 cs1cfg; /* 0x24 */
u32 cs2cfg; /* 0x28 */
u32 cs3cfg; /* 0x2C */
u32 rsvd3[2]; /* 0x30 - 0x37 */
u32 secsacr; /* 0x38 */
u32 rsvd4[2]; /* 0x3C - 0x43 */
u32 rsr; /* 0x44 */
u32 rsvd5[2]; /* 0x48 - 0x4F */
u32 jtagid; /* 0x50 */
} siu_t;
typedef struct sdram {
u32 mode; /* 0x00 */
u32 ctrl; /* 0x04 */
u32 cfg1; /* 0x08 */
u32 cfg2; /* 0x0c */
} sdram_t;
typedef struct xlb_arb {
u32 cfg; /* 0x240 */
u32 ver; /* 0x244 */
u32 sr; /* 0x248 */
u32 imr; /* 0x24c */
u32 adrcap; /* 0x250 */
u32 sigcap; /* 0x254 */
u32 adrto; /* 0x258 */
u32 datto; /* 0x25c */
u32 busto; /* 0x260 */
u32 prien; /* 0x264 */
u32 pri; /* 0x268 */
} xlbarb_t;
typedef struct gptmr {
u8 ocpw;
u8 octict;
u8 ctrl;
u8 mode;
u16 pre; /* Prescale */
u16 cnt;
u16 pwmwidth;
u8 pwmop; /* Output Polarity */
u8 pwmld; /* Immediate Update */
u16 cap; /* Capture internal counter */
u8 ovfpin; /* Ovf and Pin */
u8 intr; /* Interrupts */
} gptmr_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
typedef struct slt {
u32 tcnt; /* 0x00 */
u32 cr; /* 0x04 */
u32 cnt; /* 0x08 */
u32 sr; /* 0x0C */
} slt_t;
typedef struct gpio {
/* Port Output Data Registers */
u8 podr_fbctl; /*0x00 */
u8 podr_fbcs; /*0x01 */
u8 podr_dma; /*0x02 */
u8 rsvd1; /*0x03 */
u8 podr_fec0h; /*0x04 */
u8 podr_fec0l; /*0x05 */
u8 podr_fec1h; /*0x06 */
u8 podr_fec1l; /*0x07 */
u8 podr_feci2c; /*0x08 */
u8 podr_pcibg; /*0x09 */
u8 podr_pcibr; /*0x0A */
u8 rsvd2; /*0x0B */
u8 podr_psc3psc2; /*0x0C */
u8 podr_psc1psc0; /*0x0D */
u8 podr_dspi; /*0x0E */
u8 rsvd3; /*0x0F */
/* Port Data Direction Registers */
u8 pddr_fbctl; /*0x10 */
u8 pddr_fbcs; /*0x11 */
u8 pddr_dma; /*0x12 */
u8 rsvd4; /*0x13 */
u8 pddr_fec0h; /*0x14 */
u8 pddr_fec0l; /*0x15 */
u8 pddr_fec1h; /*0x16 */
u8 pddr_fec1l; /*0x17 */
u8 pddr_feci2c; /*0x18 */
u8 pddr_pcibg; /*0x19 */
u8 pddr_pcibr; /*0x1A */
u8 rsvd5; /*0x1B */
u8 pddr_psc3psc2; /*0x1C */
u8 pddr_psc1psc0; /*0x1D */
u8 pddr_dspi; /*0x1E */
u8 rsvd6; /*0x1F */
/* Port Pin Data/Set Data Registers */
u8 ppdsdr_fbctl; /*0x20 */
u8 ppdsdr_fbcs; /*0x21 */
u8 ppdsdr_dma; /*0x22 */
u8 rsvd7; /*0x23 */
u8 ppdsdr_fec0h; /*0x24 */
u8 ppdsdr_fec0l; /*0x25 */
u8 ppdsdr_fec1h; /*0x26 */
u8 ppdsdr_fec1l; /*0x27 */
u8 ppdsdr_feci2c; /*0x28 */
u8 ppdsdr_pcibg; /*0x29 */
u8 ppdsdr_pcibr; /*0x2A */
u8 rsvd8; /*0x2B */
u8 ppdsdr_psc3psc2; /*0x2C */
u8 ppdsdr_psc1psc0; /*0x2D */
u8 ppdsdr_dspi; /*0x2E */
u8 rsvd9; /*0x2F */
/* Port Clear Output Data Registers */
u8 pclrr_fbctl; /*0x30 */
u8 pclrr_fbcs; /*0x31 */
u8 pclrr_dma; /*0x32 */
u8 rsvd10; /*0x33 */
u8 pclrr_fec0h; /*0x34 */
u8 pclrr_fec0l; /*0x35 */
u8 pclrr_fec1h; /*0x36 */
u8 pclrr_fec1l; /*0x37 */
u8 pclrr_feci2c; /*0x38 */
u8 pclrr_pcibg; /*0x39 */
u8 pclrr_pcibr; /*0x3A */
u8 rsvd11; /*0x3B */
u8 pclrr_psc3psc2; /*0x3C */
u8 pclrr_psc1psc0; /*0x3D */
u8 pclrr_dspi; /*0x3E */
u8 rsvd12; /*0x3F */
/* Pin Assignment Registers */
u16 par_fbctl; /*0x40 */
u8 par_fbcs; /*0x42 */
u8 par_dma; /*0x43 */
u16 par_feci2cirq; /*0x44 */
u16 rsvd13; /*0x46 */
u16 par_pcibg; /*0x48 */
u16 par_pcibr; /*0x4A */
u8 par_psc3; /*0x4C */
u8 par_psc2; /*0x4D */
u8 par_psc1; /*0x4E */
u8 par_psc0; /*0x4F */
u16 par_dspi; /*0x50 */
u8 par_timer; /*0x52 */
u8 rsvd14; /*0x53 */
} gpio_t;
typedef struct pci {
u32 idr; /* 0x00 Device Id / Vendor Id */
u32 scr; /* 0x04 Status / command */
u32 ccrir; /* 0x08 Class Code / Revision Id */
u32 cr1; /* 0x0c Configuration 1 */
u32 bar0; /* 0x10 Base address register 0 */
u32 bar1; /* 0x14 Base address register 1 */
u32 bar2; /* 0x18 NA */
u32 bar3; /* 0x1c NA */
u32 bar4; /* 0x20 NA */
u32 bar5; /* 0x24 NA */
u32 ccpr; /* 0x28 Cardbus CIS Pointer */
u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */
u32 erbar; /* 0x30 Expansion ROM Base Address */
u32 cpr; /* 0x34 Capabilities Pointer */
u32 rsvd1; /* 0x38 */
u32 cr2; /* 0x3c Configuration 2 */
u32 rsvd2[8]; /* 0x40 - 0x5f */
/* General control / status registers */
u32 gscr; /* 0x60 Global Status / Control */
u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */
u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */
u32 tcr1; /* 0x6c Target Control 1 Register */
u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */
u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */
u32 iw2btar; /* 0x78 NA */
u32 rsvd3; /* 0x7c */
u32 iwcr; /* 0x80 Initiator Window Configuration */
u32 icr; /* 0x84 Initiator Control */
u32 isr; /* 0x88 Initiator Status */
u32 tcr2; /* 0x8c NA */
u32 tbatr0; /* 0x90 NA */
u32 tbatr1; /* 0x94 NA */
u32 tbatr2; /* 0x98 NA */
u32 tbatr3; /* 0x9c NA */
u32 tbatr4; /* 0xa0 NA */
u32 tbatr5; /* 0xa4 NA */
u32 intr; /* 0xa8 NA */
u32 rsvd4[19]; /* 0xac - 0xf7 */
u32 car; /* 0xf8 Configuration Address */
} pci_t;
typedef struct pci_arbiter {
/* Pci Arbiter Registers */
union {
u32 acr; /* Arbiter Control */
u32 asr; /* Arbiter Status */
};
} pciarb_t;
#endif /* __IMMAP_547x_8x__ */

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/*
* IO header file
*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_M68K_IO_H__
#define __ASM_M68K_IO_H__
#include <asm/byteorder.h>
#ifndef _IO_BASE
#define _IO_BASE 0
#endif
#define __raw_readb(addr) (*(volatile u8 *)(addr))
#define __raw_readw(addr) (*(volatile u16 *)(addr))
#define __raw_readl(addr) (*(volatile u32 *)(addr))
#define __raw_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
#define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w))
#define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l))
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
#if !defined(__BIG_ENDIAN)
#define readw(addr) (*(volatile u16 *) (addr))
#define readl(addr) (*(volatile u32 *) (addr))
#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
#else
#define readw(addr) in_be16((volatile u16 *)(addr))
#define readl(addr) in_be32((volatile u32 *)(addr))
#define writew(b,addr) out_be16((volatile u16 *)(addr),(b))
#define writel(b,addr) out_be32((volatile u32 *)(addr),(b))
#endif
/*
* The insw/outsw/insl/outsl macros don't do byte-swapping.
* They are only used in practice for transferring buffers which
* are arrays of bytes, and byte-swapping is not appropriate in
* that case. - paulus
*/
#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define inb(port) in_8((u8 *)((port)+_IO_BASE))
#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
#if !defined(__BIG_ENDIAN)
#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
#else
#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
#endif
#define mb() __asm__ __volatile__ ("" : : : "memory")
static inline void _insb(volatile u8 * port, void *buf, int ns)
{
u8 *data = (u8 *) buf;
while (ns--)
*data++ = *port;
}
static inline void _outsb(volatile u8 * port, const void *buf, int ns)
{
u8 *data = (u8 *) buf;
while (ns--)
*port = *data++;
}
static inline void _insw(volatile u16 * port, void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--)
*data++ = __sw16(*port);
}
static inline void _outsw(volatile u16 * port, const void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--) {
*port = __sw16(*data);
data++;
}
}
static inline void _insl(volatile u32 * port, void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--)
*data++ = __sw32(*port);
}
static inline void _outsl(volatile u32 * port, const void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--) {
*port = __sw32(*data);
data++;
}
}
static inline void _insw_ns(volatile u16 * port, void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--)
*data++ = *port;
}
static inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
{
u16 *data = (u16 *) buf;
while (ns--) {
*port = *data++;
}
}
static inline void _insl_ns(volatile u32 * port, void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--)
*data++ = *port;
}
static inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
{
u32 *data = (u32 *) buf;
while (nl--) {
*port = *data;
data++;
}
}
/*
* The *_ns versions below don't do byte-swapping.
* Neither do the standard versions now, these are just here
* for older code.
*/
#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define IO_SPACE_LIMIT ~0
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*/
static inline int in_8(volatile u8 * addr)
{
return (int)*addr;
}
static inline void out_8(volatile u8 * addr, int val)
{
*addr = (u8) val;
}
static inline int in_le16(volatile u16 * addr)
{
return __sw16(*addr);
}
static inline int in_be16(volatile u16 * addr)
{
return (*addr & 0xFFFF);
}
static inline void out_le16(volatile u16 * addr, int val)
{
*addr = __sw16(val);
}
static inline void out_be16(volatile u16 * addr, int val)
{
*addr = (u16) val;
}
static inline unsigned in_le32(volatile u32 * addr)
{
return __sw32(*addr);
}
static inline unsigned in_be32(volatile u32 * addr)
{
return (*addr);
}
static inline void out_le32(volatile unsigned *addr, int val)
{
*addr = __sw32(val);
}
static inline void out_be32(volatile unsigned *addr, int val)
{
*addr = val;
}
/* Clear and set bits in one shot. These macros can be used to clear and
* set multiple bits in a register using a single call. These macros can
* also be used to set a multiple-bit bit pattern using a mask, by
* specifying the mask in the 'clear' parameter and the new bit pattern
* in the 'set' parameter.
*/
#define clrbits(type, addr, clear) \
out_##type((addr), in_##type(addr) & ~(clear))
#define setbits(type, addr, set) \
out_##type((addr), in_##type(addr) | (set))
#define clrsetbits(type, addr, clear, set) \
out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
#define setbits_be32(addr, set) setbits(be32, addr, set)
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
#define setbits_le32(addr, set) setbits(le32, addr, set)
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
#define setbits_be16(addr, set) setbits(be16, addr, set)
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
#define setbits_le16(addr, set) setbits(le16, addr, set)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrbits_8(addr, clear) clrbits(8, addr, clear)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
static inline void sync(void)
{
/* This sync function is for PowerPC or other architecture instruction
* ColdFire does not have this instruction. Dummy function, added for
* compatibility (CFI driver)
*/
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *map_physmem(phys_addr_t paddr, unsigned long len,
unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
static inline phys_addr_t virt_to_phys(void * vaddr)
{
return (phys_addr_t)(vaddr);
}
#endif /* __ASM_M68K_IO_H__ */

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/*
* m520x.h -- Definitions for Freescale Coldfire 520x
*
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __M520X__
#define __M520X__
/* *** System Control Module (SCM) *** */
#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28)
#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24)
#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20)
#define MPROT_MTR 4
#define MPROT_MTW 2
#define MPROT_MPL 1
#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28)
#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24)
#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20)
#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12)
#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28)
#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24)
#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20)
#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8)
#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4)
#define SCM_PACRC_PACR23(x) ((x) & 0x0F)
#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28)
#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24)
#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20)
#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12)
#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8)
#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4)
#define SCM_PACRD_PACR31(x) ((x) & 0x0F)
#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28)
#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24)
#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20)
#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16)
#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12)
#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28)
#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24)
#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20)
#define PACR_SP 4
#define PACR_WP 2
#define PACR_TP 1
#define SCM_BMT_BME (0x00000008)
#define SCM_BMT_BMT(x) ((x) & 0x07)
#define SCM_BMT_BMT1024 (0x0000)
#define SCM_BMT_BMT512 (0x0001)
#define SCM_BMT_BMT256 (0x0002)
#define SCM_BMT_BMT128 (0x0003)
#define SCM_BMT_BMT64 (0x0004)
#define SCM_BMT_BMT32 (0x0005)
#define SCM_BMT_BMT16 (0x0006)
#define SCM_BMT_BMT8 (0x0007)
#define SCM_CWCR_RO (0x8000)
#define SCM_CWCR_CWR_WH (0x0100)
#define SCM_CWCR_CWE (0x0080)
#define SCM_CWRI_WINDOW (0x0060)
#define SCM_CWRI_RESET (0x0040)
#define SCM_CWRI_INT_RESET (0x0020)
#define SCM_CWRI_INT (0x0000)
#define SCM_CWCR_CWT(x) (((x) & 0x001F))
#define SCM_ISR_CFEI (0x02)
#define SCM_ISR_CWIC (0x01)
#define SCM_CFIER_ECFEI (0x01)
#define SCM_CFLOC_LOC (0x80)
#define SCM_CFATR_WRITE (0x80)
#define SCM_CFATR_SZ32 (0x20)
#define SCM_CFATR_SZ16 (0x10)
#define SCM_CFATR_SZ08 (0x00)
#define SCM_CFATR_CACHE (0x08)
#define SCM_CFATR_MODE (0x02)
#define SCM_CFATR_TYPE (0x01)
/* *** Interrupt Controller (INTC) *** */
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT_F1 (1)
#define INT0_LO_EPORT_F4 (2)
#define INT0_LO_EPORT_F7 (3)
#define INT1_LO_PIT0 (4)
#define INT1_LO_PIT1 (5)
/* 6 - 7 rsvd */
#define INT0_LO_EDMA_00 (8)
#define INT0_LO_EDMA_01 (9)
#define INT0_LO_EDMA_02 (10)
#define INT0_LO_EDMA_03 (11)
#define INT0_LO_EDMA_04 (12)
#define INT0_LO_EDMA_05 (13)
#define INT0_LO_EDMA_06 (14)
#define INT0_LO_EDMA_07 (15)
#define INT0_LO_EDMA_08 (16)
#define INT0_LO_EDMA_09 (17)
#define INT0_LO_EDMA_10 (18)
#define INT0_LO_EDMA_11 (19)
#define INT0_LO_EDMA_12 (20)
#define INT0_LO_EDMA_13 (21)
#define INT0_LO_EDMA_14 (22)
#define INT0_LO_EDMA_15 (23)
#define INT0_LO_EDMA_ERR (24)
#define INT0_LO_SCM_CWIC (25)
#define INT0_LO_UART0 (26)
#define INT0_LO_UART1 (27)
#define INT0_LO_UART2 (28)
/* 29 rsvd */
#define INT0_LO_I2C (30)
#define INT0_LO_QSPI (31)
#define INT0_HI_DTMR0 (32)
#define INT0_HI_DTMR1 (33)
#define INT0_HI_DTMR2 (34)
#define INT0_HI_DTMR3 (35)
#define INT0_HI_FEC0_TXF (36)
#define INT0_HI_FEC0_TXB (37)
#define INT0_HI_FEC0_UN (38)
#define INT0_HI_FEC0_RL (39)
#define INT0_HI_FEC0_RXF (40)
#define INT0_HI_FEC0_RXB (41)
#define INT0_HI_FEC0_MII (42)
#define INT0_HI_FEC0_LC (43)
#define INT0_HI_FEC0_HBERR (44)
#define INT0_HI_FEC0_GRA (45)
#define INT0_HI_FEC0_EBERR (46)
#define INT0_HI_FEC0_BABT (47)
#define INT0_HI_FEC0_BABR (48)
/* 49 - 61 rsvd */
#define INT0_HI_SCMISR_CFEI (62)
/* *** Reset Controller Module (RCM) *** */
#define RCM_RCR_SOFTRST (0x80)
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RSR_SOFT (0x20)
#define RCM_RSR_WDOG (0x10)
#define RCM_RSR_POR (0x08)
#define RCM_RSR_EXT (0x04)
#define RCM_RSR_WDR_CORE (0x02)
#define RCM_RSR_LOL (0x01)
/* *** Chip Configuration Module (CCM) *** */
#define CCM_CCR_CSC (0x0200)
#define CCM_CCR_OSCFREQ (0x0080)
#define CCM_CCR_LIMP (0x0040)
#define CCM_CCR_LOAD (0x0020)
#define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3)
#define CCM_CCR_OSC_MODE (0x0004)
#define CCM_CCR_PLL_MODE (0x0002)
#define CCM_CCR_RESERVED (0x0001)
#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
#define CCM_CIR_PRN(x) ((x) & 0x003F)
/* *** General Purpose I/O (GPIO) *** */
#define GPIO_PDR_BUSCTL(x) ((x) & 0x0F)
#define GPIO_PDR_BE(x) ((x) & 0x0F)
#define GPIO_PDR_CS(x) (((x) & 0x07) << 1)
#define GPIO_PDR_FECI2C(x) ((x) & 0x0F)
#define GPIO_PDR_QSPI(x) ((x) & 0x0F)
#define GPIO_PDR_TIMER(x) ((x) & 0x0F)
#define GPIO_PDR_UART(x) ((x) & 0xFF)
#define GPIO_PDR_FECH(x) ((x) & 0xFF)
#define GPIO_PDR_FECL(x) ((x) & 0xFF)
#define GPIO_PAR_FBCTL_OE (0x10)
#define GPIO_PAR_FBCTL_TA (0x08)
#define GPIO_PAR_FBCTL_RWB (0x04)
#define GPIO_PAR_FBCTL_TS_UNMASK (0xFC)
#define GPIO_PAR_FBCTL_TS_TS (0x03)
#define GPIO_PAR_FBCTL_TS_DMA (0x02)
#define GPIO_PAR_BE3 (0x08)
#define GPIO_PAR_BE2 (0x04)
#define GPIO_PAR_BE1 (0x02)
#define GPIO_PAR_BE0 (0x01)
#define GPIO_PAR_CS3 (0x08)
#define GPIO_PAR_CS2 (0x04)
#define GPIO_PAR_CS1_UNMASK (0xFC)
#define GPIO_PAR_CS1_CS1 (0x03)
#define GPIO_PAR_CS1_SDCS1 (0x02)
#define GPIO_PAR_FECI2C_RMII_UNMASK (0x0F)
#define GPIO_PAR_FECI2C_MDC_UNMASK (0x3F)
#define GPIO_PAR_FECI2C_MDC_MDC (0xC0)
#define GPIO_PAR_FECI2C_MDC_SCL (0x80)
#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40)
#define GPIO_PAR_FECI2C_MDIO_UNMASK (0xCF)
#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30)
#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10)
#define GPIO_PAR_FECI2C_I2C_UNMASK (0xF0)
#define GPIO_PAR_FECI2C_SCL_UNMASK (0xF3)
#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04)
#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFC)
#define GPIO_PAR_FECI2C_SDA_SDA (0x03)
#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01)
#define GPIO_PAR_QSPI_PCS2_UNMASK (0x3F)
#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0)
#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80)
#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40)
#define GPIO_PAR_QSPI_DIN_UNMASK (0xCF)
#define GPIO_PAR_QSPI_DIN_DIN (0x30)
#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20)
#define GPIO_PAR_QSPI_DIN_U2CTS (0x10)
#define GPIO_PAR_QSPI_DOUT_UNMASK (0xF3)
#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C)
#define GPIO_PAR_QSPI_DOUT_SDA (0x08)
#define GPIO_PAR_QSPI_SCK_UNMASK (0xFC)
#define GPIO_PAR_QSPI_SCK_SCK (0x03)
#define GPIO_PAR_QSPI_SCK_SCL (0x02)
#define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6)
#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4)
#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2)
#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03)
#define GPIO_PAR_TMR_TIN3_UNMASK (0x3F)
#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0)
#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80)
#define GPIO_PAR_TMR_TIN3_U2CTS (0x40)
#define GPIO_PAR_TMR_TIN2_UNMASK (0xCF)
#define GPIO_PAR_TMR_TIN2_TIN2 (0x30)
#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20)
#define GPIO_PAR_TMR_TIN2_U2RTS (0x10)
#define GPIO_PAR_TMR_TIN1_UNMASK (0xF3)
#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C)
#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08)
#define GPIO_PAR_TMR_TIN1_U2RXD (0x04)
#define GPIO_PAR_TMR_TIN0_UNMASK (0xFC)
#define GPIO_PAR_TMR_TIN0_TIN0 (0x03)
#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02)
#define GPIO_PAR_TMR_TIN0_U2TXD (0x01)
#define GPIO_PAR_UART1_UNMASK (0xF03F)
#define GPIO_PAR_UART0_UNMASK (0xFFC0)
#define GPIO_PAR_UART_U1CTS_UNMASK (0xF3FF)
#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00)
#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800)
#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400)
#define GPIO_PAR_UART_U1RTS_UNMASK (0xFCFF)
#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300)
#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200)
#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100)
#define GPIO_PAR_UART_U1TXD (0x0080)
#define GPIO_PAR_UART_U1RXD (0x0040)
#define GPIO_PAR_UART_U0CTS_UNMASK (0xFFCF)
#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030)
#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020)
#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010)
#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFF3)
#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C)
#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008)
#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004)
#define GPIO_PAR_UART_U0TXD (0x0002)
#define GPIO_PAR_UART_U0RXD (0x0001)
#define GPIO_PAR_FEC_7W_UNMASK (0xF3)
#define GPIO_PAR_FEC_7W_FEC (0x0C)
#define GPIO_PAR_FEC_7W_U1RTS (0x04)
#define GPIO_PAR_FEC_MII_UNMASK (0xFC)
#define GPIO_PAR_FEC_MII_FEC (0x03)
#define GPIO_PAR_FEC_MII_UnCTS (0x01)
#define GPIO_PAR_IRQ_IRQ4 (0x01)
#define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6)
#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4)
#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2)
#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03)
#define GPIO_MSCR_FB_FBCLK_UNMASK (0x3F)
#define GPIO_MSCR_FB_DUP_UNMASK (0xCF)
#define GPIO_MSCR_FB_DLO_UNMASK (0xF3)
#define GPIO_MSCR_FB_ADRCTL_UNMASK (0xFC)
#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4)
#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2)
#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03)
#define GPIO_MSCR_SDR_SDCLKB_UNMASK (0xCF)
#define GPIO_MSCR_SDR_SDCLK_UNMASK (0xF3)
#define GPIO_MSCR_SDR_SDRAM_UNMASK (0xFC)
#define MSCR_25VDDR (0x03)
#define MSCR_18VDDR_FULL (0x02)
#define MSCR_OPENDRAIN (0x01)
#define MSCR_18VDDR_HALF (0x00)
#define GPIO_DSCR_I2C(x) ((x) & 0x03)
#define GPIO_DSCR_I2C_UNMASK (0xFC)
#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4)
#define GPIO_DSCR_MISC_DBG_UNMASK (0xCF)
#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2)
#define GPIO_DSCR_MISC_RSTOUT_UNMASK (0xF3)
#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03)
#define GPIO_DSCR_MISC_TIMER_UNMASK (0xFC)
#define GPIO_DSCR_FEC(x) ((x) & 0x03)
#define GPIO_DSCR_FEC_UNMASK (0xFC)
#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4)
#define GPIO_DSCR_UART_UART1_UNMASK (0xCF)
#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2)
#define GPIO_DSCR_UART_UART0_UNMASK (0xF3)
#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03)
#define GPIO_DSCR_UART_IRQ_UNMASK (0xFC)
#define GPIO_DSCR_QSPI(x) ((x) & 0x03)
#define GPIO_DSCR_QSPI_UNMASK (0xFC)
#define DSCR_50PF (0x03)
#define DSCR_30PF (0x02)
#define DSCR_20PF (0x01)
#define DSCR_10PF (0x00)
/* *** Phase Locked Loop (PLL) *** */
#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4)
#define PLL_PODR_CPUDIV_UNMASK (0x0F)
#define PLL_PODR_BUSDIV(x) ((x) & 0x0F)
#define PLL_PODR_BUSDIV_UNMASK (0xF0)
#define PLL_PCR_DITHEN (0x80)
#define PLL_PCR_DITHDEV(x) ((x) & 0x07)
#define PLL_PCR_DITHDEV_UNMASK (0xF8)
#endif /* __M520X__ */

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u-boot/arch/m68k/include/asm/m5227x.h Normal file
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@@ -0,0 +1,547 @@
/*
* MCF5227x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MCF5227X__
#define __MCF5227X__
/* Interrupt Controller (INTC) */
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_EDMA_00 (8)
#define INT0_LO_EDMA_01 (9)
#define INT0_LO_EDMA_02 (10)
#define INT0_LO_EDMA_03 (11)
#define INT0_LO_EDMA_04 (12)
#define INT0_LO_EDMA_05 (13)
#define INT0_LO_EDMA_06 (14)
#define INT0_LO_EDMA_07 (15)
#define INT0_LO_EDMA_08 (16)
#define INT0_LO_EDMA_09 (17)
#define INT0_LO_EDMA_10 (18)
#define INT0_LO_EDMA_11 (19)
#define INT0_LO_EDMA_12 (20)
#define INT0_LO_EDMA_13 (21)
#define INT0_LO_EDMA_14 (22)
#define INT0_LO_EDMA_15 (23)
#define INT0_LO_EDMA_ERR (24)
#define INT0_LO_SCM_CWIC (25)
#define INT0_LO_UART0 (26)
#define INT0_LO_UART1 (27)
#define INT0_LO_UART2 (28)
#define INT0_LO_I2C (30)
#define INT0_LO_DSPI (31)
#define INT0_HI_DTMR0 (32)
#define INT0_HI_DTMR1 (33)
#define INT0_HI_DTMR2 (34)
#define INT0_HI_DTMR3 (35)
#define INT0_HI_SCMIR (62)
#define INT0_HI_RTC_ISR (63)
#define INT1_HI_CAN_BOFFINT (1)
#define INT1_HI_CAN_ERRINT (3)
#define INT1_HI_CAN_BUF0I (4)
#define INT1_HI_CAN_BUF1I (5)
#define INT1_HI_CAN_BUF2I (6)
#define INT1_HI_CAN_BUF3I (7)
#define INT1_HI_CAN_BUF4I (8)
#define INT1_HI_CAN_BUF5I (9)
#define INT1_HI_CAN_BUF6I (10)
#define INT1_HI_CAN_BUF7I (11)
#define INT1_HI_CAN_BUF8I (12)
#define INT1_HI_CAN_BUF9I (13)
#define INT1_HI_CAN_BUF10I (14)
#define INT1_HI_CAN_BUF11I (15)
#define INT1_HI_CAN_BUF12I (16)
#define INT1_HI_CAN_BUF13I (17)
#define INT1_HI_CAN_BUF14I (18)
#define INT1_HI_CAN_BUF15I (19)
#define INT1_HI_PIT0_PIF (43)
#define INT1_HI_PIT1_PIF (44)
#define INT1_HI_USBOTG_STS (47)
#define INT1_HI_SSI_ISR (49)
#define INT1_HI_PWM_INT (50)
#define INT1_HI_LCDC_ISR (51)
#define INT1_HI_CCM_UOCSR (53)
#define INT1_HI_DSPI_EOQF (54)
#define INT1_HI_DSPI_TFFF (55)
#define INT1_HI_DSPI_TCF (56)
#define INT1_HI_DSPI_TFUF (57)
#define INT1_HI_DSPI_RFDF (58)
#define INT1_HI_DSPI_RFOF (59)
#define INT1_HI_DSPI_RFOF_TFUF (60)
#define INT1_HI_TOUCH_ADC (61)
#define INT1_HI_PLL_LOCKS (62)
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
/* Bit definitions and macros for RCR */
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RCR_SOFTRST (0x80)
/* Bit definitions and macros for RSR */
#define RCM_RSR_LOL (0x01)
#define RCM_RSR_WDR_CORE (0x02)
#define RCM_RSR_EXT (0x04)
#define RCM_RSR_POR (0x08)
#define RCM_RSR_SOFT (0x20)
/*********************************************************************
* Chip Configuration Module (CCM)
*********************************************************************/
/* Bit definitions and macros for CCR */
#define CCM_CCR_DRAMSEL (0x0100)
#define CCM_CCR_CSC_UNMASK (0xFF3F)
#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0)
#define CCM_CCR_CSC_FBCS5_A22 (0x0080)
#define CCM_CCR_CSC_FB_A23_A22 (0x0040)
#define CCM_CCR_LIMP (0x0020)
#define CCM_CCR_LOAD (0x0010)
#define CCM_CCR_BOOTPS_UNMASK (0xFFF3)
#define CCM_CCR_BOOTPS_PS16 (0x0008)
#define CCM_CCR_BOOTPS_PS8 (0x0004)
#define CCM_CCR_BOOTPS_PS32 (0x0000)
#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002)
/* Bit definitions and macros for RCON */
#define CCM_RCON_CSC_UNMASK (0xFF3F)
#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0)
#define CCM_RCON_CSC_FBCS5_A22 (0x0080)
#define CCM_RCON_CSC_FB_A23_A22 (0x0040)
#define CCM_RCON_LIMP (0x0020)
#define CCM_RCON_LOAD (0x0010)
#define CCM_RCON_BOOTPS_UNMASK (0xFFF3)
#define CCM_RCON_BOOTPS_PS16 (0x0008)
#define CCM_RCON_BOOTPS_PS8 (0x0004)
#define CCM_RCON_BOOTPS_PS32 (0x0000)
#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002)
/* Bit definitions and macros for CIR */
#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
#define CCM_CIR_PRN(x) ((x) & 0x003F)
#define CCM_CIR_PIN_MCF52277 (0x0000)
/* Bit definitions and macros for MISCCR */
#define CCM_MISCCR_RTCSRC (0x4000)
#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */
#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */
#define CCM_MISCCR_BMT_65536 (0)
#define CCM_MISCCR_BMT_32768 (1)
#define CCM_MISCCR_BMT_16384 (2)
#define CCM_MISCCR_BMT_8192 (3)
#define CCM_MISCCR_BMT_4096 (4)
#define CCM_MISCCR_BMT_2048 (5)
#define CCM_MISCCR_BMT_1024 (6)
#define CCM_MISCCR_BMT_512 (7)
#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */
#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */
#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
/* Bit definitions and macros for CDR */
#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12)
#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */
#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */
/* Bit definitions and macros for UOCSR */
#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */
#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */
#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */
#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */
#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */
#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
#define CCM_UOCSR_SEND (0x0010) /* Session end */
#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */
#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */
/*********************************************************************
* General Purpose I/O Module (GPIO)
*********************************************************************/
/* Bit definitions and macros for PAR_BE */
#define GPIO_PAR_BE_UNMASK (0x0F)
#define GPIO_PAR_BE_BE3_BE3 (0x08)
#define GPIO_PAR_BE_BE3_GPIO (0x00)
#define GPIO_PAR_BE_BE2_BE2 (0x04)
#define GPIO_PAR_BE_BE2_GPIO (0x00)
#define GPIO_PAR_BE_BE1_BE1 (0x02)
#define GPIO_PAR_BE_BE1_GPIO (0x00)
#define GPIO_PAR_BE_BE0_BE0 (0x01)
#define GPIO_PAR_BE_BE0_GPIO (0x00)
/* Bit definitions and macros for PAR_CS */
#define GPIO_PAR_CS_CS3 (0x10)
#define GPIO_PAR_CS_CS2 (0x08)
#define GPIO_PAR_CS_CS1_FBCS1 (0x06)
#define GPIO_PAR_CS_CS1_SDCS1 (0x04)
#define GPIO_PAR_CS_CS1_GPIO (0x00)
#define GPIO_PAR_CS_CS0 (0x01)
/* Bit definitions and macros for PAR_FBCTL */
#define GPIO_PAR_FBCTL_OE (0x80)
#define GPIO_PAR_FBCTL_TA (0x40)
#define GPIO_PAR_FBCTL_RW (0x20)
#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7)
#define GPIO_PAR_FBCTL_TS_FBTS (0x18)
#define GPIO_PAR_FBCTL_TS_DMAACK (0x10)
#define GPIO_PAR_FBCTL_TS_GPIO (0x00)
/* Bit definitions and macros for PAR_FECI2C */
#define GPIO_PAR_I2C_SCL_UNMASK (0xF3)
#define GPIO_PAR_I2C_SCL_SCL (0x0C)
#define GPIO_PAR_I2C_SCL_CANTXD (0x08)
#define GPIO_PAR_I2C_SCL_U2TXD (0x04)
#define GPIO_PAR_I2C_SCL_GPIO (0x00)
#define GPIO_PAR_I2C_SDA_UNMASK (0xFC)
#define GPIO_PAR_I2C_SDA_SDA (0x03)
#define GPIO_PAR_I2C_SDA_CANRXD (0x02)
#define GPIO_PAR_I2C_SDA_U2RXD (0x01)
#define GPIO_PAR_I2C_SDA_GPIO (0x00)
/* Bit definitions and macros for PAR_UART */
#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF)
#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000)
#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000)
#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000)
#define GPIO_PAR_UART_U1CTS_GPIO (0x0000)
#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF)
#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000)
#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000)
#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000)
#define GPIO_PAR_UART_U1RTS_GPIO (0x0000)
#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF)
#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800)
#define GPIO_PAR_UART_U1RXD_GPIO (0x0000)
#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF)
#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200)
#define GPIO_PAR_UART_U1TXD_GPIO (0x0000)
#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F)
#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0)
#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080)
#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040)
#define GPIO_PAR_UART_U0CTS_GPIO (0x0000)
#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF)
#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030)
#define GPIO_PAR_UART_U0RTS_T1IN (0x0020)
#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010)
#define GPIO_PAR_UART_U0RTS_GPIO (0x0000)
#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3)
#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C)
#define GPIO_PAR_UART_U0RXD_CANRX (0x0008)
#define GPIO_PAR_UART_U0RXD_GPIO (0x0000)
#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC)
#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003)
#define GPIO_PAR_UART_U0TXD_CANTX (0x0002)
#define GPIO_PAR_UART_U0TXD_GPIO (0x0000)
/* Bit definitions and macros for PAR_DSPI */
#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F)
#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0)
#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80)
#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF)
#define GPIO_PAR_DSPI_SIN_SIN (0x30)
#define GPIO_PAR_DSPI_SIN_U2RXD (0x20)
#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3)
#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C)
#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08)
#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC)
#define GPIO_PAR_DSPI_SCK_SCK (0x03)
#define GPIO_PAR_DSPI_SCK_U2CTS (0x02)
#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
/* Bit definitions and macros for PAR_TIMER */
#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F)
#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40)
#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF)
#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10)
#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3)
#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04)
#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC)
#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01)
#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
/* Bit definitions and macros for GPIO_PAR_LCDCTL */
#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7)
#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18)
#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10)
#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00)
#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04)
#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02)
#define GPIO_PAR_LCDCTL_LSCLK (0x01)
/* Bit definitions and macros for PAR_IRQ */
#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3)
#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C)
#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08)
#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC)
#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03)
#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02)
#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01)
#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
/* Bit definitions and macros for GPIO_PAR_LCDH */
#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF)
#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00)
#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800)
#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000)
#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF)
#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300)
#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200)
#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000)
#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F)
#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0)
#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080)
#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000)
#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF)
#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030)
#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020)
#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000)
#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3)
#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C)
#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008)
#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000)
#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC)
#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003)
#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002)
#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000)
/* Bit definitions and macros for GPIO_PAR_LCDL */
#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF)
#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000)
#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000)
#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF)
#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000)
#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000)
#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF)
#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000)
#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000)
#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF)
#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000)
#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000)
#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF)
#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000)
#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000)
#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF)
#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000)
#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000)
#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF)
#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000)
#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000)
#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF)
#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000)
#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000)
#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF)
#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000)
#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000)
#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF)
#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000)
#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000)
#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF)
#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00)
#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800)
#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF)
#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300)
#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200)
#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000)
/* Bit definitions and macros for MSCR_FB */
#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF)
#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30)
#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20)
#define GPIO_MSCR_FB_DUPPER_OD (0x10)
#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00)
#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3)
#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C)
#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08)
#define GPIO_MSCR_FB_DLOWER_OD (0x04)
#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00)
#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC)
#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03)
#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02)
#define GPIO_MSCR_FB_ADDRCTL_OD (0x01)
#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00)
/* Bit definitions and macros for MSCR_SDRAM */
#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF)
#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30)
#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20)
#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10)
#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00)
#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3)
#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C)
#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08)
#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04)
#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00)
#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC)
#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03)
#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02)
#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01)
#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00)
/* Bit definitions and macros for Drive Strength Control */
#define DSCR_LOAD_50PF (0x03)
#define DSCR_LOAD_30PF (0x02)
#define DSCR_LOAD_20PF (0x01)
#define DSCR_LOAD_10PF (0x00)
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
/* Bit definitions and macros for SDMR */
#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
#define SDRAMC_SDMR_BK_LMR (0x00000000)
#define SDRAMC_SDMR_BK_LEMR (0x40000000)
/* Bit definitions and macros for SDCR */
#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
/* Bit definitions and macros for SDCFG1 */
#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
/* Bit definitions and macros for SDCFG2 */
#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
/* Bit definitions and macros for SDCS group */
#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/
/* Bit definitions and macros for PCR */
#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */
#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */
#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
#define PLL_PCR_PFDR_MASK (0x000F0000)
#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
/* Bit definitions and macros for PSR */
#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
/********************************************************************/
#endif /* __MCF5227X__ */

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u-boot/arch/m68k/include/asm/m5235.h Normal file
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/*
* mcf5329.h -- Definitions for Freescale Coldfire 5329
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef mcf5235_h
#define mcf5235_h
/****************************************************************************/
/*********************************************************************
* System Control Module (SCM)
*********************************************************************/
/* Bit definition and macros for SCM_IPSBAR */
#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30)
#define SCM_IPSBAR_V (0x00000001)
/* Bit definition and macros for SCM_RAMBAR */
#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16)
#define SCM_RAMBAR_BDE (0x00000200)
/* Bit definition and macros for SCM_CRSR */
#define SCM_CRSR_EXT (0x80)
/* Bit definitions and macros for SCM_CWCR */
#define SCM_CWCR_CWE (0x80)
#define SCM_CWCR_CWRI (0x40)
#define SCM_CWCR_CWT(x) (((x)&0x07)<<3)
#define SCM_CWCR_CWTA (0x04)
#define SCM_CWCR_CWTAVAL (0x02)
#define SCM_CWCR_CWTIC (0x01)
/* Bit definitions and macros for SCM_LPICR */
#define SCM_LPICR_ENBSTOP (0x80)
#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
#define SCM_LPICR_XLPM_IPL_ANY (0x00)
#define SCM_LPICR_XLPM_IPL_L2_7 (0x10)
#define SCM_LPICR_XLPM_IPL_L3_7 (0x20)
#define SCM_LPICR_XLPM_IPL_L4_7 (0x30)
#define SCM_LPICR_XLPM_IPL_L5_7 (0x40)
#define SCM_LPICR_XLPM_IPL_L6_7 (0x50)
#define SCM_LPICR_XLPM_IPL_L7 (0x70)
/* Bit definitions and macros for SCM_DMAREQC */
#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16)
#define SCM_DMAREQC_EXT_ETPU (0x00080000)
#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000)
#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000)
#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000)
#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12)
#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8)
#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4)
#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F))
#define SCM_DMAREQC_DMACn_DTMR0 (0x04)
#define SCM_DMAREQC_DMACn_DTMR1 (0x05)
#define SCM_DMAREQC_DMACn_DTMR2 (0x06)
#define SCM_DMAREQC_DMACn_DTMR3 (0x07)
#define SCM_DMAREQC_DMACn_UART0RX (0x08)
#define SCM_DMAREQC_DMACn_UART1RX (0x09)
#define SCM_DMAREQC_DMACn_UART2RX (0x0A)
#define SCM_DMAREQC_DMACn_UART0TX (0x0C)
#define SCM_DMAREQC_DMACn_UART1TX (0x0D)
#define SCM_DMAREQC_DMACn_UART3TX (0x0E)
/* Bit definitions and macros for SCM_MPARK */
#define SCM_MPARK_M2_P_EN (0x02000000)
#define SCM_MPARK_M3_PRTY_MSK (0x00C00000)
#define SCM_MPARK_M3_PRTY_4TH (0x00000000)
#define SCM_MPARK_M3_PRTY_3RD (0x00400000)
#define SCM_MPARK_M3_PRTY_2ND (0x00800000)
#define SCM_MPARK_M3_PRTY_1ST (0x00C00000)
#define SCM_MPARK_M2_PRTY_MSK (0x00300000)
#define SCM_MPARK_M2_PRTY_4TH (0x00000000)
#define SCM_MPARK_M2_PRTY_3RD (0x00100000)
#define SCM_MPARK_M2_PRTY_2ND (0x00200000)
#define SCM_MPARK_M2_PRTY_1ST (0x00300000)
#define SCM_MPARK_M0_PRTY_MSK (0x000C0000)
#define SCM_MPARK_M0_PRTY_4TH (0x00000000)
#define SCM_MPARK_M0_PRTY_3RD (0x00040000)
#define SCM_MPARK_M0_PRTY_2ND (0x00080000)
#define SCM_MPARK_M0_PRTY_1ST (0x000C0000)
#define SCM_MPARK_FIXED (0x00004000)
#define SCM_MPARK_TIMEOUT (0x00002000)
#define SCM_MPARK_PRKLAST (0x00001000)
#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8)
/* Bit definitions and macros for SCM_MPR */
#define SCM_MPR_MPR3 (0x08)
#define SCM_MPR_MPR2 (0x04)
#define SCM_MPR_MPR1 (0x02)
#define SCM_MPR_MPR0 (0x01)
/* Bit definitions and macros for SCM_PACRn */
#define SCM_PACRn_LOCK1 (0x80)
#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4)
#define SCM_PACRn_LOCK0 (0x08)
#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
/* Bit definitions and macros for SCM_GPACR */
#define SCM_PACRn_LOCK (0x80)
#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
/* Bit definitions and macros for SDRAMC_DCR */
#define SDRAMC_DCR_NAM (0x2000)
#define SDRAMC_DCR_COC (0x1000)
#define SDRAMC_DCR_IS (0x0800)
#define SDRAMC_DCR_RTIM_MASK (0x0C00)
#define SDRAMC_DCR_RTIM_3CLKS (0x0000)
#define SDRAMC_DCR_RTIM_6CLKS (0x0200)
#define SDRAMC_DCR_RTIM_9CLKS (0x0400)
#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8)
/* Bit definitions and macros for SDRAMC_DARCn */
#define SDRAMC_DARCn_BA(x) ((x)&0xFFFC0000)
#define SDRAMC_DARCn_RE (0x00008000)
#define SDRAMC_DARCn_CASL_MASK (0x00003000)
#define SDRAMC_DARCn_CASL_C0 (0x00000000)
#define SDRAMC_DARCn_CASL_C1 (0x00001000)
#define SDRAMC_DARCn_CASL_C2 (0x00002000)
#define SDRAMC_DARCn_CASL_C3 (0x00003000)
#define SDRAMC_DARCn_CBM_MASK (0x00000700)
#define SDRAMC_DARCn_CBM_CMD17 (0x00000000)
#define SDRAMC_DARCn_CBM_CMD18 (0x00000100)
#define SDRAMC_DARCn_CBM_CMD19 (0x00000200)
#define SDRAMC_DARCn_CBM_CMD20 (0x00000300)
#define SDRAMC_DARCn_CBM_CMD21 (0x00000400)
#define SDRAMC_DARCn_CBM_CMD22 (0x00000500)
#define SDRAMC_DARCn_CBM_CMD23 (0x00000600)
#define SDRAMC_DARCn_CBM_CMD24 (0x00000700)
#define SDRAMC_DARCn_IMRS (0x00000040)
#define SDRAMC_DARCn_PS_MASK (0x00000030)
#define SDRAMC_DARCn_PS_32 (0x00000000)
#define SDRAMC_DARCn_PS_16 (0x00000010)
#define SDRAMC_DARCn_PS_8 (0x00000020)
#define SDRAMC_DARCn_IP (0x00000008)
/* Bit definitions and macros for SDRAMC_DMRn */
#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18)
#define SDRAMC_DMRn_WP (0x00000100)
#define SDRAMC_DMRn_V (0x00000001)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_SCM (8)
#define INT0_LO_DMA0 (9)
#define INT0_LO_DMA1 (10)
#define INT0_LO_DMA2 (11)
#define INT0_LO_DMA3 (12)
#define INT0_LO_UART0 (13)
#define INT0_LO_UART1 (14)
#define INT0_LO_UART2 (15)
#define INT0_LO_RSVD1 (16)
#define INT0_LO_I2C (17)
#define INT0_LO_QSPI (18)
#define INT0_LO_DTMR0 (19)
#define INT0_LO_DTMR1 (20)
#define INT0_LO_DTMR2 (21)
#define INT0_LO_DTMR3 (22)
#define INT0_LO_FEC_TXF (23)
#define INT0_LO_FEC_TXB (24)
#define INT0_LO_FEC_UN (25)
#define INT0_LO_FEC_RL (26)
#define INT0_LO_FEC_RXF (27)
#define INT0_LO_FEC_RXB (28)
#define INT0_LO_FEC_MII (29)
#define INT0_LO_FEC_LC (30)
#define INT0_LO_FEC_HBERR (31)
#define INT0_HI_FEC_GRA (32)
#define INT0_HI_FEC_EBERR (33)
#define INT0_HI_FEC_BABT (34)
#define INT0_HI_FEC_BABR (35)
#define INT0_HI_PIT0 (36)
#define INT0_HI_PIT1 (37)
#define INT0_HI_PIT2 (38)
#define INT0_HI_PIT3 (39)
#define INT0_HI_RNG (40)
#define INT0_HI_SKHA (41)
#define INT0_HI_MDHA (42)
#define INT0_HI_CAN1_BUF0I (43)
#define INT0_HI_CAN1_BUF1I (44)
#define INT0_HI_CAN1_BUF2I (45)
#define INT0_HI_CAN1_BUF3I (46)
#define INT0_HI_CAN1_BUF4I (47)
#define INT0_HI_CAN1_BUF5I (48)
#define INT0_HI_CAN1_BUF6I (49)
#define INT0_HI_CAN1_BUF7I (50)
#define INT0_HI_CAN1_BUF8I (51)
#define INT0_HI_CAN1_BUF9I (52)
#define INT0_HI_CAN1_BUF10I (53)
#define INT0_HI_CAN1_BUF11I (54)
#define INT0_HI_CAN1_BUF12I (55)
#define INT0_HI_CAN1_BUF13I (56)
#define INT0_HI_CAN1_BUF14I (57)
#define INT0_HI_CAN1_BUF15I (58)
#define INT0_HI_CAN1_ERRINT (59)
#define INT0_HI_CAN1_BOFFINT (60)
/* 60-63 Reserved */
/* 0 - 7 Reserved */
#define INT1_LO_CAN1_BUF0I (8)
#define INT1_LO_CAN1_BUF1I (9)
#define INT1_LO_CAN1_BUF2I (10)
#define INT1_LO_CAN1_BUF3I (11)
#define INT1_LO_CAN1_BUF4I (12)
#define INT1_LO_CAN1_BUF5I (13)
#define INT1_LO_CAN1_BUF6I (14)
#define INT1_LO_CAN1_BUF7I (15)
#define INT1_LO_CAN1_BUF8I (16)
#define INT1_LO_CAN1_BUF9I (17)
#define INT1_LO_CAN1_BUF10I (18)
#define INT1_LO_CAN1_BUF11I (19)
#define INT1_LO_CAN1_BUF12I (20)
#define INT1_LO_CAN1_BUF13I (21)
#define INT1_LO_CAN1_BUF14I (22)
#define INT1_LO_CAN1_BUF15I (23)
#define INT1_LO_CAN1_ERRINT (24)
#define INT1_LO_CAN1_BOFFINT (25)
/* 26 Reserved */
#define INT1_LO_ETPU_TC0F (27)
#define INT1_LO_ETPU_TC1F (28)
#define INT1_LO_ETPU_TC2F (29)
#define INT1_LO_ETPU_TC3F (30)
#define INT1_LO_ETPU_TC4F (31)
#define INT1_HI_ETPU_TC5F (32)
#define INT1_HI_ETPU_TC6F (33)
#define INT1_HI_ETPU_TC7F (34)
#define INT1_HI_ETPU_TC8F (35)
#define INT1_HI_ETPU_TC9F (36)
#define INT1_HI_ETPU_TC10F (37)
#define INT1_HI_ETPU_TC11F (38)
#define INT1_HI_ETPU_TC12F (39)
#define INT1_HI_ETPU_TC13F (40)
#define INT1_HI_ETPU_TC14F (41)
#define INT1_HI_ETPU_TC15F (42)
#define INT1_HI_ETPU_TC16F (43)
#define INT1_HI_ETPU_TC17F (44)
#define INT1_HI_ETPU_TC18F (45)
#define INT1_HI_ETPU_TC19F (46)
#define INT1_HI_ETPU_TC20F (47)
#define INT1_HI_ETPU_TC21F (48)
#define INT1_HI_ETPU_TC22F (49)
#define INT1_HI_ETPU_TC23F (50)
#define INT1_HI_ETPU_TC24F (51)
#define INT1_HI_ETPU_TC25F (52)
#define INT1_HI_ETPU_TC26F (53)
#define INT1_HI_ETPU_TC27F (54)
#define INT1_HI_ETPU_TC28F (55)
#define INT1_HI_ETPU_TC29F (56)
#define INT1_HI_ETPU_TC30F (57)
#define INT1_HI_ETPU_TC31F (58)
#define INT1_HI_ETPU_TGIF (59)
/*********************************************************************
* General Purpose I/O (GPIO)
*********************************************************************/
/* Bit definitions and macros for GPIO_PODR */
#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5)
#define GPIO_PODR_ADDR_MASK (0xE0)
#define GPIO_PODR_BS(x) ((x)&0x0F)
#define GPIO_PODR_BS_MASK (0x0F)
#define GPIO_PODR_CS(x) (((x)&0x7F)<<1)
#define GPIO_PODR_CS_MASK (0xFE)
#define GPIO_PODR_SDRAM(X) ((x)&0x3F)
#define GPIO_PODR_SDRAM_MASK (0x3F)
#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x)
#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK
#define GPIO_PODR_UARTH(x) ((x)&0x03)
#define GPIO_PODR_UARTH_MASK (0x03)
#define GPIO_PODR_QSPI(x) ((x)&0x1F)
#define GPIO_PODR_QSPI_MASK (0x1F)
#define GPIO_PODR_ETPU(x) ((x)&0x07)
#define GPIO_PODR_ETPU_MASK (0x07)
/* Bit definitions and macros for GPIO_PDDR */
#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x)
#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK
#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PPDSDR */
#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x)
#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK
#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PCLRR */
#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x)
#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK
#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PAR */
#define GPIO_PAR_AD_ADDR23 (0x80)
#define GPIO_PAR_AD_ADDR22 (0x40)
#define GPIO_PAR_AD_ADDR21 (0x20)
#define GPIO_PAR_AD_DATAL (0x01)
#define GPIO_PAR_BUSCTL_OE (0x4000)
#define GPIO_PAR_BUSCTL_TA (0x1000)
#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10)
#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00)
#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400)
#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800)
#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00)
#define GPIO_PAR_BUSCTL_RWB (0x0100)
#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040)
#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010)
#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2)
#define GPIO_PAR_BUSCTL_TS_MASK (0x0C)
#define GPIO_PAR_BUSCTL_TS_GPIO (0x04)
#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08)
#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C)
#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03)
#define GPIO_PAR_BUSCTL_TIP_MASK (0x03)
#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01)
#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02)
#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03)
#define GPIO_PAR_BS(x) ((x)&0x0F)
#define GPIO_PAR_BS_MASK (0x0F)
#define GPIO_PAR_CS(x) (((x)&0x7F)<<1)
#define GPIO_PAR_CS_MASK (0xFE)
#define GPIO_PAR_CS_CS7 (0x80)
#define GPIO_PAR_CS_CS6 (0x40)
#define GPIO_PAR_CS_CS5 (0x20)
#define GPIO_PAR_CS_CS4 (0x10)
#define GPIO_PAR_CS_CS3 (0x08)
#define GPIO_PAR_CS_CS2 (0x04)
#define GPIO_PAR_CS_CS1 (0x02)
#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3
#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2
#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6)
#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0)
#define GPIO_PAR_SDRAM_SDWE (0x20)
#define GPIO_PAR_SDRAM_SCAS (0x10)
#define GPIO_PAR_SDRAM_SRAS (0x08)
#define GPIO_PAR_SDRAM_SCKE (0x04)
#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03)
#define GPIO_PAR_SDRAM_SDCS_MASK (0x03)
#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6)
#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0)
#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40)
#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80)
#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0)
#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4)
#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30)
#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10)
#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20)
#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30)
#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
#define GPIO_PAR_FECI2C_SCL_MASK (0x0C)
#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08)
#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C)
#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03)
#define GPIO_PAR_FECI2C_SDA_MASK (0x03)
#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02)
#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03)
#define GPIO_PAR_UART_DREQ2 (0x8000)
#define GPIO_PAR_UART_CAN1EN (0x4000)
#define GPIO_PAR_UART_U2RXD (0x2000)
#define GPIO_PAR_UART_U2TXD (0x1000)
#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10)
#define GPIO_PAR_UART_U1RXD_MASK (0x0C00)
#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800)
#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8)
#define GPIO_PAR_UART_U1TXD_MASK (0x0300)
#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200)
#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6)
#define GPIO_PAR_UART_U1CTS_MASK (0x00C0)
#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080)
#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0)
#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4)
#define GPIO_PAR_UART_U1RTS_MASK (0x0030)
#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020)
#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030)
#define GPIO_PAR_UART_U0RXD (0x0008)
#define GPIO_PAR_UART_U0TXD (0x0004)
#define GPIO_PAR_UART_U0CTS (0x0002)
#define GPIO_PAR_UART_U0RTS (0x0001)
#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6)
#define GPIO_PAR_QSPI_CS1_MASK (0xC0)
#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80)
#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0)
#define GPIO_PAR_QSPI_CS0 (0x20)
#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3)
#define GPIO_PAR_QSPI_DIN_MASK (0x18)
#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10)
#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18)
#define GPIO_PAR_QSPI_DOUT (0x04)
#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03)
#define GPIO_PAR_QSPI_SCK_MASK (0x03)
#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02)
#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03)
#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14)
#define GPIO_PAR_DT3IN_MASK (0xC000)
#define GPIO_PAR_DT3IN_QSPICS2 (0x4000)
#define GPIO_PAR_DT3IN_U2CTS (0x8000)
#define GPIO_PAR_DT3IN_DT3IN (0xC000)
#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12)
#define GPIO_PAR_DT2IN_MASK (0x3000)
#define GPIO_PAR_DT2IN_DT2OUT (0x1000)
#define GPIO_PAR_DT2IN_DREQ2 (0x2000)
#define GPIO_PAR_DT2IN_DT2IN (0x3000)
#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10)
#define GPIO_PAR_DT1IN_MASK (0x0C00)
#define GPIO_PAR_DT1IN_DT1OUT (0x0400)
#define GPIO_PAR_DT1IN_DREQ1 (0x0800)
#define GPIO_PAR_DT1IN_DT1IN (0x0C00)
#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8)
#define GPIO_PAR_DT0IN_MASK (0x0300)
#define GPIO_PAR_DT0IN_DREQ0 (0x0200)
#define GPIO_PAR_DT0IN_DT0IN (0x0300)
#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6)
#define GPIO_PAR_DT3OUT_MASK (0x00C0)
#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040)
#define GPIO_PAR_DT3OUT_U2RTS (0x0080)
#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0)
#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4)
#define GPIO_PAR_DT2OUT_MASK (0x0030)
#define GPIO_PAR_DT2OUT_DACK2 (0x0020)
#define GPIO_PAR_DT2OUT_DT2OUT (0x0030)
#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2)
#define GPIO_PAR_DT1OUT_MASK (0x000C)
#define GPIO_PAR_DT1OUT_DACK1 (0x0008)
#define GPIO_PAR_DT1OUT_DT1OUT (0x000C)
#define GPIO_PAR_DT0OUT(x) ((x)&0x03)
#define GPIO_PAR_DT0OUT_MASK (0x0003)
#define GPIO_PAR_DT0OUT_DACK0 (0x0002)
#define GPIO_PAR_DT0OUT_DT0OUT (0x0003)
#define GPIO_PAR_ETPU_TCRCLK (0x04)
#define GPIO_PAR_ETPU_UTPU_ODIS (0x02)
#define GPIO_PAR_ETPU_LTPU_ODIS (0x01)
/* Bit definitions and macros for GPIO_DSCR */
#define GPIO_DSCR_EIM_EIM1 (0x10)
#define GPIO_DSCR_EIM_EIM0 (0x01)
#define GPIO_DSCR_ETPU_ETPU31_24 (0x40)
#define GPIO_DSCR_ETPU_ETPU23_16 (0x10)
#define GPIO_DSCR_ETPU_ETPU15_8 (0x04)
#define GPIO_DSCR_ETPU_ETPU7_0 (0x01)
#define GPIO_DSCR_FECI2C_FEC (0x10)
#define GPIO_DSCR_FECI2C_I2C (0x01)
#define GPIO_DSCR_UART_IRQ (0x40)
#define GPIO_DSCR_UART_UART2 (0x10)
#define GPIO_DSCR_UART_UART1 (0x04)
#define GPIO_DSCR_UART_UART0 (0x01)
#define GPIO_DSCR_QSPI_QSPI (0x01)
#define GPIO_DSCR_TIMER (0x01)
/*********************************************************************
* Chip Configuration Module (CCM)
*********************************************************************/
/* Bit definitions and macros for CCM_RCR */
#define CCM_RCR_SOFTRST (0x80)
#define CCM_RCR_FRCRSTOUT (0x40)
/* Bit definitions and macros for CCM_RSR */
#define CCM_RSR_SOFT (0x20)
#define CCM_RSR_WDR (0x10)
#define CCM_RSR_POR (0x08)
#define CCM_RSR_EXT (0x04)
#define CCM_RSR_LOC (0x02)
#define CCM_RSR_LOL (0x01)
/* Bit definitions and macros for CCM_CCR */
#define CCM_CCR_LOAD (0x8000)
#define CCM_CCR_SZEN (0x0040)
#define CCM_CCR_PSTEN (0x0020)
#define CCM_CCR_BME (0x0008)
#define CCM_CCR_BMT(x) ((x)&0x07)
#define CCM_CCR_BMT_MASK (0x0007)
#define CCM_CCR_BMT_64K (0x0000)
#define CCM_CCR_BMT_32K (0x0001)
#define CCM_CCR_BMT_16K (0x0002)
#define CCM_CCR_BMT_8K (0x0003)
#define CCM_CCR_BMT_4K (0x0004)
#define CCM_CCR_BMT_2K (0x0005)
#define CCM_CCR_BMT_1K (0x0006)
#define CCM_CCR_BMT_512 (0x0007)
/* Bit definitions and macros for CCM_RCON */
#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
#define CCM_RCON_RLOAD (0x0020)
#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
#define CCM_RCON_BOOTPS_MASK (0x0018)
#define CCM_RCON_BOOTPS_32 (0x0018)
#define CCM_RCON_BOOTPS_16 (0x0008)
#define CCM_RCON_BOOTPS_8 (0x0010)
#define CCM_RCON_MODE (0x0001)
/* Bit definitions and macros for CCM_CIR */
#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
#define CCM_CIR_PRN(x) ((x) & 0x003F)
/*********************************************************************
* PLL Clock Module
*********************************************************************/
/* Bit definitions and macros for PLL_SYNCR */
#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24)
#define PLL_SYNCR_MFD_MASK (0x07000000)
#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19)
#define PLL_SYNCR_RFC_MASK (0x00380000)
#define PLL_SYNCR_LOCEN (0x00040000)
#define PLL_SYNCR_LOLRE (0x00020000)
#define PLL_SYNCR_LOCRE (0x00010000)
#define PLL_SYNCR_DISCLK (0x00008000)
#define PLL_SYNCR_LOLIRQ (0x00004000)
#define PLL_SYNCR_LOCIRQ (0x00002000)
#define PLL_SYNCR_RATE (0x00001000)
#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10)
#define PLL_SYNCR_EXP(x) ((x)&0x03FF)
/* Bit definitions and macros for PLL_SYNSR */
#define PLL_SYNSR_LOLF (0x00000200)
#define PLL_SYNSR_LOC (0x00000100)
#define PLL_SYNSR_MODE (0x00000080)
#define PLL_SYNSR_PLLSEL (0x00000040)
#define PLL_SYNSR_PLLREF (0x00000020)
#define PLL_SYNSR_LOCKS (0x00000010)
#define PLL_SYNSR_LOCK (0x00000008)
#define PLL_SYNSR_LOCF (0x00000004)
#define PLL_SYNSR_CALDONE (0x00000002)
#define PLL_SYNSR_CALPASS (0x00000001)
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
/* Bit definitions and macros for WTM_WCR */
#define WTM_WCR_WAIT (0x0008)
#define WTM_WCR_DOZE (0x0004)
#define WTM_WCR_HALTED (0x0002)
#define WTM_WCR_EN (0x0001)
#endif /* mcf5235_h */

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/*
* mcf5249.h -- Definitions for Motorola Coldfire 5249
*
* Based on mcf5272sim.h of uCLinux distribution:
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef mcf5249_h
#define mcf5249_h
/****************************************************************************/
/*
* useful definitions for reading/writing MBAR offset memory
*/
#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
#define mbar2_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x))
#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y
#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y
#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y
/*
* Size of internal RAM
*/
#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
/*
* Define the 5249 SIM register set addresses.
*/
/*****************
***** MBAR1 *****
*****************/
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
/*****************
***** MBAR2 *****
*****************/
/* GPIO Addresses
* Note: These are offset from MBAR2!
*/
#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */
#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w) */
#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w) */
#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */
#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */
#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */
#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */
#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */
#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */
#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */
#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */
#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */
#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */
#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */
#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */
#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */
#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */
#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */
#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */
#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */
#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */
#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */
#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */
#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */
#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */
#define MCFSIM_PLLCR 0x180 /* PLL Control register */
/*
* Some symbol defines for the above...
*/
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
/* XXX - If needed, DMA ICRs go here */
#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
/*
* Bit definitions for the ICR family of registers.
*/
#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
/*
* Macros to read/set IMR register. It is 32 bits on the 5249.
*/
#define mcf_getimr() \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
#define mcf_setimr(imr) \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
#endif /* mcf5249_h */

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/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef m5253_h
#define m5253_h
/****************************************************************************/
/*
* PLL Module (PLL)
*/
/* Register read/write macros */
#define PLL_PLLCR (0x000180)
#define SIM_RSR (0x000000)
#define SIM_SYPCR (0x000001)
#define SIM_SWIVR (0x000002)
#define SIM_SWSR (0x000003)
#define SIM_MPARK (0x00000C)
/* Bit definitions and macros for RSR */
#define SIM_RSR_SWTR (0x20)
#define SIM_RSR_HRST (0x80)
/* Register read/write macros */
#define CIM_MISCCR (0x000500)
#define CIM_ATA_DADDR (0x000504)
#define CIM_ATA_DCOUNT (0x000508)
#define CIM_RTC_TIME (0x00050C)
#define CIM_USB_CANCLK (0x000510)
/* Bit definitions and macros for MISCCR */
#define CIM_MISCCR_ADTA (0x00000001)
#define CIM_MISCCR_ADTD (0x00000002)
#define CIM_MISCCR_ADIE (0x00000004)
#define CIM_MISCCR_ADIC (0x00000008)
#define CIM_MISCCR_ADIP (0x00000010)
#define CIM_MISCCR_CPUEND (0x00000020)
#define CIM_MISCCR_DMAEND (0x00000040)
#define CIM_MISCCR_RTCCLR (0x00000080)
#define CIM_MISCCR_RTCPL (0x00000100)
#define CIM_MISCCR_URIE (0x00000800)
#define CIM_MISCCR_URIC (0x00001000)
#define CIM_MISCCR_URIP (0x00002000)
/* Bit definitions and macros for ATA_DADDR */
#define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2)
#define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18)
/* Bit definitions and macros for ATA_DCOUNT */
#define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF))
#endif /* m5253_h */

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/*
* mcf5271.h -- Definitions for Motorola Coldfire 5271
*
* (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com>
* Based on mcf5272sim.h of uCLinux distribution:
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _MCF5271_H_
#define _MCF5271_H_
#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
#define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x))
#define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x))
#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
#define MCF_FMPLL_SYNCR 0x120000
#define MCF_FMPLL_SYNSR 0x120004
#define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24)
#define MCF_SYNCR_MFD_4X 0x00000000
#define MCF_SYNCR_MFD_6X 0x01000000
#define MCF_SYNCR_MFD_8X 0x02000000
#define MCF_SYNCR_MFD_10X 0x03000000
#define MCF_SYNCR_MFD_12X 0x04000000
#define MCF_SYNCR_MFD_14X 0x05000000
#define MCF_SYNCR_MFD_16X 0x06000000
#define MCF_SYNCR_MFD_18X 0x07000000
#define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19)
#define MCF_SYNCR_RFD_DIV1 0x00000000
#define MCF_SYNCR_RFD_DIV2 0x00080000
#define MCF_SYNCR_RFD_DIV4 0x00100000
#define MCF_SYNCR_RFD_DIV8 0x00180000
#define MCF_SYNCR_RFD_DIV16 0x00200000
#define MCF_SYNCR_RFD_DIV32 0x00280000
#define MCF_SYNCR_RFD_DIV64 0x00300000
#define MCF_SYNCR_RFD_DIV128 0x00380000
#define MCF_FMPLL_SYNSR_LOCK 0x8
#define MCF_WTM_WCR 0x140000
#define MCF_WTM_WCNTR 0x140004
#define MCF_WTM_WSR 0x140006
#define MCF_WTM_WCR_EN 0x0001
#define MCF_RCM_RCR 0x110000
#define MCF_RCM_RCR_FRCRSTOUT 0x40
#define MCF_RCM_RCR_SOFTRST 0x80
#define MCF_GPIO_PODR_ADDR 0x100000
#define MCF_GPIO_PODR_DATAH 0x100001
#define MCF_GPIO_PODR_DATAL 0x100002
#define MCF_GPIO_PODR_BUSCTL 0x100003
#define MCF_GPIO_PODR_BS 0x100004
#define MCF_GPIO_PODR_CS 0x100005
#define MCF_GPIO_PODR_SDRAM 0x100006
#define MCF_GPIO_PODR_FECI2C 0x100007
#define MCF_GPIO_PODR_UARTH 0x100008
#define MCF_GPIO_PODR_UARTL 0x100009
#define MCF_GPIO_PODR_QSPI 0x10000A
#define MCF_GPIO_PODR_TIMER 0x10000B
#define MCF_GPIO_PDDR_ADDR 0x100010
#define MCF_GPIO_PDDR_DATAH 0x100011
#define MCF_GPIO_PDDR_DATAL 0x100012
#define MCF_GPIO_PDDR_BUSCTL 0x100013
#define MCF_GPIO_PDDR_BS 0x100014
#define MCF_GPIO_PDDR_CS 0x100015
#define MCF_GPIO_PDDR_SDRAM 0x100016
#define MCF_GPIO_PDDR_FECI2C 0x100017
#define MCF_GPIO_PDDR_UARTH 0x100018
#define MCF_GPIO_PDDR_UARTL 0x100019
#define MCF_GPIO_PDDR_QSPI 0x10001A
#define MCF_GPIO_PDDR_TIMER 0x10001B
#define MCF_GPIO_PPDSDR_ADDR 0x100020
#define MCF_GPIO_PPDSDR_DATAH 0x100021
#define MCF_GPIO_PPDSDR_DATAL 0x100022
#define MCF_GPIO_PPDSDR_BUSCTL 0x100023
#define MCF_GPIO_PPDSDR_BS 0x100024
#define MCF_GPIO_PPDSDR_CS 0x100025
#define MCF_GPIO_PPDSDR_SDRAM 0x100026
#define MCF_GPIO_PPDSDR_FECI2C 0x100027
#define MCF_GPIO_PPDSDR_UARTH 0x100028
#define MCF_GPIO_PPDSDR_UARTL 0x100029
#define MCF_GPIO_PPDSDR_QSPI 0x10002A
#define MCF_GPIO_PPDSDR_TIMER 0x10002B
#define MCF_GPIO_PCLRR_ADDR 0x100030
#define MCF_GPIO_PCLRR_DATAH 0x100031
#define MCF_GPIO_PCLRR_DATAL 0x100032
#define MCF_GPIO_PCLRR_BUSCTL 0x100033
#define MCF_GPIO_PCLRR_BS 0x100034
#define MCF_GPIO_PCLRR_CS 0x100035
#define MCF_GPIO_PCLRR_SDRAM 0x100036
#define MCF_GPIO_PCLRR_FECI2C 0x100037
#define MCF_GPIO_PCLRR_UARTH 0x100038
#define MCF_GPIO_PCLRR_UARTL 0x100039
#define MCF_GPIO_PCLRR_QSPI 0x10003A
#define MCF_GPIO_PCLRR_TIMER 0x10003B
#define MCF_GPIO_PAR_AD 0x100040
#define MCF_GPIO_PAR_BUSCTL 0x100042
#define MCF_GPIO_PAR_BS 0x100044
#define MCF_GPIO_PAR_CS 0x100045
#define MCF_GPIO_PAR_SDRAM 0x100046
#define MCF_GPIO_PAR_FECI2C 0x100047
#define MCF_GPIO_PAR_UART 0x100048
#define MCF_GPIO_PAR_QSPI 0x10004A
#define MCF_GPIO_PAR_TIMER 0x10004C
#define MCF_DSCR_EIM 0x100050
#define MCF_DCSR_FEC12C 0x100052
#define MCF_DCSR_UART 0x100053
#define MCF_DCSR_QSPI 0x100054
#define MCF_DCSR_TIMER 0x100055
#define MCF_CCM_CIR 0x11000A
#define MCF_CCM_CIR_PRN_MASK 0x3F
#define MCF_CCM_CIR_PIN_LEN 6
#define MCF_CCM_CIR_PIN_MCF5270 0x002e
#define MCF_CCM_CIR_PIN_MCF5271 0x0032
#define MCF_GPIO_AD_ADDR23 0x80
#define MCF_GPIO_AD_ADDR22 0x40
#define MCF_GPIO_AD_ADDR21 0x20
#define MCF_GPIO_AD_DATAL 0x01
#define MCF_GPIO_AD_MASK 0xe1
#define MCF_GPIO_PAR_CS_PAR_CS2 0x04
#define MCF_GPIO_SDRAM_CSSDCS_00 0x00 /* CS[3:2] pins: CS3, CS2 */
#define MCF_GPIO_SDRAM_CSSDCS_01 0x40 /* CS[3:2] pins: CS3, SD_CS0 */
#define MCF_GPIO_SDRAM_CSSDCS_10 0x80 /* CS[3:2] pins: SD_CS1, SC2 */
#define MCF_GPIO_SDRAM_CSSDCS_11 0xc0 /* CS[3:2] pins: SD_CS1, SD_CS0 */
#define MCF_GPIO_SDRAM_SDWE 0x20 /* WE pin */
#define MCF_GPIO_SDRAM_SCAS 0x10 /* CAS pin */
#define MCF_GPIO_SDRAM_SRAS 0x08 /* RAS pin */
#define MCF_GPIO_SDRAM_SCKE 0x04 /* CKE pin */
#define MCF_GPIO_SDRAM_SDCS_00 0x00 /* SD_CS[0:1] pins: GPIO, GPIO */
#define MCF_GPIO_SDRAM_SDCS_01 0x01 /* SD_CS[0:1] pins: GPIO, SD_CS0 */
#define MCF_GPIO_SDRAM_SDCS_10 0x02 /* SD_CS[0:1] pins: SD_CS1, GPIO */
#define MCF_GPIO_SDRAM_SDCS_11 0x03 /* SD_CS[0:1] pins: SD_CS1, SD_CS0 */
#define MCF_GPIO_PAR_UART_U0RTS 0x0001
#define MCF_GPIO_PAR_UART_U0CTS 0x0002
#define MCF_GPIO_PAR_UART_U0TXD 0x0004
#define MCF_GPIO_PAR_UART_U0RXD 0x0008
#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
/* Bit definitions and macros for PAR_QSPI */
#define MCF_GPIO_PAR_QSPI_PCS1_UNMASK 0x3F
#define MCF_GPIO_PAR_QSPI_PCS1_PCS1 0xC0
#define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE 0x80
#define MCF_GPIO_PAR_QSPI_PCS1_GPIO 0x00
#define MCF_GPIO_PAR_QSPI_PCS0_UNMASK 0xDF
#define MCF_GPIO_PAR_QSPI_PCS0_PCS0 0x20
#define MCF_GPIO_PAR_QSPI_PCS0_GPIO 0x00
#define MCF_GPIO_PAR_QSPI_SIN_UNMASK 0xE7
#define MCF_GPIO_PAR_QSPI_SIN_SIN 0x18
#define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA 0x10
#define MCF_GPIO_PAR_QSPI_SIN_GPIO 0x00
#define MCF_GPIO_PAR_QSPI_SOUT_UNMASK 0xFB
#define MCF_GPIO_PAR_QSPI_SOUT_SOUT 0x04
#define MCF_GPIO_PAR_QSPI_SOUT_GPIO 0x00
#define MCF_GPIO_PAR_QSPI_SCK_UNMASK 0xFC
#define MCF_GPIO_PAR_QSPI_SCK_SCK 0x03
#define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL 0x02
#define MCF_GPIO_PAR_QSPI_SCK_GPIO 0x00
/* Bit definitions and macros for PAR_TIMER for QSPI */
#define MCF_GPIO_PAR_TIMER_T3IN_UNMASK 0x3FFF
#define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2 0x4000
#define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK 0xFF3F
#define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3 0x0040
#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
#define MCF_SDRAMC_DCR 0x000040
#define MCF_SDRAMC_DACR0 0x000048
#define MCF_SDRAMC_DMR0 0x00004C
#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
#define MCF_SDRAMC_DCR_IS 0x0800
#define MCF_SDRAMC_DCR_COC 0x1000
#define MCF_SDRAMC_DCR_NAM 0x2000
#define MCF_SDRAMC_DACRn_IP 0x00000008
#define MCF_SDRAMC_DACRn_PS(x) (((x)&0x00000003)<<4)
#define MCF_SDRAMC_DACRn_MRS 0x00000040
#define MCF_SDRAMC_DACRn_CBM(x) (((x)&0x00000007)<<8)
#define MCF_SDRAMC_DACRn_CASL(x) (((x)&0x00000003)<<12)
#define MCF_SDRAMC_DACRn_RE 0x00008000
#define MCF_SDRAMC_DACRn_BA(x) (((x)&0x00003FFF)<<18)
#define MCF_SDRAMC_DMRn_BAM_8M 0x007C0000
#define MCF_SDRAMC_DMRn_BAM_16M 0x00FC0000
#define MCF_SDRAMC_DMRn_V 0x00000001
#define MCFSIM_ICR1 0x000C41
/* Interrupt Controller (INTC) */
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_SCM (8)
#define INT0_LO_DMA0 (9)
#define INT0_LO_DMA1 (10)
#define INT0_LO_DMA2 (11)
#define INT0_LO_DMA3 (12)
#define INT0_LO_UART0 (13)
#define INT0_LO_UART1 (14)
#define INT0_LO_UART2 (15)
#define INT0_LO_RSVD1 (16)
#define INT0_LO_I2C (17)
#define INT0_LO_QSPI (18)
#define INT0_LO_DTMR0 (19)
#define INT0_LO_DTMR1 (20)
#define INT0_LO_DTMR2 (21)
#define INT0_LO_DTMR3 (22)
#define INT0_LO_FEC_TXF (23)
#define INT0_LO_FEC_TXB (24)
#define INT0_LO_FEC_UN (25)
#define INT0_LO_FEC_RL (26)
#define INT0_LO_FEC_RXF (27)
#define INT0_LO_FEC_RXB (28)
#define INT0_LO_FEC_MII (29)
#define INT0_LO_FEC_LC (30)
#define INT0_LO_FEC_HBERR (31)
#define INT0_HI_FEC_GRA (32)
#define INT0_HI_FEC_EBERR (33)
#define INT0_HI_FEC_BABT (34)
#define INT0_HI_FEC_BABR (35)
#define INT0_HI_PIT0 (36)
#define INT0_HI_PIT1 (37)
#define INT0_HI_PIT2 (38)
#define INT0_HI_PIT3 (39)
#define INT0_HI_RNG (40)
#define INT0_HI_SKHA (41)
#define INT0_HI_MDHA (42)
#define INT0_HI_CAN1_BUF0I (43)
#define INT0_HI_CAN1_BUF1I (44)
#define INT0_HI_CAN1_BUF2I (45)
#define INT0_HI_CAN1_BUF3I (46)
#define INT0_HI_CAN1_BUF4I (47)
#define INT0_HI_CAN1_BUF5I (48)
#define INT0_HI_CAN1_BUF6I (49)
#define INT0_HI_CAN1_BUF7I (50)
#define INT0_HI_CAN1_BUF8I (51)
#define INT0_HI_CAN1_BUF9I (52)
#define INT0_HI_CAN1_BUF10I (53)
#define INT0_HI_CAN1_BUF11I (54)
#define INT0_HI_CAN1_BUF12I (55)
#define INT0_HI_CAN1_BUF13I (56)
#define INT0_HI_CAN1_BUF14I (57)
#define INT0_HI_CAN1_BUF15I (58)
#define INT0_HI_CAN1_ERRINT (59)
#define INT0_HI_CAN1_BOFFINT (60)
/* 60-63 Reserved */
#endif /* _MCF5271_H_ */

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/*
* mcf5272.h -- Definitions for Motorola Coldfire 5272
*
* Based on mcf5272sim.h of uCLinux distribution:
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef mcf5272_h
#define mcf5272_h
/****************************************************************************/
/*
* Size of internal RAM
*/
#define INT_RAM_SIZE 4096
#define GPIO_PACNT_PA15MSK (0xC0000000)
#define GPIO_PACNT_DGNT1 (0x40000000)
#define GPIO_PACNT_PA14MSK (0x30000000)
#define GPIO_PACNT_DREQ1 (0x10000000)
#define GPIO_PACNT_PA13MSK (0x0C000000)
#define GPIO_PACNT_DFSC3 (0x04000000)
#define GPIO_PACNT_PA12MSK (0x03000000)
#define GPIO_PACNT_DFSC2 (0x01000000)
#define GPIO_PACNT_PA11MSK (0x00C00000)
#define GPIO_PACNT_QSPI_CS1 (0x00800000)
#define GPIO_PACNT_PA10MSK (0x00300000)
#define GPIO_PACNT_DREQ0 (0x00100000)
#define GPIO_PACNT_PA9MSK (0x000C0000)
#define GPIO_PACNT_DGNT0 (0x00040000)
#define GPIO_PACNT_PA8MSK (0x00030000)
#define GPIO_PACNT_FSC0 (0x00010000)
#define GPIO_PACNT_FSR0 (0x00010000)
#define GPIO_PACNT_PA7MSK (0x0000C000)
#define GPIO_PACNT_DOUT3 (0x00008000)
#define GPIO_PACNT_QSPI_CS3 (0x00004000)
#define GPIO_PACNT_PA6MSK (0x00003000)
#define GPIO_PACNT_USB_RXD (0x00001000)
#define GPIO_PACNT_PA5MSK (0x00000C00)
#define GPIO_PACNT_USB_TXEN (0x00000400)
#define GPIO_PACNT_PA4MSK (0x00000300)
#define GPIO_PACNT_USB_SUSP (0x00000100)
#define GPIO_PACNT_PA3MSK (0x000000C0)
#define GPIO_PACNT_USB_TN (0x00000040)
#define GPIO_PACNT_PA2MSK (0x00000030)
#define GPIO_PACNT_USB_RN (0x00000010)
#define GPIO_PACNT_PA1MSK (0x0000000C)
#define GPIO_PACNT_USB_RP (0x00000004)
#define GPIO_PACNT_PA0MSK (0x00000003)
#define GPIO_PACNT_USB_TP (0x00000001)
#define GPIO_PBCNT_PB15MSK (0xC0000000)
#define GPIO_PBCNT_E_MDC (0x40000000)
#define GPIO_PBCNT_PB14MSK (0x30000000)
#define GPIO_PBCNT_E_RXER (0x10000000)
#define GPIO_PBCNT_PB13MSK (0x0C000000)
#define GPIO_PBCNT_E_RXD1 (0x04000000)
#define GPIO_PBCNT_PB12MSK (0x03000000)
#define GPIO_PBCNT_E_RXD2 (0x01000000)
#define GPIO_PBCNT_PB11MSK (0x00C00000)
#define GPIO_PBCNT_E_RXD3 (0x00400000)
#define GPIO_PBCNT_PB10MSK (0x00300000)
#define GPIO_PBCNT_E_TXD1 (0x00100000)
#define GPIO_PBCNT_PB9MSK (0x000C0000)
#define GPIO_PBCNT_E_TXD2 (0x00040000)
#define GPIO_PBCNT_PB8MSK (0x00030000)
#define GPIO_PBCNT_E_TXD3 (0x00010000)
#define GPIO_PBCNT_PB7MSK (0x0000C000)
#define GPIO_PBCNT_TOUT0 (0x00004000)
#define GPIO_PBCNT_PB6MSK (0x00003000)
#define GPIO_PBCNT_TA (0x00001000)
#define GPIO_PBCNT_PB4MSK (0x00000300)
#define GPIO_PBCNT_URT0_CLK (0x00000100)
#define GPIO_PBCNT_PB3MSK (0x000000C0)
#define GPIO_PBCNT_URT0_RTS (0x00000040)
#define GPIO_PBCNT_PB2MSK (0x00000030)
#define GPIO_PBCNT_URT0_CTS (0x00000010)
#define GPIO_PBCNT_PB1MSK (0x0000000C)
#define GPIO_PBCNT_URT0_RXD (0x00000004)
#define GPIO_PBCNT_URT0_TIN2 (0x00000004)
#define GPIO_PBCNT_PB0MSK (0x00000003)
#define GPIO_PBCNT_URT0_TXD (0x00000001)
#define GPIO_PDCNT_PD7MSK (0x0000C000)
#define GPIO_PDCNT_TIN1 (0x00008000)
#define GPIO_PDCNT_PWM_OUT2 (0x00004000)
#define GPIO_PDCNT_PD6MSK (0x00003000)
#define GPIO_PDCNT_TOUT1 (0x00002000)
#define GPIO_PDCNT_PWM_OUT1 (0x00001000)
#define GPIO_PDCNT_PD5MSK (0x00000C00)
#define GPIO_PDCNT_INT4 (0x00000C00)
#define GPIO_PDCNT_DIN3 (0x00000800)
#define GPIO_PDCNT_PD4MSK (0x00000300)
#define GPIO_PDCNT_URT1_TXD (0x00000200)
#define GPIO_PDCNT_DOUT0 (0x00000100)
#define GPIO_PDCNT_PD3MSK (0x000000C0)
#define GPIO_PDCNT_INT5 (0x000000C0)
#define GPIO_PDCNT_URT1_RTS (0x00000080)
#define GPIO_PDCNT_PD2MSK (0x00000030)
#define GPIO_PDCNT_QSPI_CS2 (0x00000030)
#define GPIO_PDCNT_URT1_CTS (0x00000020)
#define GPIO_PDCNT_PD1MSK (0x0000000C)
#define GPIO_PDCNT_URT1_RXD (0x00000008)
#define GPIO_PDCNT_URT1_TIN3 (0x00000008)
#define GPIO_PDCNT_DIN0 (0x00000004)
#define GPIO_PDCNT_PD0MSK (0x00000003)
#define GPIO_PDCNT_URT1_CLK (0x00000002)
#define GPIO_PDCNT_DCL0 (0x00000001)
#define INT_RSVD0 (0)
#define INT_INT1 (1)
#define INT_INT2 (2)
#define INT_INT3 (3)
#define INT_INT4 (4)
#define INT_TMR0 (5)
#define INT_TMR1 (6)
#define INT_TMR2 (7)
#define INT_TMR3 (8)
#define INT_UART1 (9)
#define INT_UART2 (10)
#define INT_PLIP (11)
#define INT_PLIA (12)
#define INT_USB0 (13)
#define INT_USB1 (14)
#define INT_USB2 (15)
#define INT_USB3 (16)
#define INT_USB4 (17)
#define INT_USB5 (18)
#define INT_USB6 (19)
#define INT_USB7 (20)
#define INT_DMA (21)
#define INT_ERX (22)
#define INT_ETX (23)
#define INT_ENTC (24)
#define INT_QSPI (25)
#define INT_INT5 (26)
#define INT_INT6 (27)
#define INT_SWTO (28)
#define INT_ICR1_TMR0MASK (0x000F000)
#define INT_ICR1_TMR0PI (0x0008000)
#define INT_ICR1_TMR0IPL(x) (((x)&0x7)<<12)
#define INT_ICR1_TMR1MASK (0x0000F00)
#define INT_ICR1_TMR1PI (0x0000800)
#define INT_ICR1_TMR1IPL(x) (((x)&0x7)<<8)
#define INT_ICR1_TMR2MASK (0x00000F0)
#define INT_ICR1_TMR2PI (0x0000080)
#define INT_ICR1_TMR2IPL(x) (((x)&0x7)<<4)
#define INT_ICR1_TMR3MASK (0x000000F)
#define INT_ICR1_TMR3PI (0x0000008)
#define INT_ICR1_TMR3IPL(x) (((x)&0x7))
#define INT_ISR_INT31 (0x80000000)
#define INT_ISR_INT30 (0x40000000)
#define INT_ISR_INT29 (0x20000000)
#define INT_ISR_INT28 (0x10000000)
#define INT_ISR_INT27 (0x08000000)
#define INT_ISR_INT26 (0x04000000)
#define INT_ISR_INT25 (0x02000000)
#define INT_ISR_INT24 (0x01000000)
#define INT_ISR_INT23 (0x00800000)
#define INT_ISR_INT22 (0x00400000)
#define INT_ISR_INT21 (0x00200000)
#define INT_ISR_INT20 (0x00100000)
#define INT_ISR_INT19 (0x00080000)
#define INT_ISR_INT18 (0x00040000)
#define INT_ISR_INT17 (0x00020000)
#define INT_ISR_INT16 (0x00010000)
#define INT_ISR_INT15 (0x00008000)
#define INT_ISR_INT14 (0x00004000)
#define INT_ISR_INT13 (0x00002000)
#define INT_ISR_INT12 (0x00001000)
#define INT_ISR_INT11 (0x00000800)
#define INT_ISR_INT10 (0x00000400)
#define INT_ISR_INT9 (0x00000200)
#define INT_ISR_INT8 (0x00000100)
#define INT_ISR_INT7 (0x00000080)
#define INT_ISR_INT6 (0x00000040)
#define INT_ISR_INT5 (0x00000020)
#define INT_ISR_INT4 (0x00000010)
#define INT_ISR_INT3 (0x00000008)
#define INT_ISR_INT2 (0x00000004)
#define INT_ISR_INT1 (0x00000002)
#define INT_ISR_INT0 (0x00000001)
#endif /* mcf5272_h */

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/*
* MCF5275 Internal Memory Map
*
* Copyright (C) 2003-2004, Greg Ungerer (gerg@snapgear.com)
* Copyright (C) 2004-2008 Arthur Shipkowski (art@videon-central.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __M5275_H__
#define __M5275_H__
/*
* Define the 5275 SIM register set addresses. These are similar,
* but not quite identical to the 5282 registers and offsets.
*/
#define MCF_GPIO_PAR_UART 0x10007c
#define UART0_ENABLE_MASK 0x000f
#define UART1_ENABLE_MASK 0x00f0
#define UART2_ENABLE_MASK 0x3f00
#define MCF_GPIO_PAR_FECI2C 0x100082
#define PAR_SDA_ENABLE_MASK 0x0003
#define PAR_SCL_ENABLE_MASK 0x000c
#define MCFSIM_WRRR 0x140000
#define MCFSIM_SDCR 0x40
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
/* Register read/write macros */
#define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040]))
#define MCF_SDRAMC_SDCR (*(vuint32*)(void*)(&__IPSBAR[0x000044]))
#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
#define MCF_SDRAMC_SDBAR0 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
#define MCF_SDRAMC_SDBAR1 (*(vuint32*)(void*)(&__IPSBAR[0x000058]))
#define MCF_SDRAMC_SDMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
#define MCF_SDRAMC_SDMR1 (*(vuint32*)(void*)(&__IPSBAR[0x00005C]))
/* Bit definitions and macros for MCF_SDRAMC_SDMR */
#define MCF_SDRAMC_SDMR_CMD (0x00010000)
#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
/* Bit definitions and macros for MCF_SDRAMC_SDCR */
#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
#define MCF_SDRAMC_SDCR_IREF (0x00000004)
#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10)
#define MCF_SDRAMC_SDCR_DQP_BP (0x00008000)
#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
#define MCF_SDRAMC_SDCR_REF (0x10000000)
#define MCF_SDRAMC_SDCR_CKE (0x40000000)
#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
/* Bit definitions and macros for MCF_SDRAMC_SDBARn */
#define MCF_SDRAMC_SDBARn_BASE(x) (((x)&0x00003FFF)<<18)
#define MCF_SDRAMC_SDBARn_BA(x) ((x)&0xFFFF0000)
/* Bit definitions and macros for MCF_SDRAMC_SDMRn */
#define MCF_SDRAMC_SDMRn_V (0x00000001)
#define MCF_SDRAMC_SDMRn_WP (0x00000080)
#define MCF_SDRAMC_SDMRn_MASK(x) (((x)&0x00003FFF)<<18)
#define MCF_SDRAMC_SDMRn_BAM_4G (0xFFFF0000)
#define MCF_SDRAMC_SDMRn_BAM_2G (0x7FFF0000)
#define MCF_SDRAMC_SDMRn_BAM_1G (0x3FFF0000)
#define MCF_SDRAMC_SDMRn_BAM_1024M (0x3FFF0000)
#define MCF_SDRAMC_SDMRn_BAM_512M (0x1FFF0000)
#define MCF_SDRAMC_SDMRn_BAM_256M (0x0FFF0000)
#define MCF_SDRAMC_SDMRn_BAM_128M (0x07FF0000)
#define MCF_SDRAMC_SDMRn_BAM_64M (0x03FF0000)
#define MCF_SDRAMC_SDMRn_BAM_32M (0x01FF0000)
#define MCF_SDRAMC_SDMRn_BAM_16M (0x00FF0000)
#define MCF_SDRAMC_SDMRn_BAM_8M (0x007F0000)
#define MCF_SDRAMC_SDMRn_BAM_4M (0x003F0000)
#define MCF_SDRAMC_SDMRn_BAM_2M (0x001F0000)
#define MCF_SDRAMC_SDMRn_BAM_1M (0x000F0000)
#define MCF_SDRAMC_SDMRn_BAM_1024K (0x000F0000)
#define MCF_SDRAMC_SDMRn_BAM_512K (0x00070000)
#define MCF_SDRAMC_SDMRn_BAM_256K (0x00030000)
#define MCF_SDRAMC_SDMRn_BAM_128K (0x00010000)
#define MCF_SDRAMC_SDMRn_BAM_64K (0x00000000)
/*********************************************************************
* Interrupt Controller (INTC)
********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_SCM (8)
#define INT0_LO_DMA0 (9)
#define INT0_LO_DMA1 (10)
#define INT0_LO_DMA2 (11)
#define INT0_LO_DMA3 (12)
#define INT0_LO_UART0 (13)
#define INT0_LO_UART1 (14)
#define INT0_LO_UART2 (15)
#define INT0_LO_RSVD1 (16)
#define INT0_LO_I2C (17)
#define INT0_LO_QSPI (18)
#define INT0_LO_DTMR0 (19)
#define INT0_LO_DTMR1 (20)
#define INT0_LO_DTMR2 (21)
#define INT0_LO_DTMR3 (22)
#define INT0_LO_FEC0_TXF (23)
#define INT0_LO_FEC0_TXB (24)
#define INT0_LO_FEC0_UN (25)
#define INT0_LO_FEC0_RL (26)
#define INT0_LO_FEC0_RXF (27)
#define INT0_LO_FEC0_RXB (28)
#define INT0_LO_FEC0_MII (29)
#define INT0_LO_FEC0_LC (30)
#define INT0_LO_FEC0_HBERR (31)
#define INT0_HI_FEC0_GRA (32)
#define INT0_HI_FEC0_EBERR (33)
#define INT0_HI_FEC0_BABT (34)
#define INT0_HI_FEC0_BABR (35)
#define INT0_HI_PIT0 (36)
#define INT0_HI_PIT1 (37)
#define INT0_HI_PIT2 (38)
#define INT0_HI_PIT3 (39)
#define INT0_HI_RNG (40)
#define INT0_HI_SKHA (41)
#define INT0_HI_MDHA (42)
#define INT0_HI_USB (43)
#define INT0_HI_USB_EP0 (44)
#define INT0_HI_USB_EP1 (45)
#define INT0_HI_USB_EP2 (46)
#define INT0_HI_USB_EP3 (47)
/* 48-63 Reserved */
/* 0-22 Reserved */
#define INT1_LO_FEC1_TXF (23)
#define INT1_LO_FEC1_TXB (24)
#define INT1_LO_FEC1_UN (25)
#define INT1_LO_FEC1_RL (26)
#define INT1_LO_FEC1_RXF (27)
#define INT1_LO_FEC1_RXB (28)
#define INT1_LO_FEC1_MII (29)
#define INT1_LO_FEC1_LC (30)
#define INT1_LO_FEC1_HBERR (31)
#define INT1_HI_FEC1_GRA (32)
#define INT1_HI_FEC1_EBERR (33)
#define INT1_HI_FEC1_BABT (34)
#define INT1_HI_FEC1_BABR (35)
/* 36-63 Reserved */
/* Bit definitions and macros for RCR */
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RCR_SOFTRST (0x80)
#define FMPLL_SYNSR_LOCK (0x00000008)
#endif /* __M5275_H__ */

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/*
* mcf5282.h -- Definitions for Motorola Coldfire 5282
*
* SPDX-License-Identifier: GPL-2.0+
*/
/****************************************************************************/
#ifndef m5282_h
#define m5282_h
/*********************************************************************
* PLL Clock Module
*********************************************************************/
/* Bit definitions and macros for PLL_SYNCR */
#define PLL_SYNCR_LOLRE (0x8000)
#define PLL_SYNCR_MFD2 (0x4000)
#define PLL_SYNCR_MFD1 (0x2000)
#define PLL_SYNCR_MFD0 (0x1000)
#define PLL_SYNCR_LOCRE (0x0800)
#define PLL_SYNCR_RFC2 (0x0400)
#define PLL_SYNCR_RFC1 (0x0200)
#define PLL_SYNCR_RFC0 (0x0100)
#define PLL_SYNCR_LOCEN (0x0080)
#define PLL_SYNCR_DISCLK (0x0040)
#define PLL_SYNCR_FWKUP (0x0020)
#define PLL_SYNCR_STPMD1 (0x0008)
#define PLL_SYNCR_STPMD0 (0x0004)
/* Bit definitions and macros for PLL_SYNSR */
#define PLL_SYNSR_MODE (0x0080)
#define PLL_SYNSR_PLLSEL (0x0040)
#define PLL_SYNSR_PLLREF (0x0020)
#define PLL_SYNSR_LOCKS (0x0010)
#define PLL_SYNSR_LOCK (0x0008)
#define PLL_SYNSR_LOCS (0x0004)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_SCM_SWT1 (8)
#define INT0_LO_DMA_00 (9)
#define INT0_LO_DMA_01 (10)
#define INT0_LO_DMA_02 (11)
#define INT0_LO_DMA_03 (12)
#define INT0_LO_UART0 (13)
#define INT0_LO_UART1 (14)
#define INT0_LO_UART2 (15)
#define INT0_LO_RSVD1 (16)
#define INT0_LO_I2C (17)
#define INT0_LO_QSPI (18)
#define INT0_LO_DTMR0 (19)
#define INT0_LO_DTMR1 (20)
#define INT0_LO_DTMR2 (21)
#define INT0_LO_DTMR3 (22)
#define INT0_LO_FEC_TXF (23)
#define INT0_LO_FEC_TXB (24)
#define INT0_LO_FEC_UN (25)
#define INT0_LO_FEC_RL (26)
#define INT0_LO_FEC_RXF (27)
#define INT0_LO_FEC_RXB (28)
#define INT0_LO_FEC_MII (29)
#define INT0_LO_FEC_LC (30)
#define INT0_LO_FEC_HBERR (31)
#define INT0_HI_FEC_GRA (32)
#define INT0_HI_FEC_EBERR (33)
#define INT0_HI_FEC_BABT (34)
#define INT0_HI_FEC_BABR (35)
#define INT0_HI_PMM_LVDF (36)
#define INT0_HI_QADC_CF1 (37)
#define INT0_HI_QADC_CF2 (38)
#define INT0_HI_QADC_PF1 (39)
#define INT0_HI_QADC_PF2 (40)
#define INT0_HI_GPTA_TOF (41)
#define INT0_HI_GPTA_PAIF (42)
#define INT0_HI_GPTA_PAOVF (43)
#define INT0_HI_GPTA_C0F (44)
#define INT0_HI_GPTA_C1F (45)
#define INT0_HI_GPTA_C2F (46)
#define INT0_HI_GPTA_C3F (47)
#define INT0_HI_GPTB_TOF (48)
#define INT0_HI_GPTB_PAIF (49)
#define INT0_HI_GPTB_PAOVF (50)
#define INT0_HI_GPTB_C0F (51)
#define INT0_HI_GPTB_C1F (52)
#define INT0_HI_GPTB_C2F (53)
#define INT0_HI_GPTB_C3F (54)
#define INT0_HI_PIT0 (55)
#define INT0_HI_PIT1 (56)
#define INT0_HI_PIT2 (57)
#define INT0_HI_PIT3 (58)
#define INT0_HI_CFM_CBEIF (59)
#define INT0_HI_CFM_CCIF (60)
#define INT0_HI_CFM_PVIF (61)
#define INT0_HI_CFM_AEIF (62)
/*
* Size of internal RAM
*/
#define INT_RAM_SIZE 65536
/* General Purpose I/O Module GPIO */
#define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000))
#define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001))
#define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002))
#define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003))
#define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004))
#define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005))
#define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006))
#define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007))
#define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008))
#define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009))
#define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A))
#define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B))
#define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C))
#define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D))
#define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E))
#define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F))
#define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010))
#define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011))
#define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014))
#define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015))
#define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016))
#define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017))
#define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018))
#define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019))
#define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A))
#define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B))
#define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C))
#define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D))
#define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E))
#define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F))
#define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020))
#define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021))
#define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022))
#define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023))
#define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024))
#define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025))
#define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
#define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
#define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
#define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
#define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
#define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
#define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
#define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
#define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
#define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
#define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
#define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
#define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
#define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
#define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
#define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
#define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
#define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
#define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
#define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
#define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
#define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
#define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
#define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
#define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
#define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
#define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
#define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
#define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
#define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
#define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
#define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
#define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
#define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
#define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
#define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
#define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C))
#define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D))
#define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E))
#define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F))
#define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040))
#define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041))
#define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042))
#define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043))
#define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044))
#define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045))
#define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046))
#define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047))
#define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048))
#define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049))
#define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A))
#define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B))
#define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C))
#define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D))
#define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050))
#define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051))
#define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052))
#define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054))
#define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055))
#define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056))
#define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058))
#define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059))
#define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A))
#define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B))
#define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C))
/* Bit level definitions and macros */
#define MCFGPIO_PORT7 (0x80)
#define MCFGPIO_PORT6 (0x40)
#define MCFGPIO_PORT5 (0x20)
#define MCFGPIO_PORT4 (0x10)
#define MCFGPIO_PORT3 (0x08)
#define MCFGPIO_PORT2 (0x04)
#define MCFGPIO_PORT1 (0x02)
#define MCFGPIO_PORT0 (0x01)
#define MCFGPIO_PORT(x) (0x01<<x)
#define MCFGPIO_DDR7 (0x80)
#define MCFGPIO_DDR6 (0x40)
#define MCFGPIO_DDR5 (0x20)
#define MCFGPIO_DDR4 (0x10)
#define MCFGPIO_DDR3 (0x08)
#define MCFGPIO_DDR2 (0x04)
#define MCFGPIO_DDR1 (0x02)
#define MCFGPIO_DDR0 (0x01)
#define MCFGPIO_DDR(x) (0x01<<x)
#define MCFGPIO_Px7 (0x80)
#define MCFGPIO_Px6 (0x40)
#define MCFGPIO_Px5 (0x20)
#define MCFGPIO_Px4 (0x10)
#define MCFGPIO_Px3 (0x08)
#define MCFGPIO_Px2 (0x04)
#define MCFGPIO_Px1 (0x02)
#define MCFGPIO_Px0 (0x01)
#define MCFGPIO_Px(x) (0x01<<x)
#define MCFGPIO_PBCDPAR_PBPA (0x80)
#define MCFGPIO_PBCDPAR_PCDPA (0x40)
#define MCFGPIO_PEPAR_PEPA7 (0x4000)
#define MCFGPIO_PEPAR_PEPA6 (0x1000)
#define MCFGPIO_PEPAR_PEPA5 (0x0400)
#define MCFGPIO_PEPAR_PEPA4 (0x0100)
#define MCFGPIO_PEPAR_PEPA3 (0x0040)
#define MCFGPIO_PEPAR_PEPA2 (0x0010)
#define MCFGPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PEPAR_PEPA0(x) (((x)&0x3))
#define MCFGPIO_PFPAR_PFPA7 (0x80)
#define MCFGPIO_PFPAR_PFPA6 (0x40)
#define MCFGPIO_PFPAR_PFPA5 (0x20)
#define MCFGPIO_PJPAR_PJPA7 (0x80)
#define MCFGPIO_PJPAR_PJPA6 (0x40)
#define MCFGPIO_PJPAR_PJPA5 (0x20)
#define MCFGPIO_PJPAR_PJPA4 (0x10)
#define MCFGPIO_PJPAR_PJPA3 (0x08)
#define MCFGPIO_PJPAR_PJPA2 (0x04)
#define MCFGPIO_PJPAR_PJPA1 (0x02)
#define MCFGPIO_PJPAR_PJPA0 (0x01)
#define MCFGPIO_PJPAR_PJPA(x) (0x01<<x)
#define MCFGPIO_PSDPAR_PSDPA (0x80)
#define MCFGPIO_PASPAR_PASPA5(x) (((x)&0x3)<<10)
#define MCFGPIO_PASPAR_PASPA4(x) (((x)&0x3)<<8)
#define MCFGPIO_PASPAR_PASPA3(x) (((x)&0x3)<<6)
#define MCFGPIO_PASPAR_PASPA2(x) (((x)&0x3)<<4)
#define MCFGPIO_PASPAR_PASPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PASPAR_PASPA0(x) (((x)&0x3))
#define MCFGPIO_PEHLPAR_PEHPA (0x80)
#define MCFGPIO_PEHLPAR_PELPA (0x40)
#define MCFGPIO_PQSPAR_PQSPA6 (0x40)
#define MCFGPIO_PQSPAR_PQSPA5 (0x20)
#define MCFGPIO_PQSPAR_PQSPA4 (0x10)
#define MCFGPIO_PQSPAR_PQSPA3 (0x08)
#define MCFGPIO_PQSPAR_PQSPA2 (0x04)
#define MCFGPIO_PQSPAR_PQSPA1 (0x02)
#define MCFGPIO_PQSPAR_PQSPA0 (0x01)
#define MCFGPIO_PQSPAR_PQSPA(x) (0x01<<x)
#define MCFGPIO_PTCPAR_PTCPA3(x) (((x)&0x3)<<6)
#define MCFGPIO_PTCPAR_PTCPA2(x) (((x)&0x3)<<4)
#define MCFGPIO_PTCPAR_PTCPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PTCPAR_PTCPA0(x) (((x)&0x3))
#define MCFGPIO_PTDPAR_PTDPA3(x) (((x)&0x3)<<6)
#define MCFGPIO_PTDPAR_PTDPA2(x) (((x)&0x3)<<4)
#define MCFGPIO_PTDPAR_PTDPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PTDPAR_PTDPA0(x) (((x)&0x3))
#define MCFGPIO_PUAPAR_PUAPA3 (0x08)
#define MCFGPIO_PUAPAR_PUAPA2 (0x04)
#define MCFGPIO_PUAPAR_PUAPA1 (0x02)
#define MCFGPIO_PUAPAR_PUAPA0 (0x01)
/* System Conrol Module SCM */
#define MCFSCM_RAMBAR (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008))
#define MCFSCM_CRSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010))
#define MCFSCM_CWCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011))
#define MCFSCM_LPICR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012))
#define MCFSCM_CWSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013))
#define MCFSCM_MPARK (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C))
#define MCFSCM_MPR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020))
#define MCFSCM_PACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024))
#define MCFSCM_PACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025))
#define MCFSCM_PACR2 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026))
#define MCFSCM_PACR3 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027))
#define MCFSCM_PACR4 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028))
#define MCFSCM_PACR5 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A))
#define MCFSCM_PACR6 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B))
#define MCFSCM_PACR7 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C))
#define MCFSCM_PACR8 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E))
#define MCFSCM_GPACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030))
#define MCFSCM_GPACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031))
#define MCFSCM_CRSR_EXT (0x80)
#define MCFSCM_CRSR_CWDR (0x20)
#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
#define MCFSCM_RAMBAR_BDE (0x00000200)
/* Reset Controller Module RCM */
#define MCFRESET_RCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000))
#define MCFRESET_RSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001))
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
#define MCFRESET_RCR_LVDF (0x10)
#define MCFRESET_RCR_LVDIE (0x08)
#define MCFRESET_RCR_LVDRE (0x04)
#define MCFRESET_RCR_LVDE (0x01)
#define MCFRESET_RSR_LVD (0x40)
#define MCFRESET_RSR_SOFT (0x20)
#define MCFRESET_RSR_WDR (0x10)
#define MCFRESET_RSR_POR (0x08)
#define MCFRESET_RSR_EXT (0x04)
#define MCFRESET_RSR_LOC (0x02)
#define MCFRESET_RSR_LOL (0x01)
#define MCFRESET_RSR_ALL (0x7F)
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
/* Chip Configuration Module CCM */
#define MCFCCM_CCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004))
#define MCFCCM_RCON (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008))
#define MCFCCM_CIR (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A))
/* Bit level definitions and macros */
#define MCFCCM_CCR_LOAD (0x8000)
#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
#define MCFCCM_CCR_SZEN (0x0040)
#define MCFCCM_CCR_PSTEN (0x0020)
#define MCFCCM_CCR_BME (0x0008)
#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
#define MCFCCM_CIR_PIN_MASK (0xFF00)
#define MCFCCM_CIR_PRN_MASK (0x00FF)
/* Clock Module */
#define MCFCLOCK_SYNCR (*(vu_short *)(CONFIG_SYS_MBAR+0x120000))
#define MCFCLOCK_SYNSR (*(vu_char *) (CONFIG_SYS_MBAR+0x120002))
#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
#define MCFCLOCK_SYNSR_LOCK 0x08
#define MCFSDRAMC_DCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040))
#define MCFSDRAMC_DACR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048))
#define MCFSDRAMC_DMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c))
#define MCFSDRAMC_DACR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050))
#define MCFSDRAMC_DMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054))
#define MCFSDRAMC_DCR_NAM (0x2000)
#define MCFSDRAMC_DCR_COC (0x1000)
#define MCFSDRAMC_DCR_IS (0x0800)
#define MCFSDRAMC_DCR_RTIM_3 (0x0000)
#define MCFSDRAMC_DCR_RTIM_6 (0x0200)
#define MCFSDRAMC_DCR_RTIM_9 (0x0400)
#define MCFSDRAMC_DCR_RC(x) ((x)&0x01FF)
#define MCFSDRAMC_DACR_BASE(x) ((x)&0xFFFC0000)
#define MCFSDRAMC_DACR_RE (0x00008000)
#define MCFSDRAMC_DACR_CASL(x) (((x)&0x03)<<12)
#define MCFSDRAMC_DACR_CBM(x) (((x)&0x07)<<8)
#define MCFSDRAMC_DACR_PS_32 (0x00000000)
#define MCFSDRAMC_DACR_PS_16 (0x00000020)
#define MCFSDRAMC_DACR_PS_8 (0x00000010)
#define MCFSDRAMC_DACR_IP (0x00000008)
#define MCFSDRAMC_DACR_IMRS (0x00000040)
#define MCFSDRAMC_DMR_BAM_16M (0x00FC0000)
#define MCFSDRAMC_DMR_WP (0x00000100)
#define MCFSDRAMC_DMR_CI (0x00000040)
#define MCFSDRAMC_DMR_AM (0x00000020)
#define MCFSDRAMC_DMR_SC (0x00000010)
#define MCFSDRAMC_DMR_SD (0x00000008)
#define MCFSDRAMC_DMR_UC (0x00000004)
#define MCFSDRAMC_DMR_UD (0x00000002)
#define MCFSDRAMC_DMR_V (0x00000001)
#define MCFWTM_WCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000))
#define MCFWTM_WMR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002))
#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004))
#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006))
/*********************************************************************
* General Purpose Timer (GPT) Module
*********************************************************************/
#define MCFGPTA_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000))
#define MCFGPTA_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001))
#define MCFGPTA_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002))
#define MCFGPTA_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003))
#define MCFGPTA_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004))
#define MCFGPTA_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006))
#define MCFGPTA_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008))
#define MCFGPTA_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009))
#define MCFGPTA_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B))
#define MCFGPTA_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C))
#define MCFGPTA_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D))
#define MCFGPTA_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E))
#define MCFGPTA_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F))
#define MCFGPTA_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010))
#define MCFGPTA_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012))
#define MCFGPTA_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014))
#define MCFGPTA_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016))
#define MCFGPTA_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018))
#define MCFGPTA_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019))
#define MCFGPTA_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A))
#define MCFGPTA_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D))
#define MCFGPTA_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E))
#define MCFGPTB_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000))
#define MCFGPTB_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001))
#define MCFGPTB_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002))
#define MCFGPTB_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003))
#define MCFGPTB_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004))
#define MCFGPTB_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006))
#define MCFGPTB_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008))
#define MCFGPTB_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009))
#define MCFGPTB_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B))
#define MCFGPTB_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C))
#define MCFGPTB_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D))
#define MCFGPTB_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E))
#define MCFGPTB_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F))
#define MCFGPTB_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010))
#define MCFGPTB_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012))
#define MCFGPTB_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014))
#define MCFGPTB_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016))
#define MCFGPTB_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018))
#define MCFGPTB_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019))
#define MCFGPTB_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A))
#define MCFGPTB_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D))
#define MCFGPTB_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E))
/* Bit level definitions and macros */
#define MCFGPT_GPTIOS_IOS3 (0x08)
#define MCFGPT_GPTIOS_IOS2 (0x04)
#define MCFGPT_GPTIOS_IOS1 (0x02)
#define MCFGPT_GPTIOS_IOS0 (0x01)
#define MCFGPT_GPTCFORC_FOC3 (0x08)
#define MCFGPT_GPTCFORC_FOC2 (0x04)
#define MCFGPT_GPTCFORC_FOC1 (0x02)
#define MCFGPT_GPTCFORC_FOC0 (0x01)
#define MCFGPT_GPTOC3M_OC3M3 (0x08)
#define MCFGPT_GPTOC3M_OC3M2 (0x04)
#define MCFGPT_GPTOC3M_OC3M1 (0x02)
#define MCFGPT_GPTOC3M_OC3M0 (0x01)
#define MCFGPT_GPTOC3M_OC3D(x) (((x)&0x04))
#define MCFGPT_GPTSCR1_GPTEN (0x80)
#define MCFGPT_GPTSCR1_TFFCA (0x10)
#define MCFGPT_GPTTOV3 (0x08)
#define MCFGPT_GPTTOV2 (0x04)
#define MCFGPT_GPTTOV1 (0x02)
#define MCFGPT_GPTTOV0 (0x01)
#define MCFGPT_GPTCTL_OMOL3(x) (((x)&0x03)<<6)
#define MCFGPT_GPTCTL_OMOL2(x) (((x)&0x03)<<4)
#define MCFGPT_GPTCTL_OMOL1(x) (((x)&0x03)<<2)
#define MCFGPT_GPTCTL_OMOL0(x) (((x)&0x03))
#define MCFGPT_GPTCTL2_EDG3(x) (((x)&0x03)<<6)
#define MCFGPT_GPTCTL2_EDG2(x) (((x)&0x03)<<4)
#define MCFGPT_GPTCTL2_EDG1(x) (((x)&0x03)<<2)
#define MCFGPT_GPTCTL2_EDG0(x) (((x)&0x03))
#define MCFGPT_GPTIE_C3I (0x08)
#define MCFGPT_GPTIE_C2I (0x04)
#define MCFGPT_GPTIE_C1I (0x02)
#define MCFGPT_GPTIE_C0I (0x01)
#define MCFGPT_GPTSCR2_TOI (0x80)
#define MCFGPT_GPTSCR2_PUPT (0x20)
#define MCFGPT_GPTSCR2_RDPT (0x10)
#define MCFGPT_GPTSCR2_TCRE (0x08)
#define MCFGPT_GPTSCR2_PR(x) (((x)&0x07))
#define MCFGPT_GPTFLG1_C3F (0x08)
#define MCFGPT_GPTFLG1_C2F (0x04)
#define MCFGPT_GPTFLG1_C1F (0x02)
#define MCFGPT_GPTFLG1_C0F (0x01)
#define MCFGPT_GPTFLG2_TOF (0x80)
#define MCFGPT_GPTFLG2_C3F (0x08)
#define MCFGPT_GPTFLG2_C2F (0x04)
#define MCFGPT_GPTFLG2_C1F (0x02)
#define MCFGPT_GPTFLG2_C0F (0x01)
#define MCFGPT_GPTPACTL_PAE (0x40)
#define MCFGPT_GPTPACTL_PAMOD (0x20)
#define MCFGPT_GPTPACTL_PEDGE (0x10)
#define MCFGPT_GPTPACTL_CLK_PACLK (0x04)
#define MCFGPT_GPTPACTL_CLK_PACLK256 (0x08)
#define MCFGPT_GPTPACTL_CLK_PACLK65536 (0x0C)
#define MCFGPT_GPTPACTL_CLK(x) (((x)&0x03)<<2)
#define MCFGPT_GPTPACTL_PAOVI (0x02)
#define MCFGPT_GPTPACTL_PAI (0x01)
#define MCFGPT_GPTPAFLG_PAOVF (0x02)
#define MCFGPT_GPTPAFLG_PAIF (0x01)
#define MCFGPT_GPTPORT_PORTT3 (0x08)
#define MCFGPT_GPTPORT_PORTT2 (0x04)
#define MCFGPT_GPTPORT_PORTT1 (0x02)
#define MCFGPT_GPTPORT_PORTT0 (0x01)
#define MCFGPT_GPTDDR_DDRT3 (0x08)
#define MCFGPT_GPTDDR_DDRT2 (0x04)
#define MCFGPT_GPTDDR_DDRT1 (0x02)
#define MCFGPT_GPTDDR_DDRT0 (0x01)
/* Coldfire Flash Module CFM */
#define MCFCFM_MCR (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000))
#define MCFCFM_MCR_LOCK (0x0400)
#define MCFCFM_MCR_PVIE (0x0200)
#define MCFCFM_MCR_AEIE (0x0100)
#define MCFCFM_MCR_CBEIE (0x0080)
#define MCFCFM_MCR_CCIE (0x0040)
#define MCFCFM_MCR_KEYACC (0x0020)
#define MCFCFM_CLKD (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002))
#define MCFCFM_SEC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008))
#define MCFCFM_SEC_KEYEN (0x80000000)
#define MCFCFM_SEC_SECSTAT (0x40000000)
#define MCFCFM_PROT (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010))
#define MCFCFM_SACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014))
#define MCFCFM_DACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018))
#define MCFCFM_USTAT (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020))
#define MCFCFM_USTAT_CBEIF 0x80
#define MCFCFM_USTAT_CCIF 0x40
#define MCFCFM_USTAT_PVIOL 0x20
#define MCFCFM_USTAT_ACCERR 0x10
#define MCFCFM_USTAT_BLANK 0x04
#define MCFCFM_CMD (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024))
#define MCFCFM_CMD_ERSVER 0x05
#define MCFCFM_CMD_PGERSVER 0x06
#define MCFCFM_CMD_PGM 0x20
#define MCFCFM_CMD_PGERS 0x40
#define MCFCFM_CMD_MASERS 0x41
/****************************************************************************/
#endif /* m5282_h */

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u-boot/arch/m68k/include/asm/m5301x.h Normal file
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/*
* m5301x.h -- Definitions for Freescale Coldfire 5301x
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef m5301x_h
#define m5301x_h
/* *** System Control Module (SCM) *** */
#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28)
#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24)
#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20)
#define SCM_MPR_MPROT4(x) (((x) & 0x0F) << 12)
#define SCM_MPR_MPROT5(x) (((x) & 0x0F) << 8)
#define SCM_MPR_MPROT6(x) (((x) & 0x0F) << 4)
#define MPROT_MTR 4
#define MPROT_MTW 2
#define MPROT_MPL 1
#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28)
#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24)
#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20)
#define SCM_PACRA_PACR5(x) (((x) & 0x0F) << 8)
#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12)
#define SCM_PACRB_PACR13(x) (((x) & 0x0F) << 8)
#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28)
#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24)
#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20)
#define SCM_PACRC_PACR19(x) (((x) & 0x0F) << 16)
#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8)
#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4)
#define SCM_PACRC_PACR23(x) ((x) & 0x0F)
#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28)
#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24)
#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20)
#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12)
#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8)
#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4)
#define SCM_PACRD_PACR31(x) ((x) & 0x0F)
#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28)
#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24)
#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20)
#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16)
#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12)
#define SCM_PACRE_PACR37(x) (((x) & 0x0F) << 8)
#define SCM_PACRE_PACR39(x) ((x) & 0x0F)
#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28)
#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24)
#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20)
#define SCM_PACRF_PACR43(x) (((x) & 0x0F) << 16)
#define SCM_PACRF_PACR44(x) (((x) & 0x0F) << 12)
#define SCM_PACRF_PACR45(x) (((x) & 0x0F) << 8)
#define SCM_PACRF_PACR46(x) (((x) & 0x0F) << 4)
#define SCM_PACRF_PACR47(x) ((x) & 0x0F)
#define SCM_PACRG_PACR48(x) (((x) & 0x0F) << 28)
#define SCM_PACRG_PACR49(x) (((x) & 0x0F) << 24)
#define SCM_PACRG_PACR50(x) (((x) & 0x0F) << 20)
#define SCM_PACRG_PACR51(x) (((x) & 0x0F) << 16)
#define PACR_SP 4
#define PACR_WP 2
#define PACR_TP 1
#define SCM_CWCR_RO (0x8000)
#define SCM_CWCR_CWR_WH (0x0100)
#define SCM_CWCR_CWE (0x0080)
#define SCM_CWCR_CWRI_WINDOW (0x0060)
#define SCM_CWCR_CWRI_RESET (0x0040)
#define SCM_CWCR_CWRI_INT_RESET (0x0020)
#define SCM_CWCR_CWRI_INT (0x0000)
#define SCM_CWCR_CWT(x) (((x) & 0x001F))
#define SCM_ISR_CFEI (0x02)
#define SCM_ISR_CWIC (0x01)
#define BCR_GBR (0x00000200)
#define BCR_GBW (0x00000100)
#define BCR_S7 (0x00000080)
#define BCR_S6 (0x00000040)
#define BCR_S4 (0x00000010)
#define BCR_S1 (0x00000002)
#define SCM_CFIER_ECFEI (0x01)
#define SCM_CFLOC_LOC (0x80)
#define SCM_CFATR_WRITE (0x80)
#define SCM_CFATR_SZ32 (0x20)
#define SCM_CFATR_SZ16 (0x10)
#define SCM_CFATR_SZ08 (0x00)
#define SCM_CFATR_CACHE (0x08)
#define SCM_CFATR_MODE (0x02)
#define SCM_CFATR_TYPE (0x01)
/* *** Interrupt Controller (INTC) *** */
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_EDMA_00 (8)
#define INT0_LO_EDMA_01 (9)
#define INT0_LO_EDMA_02 (10)
#define INT0_LO_EDMA_03 (11)
#define INT0_LO_EDMA_04 (12)
#define INT0_LO_EDMA_05 (13)
#define INT0_LO_EDMA_06 (14)
#define INT0_LO_EDMA_07 (15)
#define INT0_LO_EDMA_08 (16)
#define INT0_LO_EDMA_09 (17)
#define INT0_LO_EDMA_10 (18)
#define INT0_LO_EDMA_11 (19)
#define INT0_LO_EDMA_12 (20)
#define INT0_LO_EDMA_13 (21)
#define INT0_LO_EDMA_14 (22)
#define INT0_LO_EDMA_15 (23)
#define INT0_LO_EDMA_ERR (24)
#define INT0_LO_SCM_CWIC (25)
#define INT0_LO_UART0 (26)
#define INT0_LO_UART1 (27)
#define INT0_LO_UART2 (28)
#define INT0_LO_RSVD1 (29)
#define INT0_LO_I2C (30)
#define INT0_LO_DSPI (31)
#define INT0_HI_DTMR0 (32)
#define INT0_HI_DTMR1 (33)
#define INT0_HI_DTMR2 (34)
#define INT0_HI_DTMR3 (35)
#define INT0_HI_FEC0_TXF (36)
#define INT0_HI_FEC0_TXB (37)
#define INT0_HI_FEC0_UN (38)
#define INT0_HI_FEC0_RL (39)
#define INT0_HI_FEC0_RXF (40)
#define INT0_HI_FEC0_RXB (41)
#define INT0_HI_FEC0_MII (42)
#define INT0_HI_FEC0_LC (43)
#define INT0_HI_FEC0_HBERR (44)
#define INT0_HI_FEC0_GRA (45)
#define INT0_HI_FEC0_EBERR (46)
#define INT0_HI_FEC0_BABT (47)
#define INT0_HI_FEC0_BABR (48)
#define INT0_HI_FEC1_TXF (49)
#define INT0_HI_FEC1_TXB (50)
#define INT0_HI_FEC1_UN (51)
#define INT0_HI_FEC1_RL (52)
#define INT0_HI_FEC1_RXF (53)
#define INT0_HI_FEC1_RXB (54)
#define INT0_HI_FEC1_MII (55)
#define INT0_HI_FEC1_LC (56)
#define INT0_HI_FEC1_HBERR (57)
#define INT0_HI_FEC1_GRA (58)
#define INT0_HI_FEC1_EBERR (59)
#define INT0_HI_FEC1_BABT (60)
#define INT0_HI_FEC1_BABR (61)
#define INT0_HI_SCM_CFEI (62)
/* 0 - 24 reserved */
#define INT1_LO_EPORT1_FLAG0 (25)
#define INT1_LO_EPORT1_FLAG1 (26)
#define INT1_LO_EPORT1_FLAG2 (27)
#define INT1_LO_EPORT1_FLAG3 (28)
#define INT1_LO_EPORT1_FLAG4 (29)
#define INT1_LO_EPORT1_FLAG5 (30)
#define INT1_LO_EPORT1_FLAG6 (31)
#define INT1_LO_EPORT1_FLAG7 (32)
#define INT1_HI_DSPI_EOQF (33)
#define INT1_HI_DSPI_TFFF (34)
#define INT1_HI_DSPI_TCF (35)
#define INT1_HI_DSPI_TFUF (36)
#define INT1_HI_DSPI_RFDF (37)
#define INT1_HI_DSPI_RFOF (38)
#define INT1_HI_DSPI_RFOF_TFUF (39)
#define INT1_HI_RNG_EI (40)
#define INT1_HI_PLL_LOCF (41)
#define INT1_HI_PLL_LOLF (42)
#define INT1_HI_PIT0 (43)
#define INT1_HI_PIT1 (44)
#define INT1_HI_PIT2 (45)
#define INT1_HI_PIT3 (46)
#define INT1_HI_USBOTG_STS (47)
#define INT1_HI_USBHOST_STS (48)
#define INT1_HI_SSI (49)
/* 50 - 51 reserved */
#define INT1_HI_RTC (52)
#define INT1_HI_CCM_USBSTAT (53)
#define INT1_HI_CODEC_OR (54)
#define INT1_HI_CODEC_RF_TE (55)
#define INT1_HI_CODEC_ROE (56)
#define INT1_HI_CODEC_TUE (57)
/* 58 reserved */
#define INT1_HI_SIM1_DATA (59)
#define INT1_HI_SIM1_GENERAL (60)
/* 61 - 62 reserved */
#define INT1_HI_SDHC (63)
/* *** Reset Controller Module (RCM) *** */
#define RCM_RCR_SOFTRST (0x80)
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RSR_SOFT (0x20)
#define RCM_RSR_LOC (0x10)
#define RCM_RSR_POR (0x08)
#define RCM_RSR_EXT (0x04)
#define RCM_RSR_WDR_CORE (0x02)
#define RCM_RSR_LOL (0x01)
/* *** Chip Configuration Module (CCM) *** */
#define CCM_CCR_CSC (0x0020)
#define CCM_CCR_BOOTPS (0x0010)
#define CCM_CCR_LOAD (0x0008)
#define CCM_CCR_OSC_MODE (0x0004)
#define CCM_CCR_SDR_MODE (0x0002)
#define CCM_CCR_RESERVED (0x0001)
#define CCM_RCON_SDR_32BIT_UNIFIED (0x0012)
#define CCM_RCON_DDR_8BIT_SPLIT (0x0010)
#define CCM_RCON_SDR_16BIT_UNIFIED (0x0002)
#define CCM_RCON_DDR_16BIT_SPLIT (0x0000)
#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
#define CCM_CIR_PRN(x) ((x) & 0x003F)
#define CCM_MISCCR_FECM (0x8000)
#define CCM_MISCCR_CDCSRC (0x4000)
#define CCM_MISCCR_PLL_LOCK (0x2000)
#define CCM_MISCCR_LIMP (0x1000)
#define CCM_MISCCR_BME (0x8000)
#define CCM_MISCCR_BMT_UNMASK (0xF8FF)
#define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8)
#define CCM_MISCCR_BMT_512 (0x0700)
#define CCM_MISCCR_BMT_1024 (0x0600)
#define CCM_MISCCR_BMT_2048 (0x0500)
#define CCM_MISCCR_BMT_4096 (0x0400)
#define CCM_MISCCR_BMT_8192 (0x0300)
#define CCM_MISCCR_BMT_16384 (0x0200)
#define CCM_MISCCR_BMT_32768 (0x0100)
#define CCM_MISCCR_BMT_65536 (0x0000)
#define CCM_MISCCR_TIM_DMA (0x0020)
#define CCM_MISCCR_SSI_SRC (0x0010)
#define CCM_MISCCR_USBH_OC (0x0008)
#define CCM_MISCCR_USBO_OC (0x0004)
#define CCM_MISCCR_USB_PUE (0x0002)
#define CCM_MISCCR_USB_SRC (0x0001)
#define CCM_CDR_LPDIV(x) (((x) & 0x0F) << 8)
#define CCM_CDR_SSIDIV(x) ((x) & 0xFF)
#define CCM_UOCSR_DPPD (0x2000)
#define CCM_UOCSR_DMPD (0x1000)
#define CCM_UOCSR_DRV_VBUS (0x0800)
#define CCM_UOCSR_CRG_VBUS (0x0400)
#define CCM_UOCSR_DCR_VBUS (0x0200)
#define CCM_UOCSR_DPPU (0x0100)
#define CCM_UOCSR_AVLD (0x0080)
#define CCM_UOCSR_BVLD (0x0040)
#define CCM_UOCSR_VVLD (0x0020)
#define CCM_UOCSR_SEND (0x0010)
#define CCM_UOCSR_PWRFLT (0x0008)
#define CCM_UOCSR_WKUP (0x0004)
#define CCM_UOCSR_UOMIE (0x0002)
#define CCM_UOCSR_XPDE (0x0001)
#define CCM_UHCSR_PORTIND(x) (((x) & 0x0003) << 14)
#define CCM_UHCSR_DRV_VBUS (0x0010)
#define CCM_UHCSR_PWRFLT (0x0008)
#define CCM_UHCSR_WKUP (0x0004)
#define CCM_UHCSR_UHMIE (0x0002)
#define CCM_UHCSR_XPDE (0x0001)
#define CCM_CODCR_BGREN (0x8000)
#define CCM_CODCR_REGEN (0x0080)
#define CCM_MISC2_IGNLL (0x0008)
#define CCM_MISC2_DPS (0x0001)
/* *** General Purpose I/O (GPIO) *** */
#define GPIO_PDR_FBCTL ((x) & 0x0F)
#define GPIO_PDR_BE ((x) & 0x0F)
#define GPIO_PDR_CS32 (((x) & 0x03) << 4)
#define GPIO_PDR_CS10 (((x) & 0x03) << 4)
#define GPIO_PDR_DSPI ((x) & 0x7F)
#define GPIO_PDR_FEC0 ((x) & 0x7F)
#define GPIO_PDR_FECI2C ((x) & 0x3F)
#define GPIO_PDR_SIMP1 ((x) & 0x1F)
#define GPIO_PDR_SIMP0 ((x) & 0x1F)
#define GPIO_PDR_TIMER ((x) & 0x0F)
#define GPIO_PDR_UART ((x) & 0x3F)
#define GPIO_PDR_DEBUG (0x01)
#define GPIO_PDR_SDHC ((x) & 0x3F)
#define GPIO_PDR_SSI ((x) & 0x1F)
#define GPIO_PAR_FBCTL_OE (0x80)
#define GPIO_PAR_FBCTL_TA (0x40)
#define GPIO_PAR_FBCTL_RWB (0x20)
#define GPIO_PAR_FBCTL_TS (0x18)
#define GPIO_PAR_BE3 (0x40)
#define GPIO_PAR_BE2 (0x10)
#define GPIO_PAR_BE1 (0x04)
#define GPIO_PAR_BE0 (0x01)
#define GPIO_PAR_CS5 (0x40)
#define GPIO_PAR_CS4 (0x10)
#define GPIO_PAR_CS1_UNMASK (0xF3)
#define GPIO_PAR_CS1_CS1 (0x0C)
#define GPIO_PAR_CS1_SDCS1 (0x08)
#define GPIO_PAR_CS0_UNMASK (0xFC)
#define GPIO_PAR_CS0_CS0 (0x03)
#define GPIO_PAR_CS0_CS4 (0x02)
#define GPIO_PAR_DSPIH_SIN_UNMASK (0x3F)
#define GPIO_PAR_DSPIH_SIN (0xC0)
#define GPIO_PAR_DSPIH_SIN_U2RXD (0x80)
#define GPIO_PAR_DSPIH_SOUT_UNMASK (0xCF)
#define GPIO_PAR_DSPIH_SOUT (0x30)
#define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20)
#define GPIO_PAR_DSPIH_SCK_UNMASK (0xF3)
#define GPIO_PAR_DSPIH_SCK (0x0C)
#define GPIO_PAR_DSPIH_SCK_U2CTS (0x08)
#define GPIO_PAR_DSPIH_PCS0_UNMASK (0xFC)
#define GPIO_PAR_DSPIH_PCS0 (0x03)
#define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02)
#define GPIO_PAR_DSPIL_PCS1_UNMASK (0x3F)
#define GPIO_PAR_DSPIL_PCS1 (0xC0)
#define GPIO_PAR_DSPIL_PCS2_UNMASK (0xCF)
#define GPIO_PAR_DSPIL_PCS2 (0x30)
#define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20)
#define GPIO_PAR_DSPIL_PCS3_UNMASK (0xF3)
#define GPIO_PAR_DSPIL_PCS3 (0x0C)
#define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08)
#define GPIO_PAR_FEC1_7W_FEC (0x40)
#define GPIO_PAR_FEC1_RMII_FEC (0x10)
#define GPIO_PAR_FEC0_7W_FEC (0x04)
#define GPIO_PAR_FEC0_RMII_FEC (0x01)
/* GPIO_PAR_FECI2C */
#define GPIO_PAR_FECI2C_RMII0_UNMASK (0x3F)
#define GPIO_PAR_FECI2C_MDC0 (0x80)
#define GPIO_PAR_FECI2C_MDIO0 (0x40)
#define GPIO_PAR_FECI2C_RMII1_UNMASK (0xCF)
#define GPIO_PAR_FECI2C_MDC1 (0x20)
#define GPIO_PAR_FECI2C_MDIO1 (0x10)
#define GPIO_PAR_FECI2C_SDA_UNMASK (0xF3)
#define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2)
#define GPIO_PAR_FECI2C_SDA_SDA (0x0C)
#define GPIO_PAR_FECI2C_SDA_U2TXD (0x08)
#define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04)
#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFC)
#define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03)
#define GPIO_PAR_FECI2C_SCL_SCL (0x03)
#define GPIO_PAR_FECI2C_SCL_U2RXD (0x02)
#define GPIO_PAR_FECI2C_SCL_MDC1 (0x01)
#define GPIO_PAR_IRQ0H_IRQ07_UNMASK (0x3F)
#define GPIO_PAR_IRQ0H_IRQ06_UNMASK (0xCF)
#define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10)
#define GPIO_PAR_IRQ0H_IRQ04_UNMASK (0xFC)
#define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02)
#define GPIO_PAR_IRQ0L_IRQ01_UNMASK (0xF3)
#define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08)
#define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40)
#define GPIO_PAR_IRQ1H_IRQ16_DDATA2 (0x10)
#define GPIO_PAR_IRQ1H_IRQ15_DDATA1 (0x04)
#define GPIO_PAR_IRQ1H_IRQ14_DDATA0 (0x01)
#define GPIO_PAR_IRQ1L_IRQ13_PST3 (0x40)
#define GPIO_PAR_IRQ1L_IRQ12_PST2 (0x10)
#define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04)
#define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01)
#define GPIO_PAR_SIMP1H_DATA1_UNMASK (0x3F)
#define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0)
#define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80)
#define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40)
#define GPIO_PAR_SIMP1H_VEN1_UNMASK (0xCF)
#define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30)
#define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20)
#define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10)
#define GPIO_PAR_SIMP1H_RST1_UNMASK (0xF3)
#define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C)
#define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08)
#define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04)
#define GPIO_PAR_SIMP1H_PD1_UNMASK (0xFC)
#define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03)
#define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02)
#define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01)
#define GPIO_PAR_SIMP1L_CLK_UNMASK (0x3F)
#define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0)
#define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80)
#define GPIO_PAR_SIMP0_DATA0 (0x10)
#define GPIO_PAR_SIMP0_VEN0 (0x08)
#define GPIO_PAR_SIMP0_RST0 (0x04)
#define GPIO_PAR_SIMP0_PD0 (0x02)
#define GPIO_PAR_SIMP0_CLK0 (0x01)
#define GPIO_PAR_TIN3(x) (((x) & 0x03) << 6)
#define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4)
#define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2)
#define GPIO_PAR_TIN0(x) ((x) & 0x03)
#define GPIO_PAR_TIN3_UNMASK (0x3F)
#define GPIO_PAR_TIN3_TIN3 (0xC0)
#define GPIO_PAR_TIN3_TOUT3 (0x80)
#define GPIO_PAR_TIN3_IRQ03 (0x40)
#define GPIO_PAR_TIN2_UNMASK (0xCF)
#define GPIO_PAR_TIN2_TIN2 (0x30)
#define GPIO_PAR_TIN2_TOUT2 (0x20)
#define GPIO_PAR_TIN2_IRQ02 (0x10)
#define GPIO_PAR_TIN1_UNMASK (0xF3)
#define GPIO_PAR_TIN1_TIN1 (0x0C)
#define GPIO_PAR_TIN1_TOUT1 (0x08)
#define GPIO_PAR_TIN1_DACK1 (0x04)
#define GPIO_PAR_TIN0_UNMASK (0xFC)
#define GPIO_PAR_TIN0_TIN0 (0x03)
#define GPIO_PAR_TIN0_TOUT0 (0x02)
#define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01)
#define GPIO_PAR_UART_U2TXD (0x80)
#define GPIO_PAR_UART_U2RXD (0x40)
#define GPIO_PAR_UART_U0TXD (0x20)
#define GPIO_PAR_UART_U0RXD (0x10)
#define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2)
#define GPIO_PAR_UART_CTS0(x) ((x) & 0x03)
#define GPIO_PAR_UART_RTS0_UNMASK (0xF3)
#define GPIO_PAR_UART_RTS0_U0RTS (0x0C)
#define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08)
#define GPIO_PAR_UART_CTS0_UNMASK (0xFC)
#define GPIO_PAR_UART_CTS0_U0CTS (0x03)
#define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02)
#define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01)
#define GPIO_PAR_DEBUG_ALLPST (0x80)
#define GPIO_PAR_SDHC_DATA3 (0x20)
#define GPIO_PAR_SDHC_DATA2 (0x10)
#define GPIO_PAR_SDHC_DATA1 (0x08)
#define GPIO_PAR_SDHC_DATA0 (0x04)
#define GPIO_PAR_SDHC_CMD (0x02)
#define GPIO_PAR_SDHC_CLK (0x01)
#define GPIO_PAR_SSIH_RXD(x) (((x) & 0x03) << 6)
#define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4)
#define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2)
#define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03)
#define GPIO_PAR_SSIH_RXD_UNMASK (0x3F)
#define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0)
#define GPIO_PAR_SSIH_RXD_U1RXD (0x40)
#define GPIO_PAR_SSIH_TXD_UNMASK (0xCF)
#define GPIO_PAR_SSIH_TXD_SSIRXD (0x30)
#define GPIO_PAR_SSIH_TXD_U1TXD (0x10)
#define GPIO_PAR_SSIH_FS_UNMASK (0xF3)
#define GPIO_PAR_SSIH_FS_SSIFS (0x0C)
#define GPIO_PAR_SSIH_FS_U1RTS (0x04)
#define GPIO_PAR_SSIH_MCLK_UNMASK (0xFC)
#define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03)
#define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01)
#define GPIO_PAR_SSIL_UNMASK (0x3F)
#define GPIO_PAR_SSIL_BCLK (0xC0)
#define GPIO_PAR_SSIL_U1CTS (0x40)
#define GPIO_MSCR_MSCR1(x) (((x) & 0x07) << 5)
#define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5)
#define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5)
#define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5)
#define GPIO_MSCR_MSCRn_UNMASK (0x1F)
#define GPIO_MSCR_MSCRn_SDR (0xE0)
#define GPIO_MSCR_MSCRn_25VDDR (0x60)
#define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20)
#define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00)
#define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2)
#define GPIO_MSCR_MSCR5_UNMASK (0xE3)
#define GPIO_MSCR_MSCR5_SDR (0x1C)
#define GPIO_MSCR_MSCR5_25VDDR (0x0C)
#define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04)
#define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00)
#define GPIO_SRCR_DSPI_UNMASK (0xFC)
#define GPIO_SRCR_DSPI(x) ((x) & 0x03)
#define GPIO_SRCR_I2C_UNMASK (0xFC)
#define GPIO_SRCR_I2C(x) ((x) & 0x03)
#define GPIO_SRCR_IRQ_IRQ0_UNMASK (0xF3)
#define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2)
#define GPIO_SRCR_IRQ_IRQ1DBG_UNMASK (0xFC)
#define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03)
#define GPIO_SRCR_SIM_SIMP0_UNMASK (0xF3)
#define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2)
#define GPIO_SRCR_SIM_SIMP1_UNMASK (0xFC)
#define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03)
#define GPIO_SRCR_TIMER_UNMASK (0xFC)
#define GPIO_SRCR_TIMER(x) ((x) & 0x03)
#define GPIO_SRCR_UART2_UNMASK (0xF3)
#define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2)
#define GPIO_SRCR_UART0_UNMASK (0xFC)
#define GPIO_SRCR_UART0(x) ((x) & 0x03)
#define GPIO_SRCR_SDHC_UNMASK (0xFC)
#define GPIO_SRCR_SDHC(x) ((x) & 0x03)
#define GPIO_SRCR_SSI_UNMASK (0xFC)
#define GPIO_SRCR_SSI(x) ((x) & 0x03)
#define SRCR_HIGHEST (0x03)
#define SRCR_HIGH (0x02)
#define SRCR_LOW (0x01)
#define SRCR_LOWEST (0x00)
#define GPIO_DSCR_FEC_RMIICLK_UNMASK (0xCF)
#define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4)
#define GPIO_DSCR_FEC_RMII0_UNMASK (0xF3)
#define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2)
#define GPIO_DSCR_FEC_RMII1_UNMASK (0xFC)
#define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03)
#define DSCR_50PF (0x03)
#define DSCR_30PF (0x02)
#define DSCR_20PF (0x01)
#define DSCR_10PF (0x00)
#define GPIO_PCRH_DSPI_PCS0_PULLUP_EN (0x80)
#define GPIO_PCRH_SIM_VEN1_PULLUP_EN (0x40)
#define GPIO_PCRH_SIM_VEN1_PULLUP (0x20)
#define GPIO_PCRH_SIM_DATA1_PULLUP_EN (0x10)
#define GPIO_PCRH_SIM_DATA1_PULLUP (0x08)
#define GPIO_PCRH_SSI_PULLUP_EN (0x02)
#define GPIO_PCRH_SSI_PULLUP (0x01)
#define GPIO_PCRL_SDHC_DATA3_PULLUP_EN (0x80)
#define GPIO_PCRL_SDHC_DATA3_PULLUP (0x40)
#define GPIO_PCRL_SDHC_DATA2_PULLUP_EN (0x20)
#define GPIO_PCRL_SDHC_DATA1_PULLUP_EN (0x10)
#define GPIO_PCRL_SDHC_DATA0_PULLUP_EN (0x08)
#define GPIO_PCRL_SDHC_CMD_PULLUP_EN (0x04)
/* *** Phase Locked Loop (PLL) *** */
#define PLL_PCR_LOC_IRQ (0x00040000)
#define PLL_PCR_LOC_RE (0x00020000)
#define PLL_PCR_LOC_EN (0x00010000)
#define PLL_PCR_LOL_IRQ (0x00004000)
#define PLL_PCR_LOL_RE (0x00002000)
#define PLL_PCR_LOL_EN (0x00001000)
#define PLL_PCR_REFDIV_UNMASK (0xFFFFF8FF)
#define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8)
#define PLL_PCR_FBDIV_UNMASK (0xFFFFFFC0)
#define PLL_PCR_FBDIV(x) ((x) & 0x3F)
#define PLL_PDR_OUTDIV4_UNMASK (0x0FFF)
#define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12)
#define PLL_PDR_OUTDIV3_UNMASK (0xF0FF)
#define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8)
#define PLL_PDR_OUTDIV2_UNMASK (0xFF0F)
#define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4)
#define PLL_PDR_OUTDIV1_UNMASK (0xFFF0)
#define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F)
#define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x)
#define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x)
#define PLL_PDR_FB(x) PLL_PDR_OUTDIV2(x)
#define PLL_PDR_CPU(x) PLL_PDR_OUTDIV1(x)
#define PLL_PSR_LOCF (0x00000200)
#define PLL_PSR_LOC (0x00000100)
#define PLL_PSR_LOLF (0x00000040)
#define PLL_PSR_LOCKS (0x00000020)
#define PLL_PSR_LOCK (0x00000010)
#define PLL_PSR_MODE(x) ((x) & 0x07)
/* *** Real Time Clock *** */
#define RTC_OCEN_OSCBYP (0x00000010)
#define RTC_OCEN_CLKEN (0x00000008)
/* SDRAM */
#define SDRAMC_SDCR_CKE (0x40000000)
#define SDRAMC_SDCR_REF (0x10000000)
#endif /* m5301x_h */

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/*
* (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
#ifndef mcf5307_h
#define mcf5307_h
/*
* Size of internal RAM (RAMBAR)
*/
#define INT_RAM_SIZE 4096
/* Bit definitions and macros for SYPCR */
#define SYPCR_SWTAVAL 0x02
#define SYPCR_SWTA 0x04
#define SYPCR_SWT(x) ((x&0x3)<<3)
#define SYPCR_SWP 0x20
#define SYPCR_SWRI 0x40
#define SYPCR_SWE 0x80
/* Bit definitions and macros for CSMR */
#define CSMR_V 0x01
#define CSMR_UD 0x02
#define CSMR_UC 0x04
#define CSMR_SD 0x08
#define CSMR_SC 0x10
#define CSMR_CI 0x20
#define CSMR_AM 0x40
#define CSMR_WP 0x100
/* Bit definitions and macros for DACR (SDRAM) */
#define DACR_PM_CONTINUOUS 0x04
#define DACR_IP_PRECHG_ALL 0x08
#define DACR_PORT_SZ_32 0
#define DACR_PORT_SZ_8 (1<<4)
#define DACR_PORT_SZ_16 (2<<4)
#define DACR_IMRS_INIT_CMD (1<<6)
#define DACR_CMD_PIN(x) ((x&7)<<8)
#define DACR_CASL(x) ((x&3)<<12)
#define DACR_RE (1<<15)
/* Bit definitions and macros for CSCR */
#define CSCR_BSTW 0x08
#define CSCR_BSTR 0x10
#define CSCR_BEM 0x20
#define CSCR_PS(x) ((x&0x3)<<6)
#define CSCR_AA 0x100
#define CSCR_WS ((x&0xf)<<10)
/* Bit definitions for the ICR family of registers */
#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
#endif /* mcf5307_h */

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/*
* MCF5441X Internal Memory Map
*
* Copyright 2010-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MCF5441X__
#define __MCF5441X__
/* Interrupt Controller (INTC) */
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_EDMA_00 (8)
#define INT0_LO_EDMA_01 (9)
#define INT0_LO_EDMA_02 (10)
#define INT0_LO_EDMA_03 (11)
#define INT0_LO_EDMA_04 (12)
#define INT0_LO_EDMA_05 (13)
#define INT0_LO_EDMA_06 (14)
#define INT0_LO_EDMA_07 (15)
#define INT0_LO_EDMA_08 (16)
#define INT0_LO_EDMA_09 (17)
#define INT0_LO_EDMA_10 (18)
#define INT0_LO_EDMA_11 (19)
#define INT0_LO_EDMA_12 (20)
#define INT0_LO_EDMA_13 (21)
#define INT0_LO_EDMA_14 (22)
#define INT0_LO_EDMA_15 (23)
#define INT0_LO_EDMA_ERR (24)
#define INT0_LO_SCM (25)
#define INT0_LO_UART0 (26)
#define INT0_LO_UART1 (27)
#define INT0_LO_UART2 (28)
#define INT0_LO_UART3 (29)
#define INT0_LO_I2C0 (30)
#define INT0_LO_DSPI0 (31)
#define INT0_HI_DTMR0 (32)
#define INT0_HI_DTMR1 (33)
#define INT0_HI_DTMR2 (34)
#define INT0_HI_DTMR3 (35)
#define INT0_HI_MACNET0_TXF (36)
#define INT0_HI_MACNET0_TXB (37)
#define INT0_HI_MACNET0_UN (38)
#define INT0_HI_MACNET0_RL (39)
#define INT0_HI_MACNET0_RXF (40)
#define INT0_HI_MACNET0_RXB (41)
#define INT0_HI_MACNET0_MII (42)
#define INT0_HI_MACNET0_LC (43)
/* not used 44 */
#define INT0_HI_MACNET0_GRA (45)
#define INT0_HI_MACNET0_EBERR (46)
#define INT0_HI_MACNET0_BABT (47)
#define INT0_HI_MACNET0_BABR (48)
#define INT0_HI_MACNET1_TXF (49)
#define INT0_HI_MACNET1_TXB (50)
#define INT0_HI_MACNET1_UN (51)
#define INT0_HI_MACNET1_RL (52)
#define INT0_HI_MACNET1_RXF (53)
#define INT0_HI_MACNET1_RXB (54)
#define INT0_HI_MACNET1_MII (55)
#define INT0_HI_MACNET1_LC (56)
/* not used 57 */
#define INT0_HI_MACNET1_GRA (58)
#define INT0_HI_MACNET1_EBERR (59)
#define INT0_HI_MACNET1_BABT (60)
#define INT0_HI_MACNET1_BABR (61)
#define INT0_HI_SCMIR (62)
#define INT0_HI_OW (63)
#define INT1_LO_CAN0_IFG (0)
#define INT1_LO_CAN0_BOFF (1)
/* not used 2 */
#define INT1_LO_CAN0_TXRXWRN (3)
#define INT1_LO_CAN1_IFG (4)
#define INT1_LO_CAN1_BOFF (5)
/* not used 6 */
#define INT1_LO_CAN1_TXRXWRN (7)
#define INT1_LO_EDMA_16 (8)
#define INT1_LO_EDMA_17 (9)
#define INT1_LO_EDMA_18 (10)
#define INT1_LO_EDMA_19 (11)
#define INT1_LO_EDMA_20 (12)
#define INT1_LO_EDMA_21 (13)
#define INT1_LO_EDMA_22 (14)
#define INT1_LO_EDMA_23 (15)
#define INT1_LO_EDMA_24 (16)
#define INT1_LO_EDMA_25 (17)
#define INT1_LO_EDMA_26 (18)
#define INT1_LO_EDMA_27 (19)
#define INT1_LO_EDMA_28 (20)
#define INT1_LO_EDMA_29 (21)
#define INT1_LO_EDMA_30 (22)
#define INT1_LO_EDMA_31 (23)
#define INT1_LO_EDMA_32 (24)
#define INT1_LO_EDMA_33 (25)
#define INT1_LO_EDMA_34 (26)
#define INT1_LO_EDMA_35 (27)
#define INT1_LO_EDMA_36 (28)
#define INT1_LO_EDMA_37 (29)
#define INT1_LO_EDMA_38 (30)
#define INT1_LO_EDMA_39 (31)
#define INT1_LO_EDMA_40 (32)
#define INT1_HI_EDMA_41 (33)
#define INT1_HI_EDMA_42 (34)
#define INT1_HI_EDMA_43 (35)
#define INT1_HI_EDMA_44 (36)
#define INT1_HI_EDMA_45 (37)
#define INT1_HI_EDMA_46 (38)
#define INT1_HI_EDMA_47 (39)
#define INT1_HI_EDMA_48 (40)
#define INT1_HI_EDMA_49 (41)
#define INT1_HI_EDMA_50 (42)
#define INT1_HI_EDMA_51 (43)
#define INT1_HI_EDMA_52 (44)
#define INT1_HI_EDMA_53 (45)
#define INT1_HI_EDMA_54 (46)
#define INT1_HI_EDMA_55 (47)
#define INT1_HI_UART4 (48)
#define INT1_HI_UART5 (49)
#define INT1_HI_UART6 (50)
#define INT1_HI_UART7 (51)
#define INT1_HI_UART8 (52)
#define INT1_HI_UART9 (53)
#define INT1_HI_DSPI1 (54)
#define INT1_HI_DSPI2 (55)
#define INT1_HI_DSPI3 (56)
#define INT1_HI_I2C1 (57)
#define INT1_HI_I2C2 (58)
#define INT1_HI_I2C3 (59)
#define INT1_HI_I2C4 (60)
#define INT1_HI_I2C5 (61)
#define INT2_LO_EDMA56_63 (0)
#define INT2_LO_PWM_SM0SR_CF (1)
#define INT2_LO_PWM_SM1SR_CF (2)
#define INT2_LO_PWM_SM2SR_CF (3)
#define INT2_LO_PWM_SM3SR_CF (4)
#define INT2_LO_PWM_SM0SR_RF (5)
#define INT2_LO_PWM_SM1SR_RF (6)
#define INT2_LO_PWM_SM2SR_RF (7)
#define INT2_LO_PWM_SM3SR_RF (8)
#define INT2_LO_PWM_FSR (9)
#define INT2_LO_PWM_SMSR_REF (10)
#define INT2_LO_PLL_SR_LOCF (11)
#define INT2_LO_PLL_SR_LOLF (12)
#define INT2_LO_PIT0_PIF (13)
#define INT2_LO_PIT1_PIF (14)
#define INT2_LO_PIT2_PIF (15)
#define INT2_LO_PIT3_PIF (16)
#define INT2_LO_USBOTG_USBSTS (17)
#define INT2_LO_USBH_USBSTS (18)
/* not used 19-20 */
#define INT2_LO_SSI0 (21)
#define INT2_LO_SSI1 (22)
#define INT2_LO_NFC (23)
/* not used 24-25 */
#define INT2_LO_RTC (26)
#define INT2_LO_CCM_UOCSR (27)
#define INT2_LO_RNG_EI (28)
#define INT2_LO_SIM1_DATA (29)
#define INT2_LO_SIM1 (30)
#define INT2_LO_SDHC (31)
/* not used 32-37 */
#define INT2_HI_L2SW_BERR (38)
#define INT2_HI_L2SW_RXB (39)
#define INT2_HI_L2SW_RXF (40)
#define INT2_HI_L2SW_TXB (41)
#define INT2_HI_L2SW_TXF (42)
#define INT2_HI_L2SW_QM (43)
#define INT2_HI_L2SW_OD0 (44)
#define INT2_HI_L2SW_OD1 (45)
#define INT2_HI_L2SW_OD2 (46)
#define INT2_HI_L2SW_LRN (47)
#define INT2_HI_MACNET0_TS (48)
#define INT2_HI_MACNET0_WAKE (49)
#define INT2_HI_MACNET0_PLR (50)
/* not used 51-54 */
#define INT2_HI_MACNET1_TS (51)
#define INT2_HI_MACNET1_WAKE (52)
#define INT2_HI_MACNET1_PLR (53)
/* Serial Boot Facility (SBF) */
#define SBF_SBFCR_BLDIV(x) (((x)&0x000F))
#define SBF_SBFCR_FR (0x0010)
/* Reset Controller Module (RCM) */
#define RCM_RCR_SOFTRST (0x80)
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RSR_SOFT (0x20)
#define RCM_RSR_LOC (0x10)
#define RCM_RSR_POR (0x08)
#define RCM_RSR_EXT (0x04)
#define RCM_RSR_WDR_CORE (0x02)
#define RCM_RSR_LOL (0x01)
/* Chip Configuration Module (CCM) */
#define CCM_CCR_BOOTMOD (0xC000)
#define CCM_CCR_PLLMULT (0x0FC0)
#define CCM_CCR_BOOTPS (0x0030)
#define CCM_CCR_BOOTPS_32 (0x0000)
#define CCM_CCR_BOOTPS_16 (0x0020)
#define CCM_CCR_BOOTPS_8 (0x0010)
#define CCM_CCR_BOOTPS_ (0x0000)
#define CCM_CCR_ALESEL (0x0008)
#define CCM_CCR_OSCMOD (0x0004)
#define CCM_CCR_PLLMOD (0x0002)
#define CCM_CCR_BOOTMEM (0x0001)
#define CCM_CIR_PIN_MASK (0xFFC0)
#define CCM_CIR_PRN_MASK (0x003F)
#define CCM_CIR_PIN_MCF54410 (0x9F<<6)
#define CCM_CIR_PIN_MCF54415 (0xA0<<6)
#define CCM_CIR_PIN_MCF54416 (0xA1<<6)
#define CCM_CIR_PIN_MCF54417 (0xA2<<6)
#define CCM_CIR_PIN_MCF54418 (0xA3<<6)
#define CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14)
#define CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF)
#define CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000)
#define CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000)
#define CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000)
#define CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000)
#define CCM_MISCCR_LIMP (0x1000)
#define CCM_MISCCR_BME (0x0800)
#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8)
#define CCM_MISCCR_BMT_65536 (0)
#define CCM_MISCCR_BMT_32768 (1)
#define CCM_MISCCR_BMT_16384 (2)
#define CCM_MISCCR_BMT_8192 (3)
#define CCM_MISCCR_BMT_4096 (4)
#define CCM_MISCCR_BMT_2048 (5)
#define CCM_MISCCR_BMT_1024 (6)
#define CCM_MISCCR_BMT_512 (7)
#define CCM_MISCCR_SDHCSRC (0x0040)
#define CCM_MISCCR_SSI1SRC (0x0020)
#define CCM_MISCCR_SSI0SRC (0x0010)
#define CCM_MISCCR_USBHOC (0x0008)
#define CCM_MISCCR_USBOOC (0x0004)
#define CCM_MISCCR_USBPUE (0x0002)
#define CCM_MISCCR_USBSRC (0x0001)
#define CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8)
#define CCM_CDRH_SSI0DIV_MASK (0x00FF)
#define CCM_CDRH_SSI1DIV(x) (((x)&0x00FF))
#define CCM_CDRH_SSI1DIV_MASK (0xFF00)
#define CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8)
#define CCM_CDRL_LPDIV_MASK (0xFF0F)
#define CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x)
#define CCM_UOCSR_DPPD (0x2000)
#define CCM_UOCSR_DMPD (0x1000)
#define CCM_UOCSR_DRV_VBUS (0x0800)
#define CCM_UOCSR_CRG_VBUS (0x0400)
#define CCM_UOCSR_DCR_VBUS (0x0200)
#define CCM_UOCSR_DPPU (0x0100)
#define CCM_UOCSR_AVLD (0x0080)
#define CCM_UOCSR_BVLD (0x0040)
#define CCM_UOCSR_VVLD (0x0020)
#define CCM_UOCSR_SEND (0x0010)
#define CCM_UOCSR_PWRFLT (0x0008)
#define CCM_UOCSR_WKUP (0x0004)
#define CCM_UOCSR_UOMIE (0x0002)
#define CCM_UOCSR_XPDE (0x0001)
#define CCM_UHCSR_DRV_VBUS (0x0010)
#define CCM_UHCSR_PWRFLT (0x0008)
#define CCM_UHCSR_WKUP (0x0004)
#define CCM_UHCSR_UOMIE (0x0002)
#define CCM_UHCSR_XPDE (0x0001)
#define CCM_MISCCR3_TMR_ENET (0x1000)
#define CCM_MISCCR3_ENETCLK(x) (((x)&7)<<8)
#define CCM_MISCCR3_ENETCLK_MASK (0xF8FF)
#define CCM_MISCCR3_ENETCLK_MII (0x0700)
#define CCM_MISCCR3_ENETCLK_OSC (0x0600)
#define CCM_MISCCR3_ENETCLK_USB (0x0500)
#define CCM_MISCCR3_ENETCLK_TMR3 (0x0400)
#define CCM_MISCCR3_ENETCLK_TMR2 (0x0300)
#define CCM_MISCCR3_ENETCLK_TMR1 (0x0200)
#define CCM_MISCCR3_ENETCLK_TMR0 (0x0100)
#define CCM_MISCCR3_ENETCLK_INTBUS (0x0000)
#define CCM_MISCCR2_EXTCLKBYP (0x8000)
#define CCM_MISCCR2_DDR2CLK (0x4000)
#define CCM_MISCCR2_RGPIO_HALF (0x2000)
#define CCM_MISCCR2_SWTSCR (0x1000)
#define CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8)
#define CCM_MISCCR2_PLLMODE_MASK (0xF8FF)
#define CCM_MISCCR2_DCCBYP (0x0080)
#define CCM_MISCCR2_DAC1SEL (0x0040)
#define CCM_MISCCR2_DAC0SEL (0x0020)
#define CCM_MISCCR2_ADCEN (0x0010)
#define CCM_MISCCR2_ADC7SEL (0x0008)
#define CCM_MISCCR2_ADC3SEL (0x0004)
#define CCM_MISCCR2_FBHALF (0x0002)
#define CCM_MISCCR2_ULPI (0x0001)
#define CCM_FNACR_PCR(x) (((x)&0x0F)<<24)
#define CCM_FNACR_PCR_MASK (0xF0FFFFFF)
#define CCM_FNACR_MCC(x) ((x)&0xFFFF)
#define CCM_FNACR_MCC_MASK (0xFFFF0000)
/* General Purpose I/O Module (GPIO) */
#define GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6)
#define GPIO_PAR_FBCTL_ALE_MASK (0x3F)
#define GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0)
#define GPIO_PAR_FBCTL_ALE_FB_TS (0x80)
#define GPIO_PAR_FBCTL_ALE_GPIO (0x00)
#define GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4)
#define GPIO_PAR_FBCTL_OE_MASK (0xCF)
#define GPIO_PAR_FBCTL_OE_FB_OE (0x30)
#define GPIO_PAR_FBCTL_OE_FB_TBST (0x20)
#define GPIO_PAR_FBCTL_OE_NFC_RE (0x20)
#define GPIO_PAR_FBCTL_OE_GPIO (0x00)
#define GPIO_PAR_FBCTL_FBCLK (0x08)
#define GPIO_PAR_FBCTL_RW (0x04)
#define GPIO_PAR_FBCTL_TA(x) ((x)&3)
#define GPIO_PAR_FBCTL_TA_MASK (0xFC)
#define GPIO_PAR_FBCTL_TA_TA (0x03)
#define GPIO_PAR_FBCTL_TA_NFC_RB (0x01)
#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
#define GPIO_PAR_BE_BE3_MASK (0x3F)
#define GPIO_PAR_BE_BE3_BE3 (0xC0)
#define GPIO_PAR_BE_BE3_CS3 (0x80)
#define GPIO_PAR_BE_BE3_FB_A1 (0x40)
#define GPIO_PAR_BE_BE3_NFC_ALE (0x40)
#define GPIO_PAR_BE_BE3_GPIO (0x00)
#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
#define GPIO_PAR_BE_BE2_MASK (0xCF)
#define GPIO_PAR_BE_BE2_BE2 (0x30)
#define GPIO_PAR_BE_BE2_CS2 (0x20)
#define GPIO_PAR_BE_BE2_FB_A0 (0x10)
#define GPIO_PAR_BE_BE2_NFC_CLE (0x10)
#define GPIO_PAR_BE_BE2_GPIO (0x00)
#define GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2)
#define GPIO_PAR_BE_BE1_MASK (0xF3)
#define GPIO_PAR_BE_BE1_BE1 (0x0C)
#define GPIO_PAR_BE_BE1_FB_TSZ1 (0x08)
#define GPIO_PAR_BE_BE1_GPIO (0x00)
#define GPIO_PAR_BE_BS0(x) ((x)&0x03)
#define GPIO_PAR_BE_BE0_MASK (0xFC)
#define GPIO_PAR_BE_BE0_BE0 (0x03)
#define GPIO_PAR_BE_BE0_FB_TSZ0 (0x02)
#define GPIO_PAR_BE_BE0_GPIO (0x00)
#define GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6)
#define GPIO_PAR_CS_CS5_MASK (0x3F)
#define GPIO_PAR_CS_CS5_CS5 (0xC0)
#define GPIO_PAR_CS_CS5_DACK1 (0x80)
#define GPIO_PAR_CS_CS5_GPIO (0x00)
#define GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4)
#define GPIO_PAR_CS_CS4_MASK (0xCF)
#define GPIO_PAR_CS_CS4_CS4 (0x30)
#define GPIO_PAR_CS_CS4_DREQ1 (0x20)
#define GPIO_PAR_CS_CS4_GPIO (0x00)
#define GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2)
#define GPIO_PAR_CS_CS1_MASK (0xF3)
#define GPIO_PAR_CS_CS1_CS1 (0x0C)
#define GPIO_PAR_CS_CS1_NFC_CE (0x04)
#define GPIO_PAR_CS_CS1_GPIO (0x00)
#define GPIO_PAR_CS_CS0_CS0 (0x01)
#define GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6)
#define GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F)
#define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0)
#define GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80)
#define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40)
#define GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00)
#define GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4)
#define GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF)
#define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30)
#define GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20)
#define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10)
#define GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00)
#define GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2)
#define GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3)
#define GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C)
#define GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08)
#define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04)
#define GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00)
#define GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03)
#define GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC)
#define GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03)
#define GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02)
#define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01)
#define GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00)
#define GPIO_PAR_IRQH_IRQ7 (0x10)
#define GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2)
#define GPIO_PAR_IRQH_IRQ4_MASK (0xF3)
#define GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C)
#define GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08)
#define GPIO_PAR_IRQH_IRQ4_GPIO (0x00)
#define GPIO_PAR_IRQH_IRQ1 (0x03)
#define GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6)
#define GPIO_PAR_IRQL_IRQ6_MASK (0x3F)
#define GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0)
#define GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40)
#define GPIO_PAR_IRQL_IRQ6_GPIO (0x00)
#define GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4)
#define GPIO_PAR_IRQL_IRQ3_MASK (0xCF)
#define GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30)
#define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20)
#define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10)
#define GPIO_PAR_IRQL_IRQ3_GPIO (0x00)
#define GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2)
#define GPIO_PAR_IRQL_IRQ2_MASK (0xF3)
#define GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C)
#define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08)
#define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04)
#define GPIO_PAR_IRQL_IRQ2_GPIO (0x00)
#define GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6)
#define GPIO_PAR_DSPI0_SIN_MASK (0x3F)
#define GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0)
#define GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0)
#define GPIO_PAR_DSPI0_SIN_U3RXD (0x80)
#define GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40)
#define GPIO_PAR_DSPI0_SIN_GPIO (0x00)
#define GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4)
#define GPIO_PAR_DSPI0_SOUT_MASK (0xCF)
#define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30)
#define GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30)
#define GPIO_PAR_DSPI0_SOUT_U3TXD (0x20)
#define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10)
#define GPIO_PAR_DSPI0_SOUT_GPIO (0x00)
#define GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2)
#define GPIO_PAR_DSPI0_SCK_MASK (0xF3)
#define GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C)
#define GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C)
#define GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08)
#define GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04)
#define GPIO_PAR_DSPI0_SCK_GPIO (0x00)
#define GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03)
#define GPIO_PAR_DSPI0_PCS0_MASK (0xFC)
#define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03)
#define GPIO_PAR_DSPI0_PCS0_SS (0x03)
#define GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02)
#define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01)
#define GPIO_PAR_DSPI0_PCS0_GPIO (0x00)
#define GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80)
#define GPIO_PAR_DSPIOW_SBF_CS (0x80)
#define GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4)
#define GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF)
#define GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30)
#define GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20)
#define GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00)
#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
#define GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0)
#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
#define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40)
#define GPIO_PAR_TIMER_T3IN_ULIPI_DIR (0x40)
#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
#define GPIO_PAR_TIMER_T2IN_EXTA2 (0x30)
#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
#define GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10)
#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
#define GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C)
#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
#define GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04)
#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T0IN(x) ((x)&0x03)
#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
#define GPIO_PAR_TIMER_T0IN_EXTA0 (0x03)
#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
#define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01)
#define GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01)
#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
#define GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6)
#define GPIO_PAR_UART2_U2CTS_MASK (0x3F)
#define GPIO_PAR_UART2_U2CTS_U2CTS (0xC0)
#define GPIO_PAR_UART2_U2CTS_U6TXD (0x80)
#define GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40)
#define GPIO_PAR_UART2_U2CTS_GPIO (0x00)
#define GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4)
#define GPIO_PAR_UART2_U2RTS_MASK (0xCF)
#define GPIO_PAR_UART2_U2RTS_U2RTS (0x30)
#define GPIO_PAR_UART2_U2RTS_U6RXD (0x20)
#define GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10)
#define GPIO_PAR_UART2_U2RTS_GPIO (0x00)
#define GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2)
#define GPIO_PAR_UART2_U2RXD_MASK (0xF3)
#define GPIO_PAR_UART2_U2RXD_U2RXD (0x0C)
#define GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08)
#define GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04)
#define GPIO_PAR_UART2_U2RXD_GPIO (0x00)
#define GPIO_PAR_UART2_U2TXD(x) ((x)&0x03)
#define GPIO_PAR_UART2_U2TXD_MASK (0xFC)
#define GPIO_PAR_UART2_U2TXD_U2TXD (0x03)
#define GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02)
#define GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01)
#define GPIO_PAR_UART2_U2TXD_GPIO (0x00)
#define GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6)
#define GPIO_PAR_UART1_U1CTS_MASK (0x3F)
#define GPIO_PAR_UART1_U1CTS_U1CTS (0xC0)
#define GPIO_PAR_UART1_U1CTS_U5TXD (0x80)
#define GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40)
#define GPIO_PAR_UART1_U1CTS_GPIO (0x00)
#define GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4)
#define GPIO_PAR_UART1_U1RTS_MASK (0xCF)
#define GPIO_PAR_UART1_U1RTS_U1RTS (0x30)
#define GPIO_PAR_UART1_U1RTS_U5RXD (0x20)
#define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10)
#define GPIO_PAR_UART1_U1RTS_GPIO (0x00)
#define GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2)
#define GPIO_PAR_UART1_U1RXD_MASK (0xF3)
#define GPIO_PAR_UART1_U1RXD_U1RXD (0x0C)
#define GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08)
#define GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04)
#define GPIO_PAR_UART1_U1RXD_GPIO (0x00)
#define GPIO_PAR_UART1_U1TXD(x) ((x)&0x03)
#define GPIO_PAR_UART1_U1TXD_MASK (0xFC)
#define GPIO_PAR_UART1_U1TXD_U1TXD (0x03)
#define GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02)
#define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01)
#define GPIO_PAR_UART1_U1TXD_GPIO (0x00)
#define GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6)
#define GPIO_PAR_UART0_U0CTS_MASK (0x3F)
#define GPIO_PAR_UART0_U0CTS_U0CTS (0xC0)
#define GPIO_PAR_UART0_U0CTS_U4TXD (0x80)
#define GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40)
#define GPIO_PAR_UART0_U0CTS_GPIO (0x00)
#define GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4)
#define GPIO_PAR_UART0_U0RTS_MASK (0xCF)
#define GPIO_PAR_UART0_U0RTS_U0RTS (0x30)
#define GPIO_PAR_UART0_U0RTS_U4RXD (0x20)
#define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10)
#define GPIO_PAR_UART0_U0RTS_GPIO (0x00)
#define GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2)
#define GPIO_PAR_UART0_U0RXD_MASK (0xF3)
#define GPIO_PAR_UART0_U0RXD_U0RXD (0x0C)
#define GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08)
#define GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04)
#define GPIO_PAR_UART0_U0RXD_GPIO (0x00)
#define GPIO_PAR_UART0_U0TXD(x) ((x)&0x03)
#define GPIO_PAR_UART0_U0TXD_MASK (0xFC)
#define GPIO_PAR_UART0_U0TXD_U0TXD (0x03)
#define GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02)
#define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01)
#define GPIO_PAR_UART0_U0TXD_GPIO (0x00)
#define GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6)
#define GPIO_PAR_SDHCH_DAT3_MASK (0x3F)
#define GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0)
#define GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80)
#define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40)
#define GPIO_PAR_SDHCH_DAT3_GPIO (0x00)
#define GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4)
#define GPIO_PAR_SDHCH_DAT2_MASK (0xCF)
#define GPIO_PAR_SDHCH_DAT2_DAT2 (0x30)
#define GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20)
#define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10)
#define GPIO_PAR_SDHCH_DAT2_GPIO (0x00)
#define GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2)
#define GPIO_PAR_SDHCH_DAT1_MASK (0xF3)
#define GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C)
#define GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08)
#define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04)
#define GPIO_PAR_SDHCH_DAT1_GPIO (0x00)
#define GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03)
#define GPIO_PAR_SDHCH_DAT0_MASK (0xFC)
#define GPIO_PAR_SDHCH_DAT0_DAT0 (0x03)
#define GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02)
#define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01)
#define GPIO_PAR_SDHCH_DAT0_GPIO (0x00)
#define GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2)
#define GPIO_PAR_SDHCL_CMD_MASK (0xF3)
#define GPIO_PAR_SDHCL_CMD_CMD (0x0C)
#define GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08)
#define GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04)
#define GPIO_PAR_SDHCL_CMD_GPIO (0x00)
#define GPIO_PAR_SDHCL_CLK(x) ((x)&0x03)
#define GPIO_PAR_SDHCL_CLK_MASK (0xFC)
#define GPIO_PAR_SDHCL_CLK_CLK (0x03)
#define GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02)
#define GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01)
#define GPIO_PAR_SDHCL_CLK_GPIO (0x00)
#define GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6)
#define GPIO_PAR_SIMP0H_DAT_MASK (0x3F)
#define GPIO_PAR_SIMP0H_DAT_DAT (0xC0)
#define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80)
#define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40)
#define GPIO_PAR_SIMP0H_DAT_GPIO (0x00)
#define GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4)
#define GPIO_PAR_SIMP0H_VEN_MASK (0xCF)
#define GPIO_PAR_SIMP0H_VEN_VEN (0x30)
#define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20)
#define GPIO_PAR_SIMP0H_VEN_GPIO (0x00)
#define GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2)
#define GPIO_PAR_SIMP0H_RST_MASK (0xF3)
#define GPIO_PAR_SIMP0H_RST_RST (0x0C)
#define GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08)
#define GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04)
#define GPIO_PAR_SIMP0H_RST_GPIO (0x00)
#define GPIO_PAR_SIMP0H_PD(x) ((x)&0x03)
#define GPIO_PAR_SIMP0H_PD_MASK (0xFC)
#define GPIO_PAR_SIMP0H_PD_PD (0x03)
#define GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02)
#define GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01)
#define GPIO_PAR_SIMP0H_PD_GPIO (0x00)
#define GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03)
#define GPIO_PAR_SIMP0L_CLK_MASK (0xFC)
#define GPIO_PAR_SIMP0L_CLK_CLK (0x03)
#define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02)
#define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01)
#define GPIO_PAR_SIMP0L_CLK_GPIO (0x00)
#define GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6)
#define GPIO_PAR_SSI0H_RXD_MASK (0x3F)
#define GPIO_PAR_SSI0H_RXD_RXD (0xC0)
#define GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80)
#define GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40)
#define GPIO_PAR_SSI0H_RXD_GPIO (0x00)
#define GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4)
#define GPIO_PAR_SSI0H_TXD_MASK (0xCF)
#define GPIO_PAR_SSI0H_TXD_TXD (0x30)
#define GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20)
#define GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10)
#define GPIO_PAR_SSI0H_TXD_GPIO (0x00)
#define GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2)
#define GPIO_PAR_SSI0H_FS_MASK (0xF3)
#define GPIO_PAR_SSI0H_FS_FS (0x0C)
#define GPIO_PAR_SSI0H_FS_U7TXD (0x08)
#define GPIO_PAR_SSI0H_FS_SIM1_RST (0x04)
#define GPIO_PAR_SSI0H_FS_GPIO (0x00)
#define GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03)
#define GPIO_PAR_SSI0H_MCLK_MASK (0xFC)
#define GPIO_PAR_SSI0H_MCLK_MCLK (0x03)
#define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02)
#define GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01)
#define GPIO_PAR_SSI0H_MCLK_GPIO (0x00)
#define GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03)
#define GPIO_PAR_SSI0L_BCLK_MASK (0xFC)
#define GPIO_PAR_SSI0L_BCLK_BCLK (0x03)
#define GPIO_PAR_SSI0L_BCLK_U7RXD (0x02)
#define GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01)
#define GPIO_PAR_SSI0L_BCLK_GPIO (0x00)
#define GPIO_PAR_DEBUGH1_DAT3 (0x40)
#define GPIO_PAR_DEBUGH1_DAT2 (0x10)
#define GPIO_PAR_DEBUGH1_DAT1 (0x04)
#define GPIO_PAR_DEBUGH1_DAT0 (0x01)
#define GPIO_PAR_DEBUGH0_PST3 (0x40)
#define GPIO_PAR_DEBUGH0_PST2 (0x10)
#define GPIO_PAR_DEBUGH0_PST1 (0x04)
#define GPIO_PAR_DEBUGH0_PST0 (0x01)
#define GPIO_PODR_G4_VAL (0x01 << 4)
#define GPIO_PODR_G4_MASK (0xff & ~GPIO_PODR_G4_VAL)
#define GPIO_PDDR_G4_OUTPUT (0x01 << 4)
#define GPIO_PDDR_G4_MASK (0xff & ~GPIO_PDDR_G4_OUTPUT)
#define GPIO_PAR_DEBUGL_ALLPST (0x01)
#define GPIO_PAR_FEC_FEC(x) ((x)&0x0F)
#define GPIO_PAR_FEC_FEC_MASK (0xF0)
#define GPIO_PAR_FEC_FEC_GPIO (0x0D)
#define GPIO_PAR_FEC_FEC_RMII1 (0x0C)
#define GPIO_PAR_FEC_FEC_RMII1FUL (0x0B)
#define GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A)
#define GPIO_PAR_FEC_FEC_RMII0 (0x09)
#define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08)
#define GPIO_PAR_FEC_FEC_RMII0FUL (0x07)
#define GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06)
#define GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */
/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
#define GPIO_PAR_FEC_FEC_RMII0_1 (0x04)
#define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03)
#define GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */
#define GPIO_PAR_FEC_FEC_MIIFUL (0x00)
/* TC: Need to edit here.... */
/* Mode Select Control */
#define GPIO_MSCR_SDRAM_MSC(x) ((x)&0x03)
#define GPIO_MSCR_SDRAM_MSC_MASK (0xFC)
/* Slew Rate Control */
#define GPIO_SRCR_FB3_FB3(x) ((x)&0x03)
#define GPIO_SRCR_FB3_FB3_MASK (0xFC)
#define GPIO_SRCR_FB2_FB2(x) ((x)&0x03)
#define GPIO_SRCR_FB2_FB2_MASK (0xFC)
#define GPIO_SRCR_FB1_FB1(x) ((x)&0x03)
#define GPIO_SRCR_FB1_FB1_MASK (0xFC)
#define GPIO_SRCR_FB4_FB5(x) (((x)&0x03)<<2)
#define GPIO_SRCR_FB4_FB5_MASK (0xF3)
#define GPIO_SRCR_FB4_FB4(x) ((x)&0x03)
#define GPIO_SRCR_FB4_FB4_MASK (0xFC)
#define GPIO_SRCR_DSPIOW_OWDAT(x) (((x)&0x03)<<4)
#define GPIO_SRCR_DSPIOW_OWDAT_MASK (0xCF)
#define GPIO_SRCR_DSPIOW_DSPI0(x) ((x)&0x03)
#define GPIO_SRCR_DSPIOW_DSPI0_MASK (0xFC)
#define GPIO_SRCR_CANI2C_CAN1(x) (((x)&0x03)<<2)
#define GPIO_SRCR_CANI2C_CAN1_MASK (0xF3)
#define GPIO_SRCR_CANI2C_I2C0(x) ((x)&0x03)
#define GPIO_SRCR_CANI2C_I2C0_MASK (0xFC)
#define GPIO_SRCR_IRQ0_IRQ0(x) ((x)&0x03)
#define GPIO_SRCR_IRQ0_IRQ0_MASK (0xFC)
#define GPIO_SRCR_TIMER_TMR3(x) (((x)&0x03)<<6)
#define GPIO_SRCR_TIMER_TMR3_MASK (0x3F)
#define GPIO_SRCR_TIMER_TMR2(x) (((x)&0x03)<<4)
#define GPIO_SRCR_TIMER_TMR2_MASK (0xCF)
#define GPIO_SRCR_TIMER_TMR1(x) (((x)&0x03)<<2)
#define GPIO_SRCR_TIMER_TMR1_MASK (0xF3)
#define GPIO_SRCR_TIMER_TMR0(x) ((x)&0x03)
#define GPIO_SRCR_TIMER_TMR0_MASK (0xFC)
#define GPIO_SRCR_UART_U2(x) (((x)&0x03)<<4)
#define GPIO_SRCR_UART_U2_MASK (0xCF)
#define GPIO_SRCR_UART_U1(x) (((x)&0x03)<<2)
#define GPIO_SRCR_UART_U1_MASK (0xF3)
#define GPIO_SRCR_UART_U0(x) ((x)&0x03)
#define GPIO_SRCR_UART_U0_MASK (0xFC)
#define GPIO_SRCR_FEC_RMII0(x) (((x)&0x03)<<2)
#define GPIO_SRCR_FEC_RMII0_MASK (0xF3)
#define GPIO_SRCR_FEC_RMII1(x) ((x)&0x03)
#define GPIO_SRCR_FEC_RMII1_MASK (0xFC)
#define GPIO_SRCR_SDHC_SDHC(x) ((x)&0x03)
#define GPIO_SRCR_SDHC_SDHC_MASK (0xFC)
#define GPIO_SRCR_SIM0_SIMP0(x) ((x)&0x03)
#define GPIO_SRCR_SIM0_SIMP0_MASK (0xFC)
#define GPIO_SRCR_SSI0_SSI0(x) ((x)&0x03)
#define GPIO_SRCR_SSI0_SSI0_MASK (0xFC)
#define GPIO_PCR_URTS_U2 (0x0004)
#define GPIO_PCR_URTS_U1 (0x0002)
#define GPIO_PCR_URTS_U0 (0x0001)
#define GPIO_PCR_UCTS_U2 (0x0004)
#define GPIO_PCR_UCTS_U1 (0x0002)
#define GPIO_PCR_UCTS_U0 (0x0001)
#define GPIO_UTXD_WOM_U9 (0x0200)
#define GPIO_UTXD_WOM_U8 (0x0100)
#define GPIO_UTXD_WOM_U7 (0x0080)
#define GPIO_UTXD_WOM_U6 (0x0040)
#define GPIO_UTXD_WOM_U5 (0x0020)
#define GPIO_UTXD_WOM_U4 (0x0010)
#define GPIO_UTXD_WOM_U3 (0x0008)
#define GPIO_UTXD_WOM_U2 (0x0004)
#define GPIO_UTXD_WOM_U1 (0x0002)
#define GPIO_UTXD_WOM_U0 (0x0001)
#define GPIO_URXD_WOM_U9(x) (((x)&3)<<18)
#define GPIO_URXD_WOM_U9_MASK (0xFFF3FFFF)
#define GPIO_URXD_WOM_U8(x) (((x)&3)<<16)
#define GPIO_URXD_WOM_U8_MASK (0xFFFCFFFF)
#define GPIO_URXD_WOM_U7(x) (((x)&3)<<14)
#define GPIO_URXD_WOM_U7_MASK (0xFFFF3FFF)
#define GPIO_URXD_WOM_U6(x) (((x)&3)<<12)
#define GPIO_URXD_WOM_U6_MASK (0xFFFFCFFF)
#define GPIO_URXD_WOM_U5(x) (((x)&3)<<10)
#define GPIO_URXD_WOM_U5_MASK (0xFFFFF3FF)
#define GPIO_URXD_WOM_U4(x) (((x)&3)<<8)
#define GPIO_URXD_WOM_U4_MASK (0xFFFFFCFF)
#define GPIO_URXD_WOM_U3(x) (((x)&3)<<6)
#define GPIO_URXD_WOM_U3_MASK (0xFFFFFF3F)
#define GPIO_URXD_WOM_U2(x) (((x)&3)<<4)
#define GPIO_URXD_WOM_U2_MASK (0xFFFFFFCF)
#define GPIO_URXD_WOM_U1(x) (((x)&3)<<2)
#define GPIO_URXD_WOM_U1_MASK (0xFFFFFFF3)
#define GPIO_URXD_WOM_U0(x) ((x)&3)
#define GPIO_URXD_WOM_U0_MASK (0xFFFFFFFC)
#define GPIO_HCR1_PG4_0(x) (((x)&0x1F)<<27)
#define GPIO_HCR1_PG4_0_MASK (0x07FFFFFF)
#define GPIO_HCR1_PF7_3(x) (((x)&0x1F)<<22)
#define GPIO_HCR1_PF7_3_MASK (0xF83FFFFF)
#define GPIO_HCR1_PE6_0(x) (((x)&0x7F)<<15)
#define GPIO_HCR1_PE6_0_MASK (0xFFC07FFF)
#define GPIO_HCR1_PD7_3(x) (((x)&0x1F)<<10)
#define GPIO_HCR1_PD7_3_MASK (0xFFFF83FF)
#define GPIO_HCR1_PC7_1(x) (((x)&0x7F)<<3)
#define GPIO_HCR1_PC7_1_MASK (0xFFFFFC07)
#define GPIO_HCR1_PB2_0(x) ((x)&7)
#define GPIO_HCR1_PB2_0_MASK (0xFFFFFFF8)
#define GPIO_HCR0_PK3 (0x00000400)
#define GPIO_HCR0_PK0 (0x00000200)
#define GPIO_HCR0_PD2_0(x) (((x)&7)<<6)
#define GPIO_HCR0_PD2_0_MASK (0xFFFFFE3F)
#define GPIO_HCR0_PE7 (0x00000020)
#define GPIO_HCR0_PH7_3(x) ((x)&0x1F)
#define GPIO_HCR0_PH7_3_MASK(x) (0xFFFFFFE0)
/* SDRAM Controller (SDRAMC) */
/* Phase Locked Loop (PLL) */
#define PLL_CR_LOCIRQ (0x00040000)
#define PLL_CR_LOCRE (0x00020000)
#define PLL_CR_LOCEN (0x00010000)
#define PLL_CR_LOLIRQ (0x00004000)
#define PLL_CR_LOLRE (0x00002000)
#define PLL_CR_LOLEN (0x00001000)
#define PLL_CR_REFDIV(x) (((x)&7)<<8)
#define PLL_CR_REFDIV_MASK (0xFFFFF8FF)
#define PLL_CR_FBKDIV(x) ((x)&0x3F)
#define PLL_CR_FBKDIV_MASK (0xFFFFFFC0)
#define PLL_CR_FBKDIV_BITS (0x3F)
#define PLL_DR_OUTDIV5(x) (((x)&0x1F)<<21)
#define PLL_DR_OUTDIV5_MASK (0xFC1FFFFF)
#define PLL_DR_OUTDIV5_BITS (0x03E00000)
#define PLL_DR_OUTDIV4(x) (((x)&0x1F)<<16)
#define PLL_DR_OUTDIV4_MASK (0xFFE0FFFF)
#define PLL_DR_OUTDIV4_BITS (0x001F0000)
#define PLL_DR_OUTDIV3(x) (((x)&0x1F)<<10)
#define PLL_DR_OUTDIV3_MASK (0xFFFF83FF)
#define PLL_DR_OUTDIV3_BITS (0x00007C00)
#define PLL_DR_OUTDIV2(x) (((x)&0x1F)<<5)
#define PLL_DR_OUTDIV2_MASK (0xFFFFFC1F)
#define PLL_DR_OUTDIV2_BITS (0x000003E0)
#define PLL_DR_OUTDIV1(x) ((x)&0x1F)
#define PLL_DR_OUTDIV1_MASK (0xFFFFFFE0)
#define PLL_DR_OUTDIV1_BITS (0x0000001F)
#define PLL_SR_LOCF (0x00000200)
#define PLL_SR_LOC (0x00000100)
#define PLL_SR_LOLF (0x00000040)
#define PLL_SR_LOCKS (0x00000020)
#define PLL_SR_LOCK (0x00000010)
#define PLL_PSR_LOCK PLL_SR_LOCK /* compatible with 5x */
#define PLL_SR_MODE(x) ((x)&7)
#define PLL_SR_MODE_MASK (0xFFFFFFF8)
#endif /* __MCF5441X__ */

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u-boot/arch/m68k/include/asm/m5445x.h Normal file
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/*
* MCF5445x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MCF5445X__
#define __MCF5445X__
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_EDMA_00 (8)
#define INT0_LO_EDMA_01 (9)
#define INT0_LO_EDMA_02 (10)
#define INT0_LO_EDMA_03 (11)
#define INT0_LO_EDMA_04 (12)
#define INT0_LO_EDMA_05 (13)
#define INT0_LO_EDMA_06 (14)
#define INT0_LO_EDMA_07 (15)
#define INT0_LO_EDMA_08 (16)
#define INT0_LO_EDMA_09 (17)
#define INT0_LO_EDMA_10 (18)
#define INT0_LO_EDMA_11 (19)
#define INT0_LO_EDMA_12 (20)
#define INT0_LO_EDMA_13 (21)
#define INT0_LO_EDMA_14 (22)
#define INT0_LO_EDMA_15 (23)
#define INT0_LO_EDMA_ERR (24)
#define INT0_LO_SCM (25)
#define INT0_LO_UART0 (26)
#define INT0_LO_UART1 (27)
#define INT0_LO_UART2 (28)
#define INT0_LO_RSVD1 (29)
#define INT0_LO_I2C (30)
#define INT0_LO_QSPI (31)
#define INT0_HI_DTMR0 (32)
#define INT0_HI_DTMR1 (33)
#define INT0_HI_DTMR2 (34)
#define INT0_HI_DTMR3 (35)
#define INT0_HI_FEC0_TXF (36)
#define INT0_HI_FEC0_TXB (37)
#define INT0_HI_FEC0_UN (38)
#define INT0_HI_FEC0_RL (39)
#define INT0_HI_FEC0_RXF (40)
#define INT0_HI_FEC0_RXB (41)
#define INT0_HI_FEC0_MII (42)
#define INT0_HI_FEC0_LC (43)
#define INT0_HI_FEC0_HBERR (44)
#define INT0_HI_FEC0_GRA (45)
#define INT0_HI_FEC0_EBERR (46)
#define INT0_HI_FEC0_BABT (47)
#define INT0_HI_FEC0_BABR (48)
#define INT0_HI_FEC1_TXF (49)
#define INT0_HI_FEC1_TXB (50)
#define INT0_HI_FEC1_UN (51)
#define INT0_HI_FEC1_RL (52)
#define INT0_HI_FEC1_RXF (53)
#define INT0_HI_FEC1_RXB (54)
#define INT0_HI_FEC1_MII (55)
#define INT0_HI_FEC1_LC (56)
#define INT0_HI_FEC1_HBERR (57)
#define INT0_HI_FEC1_GRA (58)
#define INT0_HI_FEC1_EBERR (59)
#define INT0_HI_FEC1_BABT (60)
#define INT0_HI_FEC1_BABR (61)
#define INT0_HI_SCMIR (62)
#define INT0_HI_RTC_ISR (63)
#define INT1_HI_DSPI_EOQF (33)
#define INT1_HI_DSPI_TFFF (34)
#define INT1_HI_DSPI_TCF (35)
#define INT1_HI_DSPI_TFUF (36)
#define INT1_HI_DSPI_RFDF (37)
#define INT1_HI_DSPI_RFOF (38)
#define INT1_HI_DSPI_RFOF_TFUF (39)
#define INT1_HI_RNG_EI (40)
#define INT1_HI_PIT0_PIF (43)
#define INT1_HI_PIT1_PIF (44)
#define INT1_HI_PIT2_PIF (45)
#define INT1_HI_PIT3_PIF (46)
#define INT1_HI_USBOTG_USBSTS (47)
#define INT1_HI_SSI_ISR (49)
#define INT1_HI_CCM_UOCSR (53)
#define INT1_HI_ATA_ISR (54)
#define INT1_HI_PCI_SCR (55)
#define INT1_HI_PCI_ASR (56)
#define INT1_HI_PLL_LOCKS (57)
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
/* Bit definitions and macros for WCR */
#define WTM_WCR_EN (0x0001)
#define WTM_WCR_HALTED (0x0002)
#define WTM_WCR_DOZE (0x0004)
#define WTM_WCR_WAIT (0x0008)
/*********************************************************************
* Serial Boot Facility (SBF)
*********************************************************************/
/* Bit definitions and macros for SBFCR */
#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */
#define SBF_SBFCR_FR (0x0010) /* Fast read */
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
/* Bit definitions and macros for RCR */
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RCR_SOFTRST (0x80)
/* Bit definitions and macros for RSR */
#define RCM_RSR_LOL (0x01)
#define RCM_RSR_WDR_CORE (0x02)
#define RCM_RSR_EXT (0x04)
#define RCM_RSR_POR (0x08)
#define RCM_RSR_SOFT (0x20)
/*********************************************************************
* Chip Configuration Module (CCM)
*********************************************************************/
/* Bit definitions and macros for CCR_360 */
#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */
#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */
#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */
#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */
#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */
#define CCM_CCR_360_FBCONFIG_MASK (0x00E0)
#define CCM_CCR_360_PLLMULT2_MASK (0x0003)
#define CCM_CCR_360_PLLMULT3_MASK (0x0007)
#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000)
#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020)
#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040)
#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060)
#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080)
#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0)
#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0)
#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0)
#define CCM_CCR_360_PLLMULT2_12X (0x0000)
#define CCM_CCR_360_PLLMULT2_6X (0x0001)
#define CCM_CCR_360_PLLMULT2_16X (0x0002)
#define CCM_CCR_360_PLLMULT2_8X (0x0003)
#define CCM_CCR_360_PLLMULT3_20X (0x0000)
#define CCM_CCR_360_PLLMULT3_10X (0x0001)
#define CCM_CCR_360_PLLMULT3_24X (0x0002)
#define CCM_CCR_360_PLLMULT3_18X (0x0003)
#define CCM_CCR_360_PLLMULT3_12X (0x0004)
#define CCM_CCR_360_PLLMULT3_6X (0x0005)
#define CCM_CCR_360_PLLMULT3_16X (0x0006)
#define CCM_CCR_360_PLLMULT3_8X (0x0007)
/* Bit definitions and macros for CCR_256 */
#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */
#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */
#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */
#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
#define CCM_CCR_256_FBCONFIG_MASK (0x00E0)
#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000)
#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020)
#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040)
#define CCM_CCR_256_FBCONFIG_M_32 (0x0080)
#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0)
#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0)
#define CCM_CCR_256_PLLMULT3_MASK (0x0007)
#define CCM_CCR_256_PLLMULT3_20X (0x0000)
#define CCM_CCR_256_PLLMULT3_10X (0x0001)
#define CCM_CCR_256_PLLMULT3_24X (0x0002)
#define CCM_CCR_256_PLLMULT3_18X (0x0003)
#define CCM_CCR_256_PLLMULT3_12X (0x0004)
#define CCM_CCR_256_PLLMULT3_6X (0x0005)
#define CCM_CCR_256_PLLMULT3_16X (0x0006)
#define CCM_CCR_256_PLLMULT3_8X (0x0007)
/* Bit definitions and macros for RCON_360 */
#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */
#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */
#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */
#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
/* Bit definitions and macros for RCON_256 */
#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */
#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */
#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */
#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
/* Bit definitions and macros for CIR */
#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */
#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */
#define CCM_CIR_PIN_MASK (0xFFC0)
#define CCM_CIR_PRN_MASK (0x003F)
#define CCM_CIR_PIN_MCF54450 (0x4F<<6)
#define CCM_CIR_PIN_MCF54451 (0x4D<<6)
#define CCM_CIR_PIN_MCF54452 (0x4B<<6)
#define CCM_CIR_PIN_MCF54453 (0x49<<6)
#define CCM_CIR_PIN_MCF54454 (0x4A<<6)
#define CCM_CIR_PIN_MCF54455 (0x48<<6)
/* Bit definitions and macros for MISCCR */
#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */
#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */
#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */
#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */
#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
#define CCM_MISCCR_BMT_65536 (0)
#define CCM_MISCCR_BMT_32768 (1)
#define CCM_MISCCR_BMT_16384 (2)
#define CCM_MISCCR_BMT_8192 (3)
#define CCM_MISCCR_BMT_4096 (4)
#define CCM_MISCCR_BMT_2048 (5)
#define CCM_MISCCR_BMT_1024 (6)
#define CCM_MISCCR_BMT_512 (7)
#define CCM_MISCCR_SSIPUS_UP (1)
#define CCM_MISCCR_SSIPUS_DOWN (0)
#define CCM_MISCCR_TIMDMA_TIM (1)
#define CCM_MISCCR_TIMDMA_SSI (0)
#define CCM_MISCCR_SSISRC_CLKIN (0)
#define CCM_MISCCR_SSISRC_PLL (1)
#define CCM_MISCCR_USBOC_ACTHI (0)
#define CCM_MISCCR_USBOV_ACTLO (1)
#define CCM_MISCCR_USBSRC_CLKIN (0)
#define CCM_MISCCR_USBSRC_PLL (1)
/* Bit definitions and macros for CDR */
#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */
#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */
/* Bit definitions and macros for UOCSR */
#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */
#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */
#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */
#define CCM_UOCSR_SEND (0x0010) /* Session end */
#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */
#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */
#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */
#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */
#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */
/*********************************************************************
* General Purpose I/O Module (GPIO)
*********************************************************************/
/* Bit definitions and macros for PAR_FEC */
#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
#define GPIO_PAR_FEC_FEC1_UNMASK (0x8F)
#define GPIO_PAR_FEC_FEC1_MII (0x70)
#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
#define GPIO_PAR_FEC_FEC1_ATA (0x10)
#define GPIO_PAR_FEC_FEC1_GPIO (0x00)
#define GPIO_PAR_FEC_FEC0_UNMASK (0xF8)
#define GPIO_PAR_FEC_FEC0_MII (0x07)
#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
#define GPIO_PAR_FEC_FEC0_ULPI (0x01)
#define GPIO_PAR_FEC_FEC0_GPIO (0x00)
/* Bit definitions and macros for PAR_DMA */
#define GPIO_PAR_DMA_DREQ0 (0x01)
#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
#define GPIO_PAR_DMA_DACK1_UNMASK (0x3F)
#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
#define GPIO_PAR_DMA_DACK1_GPIO (0x00)
#define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF)
#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
#define GPIO_PAR_DMA_DREQ1_GPIO (0x00)
#define GPIO_PAR_DMA_DACK0_UNMASK (0xF3)
#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
#define GPIO_PAR_DMA_DACK0_PCS3 (0x08)
#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
#define GPIO_PAR_DMA_DACK0_GPIO (0x00)
#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)
#define GPIO_PAR_DMA_DREQ0_GPIO (0x00)
/* Bit definitions and macros for PAR_FBCTL */
#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3)
#define GPIO_PAR_FBCTL_RW (0x20)
#define GPIO_PAR_FBCTL_TA (0x40)
#define GPIO_PAR_FBCTL_OE (0x80)
#define GPIO_PAR_FBCTL_OE_OE (0x80)
#define GPIO_PAR_FBCTL_OE_GPIO (0x00)
#define GPIO_PAR_FBCTL_TA_TA (0x40)
#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
#define GPIO_PAR_FBCTL_RW_RW (0x20)
#define GPIO_PAR_FBCTL_RW_GPIO (0x00)
#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7)
#define GPIO_PAR_FBCTL_TS_TS (0x18)
#define GPIO_PAR_FBCTL_TS_ALE (0x10)
#define GPIO_PAR_FBCTL_TS_TBST (0x08)
#define GPIO_PAR_FBCTL_TS_GPIO (0x80)
/* Bit definitions and macros for PAR_DSPI */
#define GPIO_PAR_DSPI_SCK (0x01)
#define GPIO_PAR_DSPI_SOUT (0x02)
#define GPIO_PAR_DSPI_SIN (0x04)
#define GPIO_PAR_DSPI_PCS0 (0x08)
#define GPIO_PAR_DSPI_PCS1 (0x10)
#define GPIO_PAR_DSPI_PCS2 (0x20)
#define GPIO_PAR_DSPI_PCS5 (0x40)
#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40)
#define GPIO_PAR_DSPI_PCS5_GPIO (0x00)
#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20)
#define GPIO_PAR_DSPI_PCS2_GPIO (0x00)
#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10)
#define GPIO_PAR_DSPI_PCS1_GPIO (0x00)
#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08)
#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
#define GPIO_PAR_DSPI_SIN_SIN (0x04)
#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
#define GPIO_PAR_DSPI_SOUT_SOUT (0x02)
#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
#define GPIO_PAR_DSPI_SCK_SCK (0x01)
#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
/* Bit definitions and macros for PAR_BE */
#define GPIO_PAR_BE_BS0 (0x01)
#define GPIO_PAR_BE_BS1 (0x04)
#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
#define GPIO_PAR_BE_BE3_UNMASK (0x3F)
#define GPIO_PAR_BE_BE3_BE3 (0xC0)
#define GPIO_PAR_BE_BE3_TSIZ1 (0x80)
#define GPIO_PAR_BE_BE3_GPIO (0x00)
#define GPIO_PAR_BE_BE2_UNMASK (0xCF)
#define GPIO_PAR_BE_BE2_BE2 (0x30)
#define GPIO_PAR_BE_BE2_TSIZ0 (0x20)
#define GPIO_PAR_BE_BE2_GPIO (0x00)
#define GPIO_PAR_BE_BE1_BE1 (0x04)
#define GPIO_PAR_BE_BE1_GPIO (0x00)
#define GPIO_PAR_BE_BE0_BE0 (0x01)
#define GPIO_PAR_BE_BE0_GPIO (0x00)
/* Bit definitions and macros for PAR_CS */
#define GPIO_PAR_CS_CS1 (0x02)
#define GPIO_PAR_CS_CS2 (0x04)
#define GPIO_PAR_CS_CS3 (0x08)
#define GPIO_PAR_CS_CS3_CS3 (0x08)
#define GPIO_PAR_CS_CS3_GPIO (0x00)
#define GPIO_PAR_CS_CS2_CS2 (0x04)
#define GPIO_PAR_CS_CS2_GPIO (0x00)
#define GPIO_PAR_CS_CS1_CS1 (0x02)
#define GPIO_PAR_CS_CS1_GPIO (0x00)
/* Bit definitions and macros for PAR_TIMER */
#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03))
#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F)
#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF)
#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3)
#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC)
#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
/* Bit definitions and macros for PAR_USB */
#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
#define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3)
#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
#define GPIO_PAR_USB_VBUSEN_GPIO (0x00)
#define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC)
#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
#define GPIO_PAR_USB_VBUSOC_GPIO (0x00)
/* Bit definitions and macros for PAR_UART */
#define GPIO_PAR_UART_U0TXD (0x01)
#define GPIO_PAR_UART_U0RXD (0x02)
#define GPIO_PAR_UART_U0RTS (0x04)
#define GPIO_PAR_UART_U0CTS (0x08)
#define GPIO_PAR_UART_U1TXD (0x10)
#define GPIO_PAR_UART_U1RXD (0x20)
#define GPIO_PAR_UART_U1RTS (0x40)
#define GPIO_PAR_UART_U1CTS (0x80)
#define GPIO_PAR_UART_U1CTS_U1CTS (0x80)
#define GPIO_PAR_UART_U1CTS_GPIO (0x00)
#define GPIO_PAR_UART_U1RTS_U1RTS (0x40)
#define GPIO_PAR_UART_U1RTS_GPIO (0x00)
#define GPIO_PAR_UART_U1RXD_U1RXD (0x20)
#define GPIO_PAR_UART_U1RXD_GPIO (0x00)
#define GPIO_PAR_UART_U1TXD_U1TXD (0x10)
#define GPIO_PAR_UART_U1TXD_GPIO (0x00)
#define GPIO_PAR_UART_U0CTS_U0CTS (0x08)
#define GPIO_PAR_UART_U0CTS_GPIO (0x00)
#define GPIO_PAR_UART_U0RTS_U0RTS (0x04)
#define GPIO_PAR_UART_U0RTS_GPIO (0x00)
#define GPIO_PAR_UART_U0RXD_U0RXD (0x02)
#define GPIO_PAR_UART_U0RXD_GPIO (0x00)
#define GPIO_PAR_UART_U0TXD_U0TXD (0x01)
#define GPIO_PAR_UART_U0TXD_GPIO (0x00)
/* Bit definitions and macros for PAR_FECI2C */
#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003))
#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2)
#define GPIO_PAR_FECI2C_MDIO0 (0x0010)
#define GPIO_PAR_FECI2C_MDC0 (0x0040)
#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
#define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF)
#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
#define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF)
#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040)
#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3)
#define GPIO_PAR_FECI2C_SCL_SCL (0x000C)
#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC)
#define GPIO_PAR_FECI2C_SDA_SDA (0x0003)
#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
/* Bit definitions and macros for PAR_SSI */
#define GPIO_PAR_SSI_MCLK (0x0001)
#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2)
#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
#define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF)
#define GPIO_PAR_SSI_BCLK_BCLK (0x0300)
#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
#define GPIO_PAR_SSI_BCLK_GPIO (0x0000)
#define GPIO_PAR_SSI_FS_UNMASK (0xFF3F)
#define GPIO_PAR_SSI_FS_FS (0x00C0)
#define GPIO_PAR_SSI_FS_U1RTS (0x0080)
#define GPIO_PAR_SSI_FS_GPIO (0x0000)
#define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF)
#define GPIO_PAR_SSI_SRXD_SRXD (0x0030)
#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
#define GPIO_PAR_SSI_SRXD_GPIO (0x0000)
#define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3)
#define GPIO_PAR_SSI_STXD_STXD (0x000C)
#define GPIO_PAR_SSI_STXD_U1TXD (0x0008)
#define GPIO_PAR_SSI_STXD_GPIO (0x0000)
#define GPIO_PAR_SSI_MCLK_MCLK (0x0001)
#define GPIO_PAR_SSI_MCLK_GPIO (0x0000)
/* Bit definitions and macros for PAR_ATA */
#define GPIO_PAR_ATA_IORDY (0x0001)
#define GPIO_PAR_ATA_DMARQ (0x0002)
#define GPIO_PAR_ATA_RESET (0x0004)
#define GPIO_PAR_ATA_DA0 (0x0020)
#define GPIO_PAR_ATA_DA1 (0x0040)
#define GPIO_PAR_ATA_DA2 (0x0080)
#define GPIO_PAR_ATA_CS0 (0x0100)
#define GPIO_PAR_ATA_CS1 (0x0200)
#define GPIO_PAR_ATA_BUFEN (0x0400)
#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400)
#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000)
#define GPIO_PAR_ATA_CS1_CS1 (0x0200)
#define GPIO_PAR_ATA_CS1_GPIO (0x0000)
#define GPIO_PAR_ATA_CS0_CS0 (0x0100)
#define GPIO_PAR_ATA_CS0_GPIO (0x0000)
#define GPIO_PAR_ATA_DA2_DA2 (0x0080)
#define GPIO_PAR_ATA_DA2_GPIO (0x0000)
#define GPIO_PAR_ATA_DA1_DA1 (0x0040)
#define GPIO_PAR_ATA_DA1_GPIO (0x0000)
#define GPIO_PAR_ATA_DA0_DA0 (0x0020)
#define GPIO_PAR_ATA_DA0_GPIO (0x0000)
#define GPIO_PAR_ATA_RESET_RESET (0x0004)
#define GPIO_PAR_ATA_RESET_GPIO (0x0000)
#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002)
#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000)
#define GPIO_PAR_ATA_IORDY_IORDY (0x0001)
#define GPIO_PAR_ATA_IORDY_GPIO (0x0000)
/* Bit definitions and macros for PAR_IRQ */
#define GPIO_PAR_IRQ_IRQ1 (0x02)
#define GPIO_PAR_IRQ_IRQ4 (0x10)
#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10)
#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02)
#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
/* Bit definitions and macros for PAR_PCI */
#define GPIO_PAR_PCI_REQ0 (0x0001)
#define GPIO_PAR_PCI_REQ1 (0x0004)
#define GPIO_PAR_PCI_REQ2 (0x0010)
#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6)
#define GPIO_PAR_PCI_GNT0 (0x0100)
#define GPIO_PAR_PCI_GNT1 (0x0400)
#define GPIO_PAR_PCI_GNT2 (0x1000)
#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
#define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF)
#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
#define GPIO_PAR_PCI_GNT3_GPIO (0x0000)
#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000)
#define GPIO_PAR_PCI_GNT2_GPIO (0x0000)
#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400)
#define GPIO_PAR_PCI_GNT1_GPIO (0x0000)
#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
#define GPIO_PAR_PCI_GNT0_GPIO (0x0000)
#define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F)
#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
#define GPIO_PAR_PCI_REQ3_GPIO (0x0000)
#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010)
#define GPIO_PAR_PCI_REQ2_GPIO (0x0000)
#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040)
#define GPIO_PAR_PCI_REQ1_GPIO (0x0000)
#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001)
#define GPIO_PAR_PCI_REQ0_GPIO (0x0000)
/* Bit definitions and macros for MSCR_SDRAM */
#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03))
#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
#define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F)
#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
#define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF)
#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3)
#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC)
#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00)
/* Bit definitions and macros for MSCR_PCI */
#define GPIO_MSCR_PCI_PCI (0x01)
#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01)
#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00)
/* Bit definitions and macros for DSCR_I2C */
#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03))
#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03)
#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02)
#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01)
#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_FLEXBUS */
#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03))
#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2)
#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4)
#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6)
#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0)
#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80)
#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40)
#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00)
#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30)
#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20)
#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10)
#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00)
#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C)
#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08)
#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04)
#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00)
#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03)
#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02)
#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01)
#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_FEC */
#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03))
#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2)
#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C)
#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08)
#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04)
#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00)
#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03)
#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02)
#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01)
#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_UART */
#define GPIO_DSCR_UART_UART0(x) (((x)&0x03))
#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2)
#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C)
#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08)
#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04)
#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00)
#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03)
#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02)
#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01)
#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_DSPI */
#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03))
#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03)
#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02)
#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01)
#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_TIMER */
#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03))
#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_SSI */
#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03))
#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03)
#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02)
#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_DMA */
#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03))
#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03)
#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02)
#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01)
#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_DEBUG */
#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03))
#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_RESET */
#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03))
#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_IRQ */
#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03))
#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03)
#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02)
#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01)
#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_USB */
#define GPIO_DSCR_USB_USB(x) (((x)&0x03))
#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03)
#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02)
#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01)
#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00)
/* Bit definitions and macros for DSCR_ATA */
#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03))
#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03)
#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02)
#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
/* Bit definitions and macros for SDMR */
#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
#define SDRAMC_SDMR_BK_LMR (0x00000000)
#define SDRAMC_SDMR_BK_LEMR (0x40000000)
/* Bit definitions and macros for SDCR */
#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
/* Bit definitions and macros for SDCFG1 */
#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
/* Bit definitions and macros for SDCFG2 */
#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
/* Bit definitions and macros for SDCS group */
#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/
/* Bit definitions and macros for PCR */
#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */
#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */
#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */
#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
#define PLL_PCR_PFDR_MASK (0x000F0000)
#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
#define PLL_PCR_OUTDIV4_MASK (0x0000F000)
#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
/* Bit definitions and macros for PSR */
#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
/*********************************************************************
* PCI
*********************************************************************/
/* Bit definitions and macros for SCR */
#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
#define PCI_SCR_SE (0x40000000) /* System error signalled */
#define PCI_SCR_MA (0x20000000) /* Master aboart received */
#define PCI_SCR_TR (0x10000000) /* Target abort received */
#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
#define PCI_SCR_DP (0x01000000) /* Master data parity err */
#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
#define PCI_SCR_R (0x00400000) /* Reserved */
#define PCI_SCR_66M (0x00200000) /* 66Mhz */
#define PCI_SCR_C (0x00100000) /* Capabilities list */
#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
#define PCI_SCR_S (0x00000100) /* SERR enable */
#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
#define PCI_SCR_PER (0x00000040) /* Parity error response */
#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
#define PCI_SCR_B (0x00000004) /* Bus master enable */
#define PCI_SCR_M (0x00000002) /* Memory access control */
#define PCI_SCR_IO (0x00000001) /* I/O access control */
#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
#define PCI_BAR_BAR1(x) (x & 0xFFF00000)
#define PCI_BAR_BAR2(x) (x & 0xFFC00000)
#define PCI_BAR_BAR3(x) (x & 0xFF000000)
#define PCI_BAR_BAR4(x) (x & 0xF8000000)
#define PCI_BAR_BAR5(x) (x & 0xE0000000)
#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
#define PCI_GSCR_SE (0x10000000) /* SERR detected */
#define PCI_GSCR_ER (0x08000000) /* Error response detected */
#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
#define PCI_GSCR_PR (0x00000001) /* PCI reset */
#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
#define PCI_TCR2_B5E (0x00002000) /* */
#define PCI_TCR2_B4E (0x00001000) /* */
#define PCI_TCR2_B3E (0x00000800) /* */
#define PCI_TCR2_B2E (0x00000400) /* */
#define PCI_TCR2_B1E (0x00000200) /* */
#define PCI_TCR2_B0E (0x00000100) /* */
#define PCI_TCR2_CR (0x00000001) /* */
#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20)
#define PCI_TBATR_EN (0x00000001) /* Enable */
#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
#define PCI_ICR_REE (0x04000000) /* Retry error enable */
#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
/********************************************************************/
#endif /* __MCF5445X__ */

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u-boot/arch/m68k/include/asm/m547x_8x.h Normal file
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/*
* mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef mcf547x_8x_h
#define mcf547x_8x_h
/*********************************************************************
* XLB Arbiter (XLB)
*********************************************************************/
/* Bit definitions and macros for XARB_CFG */
#define XARB_CFG_AT (0x00000002)
#define XARB_CFG_DT (0x00000004)
#define XARB_CFG_BA (0x00000008)
#define XARB_CFG_PM(x) (((x)&0x00000003)<<5)
#define XARB_CFG_SP(x) (((x)&0x00000007)<<8)
#define XARB_CFG_PLDIS (0x80000000)
/* Bit definitions and macros for XARB_SR */
#define XARB_SR_AT (0x00000001)
#define XARB_SR_DT (0x00000002)
#define XARB_SR_BA (0x00000004)
#define XARB_SR_TTM (0x00000008)
#define XARB_SR_ECW (0x00000010)
#define XARB_SR_TTR (0x00000020)
#define XARB_SR_TTA (0x00000040)
#define XARB_SR_MM (0x00000080)
#define XARB_SR_SEA (0x00000100)
/* Bit definitions and macros for XARB_IMR */
#define XARB_IMR_ATE (0x00000001)
#define XARB_IMR_DTE (0x00000002)
#define XARB_IMR_BAE (0x00000004)
#define XARB_IMR_TTME (0x00000008)
#define XARB_IMR_ECWE (0x00000010)
#define XARB_IMR_TTRE (0x00000020)
#define XARB_IMR_TTAE (0x00000040)
#define XARB_IMR_MME (0x00000080)
#define XARB_IMR_SEAE (0x00000100)
/* Bit definitions and macros for XARB_SIGCAP */
#define XARB_SIGCAP_TT(x) ((x)&0x0000001F)
#define XARB_SIGCAP_TBST (0x00000020)
#define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7)
/* Bit definitions and macros for XARB_PRIEN */
#define XARB_PRIEN_M0 (0x00000001)
#define XARB_PRIEN_M2 (0x00000004)
#define XARB_PRIEN_M3 (0x00000008)
/* Bit definitions and macros for XARB_PRI */
#define XARB_PRI_M0P(x) (((x)&0x00000007)<<0)
#define XARB_PRI_M2P(x) (((x)&0x00000007)<<8)
#define XARB_PRI_M3P(x) (((x)&0x00000007)<<12)
/*********************************************************************
* General Purpose I/O (GPIO)
*********************************************************************/
/* Bit definitions and macros for GPIO_PAR_FBCTL */
#define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0)
#define GPIO_PAR_FBCTL_TA (0x0004)
#define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4)
#define GPIO_PAR_FBCTL_OE (0x0040)
#define GPIO_PAR_FBCTL_BWE0 (0x0100)
#define GPIO_PAR_FBCTL_BWE1 (0x0400)
#define GPIO_PAR_FBCTL_BWE2 (0x1000)
#define GPIO_PAR_FBCTL_BWE3 (0x4000)
#define GPIO_PAR_FBCTL_TS_GPIO (0)
#define GPIO_PAR_FBCTL_TS_TBST (2)
#define GPIO_PAR_FBCTL_TS_TS (3)
#define GPIO_PAR_FBCTL_RWB_GPIO (0x0000)
#define GPIO_PAR_FBCTL_RWB_TBST (0x0020)
#define GPIO_PAR_FBCTL_RWB_RWB (0x0030)
/* Bit definitions and macros for GPIO_PAR_FBCS */
#define GPIO_PAR_FBCS_CS1 (0x02)
#define GPIO_PAR_FBCS_CS2 (0x04)
#define GPIO_PAR_FBCS_CS3 (0x08)
#define GPIO_PAR_FBCS_CS4 (0x10)
#define GPIO_PAR_FBCS_CS5 (0x20)
/* Bit definitions and macros for GPIO_PAR_DMA */
#define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0)
#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2)
#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<4)
#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
#define GPIO_PAR_DMA_DACKx_GPIO (0)
#define GPIO_PAR_DMA_DACKx_TOUT (2)
#define GPIO_PAR_DMA_DACKx_DACK (3)
#define GPIO_PAR_DMA_DREQx_GPIO (0)
#define GPIO_PAR_DMA_DREQx_TIN (2)
#define GPIO_PAR_DMA_DREQx_DREQ (3)
/* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */
#define GPIO_PAR_FECI2CIRQ_IRQ5 (0x0001)
#define GPIO_PAR_FECI2CIRQ_IRQ6 (0x0002)
#define GPIO_PAR_FECI2CIRQ_SCL (0x0004)
#define GPIO_PAR_FECI2CIRQ_SDA (0x0008)
#define GPIO_PAR_FECI2CIRQ_E1MDC(x) (((x)&0x0003)<<6)
#define GPIO_PAR_FECI2CIRQ_E1MDIO(x) (((x)&0x0003)<<8)
#define GPIO_PAR_FECI2CIRQ_E1MII (0x0400)
#define GPIO_PAR_FECI2CIRQ_E17 (0x0800)
#define GPIO_PAR_FECI2CIRQ_E0MDC (0x1000)
#define GPIO_PAR_FECI2CIRQ_E0MDIO (0x2000)
#define GPIO_PAR_FECI2CIRQ_E0MII (0x4000)
#define GPIO_PAR_FECI2CIRQ_E07 (0x8000)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX (0x0000)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA (0x0200)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO (0x0300)
#define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX (0x0000)
#define GPIO_PAR_FECI2CIRQ_E1MDC_SCL (0x0080)
#define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC (0x00C0)
/* Bit definitions and macros for GPIO_PAR_PCIBG */
#define GPIO_PAR_PCIBG_PCIBG0(x) (((x)&0x0003)<<0)
#define GPIO_PAR_PCIBG_PCIBG1(x) (((x)&0x0003)<<2)
#define GPIO_PAR_PCIBG_PCIBG2(x) (((x)&0x0003)<<4)
#define GPIO_PAR_PCIBG_PCIBG3(x) (((x)&0x0003)<<6)
#define GPIO_PAR_PCIBG_PCIBG4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for GPIO_PAR_PCIBR */
#define GPIO_PAR_PCIBR_PCIBR0(x) (((x)&0x0003)<<0)
#define GPIO_PAR_PCIBR_PCIBR1(x) (((x)&0x0003)<<2)
#define GPIO_PAR_PCIBR_PCIBR2(x) (((x)&0x0003)<<4)
#define GPIO_PAR_PCIBR_PCIBR3(x) (((x)&0x0003)<<6)
#define GPIO_PAR_PCIBR_PCIBR4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for GPIO_PAR_PSC3 */
#define GPIO_PAR_PSC3_TXD3 (0x04)
#define GPIO_PAR_PSC3_RXD3 (0x08)
#define GPIO_PAR_PSC3_RTS3(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC3_CTS3(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC3_CTS3_GPIO (0x00)
#define GPIO_PAR_PSC3_CTS3_BCLK (0x80)
#define GPIO_PAR_PSC3_CTS3_CTS (0xC0)
#define GPIO_PAR_PSC3_RTS3_GPIO (0x00)
#define GPIO_PAR_PSC3_RTS3_FSYNC (0x20)
#define GPIO_PAR_PSC3_RTS3_RTS (0x30)
#define GPIO_PAR_PSC3_CTS2_CANRX (0x40)
/* Bit definitions and macros for GPIO_PAR_PSC2 */
#define GPIO_PAR_PSC2_TXD2 (0x04)
#define GPIO_PAR_PSC2_RXD2 (0x08)
#define GPIO_PAR_PSC2_RTS2(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC2_CTS2(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC2_CTS2_GPIO (0x00)
#define GPIO_PAR_PSC2_CTS2_BCLK (0x80)
#define GPIO_PAR_PSC2_CTS2_CTS (0xC0)
#define GPIO_PAR_PSC2_RTS2_GPIO (0x00)
#define GPIO_PAR_PSC2_RTS2_CANTX (0x10)
#define GPIO_PAR_PSC2_RTS2_FSYNC (0x20)
#define GPIO_PAR_PSC2_RTS2_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_PSC1 */
#define GPIO_PAR_PSC1_TXD1 (0x04)
#define GPIO_PAR_PSC1_RXD1 (0x08)
#define GPIO_PAR_PSC1_RTS1(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC1_CTS1(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC1_CTS1_GPIO (0x00)
#define GPIO_PAR_PSC1_CTS1_BCLK (0x80)
#define GPIO_PAR_PSC1_CTS1_CTS (0xC0)
#define GPIO_PAR_PSC1_RTS1_GPIO (0x00)
#define GPIO_PAR_PSC1_RTS1_FSYNC (0x20)
#define GPIO_PAR_PSC1_RTS1_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_PSC0 */
#define GPIO_PAR_PSC0_TXD0 (0x04)
#define GPIO_PAR_PSC0_RXD0 (0x08)
#define GPIO_PAR_PSC0_RTS0(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC0_CTS0(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC0_CTS0_GPIO (0x00)
#define GPIO_PAR_PSC0_CTS0_BCLK (0x80)
#define GPIO_PAR_PSC0_CTS0_CTS (0xC0)
#define GPIO_PAR_PSC0_RTS0_GPIO (0x00)
#define GPIO_PAR_PSC0_RTS0_FSYNC (0x20)
#define GPIO_PAR_PSC0_RTS0_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_DSPI */
#define GPIO_PAR_DSPI_SOUT(x) (((x)&0x0003)<<0)
#define GPIO_PAR_DSPI_SIN(x) (((x)&0x0003)<<2)
#define GPIO_PAR_DSPI_SCK(x) (((x)&0x0003)<<4)
#define GPIO_PAR_DSPI_CS0(x) (((x)&0x0003)<<6)
#define GPIO_PAR_DSPI_CS2(x) (((x)&0x0003)<<8)
#define GPIO_PAR_DSPI_CS3(x) (((x)&0x0003)<<10)
#define GPIO_PAR_DSPI_CS5 (0x1000)
#define GPIO_PAR_DSPI_CS3_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS3_CANTX (0x0400)
#define GPIO_PAR_DSPI_CS3_TOUT (0x0800)
#define GPIO_PAR_DSPI_CS3_DSPICS (0x0C00)
#define GPIO_PAR_DSPI_CS2_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS2_CANTX (0x0100)
#define GPIO_PAR_DSPI_CS2_TOUT (0x0200)
#define GPIO_PAR_DSPI_CS2_DSPICS (0x0300)
#define GPIO_PAR_DSPI_CS0_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS0_FSYNC (0x0040)
#define GPIO_PAR_DSPI_CS0_RTS (0x0080)
#define GPIO_PAR_DSPI_CS0_DSPICS (0x00C0)
#define GPIO_PAR_DSPI_SCK_GPIO (0x0000)
#define GPIO_PAR_DSPI_SCK_BCLK (0x0010)
#define GPIO_PAR_DSPI_SCK_CTS (0x0020)
#define GPIO_PAR_DSPI_SCK_SCK (0x0030)
#define GPIO_PAR_DSPI_SIN_GPIO (0x0000)
#define GPIO_PAR_DSPI_SIN_RXD (0x0008)
#define GPIO_PAR_DSPI_SIN_SIN (0x000C)
#define GPIO_PAR_DSPI_SOUT_GPIO (0x0000)
#define GPIO_PAR_DSPI_SOUT_TXD (0x0002)
#define GPIO_PAR_DSPI_SOUT_SOUT (0x0003)
/* Bit definitions and macros for GPIO_PAR_TIMER */
#define GPIO_PAR_TIMER_TOUT2 (0x01)
#define GPIO_PAR_TIMER_TIN2(x) (((x)&0x03)<<1)
#define GPIO_PAR_TIMER_TOUT3 (0x08)
#define GPIO_PAR_TIMER_TIN3(x) (((x)&0x03)<<4)
#define GPIO_PAR_TIMER_TIN3_CANRX (0x00)
#define GPIO_PAR_TIMER_TIN3_IRQ (0x20)
#define GPIO_PAR_TIMER_TIN3_TIN (0x30)
#define GPIO_PAR_TIMER_TIN2_CANRX (0x00)
#define GPIO_PAR_TIMER_TIN2_IRQ (0x04)
#define GPIO_PAR_TIMER_TIN2_TIN (0x06)
/*********************************************************************
* Slice Timer (SLT)
*********************************************************************/
#define SLT_CR_RUN (0x04000000)
#define SLT_CR_IEN (0x02000000)
#define SLT_CR_TEN (0x01000000)
#define SLT_SR_BE (0x02000000)
#define SLT_SR_ST (0x01000000)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_EP0ISR (15)
#define INT0_LO_EP1ISR (16)
#define INT0_LO_EP2ISR (17)
#define INT0_LO_EP3ISR (18)
#define INT0_LO_EP4ISR (19)
#define INT0_LO_EP5ISR (20)
#define INT0_LO_EP6ISR (21)
#define INT0_LO_USBISR (22)
#define INT0_LO_USBAISR (23)
#define INT0_LO_USB (24)
#define INT1_LO_DSPI_RFOF_TFUF (25)
#define INT1_LO_DSPI_RFOF (26)
#define INT1_LO_DSPI_RFDF (27)
#define INT1_LO_DSPI_TFUF (28)
#define INT1_LO_DSPI_TCF (29)
#define INT1_LO_DSPI_TFFF (30)
#define INT1_LO_DSPI_EOQF (31)
#define INT0_HI_UART3 (32)
#define INT0_HI_UART2 (33)
#define INT0_HI_UART1 (34)
#define INT0_HI_UART0 (35)
#define INT0_HI_COMMTIM_TC (36)
#define INT0_HI_SEC (37)
#define INT0_HI_FEC1 (38)
#define INT0_HI_FEC0 (39)
#define INT0_HI_I2C (40)
#define INT0_HI_PCIARB (41)
#define INT0_HI_CBPCI (42)
#define INT0_HI_XLBPCI (43)
#define INT0_HI_XLBARB (47)
#define INT0_HI_DMA (48)
#define INT0_HI_CAN0_ERROR (49)
#define INT0_HI_CAN0_BUSOFF (50)
#define INT0_HI_CAN0_MBOR (51)
#define INT0_HI_SLT1 (53)
#define INT0_HI_SLT0 (54)
#define INT0_HI_CAN1_ERROR (55)
#define INT0_HI_CAN1_BUSOFF (56)
#define INT0_HI_CAN1_MBOR (57)
#define INT0_HI_GPT3 (59)
#define INT0_HI_GPT2 (60)
#define INT0_HI_GPT1 (61)
#define INT0_HI_GPT0 (62)
/*********************************************************************
* General Purpose Timers (GPTMR)
*********************************************************************/
/* Enable and Mode Select */
#define GPT_OCT(x) (x & 0x3)<<4 /* Output Compare Type */
#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
#define GPT_CTRL_CE 0x10 /* Counter Enable */
#define GPT_CTRL_STPCNT 0x04 /* Stop continous */
#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
#define GPT_MODE_GPIO(x) (x & 0x3)<<4 /* Gpio Mode Type */
#define GPT_TMS_ICT 0x01 /* Input Capture Enable */
#define GPT_TMS_OCT 0x02 /* Output Capture Enable */
#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
#define GPT_PWM_WIDTH(x) (x & 0xffff)
/* Status */
#define GPT_STA_CAPTURE(x) (x & 0xffff)
#define GPT_OVFPIN_OVF(x) (x & 0x70)
#define GPT_OVFPIN_PIN 0x01
#define GPT_INT_TEXP 0x08
#define GPT_INT_PWMP 0x04
#define GPT_INT_COMP 0x02
#define GPT_INT_CAPT 0x01
/*********************************************************************
* PCI
*********************************************************************/
/* Bit definitions and macros for SCR */
#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
#define PCI_SCR_SE (0x40000000) /* System error signalled */
#define PCI_SCR_MA (0x20000000) /* Master aboart received */
#define PCI_SCR_TR (0x10000000) /* Target abort received */
#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
#define PCI_SCR_DP (0x01000000) /* Master data parity err */
#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
#define PCI_SCR_R (0x00400000) /* Reserved */
#define PCI_SCR_66M (0x00200000) /* 66Mhz */
#define PCI_SCR_C (0x00100000) /* Capabilities list */
#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
#define PCI_SCR_S (0x00000100) /* SERR enable */
#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
#define PCI_SCR_PER (0x00000040) /* Parity error response */
#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
#define PCI_SCR_B (0x00000004) /* Bus master enable */
#define PCI_SCR_M (0x00000002) /* Memory access control */
#define PCI_SCR_IO (0x00000001) /* I/O access control */
#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
#define PCI_BAR_BAR1(x) (x & 0xC0000000)
#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
#define PCI_GSCR_SE (0x10000000) /* SERR detected */
#define PCI_GSCR_ER (0x08000000) /* Error response detected */
#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
#define PCI_GSCR_PR (0x00000001) /* PCI reset */
#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
#define PCI_TCR1_B5E (0x00002000) /* */
#define PCI_TCR1_B4E (0x00001000) /* */
#define PCI_TCR1_B3E (0x00000800) /* */
#define PCI_TCR1_B2E (0x00000400) /* */
#define PCI_TCR1_B1E (0x00000200) /* */
#define PCI_TCR1_B0E (0x00000100) /* */
#define PCI_TCR1_CR (0x00000001) /* */
#define PCI_TBATR_BAT0(x) (x & 0xFFFC0000)
#define PCI_TBATR_BAT1(x) (x & 0xC0000000)
#define PCI_TBATR_EN (0x00000001) /* Enable */
#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
#define PCI_ICR_REE (0x04000000) /* Retry error enable */
#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
#define PCIARB_ACR_DS (0x80000000)
#define PCIARB_ARC_EXTMINTEN(x) (((x)&0x1F) << 17)
#define PCIARB_ARC_INTMINTEN (0x00010000)
#define PCIARB_ARC_EXTMPRI(x) (((x)&0x1F) << 1)
#define PCIARB_ARC_INTMPRI (0x00000001)
#endif /* mcf547x_8x_h */

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u-boot/arch/m68k/include/asm/posix_types.h Normal file
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#ifndef _M68K_POSIX_TYPES_H
#define _M68K_POSIX_TYPES_H
/*
* This file is generally used by user-level software, so you need to
* be a little careful about namespace pollution etc. Also, we cannot
* assume GCC is being used.
*/
typedef unsigned int __kernel_dev_t;
typedef unsigned int __kernel_ino_t;
typedef unsigned int __kernel_mode_t;
typedef unsigned short __kernel_nlink_t;
typedef long __kernel_off_t;
typedef int __kernel_pid_t;
typedef unsigned int __kernel_uid_t;
typedef unsigned int __kernel_gid_t;
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef long __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
typedef int __kernel_daddr_t;
typedef char * __kernel_caddr_t;
typedef short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid16_t;
typedef unsigned short __kernel_gid16_t;
typedef unsigned int __kernel_uid32_t;
typedef unsigned int __kernel_gid32_t;
typedef unsigned int __kernel_old_uid_t;
typedef unsigned int __kernel_old_gid_t;
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
typedef struct {
int val[2];
} __kernel_fsid_t;
#ifndef __GNUC__
#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
#define __FD_ZERO(set) \
((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
#else /* __GNUC__ */
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
|| (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
/* With GNU C, use inline functions instead so args are evaluated only once: */
#undef __FD_SET
static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
{
unsigned long _tmp = fd / __NFDBITS;
unsigned long _rem = fd % __NFDBITS;
fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
}
#undef __FD_CLR
static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
{
unsigned long _tmp = fd / __NFDBITS;
unsigned long _rem = fd % __NFDBITS;
fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
}
#undef __FD_ISSET
static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
{
unsigned long _tmp = fd / __NFDBITS;
unsigned long _rem = fd % __NFDBITS;
return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
}
/*
* This will unroll the loop for the normal constant case (8 ints,
* for a 256-bit fd_set)
*/
#undef __FD_ZERO
static __inline__ void __FD_ZERO(__kernel_fd_set *p)
{
unsigned int *tmp = (unsigned int *)p->fds_bits;
int i;
if (__builtin_constant_p(__FDSET_LONGS)) {
switch (__FDSET_LONGS) {
case 8:
tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
return;
}
}
i = __FDSET_LONGS;
while (i) {
i--;
*tmp = 0;
tmp++;
}
}
#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
#endif /* __GNUC__ */
#endif /* _M68K_POSIX_TYPES_H */

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#ifndef __ASM_M68K_PROCESSOR_H
#define __ASM_M68K_PROCESSOR_H
#include <asm/ptrace.h>
#include <asm/types.h>
#define _GLOBAL(n)\
.globl n;\
n:
/* Macros for setting and retrieving special purpose registers */
#define setvbr(v) asm volatile("movec %0,%%VBR" : : "r" (v))
#ifndef __ASSEMBLY__
#endif /* ifndef ASSEMBLY*/
#endif /* __ASM_M68K_PROCESSOR_H */

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/*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _M68K_PTRACE_H
#define _M68K_PTRACE_H
/*
* This struct defines the way the registers are stored on the
* kernel stack during an exception.
*/
#ifndef __ASSEMBLY__
struct pt_regs {
ulong d0;
ulong d1;
ulong d2;
ulong d3;
ulong d4;
ulong d5;
ulong d6;
ulong d7;
ulong a0;
ulong a1;
ulong a2;
ulong a3;
ulong a4;
ulong a5;
ulong a6;
#if defined(__M68K__)
unsigned format:4; /* frame format specifier */
unsigned vector:12; /* vector offset */
unsigned short sr;
unsigned long pc;
#else
unsigned short sr;
unsigned long pc;
#endif
};
#endif /* #ifndef __ASSEMBLY__ */
#endif /* #ifndef _M68K_PTRACE_H */

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/*
* RealTime Clock
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MCFRTC_H__
#define __MCFRTC_H__
/* Real time Clock */
typedef struct rtc_ctrl {
u32 hourmin; /* 0x00 Hours and Minutes Counter Register */
u32 seconds; /* 0x04 Seconds Counter Register */
u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */
u32 alrm_sec; /* 0x0C Seconds Alarm Register */
u32 cr; /* 0x10 Control Register */
u32 isr; /* 0x14 Interrupt Status Register */
u32 ier; /* 0x18 Interrupt Enable Register */
u32 stpwatch; /* 0x1C Stopwatch Minutes Register */
u32 days; /* 0x20 Days Counter Register */
u32 alrm_day; /* 0x24 Days Alarm Register */
void *extended;
} rtc_t;
/* Bit definitions and macros for HOURMIN */
#define RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F))
#define RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8)
/* Bit definitions and macros for SECONDS */
#define RTC_SECONDS_SECONDS(x) (((x)&0x0000003F))
/* Bit definitions and macros for ALRM_HM */
#define RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F))
#define RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8)
/* Bit definitions and macros for ALRM_SEC */
#define RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F))
/* Bit definitions and macros for CR */
#define RTC_CR_SWR (0x00000001)
#define RTC_CR_XTL(x) (((x)&0x00000003)<<5)
#define RTC_CR_EN (0x00000080)
#define RTC_CR_32768 (0x0)
#define RTC_CR_32000 (0x1)
#define RTC_CR_38400 (0x2)
/* Bit definitions and macros for ISR */
#define RTC_ISR_SW (0x00000001)
#define RTC_ISR_MIN (0x00000002)
#define RTC_ISR_ALM (0x00000004)
#define RTC_ISR_DAY (0x00000008)
#define RTC_ISR_1HZ (0x00000010)
#define RTC_ISR_HR (0x00000020)
#define RTC_ISR_2HZ (0x00000080)
#define RTC_ISR_SAM0 (0x00000100)
#define RTC_ISR_SAM1 (0x00000200)
#define RTC_ISR_SAM2 (0x00000400)
#define RTC_ISR_SAM3 (0x00000800)
#define RTC_ISR_SAM4 (0x00001000)
#define RTC_ISR_SAM5 (0x00002000)
#define RTC_ISR_SAM6 (0x00004000)
#define RTC_ISR_SAM7 (0x00008000)
/* Bit definitions and macros for IER */
#define RTC_IER_SW (0x00000001)
#define RTC_IER_MIN (0x00000002)
#define RTC_IER_ALM (0x00000004)
#define RTC_IER_DAY (0x00000008)
#define RTC_IER_1HZ (0x00000010)
#define RTC_IER_HR (0x00000020)
#define RTC_IER_2HZ (0x00000080)
#define RTC_IER_SAM0 (0x00000100)
#define RTC_IER_SAM1 (0x00000200)
#define RTC_IER_SAM2 (0x00000400)
#define RTC_IER_SAM3 (0x00000800)
#define RTC_IER_SAM4 (0x00001000)
#define RTC_IER_SAM5 (0x00002000)
#define RTC_IER_SAM6 (0x00004000)
#define RTC_IER_SAM7 (0x00008000)
/* Bit definitions and macros for STPWCH */
#define RTC_STPWCH_CNT(x) (((x)&0x0000003F))
/* Bit definitions and macros for DAYS */
#define RTC_DAYS_DAYS(x) (((x)&0x0000FFFF))
/* Bit definitions and macros for ALRM_DAY */
#define RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF))
#endif /* __MCFRTC_H__ */

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/*
* Copyright (c) 2012 The Chromium OS Authors.
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_M68K_SECTIONS_H
#define __ASM_M68K_SECTIONS_H
#include <asm-generic/sections.h>
#endif

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#ifndef _M68K_STRING_H_
#define _M68K_STRING_H_
#if 0
#define __HAVE_ARCH_STRCPY
#define __HAVE_ARCH_STRNCPY
#define __HAVE_ARCH_STRLEN
#define __HAVE_ARCH_STRCMP
#define __HAVE_ARCH_STRCAT
#define __HAVE_ARCH_MEMSET
#define __HAVE_ARCH_BCOPY
#define __HAVE_ARCH_MEMCPY
#define __HAVE_ARCH_MEMMOVE
#define __HAVE_ARCH_MEMCMP
#define __HAVE_ARCH_MEMCHR
#endif
extern int strcasecmp(const char *, const char *);
extern int strncasecmp(const char *, const char *, __kernel_size_t);
extern char * strcpy(char *,const char *);
extern char * strncpy(char *,const char *, __kernel_size_t);
extern __kernel_size_t strlen(const char *);
extern int strcmp(const char *,const char *);
extern char * strcat(char *, const char *);
extern void * memset(void *,int,__kernel_size_t);
extern void * memcpy(void *,const void *,__kernel_size_t);
extern void * memmove(void *,const void *,__kernel_size_t);
extern int memcmp(const void *,const void *,__kernel_size_t);
extern void * memchr(const void *,int,__kernel_size_t);
#endif

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/*
* timer.h -- ColdFire internal TIMER support defines.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
/****************************************************************************/
#ifndef timer_h
#define timer_h
/****************************************************************************/
/****************************************************************************/
/* Timer structure */
/****************************************************************************/
/* DMA Timer module registers */
typedef struct dtimer_ctrl {
#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
defined(CONFIG_M5272) || defined(CONFIG_M5307)
u16 tmr; /* 0x00 Mode register */
u16 res1; /* 0x02 */
u16 trr; /* 0x04 Reference register */
u16 res2; /* 0x06 */
u16 tcr; /* 0x08 Capture register */
u16 res3; /* 0x0A */
u16 tcn; /* 0x0C Counter register */
u16 res4; /* 0x0E */
u8 res6; /* 0x10 */
u8 ter; /* 0x11 Event register */
u16 res7; /* 0x12 */
#else
u16 tmr; /* 0x00 Mode register */
u8 txmr; /* 0x02 Extended Mode register */
u8 ter; /* 0x03 Event register */
u32 trr; /* 0x04 Reference register */
u32 tcr; /* 0x08 Capture register */
u32 tcn; /* 0x0C Counter register */
#endif
} dtmr_t;
/*Programmable Interrupt Timer */
typedef struct pit_ctrl {
u16 pcsr; /* 0x00 Control and Status Register */
u16 pmr; /* 0x02 Modulus Register */
u16 pcntr; /* 0x04 Count Register */
} pit_t;
/*********************************************************************
* DMA Timers (DTIM)
*********************************************************************/
/* Bit definitions and macros for DTMR */
#define DTIM_DTMR_RST (0x0001) /* Reset */
#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */
#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
#define DTIM_DTMR_OM (0x0020) /* Output Mode */
#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
#define DTIM_DTMR_RST_EN (0x0001)
#define DTIM_DTMR_RST_RST (0x0000)
#define DTIM_DTMR_CE_ANY (0x00C0)
#define DTIM_DTMR_CE_FALL (0x0080)
#define DTIM_DTMR_CE_RISE (0x0040)
#define DTIM_DTMR_CE_NONE (0x0000)
#define DTIM_DTMR_CLK_DTIN (0x0006)
#define DTIM_DTMR_CLK_DIV16 (0x0004)
#define DTIM_DTMR_CLK_DIV1 (0x0002)
#define DTIM_DTMR_CLK_STOP (0x0000)
/* Bit definitions and macros for DTXMR */
#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */
/* Bit definitions and macros for DTER */
#define DTIM_DTER_CAP (0x01) /* Capture event */
#define DTIM_DTER_REF (0x02) /* Output reference event */
/*********************************************************************
*
* Programmable Interrupt Timer Modules (PIT)
*
*********************************************************************/
/* Bit definitions and macros for PCSR */
#define PIT_PCSR_EN (0x0001)
#define PIT_PCSR_RLD (0x0002)
#define PIT_PCSR_PIF (0x0004)
#define PIT_PCSR_PIE (0x0008)
#define PIT_PCSR_OVW (0x0010)
#define PIT_PCSR_HALTED (0x0020)
#define PIT_PCSR_DOZE (0x0040)
#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
/* Bit definitions and macros for PMR */
#define PIT_PMR_PM(x) (x)
/* Bit definitions and macros for PCNTR */
#define PIT_PCNTR_PC(x) (x)
/****************************************************************************/
#endif /* timer_h */

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#ifndef _M68K_TYPES_H
#define _M68K_TYPES_H
#ifndef __ASSEMBLY__
typedef unsigned short umode_t;
typedef __signed__ char __s8;
typedef unsigned char __u8;
typedef __signed__ short __s16;
typedef unsigned short __u16;
typedef __signed__ int __s32;
typedef unsigned int __u32;
#if defined(__GNUC__)
__extension__ typedef __signed__ long long __s64;
__extension__ typedef unsigned long long __u64;
#endif
typedef struct {
__u32 u[4];
} __attribute__((aligned(16))) vector128;
#ifdef __KERNEL__
/*
* These aren't exported outside the kernel to avoid name space clashes
*/
typedef signed char s8;
typedef unsigned char u8;
typedef signed short s16;
typedef unsigned short u16;
typedef signed int s32;
typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
#define BITS_PER_LONG 32
/* DMA addresses are 32-bits wide */
typedef u32 dma_addr_t;
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif

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/*
* (C) Copyright 2000 - 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
********************************************************************
* NOTE: This header file defines an interface to U-Boot. Including
* this (unmodified) header file in another file is considered normal
* use of U-Boot, and does *not* fall under the heading of "derived
* work".
********************************************************************
*/
#ifndef __U_BOOT_H__
#define __U_BOOT_H__
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_M68K
#endif /* __U_BOOT_H__ */

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/*
* uart.h -- ColdFire internal UART support defines.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
/****************************************************************************/
#ifndef uart_h
#define uart_h
/****************************************************************************/
/* UART module registers */
/* Register read/write struct */
typedef struct uart {
u8 umr; /* 0x00 Mode Register */
u8 resv0[0x3];
union {
u8 usr; /* 0x04 Status Register */
u8 ucsr; /* 0x04 Clock Select Register */
};
u8 resv1[0x3];
u8 ucr; /* 0x08 Command Register */
u8 resv2[0x3];
union {
u8 utb; /* 0x0c Transmit Buffer */
u8 urb; /* 0x0c Receive Buffer */
};
u8 resv3[0x3];
union {
u8 uipcr; /* 0x10 Input Port Change Register */
u8 uacr; /* 0x10 Auxiliary Control reg */
};
u8 resv4[0x3];
union {
u8 uimr; /* 0x14 Interrupt Mask reg */
u8 uisr; /* 0x14 Interrupt Status reg */
};
u8 resv5[0x3];
u8 ubg1; /* 0x18 Counter Timer Upper Register */
u8 resv6[0x3];
u8 ubg2; /* 0x1c Counter Timer Lower Register */
u8 resv7[0x17];
u8 uip; /* 0x34 Input Port Register */
u8 resv8[0x3];
u8 uop1; /* 0x38 Output Port Set Register */
u8 resv9[0x3];
u8 uop0; /* 0x3c Output Port Reset Register */
} uart_t;
/*********************************************************************
* Universal Asynchronous Receiver Transmitter (UART)
*********************************************************************/
/* Bit definitions and macros for UMR */
#define UART_UMR_BC(x) (((x)&0x03))
#define UART_UMR_PT (0x04)
#define UART_UMR_PM(x) (((x)&0x03)<<3)
#define UART_UMR_ERR (0x20)
#define UART_UMR_RXIRQ (0x40)
#define UART_UMR_RXRTS (0x80)
#define UART_UMR_SB(x) (((x)&0x0F))
#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */
#define UART_UMR_TXRTS (0x20) /* Transmit RTS */
#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */
#define UART_UMR_PM_MULTI_ADDR (0x1C)
#define UART_UMR_PM_MULTI_DATA (0x18)
#define UART_UMR_PM_NONE (0x10)
#define UART_UMR_PM_FORCE_HI (0x0C)
#define UART_UMR_PM_FORCE_LO (0x08)
#define UART_UMR_PM_ODD (0x04)
#define UART_UMR_PM_EVEN (0x00)
#define UART_UMR_BC_5 (0x00)
#define UART_UMR_BC_6 (0x01)
#define UART_UMR_BC_7 (0x02)
#define UART_UMR_BC_8 (0x03)
#define UART_UMR_CM_NORMAL (0x00)
#define UART_UMR_CM_ECH (0x40)
#define UART_UMR_CM_LOCAL_LOOP (0x80)
#define UART_UMR_CM_REMOTE_LOOP (0xC0)
#define UART_UMR_SB_STOP_BITS_1 (0x07)
#define UART_UMR_SB_STOP_BITS_15 (0x08)
#define UART_UMR_SB_STOP_BITS_2 (0x0F)
/* Bit definitions and macros for USR */
#define UART_USR_RXRDY (0x01)
#define UART_USR_FFULL (0x02)
#define UART_USR_TXRDY (0x04)
#define UART_USR_TXEMP (0x08)
#define UART_USR_OE (0x10)
#define UART_USR_PE (0x20)
#define UART_USR_FE (0x40)
#define UART_USR_RB (0x80)
/* Bit definitions and macros for UCSR */
#define UART_UCSR_TCS(x) (((x)&0x0F))
#define UART_UCSR_RCS(x) (((x)&0x0F)<<4)
#define UART_UCSR_RCS_SYS_CLK (0xD0)
#define UART_UCSR_RCS_CTM16 (0xE0)
#define UART_UCSR_RCS_CTM (0xF0)
#define UART_UCSR_TCS_SYS_CLK (0x0D)
#define UART_UCSR_TCS_CTM16 (0x0E)
#define UART_UCSR_TCS_CTM (0x0F)
/* Bit definitions and macros for UCR */
#define UART_UCR_RXC(x) (((x)&0x03))
#define UART_UCR_TXC(x) (((x)&0x03)<<2)
#define UART_UCR_MISC(x) (((x)&0x07)<<4)
#define UART_UCR_NONE (0x00)
#define UART_UCR_STOP_BREAK (0x70)
#define UART_UCR_START_BREAK (0x60)
#define UART_UCR_BKCHGINT (0x50)
#define UART_UCR_RESET_ERROR (0x40)
#define UART_UCR_RESET_TX (0x30)
#define UART_UCR_RESET_RX (0x20)
#define UART_UCR_RESET_MR (0x10)
#define UART_UCR_TX_DISABLED (0x08)
#define UART_UCR_TX_ENABLED (0x04)
#define UART_UCR_RX_DISABLED (0x02)
#define UART_UCR_RX_ENABLED (0x01)
/* Bit definitions and macros for UIPCR */
#define UART_UIPCR_CTS (0x01)
#define UART_UIPCR_COS (0x10)
/* Bit definitions and macros for UACR */
#define UART_UACR_IEC (0x01)
/* Bit definitions and macros for UIMR */
#define UART_UIMR_TXRDY (0x01)
#define UART_UIMR_RXRDY_FU (0x02)
#define UART_UIMR_DB (0x04)
#define UART_UIMR_COS (0x80)
/* Bit definitions and macros for UISR */
#define UART_UISR_TXRDY (0x01)
#define UART_UISR_RXRDY_FU (0x02)
#define UART_UISR_DB (0x04)
#define UART_UISR_RXFTO (0x08)
#define UART_UISR_TXFIFO (0x10)
#define UART_UISR_RXFIFO (0x20)
#define UART_UISR_COS (0x80)
/* Bit definitions and macros for UIP */
#define UART_UIP_CTS (0x01)
/* Bit definitions and macros for UOP1 */
#define UART_UOP1_RTS (0x01)
/* Bit definitions and macros for UOP0 */
#define UART_UOP0_RTS (0x01)
/****************************************************************************/
#endif /* mcfuart_h */

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#ifndef _ASM_M68K_UNALIGNED_H
#define _ASM_M68K_UNALIGNED_H
#ifdef CONFIG_COLDFIRE
#include <linux/unaligned/be_byteshift.h>
#else
#include <linux/unaligned/access_ok.h>
#endif
#include <linux/unaligned/generic.h>
#define get_unaligned __get_unaligned_be
#define put_unaligned __put_unaligned_be
#endif /* _ASM_M68K_UNALIGNED_H */