avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
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20
u-boot/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
Normal file
20
u-boot/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
Normal file
@@ -0,0 +1,20 @@
|
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-cdef-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_CDEF_ADSP_BF542_proc__
|
||||
#define __BFIN_CDEF_ADSP_BF542_proc__
|
||||
|
||||
#include "../mach-common/ADSP-EDN-core_cdef.h"
|
||||
|
||||
#include "ADSP-EDN-BF542-extended_cdef.h"
|
||||
|
||||
#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
||||
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
|
||||
#define bfin_read_SWRST() bfin_read16(SWRST)
|
||||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
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||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF542_proc__ */
|
||||
17
u-boot/arch/blackfin/include/asm/mach-bf548/BF542_def.h
Normal file
17
u-boot/arch/blackfin/include/asm/mach-bf548/BF542_def.h
Normal file
@@ -0,0 +1,17 @@
|
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-def-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_DEF_ADSP_BF542_proc__
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||||
#define __BFIN_DEF_ADSP_BF542_proc__
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||||
#include "../mach-common/ADSP-EDN-core_def.h"
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||||
|
||||
#include "ADSP-EDN-BF542-extended_def.h"
|
||||
|
||||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF542_proc__ */
|
||||
20
u-boot/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
Normal file
20
u-boot/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
Normal file
@@ -0,0 +1,20 @@
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||||
/* DO NOT EDIT THIS FILE
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||||
* Automatically generated by generate-cdef-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_CDEF_ADSP_BF544_proc__
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#define __BFIN_CDEF_ADSP_BF544_proc__
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|
||||
#include "../mach-common/ADSP-EDN-core_cdef.h"
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||||
|
||||
#include "ADSP-EDN-BF544-extended_cdef.h"
|
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|
||||
#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
||||
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
|
||||
#define bfin_read_SWRST() bfin_read16(SWRST)
|
||||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF544_proc__ */
|
||||
17
u-boot/arch/blackfin/include/asm/mach-bf548/BF544_def.h
Normal file
17
u-boot/arch/blackfin/include/asm/mach-bf548/BF544_def.h
Normal file
@@ -0,0 +1,17 @@
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||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-def-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_DEF_ADSP_BF544_proc__
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#define __BFIN_DEF_ADSP_BF544_proc__
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||||
#include "../mach-common/ADSP-EDN-core_def.h"
|
||||
|
||||
#include "ADSP-EDN-BF544-extended_def.h"
|
||||
|
||||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF544_proc__ */
|
||||
20
u-boot/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
Normal file
20
u-boot/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
Normal file
@@ -0,0 +1,20 @@
|
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-cdef-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_CDEF_ADSP_BF547_proc__
|
||||
#define __BFIN_CDEF_ADSP_BF547_proc__
|
||||
|
||||
#include "../mach-common/ADSP-EDN-core_cdef.h"
|
||||
|
||||
#include "ADSP-EDN-BF547-extended_cdef.h"
|
||||
|
||||
#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
||||
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
|
||||
#define bfin_read_SWRST() bfin_read16(SWRST)
|
||||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF547_proc__ */
|
||||
17
u-boot/arch/blackfin/include/asm/mach-bf548/BF547_def.h
Normal file
17
u-boot/arch/blackfin/include/asm/mach-bf548/BF547_def.h
Normal file
@@ -0,0 +1,17 @@
|
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-def-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_DEF_ADSP_BF547_proc__
|
||||
#define __BFIN_DEF_ADSP_BF547_proc__
|
||||
|
||||
#include "../mach-common/ADSP-EDN-core_def.h"
|
||||
|
||||
#include "ADSP-EDN-BF547-extended_def.h"
|
||||
|
||||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF547_proc__ */
|
||||
20
u-boot/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
Normal file
20
u-boot/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
Normal file
@@ -0,0 +1,20 @@
|
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-cdef-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_CDEF_ADSP_BF548_proc__
|
||||
#define __BFIN_CDEF_ADSP_BF548_proc__
|
||||
|
||||
#include "../mach-common/ADSP-EDN-core_cdef.h"
|
||||
|
||||
#include "ADSP-EDN-BF548-extended_cdef.h"
|
||||
|
||||
#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
||||
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
|
||||
#define bfin_read_SWRST() bfin_read16(SWRST)
|
||||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF548_proc__ */
|
||||
17
u-boot/arch/blackfin/include/asm/mach-bf548/BF548_def.h
Normal file
17
u-boot/arch/blackfin/include/asm/mach-bf548/BF548_def.h
Normal file
@@ -0,0 +1,17 @@
|
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-def-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_DEF_ADSP_BF548_proc__
|
||||
#define __BFIN_DEF_ADSP_BF548_proc__
|
||||
|
||||
#include "../mach-common/ADSP-EDN-core_def.h"
|
||||
|
||||
#include "ADSP-EDN-BF548-extended_def.h"
|
||||
|
||||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF548_proc__ */
|
||||
20
u-boot/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
Normal file
20
u-boot/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
Normal file
@@ -0,0 +1,20 @@
|
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-cdef-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_CDEF_ADSP_BF549_proc__
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||||
#define __BFIN_CDEF_ADSP_BF549_proc__
|
||||
|
||||
#include "../mach-common/ADSP-EDN-core_cdef.h"
|
||||
|
||||
#include "ADSP-EDN-BF549-extended_cdef.h"
|
||||
|
||||
#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
||||
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
|
||||
#define bfin_read_SWRST() bfin_read16(SWRST)
|
||||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF549_proc__ */
|
||||
17
u-boot/arch/blackfin/include/asm/mach-bf548/BF549_def.h
Normal file
17
u-boot/arch/blackfin/include/asm/mach-bf548/BF549_def.h
Normal file
@@ -0,0 +1,17 @@
|
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-def-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_DEF_ADSP_BF549_proc__
|
||||
#define __BFIN_DEF_ADSP_BF549_proc__
|
||||
|
||||
#include "../mach-common/ADSP-EDN-core_def.h"
|
||||
|
||||
#include "ADSP-EDN-BF549-extended_def.h"
|
||||
|
||||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF549_proc__ */
|
||||
303
u-boot/arch/blackfin/include/asm/mach-bf548/anomaly.h
Normal file
303
u-boot/arch/blackfin/include/asm/mach-bf548/anomaly.h
Normal file
@@ -0,0 +1,303 @@
|
||||
/*
|
||||
* DO NOT EDIT THIS FILE
|
||||
* This file is under version control at
|
||||
* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
|
||||
* and can be replaced with that version at any time
|
||||
* DO NOT EDIT THIS FILE
|
||||
*
|
||||
* Copyright 2004-2011 Analog Devices Inc.
|
||||
* Licensed under the ADI BSD license.
|
||||
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
|
||||
*/
|
||||
|
||||
/* This file should be up to date with:
|
||||
* - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
#define _MACH_ANOMALY_H_
|
||||
|
||||
/* We do not support 0.0 or 0.1 silicon - sorry */
|
||||
/* XXX: let u-boot slide
|
||||
#if __SILICON_REVISION__ < 2
|
||||
# error will not work on BF548 silicon version 0.0, or 0.1
|
||||
#endif
|
||||
*/
|
||||
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
|
||||
#define ANOMALY_05000119 (1)
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
|
||||
#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
|
||||
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000245 (1)
|
||||
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
||||
#define ANOMALY_05000265 (1)
|
||||
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
|
||||
#define ANOMALY_05000272 (1)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* FIFO Boot Mode Not Functional */
|
||||
#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
|
||||
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
|
||||
/*
|
||||
* Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
|
||||
* shows that the fix itself does not cover all cases.
|
||||
*/
|
||||
#define ANOMALY_05000353 (1)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
/* External Memory Read Access Hangs Core With PLL Bypass */
|
||||
#define ANOMALY_05000360 (1)
|
||||
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
|
||||
#define ANOMALY_05000365 (1)
|
||||
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
|
||||
#define ANOMALY_05000369 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
|
||||
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
|
||||
#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
|
||||
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000379 (1)
|
||||
/* Lockbox SESR Disallows Certain User Interrupts */
|
||||
#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
|
||||
#define ANOMALY_05000405 (1)
|
||||
/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
|
||||
#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
|
||||
#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
|
||||
#define ANOMALY_05000408 (1)
|
||||
/* Lockbox firmware leaves MDMA0 channel enabled */
|
||||
#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
|
||||
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
|
||||
#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
|
||||
/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
|
||||
#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
|
||||
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
|
||||
#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
|
||||
#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
|
||||
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
|
||||
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
|
||||
/* Software System Reset Corrupts PLL_LOCKCNT Register */
|
||||
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
|
||||
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
|
||||
#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
|
||||
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
|
||||
#define ANOMALY_05000434 (1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
|
||||
#define ANOMALY_05000446 (1)
|
||||
/* UART IrDA Receiver Fails on Extended Bit Pulses */
|
||||
#define ANOMALY_05000447 (1)
|
||||
/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
|
||||
#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
|
||||
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
|
||||
#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
|
||||
/* USB DMA Short Packet Data Corruption */
|
||||
#define ANOMALY_05000450 (1)
|
||||
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
|
||||
#define ANOMALY_05000456 (1)
|
||||
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
|
||||
#define ANOMALY_05000457 (1)
|
||||
/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
|
||||
#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
|
||||
#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
|
||||
/* USB DMA RX Data Corruption */
|
||||
#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
|
||||
/* USB TX DMA Hang */
|
||||
#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
|
||||
/* USB Rx DMA Hang */
|
||||
#define ANOMALY_05000465 (1)
|
||||
/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
|
||||
#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
|
||||
/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
|
||||
#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
|
||||
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
|
||||
#define ANOMALY_05000473 (1)
|
||||
/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
|
||||
#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
|
||||
/* TESTSET Instruction Cannot Be Interrupted */
|
||||
#define ANOMALY_05000477 (1)
|
||||
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
|
||||
#define ANOMALY_05000481 (1)
|
||||
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
|
||||
#define ANOMALY_05000483 (1)
|
||||
/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
|
||||
#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
|
||||
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
|
||||
#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
|
||||
/* PLL May Latch Incorrect Values Coming Out of Reset */
|
||||
#define ANOMALY_05000489 (1)
|
||||
/* SPI Master Boot Can Fail Under Certain Conditions */
|
||||
#define ANOMALY_05000490 (1)
|
||||
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
|
||||
#define ANOMALY_05000491 (1)
|
||||
/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
|
||||
#define ANOMALY_05000494 (1)
|
||||
/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
|
||||
#define ANOMALY_05000498 (1)
|
||||
/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
|
||||
#define ANOMALY_05000500 (1)
|
||||
/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
|
||||
#define ANOMALY_05000501 (1)
|
||||
/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
|
||||
#define ANOMALY_05000502 (1)
|
||||
|
||||
/*
|
||||
* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
* here to show running on older silicon just isn't feasible.
|
||||
*/
|
||||
|
||||
/* False Hardware Error when ISR Context Is Not Restored */
|
||||
#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
|
||||
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
|
||||
#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
|
||||
/* TWI Slave Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
|
||||
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
|
||||
#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
|
||||
/* Incorrect Access of OTP_STATUS During otp_write() Function */
|
||||
#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
|
||||
/* Synchronous Burst Flash Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
|
||||
/* Host DMA Boot Modes Are Not Functional */
|
||||
#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
|
||||
/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
|
||||
#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
|
||||
/* Inadequate Rotary Debounce Logic Duration */
|
||||
#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
|
||||
/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
|
||||
#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
|
||||
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
|
||||
#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
|
||||
/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
|
||||
#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
|
||||
/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
|
||||
#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
|
||||
/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
|
||||
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
|
||||
/* USB Calibration Value Is Not Initialized */
|
||||
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
|
||||
/* USB Calibration Value to use */
|
||||
#define ANOMALY_05000346_value 0x5411
|
||||
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
|
||||
#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
|
||||
/* Data Lost when Core Reads SDH Data FIFO */
|
||||
#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
|
||||
/* PLL Status Register Is Inaccurate */
|
||||
#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
|
||||
/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
|
||||
#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
|
||||
/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
|
||||
#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
|
||||
/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
|
||||
#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
|
||||
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
|
||||
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
|
||||
/* 8-Bit NAND Flash Boot Mode Not Functional */
|
||||
#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
|
||||
/* Boot from OTP Memory Not Functional */
|
||||
#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
|
||||
/* bfrom_SysControl() Firmware Routine Not Functional */
|
||||
#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
|
||||
/* Programmable Preboot Settings Not Functional */
|
||||
#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
|
||||
/* CRC32 Checksum Support Not Functional */
|
||||
#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
|
||||
/* Reset Vector Must Not Be in SDRAM Memory Space */
|
||||
#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
|
||||
/* Changed Meaning of BCODE Field in SYSCR Register */
|
||||
#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
|
||||
/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
|
||||
#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
|
||||
/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
|
||||
/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
|
||||
/* Log Buffer Not Functional */
|
||||
#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
|
||||
/* Hook Routine Not Functional */
|
||||
#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
|
||||
/* Header Indirect Bit Not Functional */
|
||||
#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
|
||||
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
|
||||
#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
|
||||
/* OTP Write Accesses Not Supported */
|
||||
#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
|
||||
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
|
||||
#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000099 (0)
|
||||
#define ANOMALY_05000120 (0)
|
||||
#define ANOMALY_05000125 (0)
|
||||
#define ANOMALY_05000149 (0)
|
||||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000171 (0)
|
||||
#define ANOMALY_05000179 (0)
|
||||
#define ANOMALY_05000182 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000189 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000202 (0)
|
||||
#define ANOMALY_05000215 (0)
|
||||
#define ANOMALY_05000219 (0)
|
||||
#define ANOMALY_05000227 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000231 (0)
|
||||
#define ANOMALY_05000233 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000242 (0)
|
||||
#define ANOMALY_05000244 (0)
|
||||
#define ANOMALY_05000248 (0)
|
||||
#define ANOMALY_05000250 (0)
|
||||
#define ANOMALY_05000254 (0)
|
||||
#define ANOMALY_05000257 (0)
|
||||
#define ANOMALY_05000261 (0)
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000274 (0)
|
||||
#define ANOMALY_05000278 (0)
|
||||
#define ANOMALY_05000283 (0)
|
||||
#define ANOMALY_05000287 (0)
|
||||
#define ANOMALY_05000301 (0)
|
||||
#define ANOMALY_05000305 (0)
|
||||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000315 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000362 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000364 (0)
|
||||
#define ANOMALY_05000380 (0)
|
||||
#define ANOMALY_05000400 (0)
|
||||
#define ANOMALY_05000402 (0)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
#define ANOMALY_05000440 (0)
|
||||
#define ANOMALY_05000475 (0)
|
||||
#define ANOMALY_05000480 (0)
|
||||
|
||||
#endif
|
||||
6
u-boot/arch/blackfin/include/asm/mach-bf548/def_local.h
Normal file
6
u-boot/arch/blackfin/include/asm/mach-bf548/def_local.h
Normal file
@@ -0,0 +1,6 @@
|
||||
#include "gpio.h"
|
||||
#include "mem_map.h"
|
||||
#include "portmux.h"
|
||||
#include "ports.h"
|
||||
|
||||
#define CONFIG_BF54x 1 /* Linux glue */
|
||||
203
u-boot/arch/blackfin/include/asm/mach-bf548/gpio.h
Normal file
203
u-boot/arch/blackfin/include/asm/mach-bf548/gpio.h
Normal file
@@ -0,0 +1,203 @@
|
||||
/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACH_GPIO_H_
|
||||
#define _MACH_GPIO_H_
|
||||
|
||||
#define GPIO_PA0 0
|
||||
#define GPIO_PA1 1
|
||||
#define GPIO_PA2 2
|
||||
#define GPIO_PA3 3
|
||||
#define GPIO_PA4 4
|
||||
#define GPIO_PA5 5
|
||||
#define GPIO_PA6 6
|
||||
#define GPIO_PA7 7
|
||||
#define GPIO_PA8 8
|
||||
#define GPIO_PA9 9
|
||||
#define GPIO_PA10 10
|
||||
#define GPIO_PA11 11
|
||||
#define GPIO_PA12 12
|
||||
#define GPIO_PA13 13
|
||||
#define GPIO_PA14 14
|
||||
#define GPIO_PA15 15
|
||||
#define GPIO_PB0 16
|
||||
#define GPIO_PB1 17
|
||||
#define GPIO_PB2 18
|
||||
#define GPIO_PB3 19
|
||||
#define GPIO_PB4 20
|
||||
#define GPIO_PB5 21
|
||||
#define GPIO_PB6 22
|
||||
#define GPIO_PB7 23
|
||||
#define GPIO_PB8 24
|
||||
#define GPIO_PB9 25
|
||||
#define GPIO_PB10 26
|
||||
#define GPIO_PB11 27
|
||||
#define GPIO_PB12 28
|
||||
#define GPIO_PB13 29
|
||||
#define GPIO_PB14 30
|
||||
#define GPIO_PB15 31 /* N/A */
|
||||
#define GPIO_PC0 32
|
||||
#define GPIO_PC1 33
|
||||
#define GPIO_PC2 34
|
||||
#define GPIO_PC3 35
|
||||
#define GPIO_PC4 36
|
||||
#define GPIO_PC5 37
|
||||
#define GPIO_PC6 38
|
||||
#define GPIO_PC7 39
|
||||
#define GPIO_PC8 40
|
||||
#define GPIO_PC9 41
|
||||
#define GPIO_PC10 42
|
||||
#define GPIO_PC11 43
|
||||
#define GPIO_PC12 44
|
||||
#define GPIO_PC13 45
|
||||
#define GPIO_PC14 46 /* N/A */
|
||||
#define GPIO_PC15 47 /* N/A */
|
||||
#define GPIO_PD0 48
|
||||
#define GPIO_PD1 49
|
||||
#define GPIO_PD2 50
|
||||
#define GPIO_PD3 51
|
||||
#define GPIO_PD4 52
|
||||
#define GPIO_PD5 53
|
||||
#define GPIO_PD6 54
|
||||
#define GPIO_PD7 55
|
||||
#define GPIO_PD8 56
|
||||
#define GPIO_PD9 57
|
||||
#define GPIO_PD10 58
|
||||
#define GPIO_PD11 59
|
||||
#define GPIO_PD12 60
|
||||
#define GPIO_PD13 61
|
||||
#define GPIO_PD14 62
|
||||
#define GPIO_PD15 63
|
||||
#define GPIO_PE0 64
|
||||
#define GPIO_PE1 65
|
||||
#define GPIO_PE2 66
|
||||
#define GPIO_PE3 67
|
||||
#define GPIO_PE4 68
|
||||
#define GPIO_PE5 69
|
||||
#define GPIO_PE6 70
|
||||
#define GPIO_PE7 71
|
||||
#define GPIO_PE8 72
|
||||
#define GPIO_PE9 73
|
||||
#define GPIO_PE10 74
|
||||
#define GPIO_PE11 75
|
||||
#define GPIO_PE12 76
|
||||
#define GPIO_PE13 77
|
||||
#define GPIO_PE14 78
|
||||
#define GPIO_PE15 79
|
||||
#define GPIO_PF0 80
|
||||
#define GPIO_PF1 81
|
||||
#define GPIO_PF2 82
|
||||
#define GPIO_PF3 83
|
||||
#define GPIO_PF4 84
|
||||
#define GPIO_PF5 85
|
||||
#define GPIO_PF6 86
|
||||
#define GPIO_PF7 87
|
||||
#define GPIO_PF8 88
|
||||
#define GPIO_PF9 89
|
||||
#define GPIO_PF10 90
|
||||
#define GPIO_PF11 91
|
||||
#define GPIO_PF12 92
|
||||
#define GPIO_PF13 93
|
||||
#define GPIO_PF14 94
|
||||
#define GPIO_PF15 95
|
||||
#define GPIO_PG0 96
|
||||
#define GPIO_PG1 97
|
||||
#define GPIO_PG2 98
|
||||
#define GPIO_PG3 99
|
||||
#define GPIO_PG4 100
|
||||
#define GPIO_PG5 101
|
||||
#define GPIO_PG6 102
|
||||
#define GPIO_PG7 103
|
||||
#define GPIO_PG8 104
|
||||
#define GPIO_PG9 105
|
||||
#define GPIO_PG10 106
|
||||
#define GPIO_PG11 107
|
||||
#define GPIO_PG12 108
|
||||
#define GPIO_PG13 109
|
||||
#define GPIO_PG14 110
|
||||
#define GPIO_PG15 111
|
||||
#define GPIO_PH0 112
|
||||
#define GPIO_PH1 113
|
||||
#define GPIO_PH2 114
|
||||
#define GPIO_PH3 115
|
||||
#define GPIO_PH4 116
|
||||
#define GPIO_PH5 117
|
||||
#define GPIO_PH6 118
|
||||
#define GPIO_PH7 119
|
||||
#define GPIO_PH8 120
|
||||
#define GPIO_PH9 121
|
||||
#define GPIO_PH10 122
|
||||
#define GPIO_PH11 123
|
||||
#define GPIO_PH12 124
|
||||
#define GPIO_PH13 125
|
||||
#define GPIO_PH14 126 /* N/A */
|
||||
#define GPIO_PH15 127 /* N/A */
|
||||
#define GPIO_PI0 128
|
||||
#define GPIO_PI1 129
|
||||
#define GPIO_PI2 130
|
||||
#define GPIO_PI3 131
|
||||
#define GPIO_PI4 132
|
||||
#define GPIO_PI5 133
|
||||
#define GPIO_PI6 134
|
||||
#define GPIO_PI7 135
|
||||
#define GPIO_PI8 136
|
||||
#define GPIO_PI9 137
|
||||
#define GPIO_PI10 138
|
||||
#define GPIO_PI11 139
|
||||
#define GPIO_PI12 140
|
||||
#define GPIO_PI13 141
|
||||
#define GPIO_PI14 142
|
||||
#define GPIO_PI15 143
|
||||
#define GPIO_PJ0 144
|
||||
#define GPIO_PJ1 145
|
||||
#define GPIO_PJ2 146
|
||||
#define GPIO_PJ3 147
|
||||
#define GPIO_PJ4 148
|
||||
#define GPIO_PJ5 149
|
||||
#define GPIO_PJ6 150
|
||||
#define GPIO_PJ7 151
|
||||
#define GPIO_PJ8 152
|
||||
#define GPIO_PJ9 153
|
||||
#define GPIO_PJ10 154
|
||||
#define GPIO_PJ11 155
|
||||
#define GPIO_PJ12 156
|
||||
#define GPIO_PJ13 157
|
||||
#define GPIO_PJ14 158 /* N/A */
|
||||
#define GPIO_PJ15 159 /* N/A */
|
||||
|
||||
#define MAX_BLACKFIN_GPIOS 160
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct gpio_port_t {
|
||||
unsigned short port_fer;
|
||||
unsigned short dummy1;
|
||||
unsigned short data;
|
||||
unsigned short dummy2;
|
||||
unsigned short data_set;
|
||||
unsigned short dummy3;
|
||||
unsigned short data_clear;
|
||||
unsigned short dummy4;
|
||||
unsigned short dir_set;
|
||||
unsigned short dummy5;
|
||||
unsigned short dir_clear;
|
||||
unsigned short dummy6;
|
||||
unsigned short inen;
|
||||
unsigned short dummy7;
|
||||
unsigned int port_mux;
|
||||
};
|
||||
|
||||
struct gpio_port_s {
|
||||
unsigned short fer;
|
||||
unsigned short data;
|
||||
unsigned short dir;
|
||||
unsigned short inen;
|
||||
unsigned int mux;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _MACH_GPIO_H_ */
|
||||
21
u-boot/arch/blackfin/include/asm/mach-bf548/mem_map.h
Normal file
21
u-boot/arch/blackfin/include/asm/mach-bf548/mem_map.h
Normal file
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Common Blackfin memory map
|
||||
*
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __BF54X_MEM_MAP_H__
|
||||
#define __BF54X_MEM_MAP_H__
|
||||
|
||||
#define L1_DATA_A_SRAM (0xFF800000)
|
||||
#define L1_DATA_A_SRAM_SIZE (0x4000)
|
||||
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
|
||||
#define L1_DATA_B_SRAM (0xFF900000)
|
||||
#define L1_DATA_B_SRAM_SIZE (0x4000)
|
||||
#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
|
||||
#define L1_INST_SRAM (0xFFA00000)
|
||||
#define L1_INST_SRAM_SIZE (0xC000)
|
||||
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
|
||||
|
||||
#endif
|
||||
320
u-boot/arch/blackfin/include/asm/mach-bf548/portmux.h
Normal file
320
u-boot/arch/blackfin/include/asm/mach-bf548/portmux.h
Normal file
@@ -0,0 +1,320 @@
|
||||
/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_PORTMUX_H_
|
||||
#define _MACH_PORTMUX_H_
|
||||
|
||||
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
|
||||
|
||||
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
|
||||
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
|
||||
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
|
||||
#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
|
||||
#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
|
||||
#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
|
||||
#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
|
||||
#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
|
||||
#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
|
||||
#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
|
||||
#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
|
||||
#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
|
||||
#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
|
||||
#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
|
||||
#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
|
||||
#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
|
||||
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
|
||||
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
|
||||
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
|
||||
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
|
||||
|
||||
#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
|
||||
#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
|
||||
#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
|
||||
#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
|
||||
#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
|
||||
#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
|
||||
#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
|
||||
#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
|
||||
#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
|
||||
#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
|
||||
#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
|
||||
#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
|
||||
#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
|
||||
#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
|
||||
#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
|
||||
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
|
||||
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
|
||||
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
|
||||
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
|
||||
|
||||
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
|
||||
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
|
||||
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
|
||||
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
|
||||
#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
|
||||
#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
|
||||
#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
|
||||
#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
|
||||
#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
|
||||
#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
|
||||
#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
|
||||
#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
|
||||
|
||||
#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
|
||||
#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
|
||||
#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
|
||||
#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
|
||||
#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
|
||||
#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
|
||||
#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
|
||||
#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
|
||||
#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
|
||||
#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
|
||||
#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
|
||||
#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
|
||||
#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
|
||||
#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
|
||||
#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
|
||||
#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
|
||||
|
||||
#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
|
||||
#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
|
||||
#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
|
||||
#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
|
||||
#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
|
||||
#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
|
||||
#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
|
||||
#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
|
||||
#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
|
||||
#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
|
||||
#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
|
||||
#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
|
||||
#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
|
||||
#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
|
||||
#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
|
||||
#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
|
||||
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
|
||||
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
|
||||
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
|
||||
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
|
||||
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
|
||||
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
|
||||
#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
|
||||
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
|
||||
#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
|
||||
#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
|
||||
#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
|
||||
#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
|
||||
#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
|
||||
#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
|
||||
#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
|
||||
#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
|
||||
#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
|
||||
#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
|
||||
#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
|
||||
#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
|
||||
#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
|
||||
#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
|
||||
#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
|
||||
#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
|
||||
#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
|
||||
#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
|
||||
#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
|
||||
#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
|
||||
#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
|
||||
#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
|
||||
|
||||
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
|
||||
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
|
||||
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
|
||||
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
|
||||
#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
|
||||
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
|
||||
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
|
||||
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
|
||||
#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
|
||||
#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
|
||||
#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
|
||||
#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
|
||||
#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
|
||||
#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
|
||||
#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
|
||||
#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
|
||||
#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
|
||||
#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
|
||||
#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
|
||||
#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
|
||||
#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
|
||||
#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
|
||||
#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
|
||||
|
||||
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
|
||||
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
|
||||
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
|
||||
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
|
||||
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
|
||||
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
|
||||
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
|
||||
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
|
||||
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
|
||||
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
|
||||
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
|
||||
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
|
||||
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
|
||||
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
|
||||
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
|
||||
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
|
||||
|
||||
#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
|
||||
# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
|
||||
# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
|
||||
# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
|
||||
# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
|
||||
# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
|
||||
# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
|
||||
# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
|
||||
# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
|
||||
# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
|
||||
# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
|
||||
# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
|
||||
# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
|
||||
# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
|
||||
# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
|
||||
# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
|
||||
# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
|
||||
#else
|
||||
# define P_ATAPI_D0A (P_DONTCARE)
|
||||
# define P_ATAPI_D1A (P_DONTCARE)
|
||||
# define P_ATAPI_D2A (P_DONTCARE)
|
||||
# define P_ATAPI_D3A (P_DONTCARE)
|
||||
# define P_ATAPI_D4A (P_DONTCARE)
|
||||
# define P_ATAPI_D5A (P_DONTCARE)
|
||||
# define P_ATAPI_D6A (P_DONTCARE)
|
||||
# define P_ATAPI_D7A (P_DONTCARE)
|
||||
# define P_ATAPI_D8A (P_DONTCARE)
|
||||
# define P_ATAPI_D9A (P_DONTCARE)
|
||||
# define P_ATAPI_D10A (P_DONTCARE)
|
||||
# define P_ATAPI_D11A (P_DONTCARE)
|
||||
# define P_ATAPI_D12A (P_DONTCARE)
|
||||
# define P_ATAPI_D13A (P_DONTCARE)
|
||||
# define P_ATAPI_D14A (P_DONTCARE)
|
||||
# define P_ATAPI_D15A (P_DONTCARE)
|
||||
#endif
|
||||
|
||||
#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
|
||||
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
|
||||
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
|
||||
#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
|
||||
#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
|
||||
#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
|
||||
#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
|
||||
#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
|
||||
#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
|
||||
#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
|
||||
#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
|
||||
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
|
||||
#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
|
||||
#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
|
||||
#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
|
||||
#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
|
||||
#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
|
||||
# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
|
||||
# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
|
||||
# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
|
||||
#else
|
||||
# define P_ATAPI_A0A (P_DONTCARE)
|
||||
# define P_ATAPI_A1A (P_DONTCARE)
|
||||
# define P_ATAPI_A2A (P_DONTCARE)
|
||||
#endif
|
||||
#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
|
||||
#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
|
||||
#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
|
||||
#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
|
||||
#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
|
||||
#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
|
||||
#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
|
||||
#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
|
||||
|
||||
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
|
||||
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
|
||||
#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
|
||||
#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
|
||||
#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
|
||||
#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
|
||||
#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
|
||||
#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
|
||||
#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
|
||||
#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
|
||||
#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
|
||||
#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
|
||||
#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
|
||||
#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
|
||||
#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
|
||||
#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
|
||||
#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
|
||||
#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
|
||||
#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
|
||||
#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
|
||||
#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
|
||||
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
|
||||
#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
|
||||
#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
|
||||
|
||||
#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
|
||||
#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
|
||||
#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
|
||||
#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
|
||||
#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
|
||||
#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
|
||||
#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
|
||||
#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
|
||||
#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
|
||||
#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
|
||||
#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
|
||||
#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
|
||||
#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
|
||||
#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
|
||||
#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
|
||||
#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
|
||||
#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
|
||||
|
||||
#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
|
||||
#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
|
||||
#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
|
||||
#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
|
||||
#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
|
||||
#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
|
||||
#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
|
||||
#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
|
||||
#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
|
||||
#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
|
||||
#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
|
||||
#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
|
||||
#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
|
||||
#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
|
||||
|
||||
|
||||
#define P_NAND_D0 (P_DONTCARE)
|
||||
#define P_NAND_D1 (P_DONTCARE)
|
||||
#define P_NAND_D2 (P_DONTCARE)
|
||||
#define P_NAND_D3 (P_DONTCARE)
|
||||
#define P_NAND_D4 (P_DONTCARE)
|
||||
#define P_NAND_D5 (P_DONTCARE)
|
||||
#define P_NAND_D6 (P_DONTCARE)
|
||||
#define P_NAND_D7 (P_DONTCARE)
|
||||
#define P_NAND_WE (P_DONTCARE)
|
||||
#define P_NAND_RE (P_DONTCARE)
|
||||
#define P_NAND_CLE (P_DONTCARE)
|
||||
#define P_NAND_ALE (P_DONTCARE)
|
||||
|
||||
#endif /* _MACH_PORTMUX_H_ */
|
||||
106
u-boot/arch/blackfin/include/asm/mach-bf548/ports.h
Normal file
106
u-boot/arch/blackfin/include/asm/mach-bf548/ports.h
Normal file
@@ -0,0 +1,106 @@
|
||||
/*
|
||||
* Port Masks
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_PERIPHERAL_PORT__
|
||||
#define __BFIN_PERIPHERAL_PORT__
|
||||
|
||||
/* PORTx_MUX Masks */
|
||||
#define PORT_x_MUX_0_MASK 0x00000003
|
||||
#define PORT_x_MUX_1_MASK 0x0000000C
|
||||
#define PORT_x_MUX_2_MASK 0x00000030
|
||||
#define PORT_x_MUX_3_MASK 0x000000C0
|
||||
#define PORT_x_MUX_4_MASK 0x00000300
|
||||
#define PORT_x_MUX_5_MASK 0x00000C00
|
||||
#define PORT_x_MUX_6_MASK 0x00003000
|
||||
#define PORT_x_MUX_7_MASK 0x0000C000
|
||||
#define PORT_x_MUX_8_MASK 0x00030000
|
||||
#define PORT_x_MUX_9_MASK 0x000C0000
|
||||
#define PORT_x_MUX_10_MASK 0x00300000
|
||||
#define PORT_x_MUX_11_MASK 0x00C00000
|
||||
#define PORT_x_MUX_12_MASK 0x03000000
|
||||
#define PORT_x_MUX_13_MASK 0x0C000000
|
||||
#define PORT_x_MUX_14_MASK 0x30000000
|
||||
#define PORT_x_MUX_15_MASK 0xC0000000
|
||||
|
||||
#define PORT_x_MUX_FUNC_1 (0x0)
|
||||
#define PORT_x_MUX_FUNC_2 (0x1)
|
||||
#define PORT_x_MUX_FUNC_3 (0x2)
|
||||
#define PORT_x_MUX_FUNC_4 (0x3)
|
||||
#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0)
|
||||
#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0)
|
||||
#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0)
|
||||
#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0)
|
||||
#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2)
|
||||
#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2)
|
||||
#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2)
|
||||
#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2)
|
||||
#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4)
|
||||
#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4)
|
||||
#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4)
|
||||
#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4)
|
||||
#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6)
|
||||
#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6)
|
||||
#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6)
|
||||
#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6)
|
||||
#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8)
|
||||
#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8)
|
||||
#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8)
|
||||
#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8)
|
||||
#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10)
|
||||
#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10)
|
||||
#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10)
|
||||
#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10)
|
||||
#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12)
|
||||
#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12)
|
||||
#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12)
|
||||
#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12)
|
||||
#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
|
||||
#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
|
||||
#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
|
||||
#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
|
||||
#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16)
|
||||
#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16)
|
||||
#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16)
|
||||
#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16)
|
||||
#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18)
|
||||
#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18)
|
||||
#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18)
|
||||
#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18)
|
||||
#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20)
|
||||
#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20)
|
||||
#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20)
|
||||
#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20)
|
||||
#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22)
|
||||
#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22)
|
||||
#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22)
|
||||
#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22)
|
||||
#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24)
|
||||
#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24)
|
||||
#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24)
|
||||
#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24)
|
||||
#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26)
|
||||
#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26)
|
||||
#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26)
|
||||
#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26)
|
||||
#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28)
|
||||
#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28)
|
||||
#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28)
|
||||
#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28)
|
||||
#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30)
|
||||
#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30)
|
||||
#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30)
|
||||
#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30)
|
||||
|
||||
#include "../mach-common/bits/ports-a.h"
|
||||
#include "../mach-common/bits/ports-b.h"
|
||||
#include "../mach-common/bits/ports-c.h"
|
||||
#include "../mach-common/bits/ports-d.h"
|
||||
#include "../mach-common/bits/ports-e.h"
|
||||
#include "../mach-common/bits/ports-f.h"
|
||||
#include "../mach-common/bits/ports-g.h"
|
||||
#include "../mach-common/bits/ports-h.h"
|
||||
#include "../mach-common/bits/ports-i.h"
|
||||
#include "../mach-common/bits/ports-j.h"
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user