avionic design with actual uboot and tooling
submodule of avionic design uboot bootloader and with included tools to get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
1624
u-boot/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h
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1624
u-boot/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h
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File diff suppressed because it is too large
Load Diff
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u-boot/arch/blackfin/include/asm/mach-bf537/BF534_def.h
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u-boot/arch/blackfin/include/asm/mach-bf537/BF534_def.h
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@@ -0,0 +1,831 @@
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/* DO NOT EDIT THIS FILE
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* Automatically generated by generate-def-headers.xsl
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* DO NOT EDIT THIS FILE
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*/
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#ifndef __BFIN_DEF_ADSP_BF534_proc__
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#define __BFIN_DEF_ADSP_BF534_proc__
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#include "../mach-common/ADSP-EDN-core_def.h"
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#define PLL_CTL 0xFFC00000 /* PLL Control Register */
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#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
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#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
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#define PLL_STAT 0xFFC0000C /* PLL Status Register */
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#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
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#define SWRST 0xFFC00100 /* Software Reset Register */
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#define SYSCR 0xFFC00104 /* System Configuration Register */
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#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
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#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
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#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
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#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
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#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
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#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
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#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
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#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
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#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
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#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
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#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
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#define RTC_STAT 0xFFC00300 /* RTC Status Register */
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#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
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#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
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#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
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#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
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#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */
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#define UART0_THR 0xFFC00400 /* Transmit Holding register */
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#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
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#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
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#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
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#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
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#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
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#define UART0_LCR 0xFFC0040C /* Line Control Register */
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#define UART0_MCR 0xFFC00410 /* Modem Control Register */
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#define UART0_LSR 0xFFC00414 /* Line Status Register */
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#define UART0_MSR 0xFFC00418 /* Modem Status Register */
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#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
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#define UART0_GCTL 0xFFC00424 /* Global Control Register */
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#define SPI_CTL 0xFFC00500 /* SPI Control Register */
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#define SPI_FLG 0xFFC00504 /* SPI Flag register */
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#define SPI_STAT 0xFFC00508 /* SPI Status register */
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#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
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#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
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#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
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#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
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#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
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#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
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#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
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#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
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#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
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#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
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#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
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#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
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#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
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#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
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#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
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#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
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#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
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#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
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#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
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#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
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#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
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#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
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#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
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#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
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#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
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#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
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#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
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#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
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#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
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#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
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#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
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#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */
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#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
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#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
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#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
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#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
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#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
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#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
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#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
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#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
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#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
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#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
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#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
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#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
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#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
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#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
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#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
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#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
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#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
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#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
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#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
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#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
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#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
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#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
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#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
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#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
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#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
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#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
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#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
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#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
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#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
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#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
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#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
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#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
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#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
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#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
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#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
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#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
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#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
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#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
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#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
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#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
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#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
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#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
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#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
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#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
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#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
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#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
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#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
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#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
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#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
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#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
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#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
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#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
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#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
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#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
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#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
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#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
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#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
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#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
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#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
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#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
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#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
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#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
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#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
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#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
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#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
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#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
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#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
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#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
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#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
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#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
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#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
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#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
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#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
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#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
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#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
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#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
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#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
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#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
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#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
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#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
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#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
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#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
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#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
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#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
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#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
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#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
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#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
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#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
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#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
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#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
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#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
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#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
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#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
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#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
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#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
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#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
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#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
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#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
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#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
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#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
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#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
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#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
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#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
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#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
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#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
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#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
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#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
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#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
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#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
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#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
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#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
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#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
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#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
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#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
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#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
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#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
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#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
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#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
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#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
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#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
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#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
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#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
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#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
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#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
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#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
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#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
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#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
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#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
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#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
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#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
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#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
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#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
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#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
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#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
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#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
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#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
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#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
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#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
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#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
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#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
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#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
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#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
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#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
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#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
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#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
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#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
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#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
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#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
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#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
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#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
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#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
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#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
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#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
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#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
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#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
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#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
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#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
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#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
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#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
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#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
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#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
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#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
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#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
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#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
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#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
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#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
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#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
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#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
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#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
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#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
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#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
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#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
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#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
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#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
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#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
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#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
|
||||
#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
|
||||
#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
|
||||
#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
|
||||
#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
|
||||
#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
|
||||
#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
|
||||
#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
|
||||
#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
|
||||
#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
|
||||
#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
|
||||
#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
|
||||
#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
|
||||
#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
|
||||
#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
|
||||
#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
|
||||
#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
|
||||
#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
|
||||
#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
|
||||
#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
|
||||
#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
|
||||
#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
|
||||
#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
|
||||
#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
|
||||
#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
|
||||
#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
|
||||
#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
|
||||
#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
|
||||
#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
|
||||
#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
|
||||
#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
|
||||
#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
|
||||
#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
|
||||
#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
|
||||
#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
|
||||
#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
|
||||
#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
|
||||
#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
|
||||
#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
|
||||
#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
|
||||
#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
|
||||
#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
|
||||
#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
|
||||
#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
|
||||
#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
|
||||
#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
|
||||
#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
|
||||
#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
|
||||
#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
|
||||
#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
|
||||
#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
|
||||
#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
|
||||
#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
|
||||
#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
|
||||
#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
|
||||
#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
|
||||
#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
|
||||
#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
|
||||
#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
|
||||
#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
|
||||
#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
|
||||
#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
|
||||
#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
|
||||
#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
|
||||
#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
|
||||
#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
|
||||
#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
|
||||
#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
|
||||
#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
|
||||
#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
|
||||
#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
|
||||
#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
|
||||
#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
|
||||
#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
|
||||
#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
|
||||
#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
|
||||
#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
|
||||
#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
|
||||
#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
|
||||
#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
|
||||
#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
|
||||
#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
|
||||
#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
|
||||
#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
|
||||
#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
|
||||
#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
|
||||
#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
|
||||
#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
|
||||
#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
|
||||
#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
|
||||
#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
|
||||
#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
|
||||
#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
|
||||
#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
|
||||
#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
|
||||
#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
|
||||
#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
|
||||
#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
|
||||
#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
|
||||
#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
|
||||
#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
|
||||
#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
|
||||
#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
|
||||
#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
|
||||
#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
|
||||
#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
|
||||
#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
|
||||
#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
|
||||
#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
|
||||
#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
|
||||
#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
|
||||
#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
|
||||
#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
|
||||
#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
|
||||
#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
|
||||
#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
|
||||
#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
|
||||
#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
|
||||
#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
|
||||
#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
|
||||
#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
|
||||
#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
|
||||
#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
|
||||
#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
|
||||
#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
|
||||
#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
|
||||
#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
|
||||
#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
|
||||
#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
|
||||
#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
|
||||
#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
|
||||
#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
|
||||
#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
|
||||
#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
|
||||
#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
|
||||
#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
|
||||
#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
|
||||
#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
|
||||
#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
|
||||
#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
|
||||
#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
|
||||
#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
|
||||
#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
|
||||
#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
|
||||
#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
|
||||
#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
|
||||
#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
|
||||
#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
|
||||
#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
|
||||
#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
|
||||
#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
|
||||
#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
|
||||
#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
|
||||
#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
|
||||
#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
|
||||
#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
|
||||
#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
|
||||
#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
|
||||
#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
|
||||
#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
|
||||
#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
|
||||
#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
|
||||
#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
|
||||
#define UART1_THR 0xFFC02000 /* Transmit Holding register */
|
||||
#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
|
||||
#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
|
||||
#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
|
||||
#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
|
||||
#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
|
||||
#define UART1_LCR 0xFFC0200C /* Line Control Register */
|
||||
#define UART1_MCR 0xFFC02010 /* Modem Control Register */
|
||||
#define UART1_LSR 0xFFC02014 /* Line Status Register */
|
||||
#define UART1_MSR 0xFFC02018 /* Modem Status Register */
|
||||
#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
|
||||
#define UART1_GCTL 0xFFC02024 /* Global Control Register */
|
||||
#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
|
||||
#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
|
||||
#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
|
||||
#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
|
||||
#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
|
||||
#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
|
||||
#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
|
||||
#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
|
||||
#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
|
||||
#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
|
||||
#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
|
||||
#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
|
||||
#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
|
||||
#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
|
||||
#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
|
||||
#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
|
||||
#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
|
||||
#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
|
||||
#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
|
||||
#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
|
||||
#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
|
||||
#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
|
||||
#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
|
||||
#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
|
||||
#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
|
||||
#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
|
||||
#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
|
||||
#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
|
||||
#define CAN_DEBUG 0xFFC02A88 /* Config register */
|
||||
#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
|
||||
#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
|
||||
#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
|
||||
#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
|
||||
#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
|
||||
#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
|
||||
#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
|
||||
#define CAN_VERSION 0xFFC02AA8 /* Version Code Register */
|
||||
#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
|
||||
#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
|
||||
#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
|
||||
#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
|
||||
#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
|
||||
#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
|
||||
#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
|
||||
#define CAN_VERSION2 0xFFC02AD4 /* Version Code Register 2 */
|
||||
#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
|
||||
#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
|
||||
#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
|
||||
#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
|
||||
#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
|
||||
#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
|
||||
#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
|
||||
#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
|
||||
#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
|
||||
#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
|
||||
#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
|
||||
#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
|
||||
#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
|
||||
#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
|
||||
#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
|
||||
#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
|
||||
#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
|
||||
#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
|
||||
#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
|
||||
#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
|
||||
#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
|
||||
#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
|
||||
#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
|
||||
#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
|
||||
#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
|
||||
#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
|
||||
#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
|
||||
#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
|
||||
#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
|
||||
#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
|
||||
#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
|
||||
#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
|
||||
#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
|
||||
#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
|
||||
#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
|
||||
#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
|
||||
#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
|
||||
#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
|
||||
#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
|
||||
#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
|
||||
#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
|
||||
#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
|
||||
#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
|
||||
#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
|
||||
#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
|
||||
#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
|
||||
#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
|
||||
#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
|
||||
#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
|
||||
#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
|
||||
#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
|
||||
#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
|
||||
#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
|
||||
#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
|
||||
#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
|
||||
#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
|
||||
#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
|
||||
#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
|
||||
#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
|
||||
#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
|
||||
#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
|
||||
#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
|
||||
#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
|
||||
#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
|
||||
#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
|
||||
#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
|
||||
#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
|
||||
#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
|
||||
#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
|
||||
#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
|
||||
#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
|
||||
#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
|
||||
#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
|
||||
#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
|
||||
#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
|
||||
#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
|
||||
#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
|
||||
#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
|
||||
#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
|
||||
#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
|
||||
#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
|
||||
#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
|
||||
#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
|
||||
#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
|
||||
#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
|
||||
#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
|
||||
#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
|
||||
#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
|
||||
#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
|
||||
#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
|
||||
#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
|
||||
#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
|
||||
#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
|
||||
#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
|
||||
#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
|
||||
#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
|
||||
#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
|
||||
#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
|
||||
#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
|
||||
#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
|
||||
#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
|
||||
#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
|
||||
#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
|
||||
#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
|
||||
#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
|
||||
#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
|
||||
#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
|
||||
#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
|
||||
#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
|
||||
#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
|
||||
#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
|
||||
#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
|
||||
#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
|
||||
#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
|
||||
#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
|
||||
#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
|
||||
#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
|
||||
#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
|
||||
#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
|
||||
#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
|
||||
#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
|
||||
#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
|
||||
#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
|
||||
#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
|
||||
#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
|
||||
#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
|
||||
#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
|
||||
#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
|
||||
#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
|
||||
#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
|
||||
#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
|
||||
#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
|
||||
#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
|
||||
#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
|
||||
#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
|
||||
#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
|
||||
#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
|
||||
#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
|
||||
#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
|
||||
#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
|
||||
#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
|
||||
#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
|
||||
#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
|
||||
#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
|
||||
#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
|
||||
#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
|
||||
#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
|
||||
#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
|
||||
#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
|
||||
#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
|
||||
#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
|
||||
#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
|
||||
#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
|
||||
#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
|
||||
#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
|
||||
#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
|
||||
#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
|
||||
#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
|
||||
#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
|
||||
#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
|
||||
#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
|
||||
#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
|
||||
#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
|
||||
#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
|
||||
#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
|
||||
#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
|
||||
#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
|
||||
#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
|
||||
#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
|
||||
#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
|
||||
#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
|
||||
#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
|
||||
#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
|
||||
#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
|
||||
#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
|
||||
#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
|
||||
#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
|
||||
#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
|
||||
#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
|
||||
#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
|
||||
#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
|
||||
#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
|
||||
#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
|
||||
#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
|
||||
#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
|
||||
#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
|
||||
#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
|
||||
#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
|
||||
#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
|
||||
#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
|
||||
#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
|
||||
#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
|
||||
#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
|
||||
#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
|
||||
#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
|
||||
#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
|
||||
#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
|
||||
#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
|
||||
#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
|
||||
#define PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
|
||||
#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
|
||||
#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
|
||||
#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
|
||||
#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
|
||||
#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
|
||||
#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
|
||||
#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
|
||||
#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
|
||||
#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
|
||||
#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
|
||||
#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
|
||||
#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
|
||||
#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
|
||||
#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
|
||||
#define CHIPID 0xFFC00014
|
||||
#define DMA_TC_CNT 0xFFC00B0C
|
||||
#define DMA_TC_PER 0xFFC00B10
|
||||
|
||||
#if !defined(__ADSPBF536__)
|
||||
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
|
||||
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
|
||||
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
|
||||
#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
|
||||
#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
|
||||
#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
|
||||
#endif
|
||||
#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
|
||||
#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
|
||||
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF534_proc__ */
|
||||
170
u-boot/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
Normal file
170
u-boot/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
Normal file
@@ -0,0 +1,170 @@
|
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-cdef-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_CDEF_ADSP_BF536_proc__
|
||||
#define __BFIN_CDEF_ADSP_BF536_proc__
|
||||
|
||||
#include "BF534_cdef.h"
|
||||
|
||||
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
|
||||
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
|
||||
#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
|
||||
#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
|
||||
#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
|
||||
#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
|
||||
#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
|
||||
#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
|
||||
#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
|
||||
#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
|
||||
#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
|
||||
#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
|
||||
#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
|
||||
#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
|
||||
#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
|
||||
#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
|
||||
#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
|
||||
#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
|
||||
#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
|
||||
#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
|
||||
#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
|
||||
#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
|
||||
#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
|
||||
#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
|
||||
#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
|
||||
#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
|
||||
#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
|
||||
#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
|
||||
#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
|
||||
#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
|
||||
#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
|
||||
#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
|
||||
#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
|
||||
#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
|
||||
#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
|
||||
#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
|
||||
#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
|
||||
#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
|
||||
#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
|
||||
#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
|
||||
#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
|
||||
#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
|
||||
#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
|
||||
#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
|
||||
#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
|
||||
#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
|
||||
#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
|
||||
#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
|
||||
#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
|
||||
#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
|
||||
#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
|
||||
#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
|
||||
#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
|
||||
#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
|
||||
#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
|
||||
#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
|
||||
#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
|
||||
#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
|
||||
#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
|
||||
#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
|
||||
#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
|
||||
#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
|
||||
#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
|
||||
#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
|
||||
#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
|
||||
#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
|
||||
#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
|
||||
#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
|
||||
#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
|
||||
#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
|
||||
#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
|
||||
#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
|
||||
#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
|
||||
#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
|
||||
#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
|
||||
#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
|
||||
#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
|
||||
#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
|
||||
#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
|
||||
#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
|
||||
#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
|
||||
#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
|
||||
#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
|
||||
#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
|
||||
#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
|
||||
#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
|
||||
#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
|
||||
#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
|
||||
#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
|
||||
#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
|
||||
#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
|
||||
#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
|
||||
#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
|
||||
#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
|
||||
#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
|
||||
#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
|
||||
#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
|
||||
#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
|
||||
#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
|
||||
#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
|
||||
#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
|
||||
#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
|
||||
#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
|
||||
#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
|
||||
#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
|
||||
#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
|
||||
#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
|
||||
#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
|
||||
#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
|
||||
#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
|
||||
#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
|
||||
#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
|
||||
#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
|
||||
#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
|
||||
#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
|
||||
#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
|
||||
#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
|
||||
#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
|
||||
#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
|
||||
#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
|
||||
#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
|
||||
#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
|
||||
#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
|
||||
#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
|
||||
#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
|
||||
#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
|
||||
#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
|
||||
#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
|
||||
#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
|
||||
#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
|
||||
#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
|
||||
#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
|
||||
#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
|
||||
#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
|
||||
#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
|
||||
#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
|
||||
#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
|
||||
#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
|
||||
#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
|
||||
#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
|
||||
#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
|
||||
#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
|
||||
#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
|
||||
#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
|
||||
#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
|
||||
#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
|
||||
#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
|
||||
#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
|
||||
#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
|
||||
#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF536_proc__ */
|
||||
91
u-boot/arch/blackfin/include/asm/mach-bf537/BF536_def.h
Normal file
91
u-boot/arch/blackfin/include/asm/mach-bf537/BF536_def.h
Normal file
@@ -0,0 +1,91 @@
|
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-def-headers.xsl
|
||||
* DO NOT EDIT THIS FILE
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_DEF_ADSP_BF536_proc__
|
||||
#define __BFIN_DEF_ADSP_BF536_proc__
|
||||
|
||||
#include "BF534_def.h"
|
||||
|
||||
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
|
||||
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
|
||||
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
|
||||
#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
|
||||
#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
|
||||
#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
|
||||
#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
|
||||
#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
|
||||
#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
|
||||
#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
|
||||
#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
|
||||
#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
|
||||
#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
|
||||
#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
|
||||
#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
|
||||
#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
|
||||
#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
|
||||
#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
|
||||
#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
|
||||
#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
|
||||
#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
|
||||
#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
|
||||
#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
|
||||
#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
|
||||
#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
|
||||
#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
|
||||
#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
|
||||
#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
|
||||
#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
|
||||
#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
|
||||
#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
|
||||
#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
|
||||
#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
|
||||
#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
|
||||
#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
|
||||
#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
|
||||
#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
|
||||
#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
|
||||
#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
|
||||
#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
|
||||
#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
|
||||
#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
|
||||
#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
|
||||
#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
|
||||
#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
|
||||
#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
|
||||
#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
|
||||
#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
|
||||
#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
|
||||
#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
|
||||
#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
|
||||
#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
|
||||
#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
|
||||
#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
|
||||
#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
|
||||
#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
|
||||
#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
|
||||
#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
|
||||
#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
|
||||
#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
|
||||
#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
|
||||
#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
|
||||
#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
|
||||
#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
|
||||
#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
|
||||
#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
|
||||
#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
|
||||
#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
|
||||
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF536_proc__ */
|
||||
1
u-boot/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
Normal file
1
u-boot/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
Normal file
@@ -0,0 +1 @@
|
||||
#include "BF536_cdef.h"
|
||||
1
u-boot/arch/blackfin/include/asm/mach-bf537/BF537_def.h
Normal file
1
u-boot/arch/blackfin/include/asm/mach-bf537/BF537_def.h
Normal file
@@ -0,0 +1 @@
|
||||
#include "BF536_def.h"
|
||||
241
u-boot/arch/blackfin/include/asm/mach-bf537/anomaly.h
Normal file
241
u-boot/arch/blackfin/include/asm/mach-bf537/anomaly.h
Normal file
@@ -0,0 +1,241 @@
|
||||
/*
|
||||
* DO NOT EDIT THIS FILE
|
||||
* This file is under version control at
|
||||
* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
|
||||
* and can be replaced with that version at any time
|
||||
* DO NOT EDIT THIS FILE
|
||||
*
|
||||
* Copyright 2004-2011 Analog Devices Inc.
|
||||
* Licensed under the ADI BSD license.
|
||||
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
|
||||
*/
|
||||
|
||||
/* This file should be up to date with:
|
||||
* - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
#define _MACH_ANOMALY_H_
|
||||
|
||||
/* We do not support 0.1 silicon - sorry */
|
||||
#if __SILICON_REVISION__ < 2
|
||||
# error will not work on BF537 silicon version 0.0 or 0.1
|
||||
#endif
|
||||
|
||||
#if defined(__ADSPBF534__)
|
||||
# define ANOMALY_BF534 1
|
||||
#else
|
||||
# define ANOMALY_BF534 0
|
||||
#endif
|
||||
#if defined(__ADSPBF536__)
|
||||
# define ANOMALY_BF536 1
|
||||
#else
|
||||
# define ANOMALY_BF536 0
|
||||
#endif
|
||||
#if defined(__ADSPBF537__)
|
||||
# define ANOMALY_BF537 1
|
||||
#else
|
||||
# define ANOMALY_BF537 0
|
||||
#endif
|
||||
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
|
||||
#define ANOMALY_05000119 (1)
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
|
||||
#define ANOMALY_05000180 (1)
|
||||
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
|
||||
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
|
||||
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000245 (1)
|
||||
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
|
||||
#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
|
||||
/* EMAC TX DMA Error After an Early Frame Abort */
|
||||
#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
|
||||
/* Maximum External Clock Speed for Timers */
|
||||
#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
|
||||
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
|
||||
#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
|
||||
/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
|
||||
#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
|
||||
/* EMAC MDIO Input Latched on Wrong MDC Edge */
|
||||
#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
|
||||
/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
|
||||
#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
|
||||
/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
|
||||
#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
|
||||
/* ICPLB_STATUS MMR Register May Be Corrupted */
|
||||
#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
|
||||
/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
|
||||
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
|
||||
/* Stores To Data Cache May Be Lost */
|
||||
#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
|
||||
/* Hardware Loop Corrupted When Taking an ICPLB Exception */
|
||||
#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
|
||||
/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
|
||||
#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
|
||||
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
||||
#define ANOMALY_05000265 (1)
|
||||
/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
|
||||
#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
|
||||
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
|
||||
#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
|
||||
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
|
||||
#define ANOMALY_05000272 (1)
|
||||
/* Writes to Synchronous SDRAM Memory May Be Lost */
|
||||
#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
|
||||
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
|
||||
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
|
||||
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
|
||||
#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
|
||||
/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
|
||||
#define ANOMALY_05000280 (1)
|
||||
/* False Hardware Error when ISR Context Is Not Restored */
|
||||
#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
|
||||
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
|
||||
#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
|
||||
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
|
||||
#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
|
||||
/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
|
||||
#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
|
||||
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
|
||||
#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
|
||||
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
|
||||
#define ANOMALY_05000301 (1)
|
||||
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
|
||||
#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
|
||||
/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
|
||||
#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
|
||||
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
|
||||
#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
|
||||
/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
|
||||
#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (1)
|
||||
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
|
||||
#define ANOMALY_05000313 (1)
|
||||
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
|
||||
#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
|
||||
/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
|
||||
#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
|
||||
/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
|
||||
#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
|
||||
/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
|
||||
#define ANOMALY_05000322 (1)
|
||||
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
|
||||
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
|
||||
/* UART Gets Disabled after UART Boot */
|
||||
#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (1)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
|
||||
#define ANOMALY_05000359 (1)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
|
||||
#define ANOMALY_05000462 (1)
|
||||
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
|
||||
#define ANOMALY_05000473 (1)
|
||||
/* Possible Lockup Condition when Modifying PLL from External Memory */
|
||||
#define ANOMALY_05000475 (1)
|
||||
/* TESTSET Instruction Cannot Be Interrupted */
|
||||
#define ANOMALY_05000477 (1)
|
||||
/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
|
||||
#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
|
||||
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
|
||||
#define ANOMALY_05000481 (1)
|
||||
/* PLL May Latch Incorrect Values Coming Out of Reset */
|
||||
#define ANOMALY_05000489 (1)
|
||||
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
|
||||
#define ANOMALY_05000491 (1)
|
||||
/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
|
||||
#define ANOMALY_05000494 (1)
|
||||
/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
|
||||
#define ANOMALY_05000501 (1)
|
||||
|
||||
/*
|
||||
* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
* here to show running on older silicon just isn't feasible.
|
||||
*/
|
||||
|
||||
/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
|
||||
#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
|
||||
/* Instruction Cache Is Not Functional */
|
||||
#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
|
||||
/* Buffered CLKIN Output Is Disabled by Default */
|
||||
#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000099 (0)
|
||||
#define ANOMALY_05000120 (0)
|
||||
#define ANOMALY_05000125 (0)
|
||||
#define ANOMALY_05000149 (0)
|
||||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000171 (0)
|
||||
#define ANOMALY_05000179 (0)
|
||||
#define ANOMALY_05000182 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000189 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000202 (0)
|
||||
#define ANOMALY_05000215 (0)
|
||||
#define ANOMALY_05000219 (0)
|
||||
#define ANOMALY_05000220 (0)
|
||||
#define ANOMALY_05000227 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000231 (0)
|
||||
#define ANOMALY_05000233 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000242 (0)
|
||||
#define ANOMALY_05000248 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000274 (0)
|
||||
#define ANOMALY_05000287 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000362 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000364 (0)
|
||||
#define ANOMALY_05000380 (0)
|
||||
#define ANOMALY_05000383 (0)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000389 (0)
|
||||
#define ANOMALY_05000400 (0)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000430 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
#define ANOMALY_05000440 (0)
|
||||
#define ANOMALY_05000447 (0)
|
||||
#define ANOMALY_05000448 (0)
|
||||
#define ANOMALY_05000456 (0)
|
||||
#define ANOMALY_05000450 (0)
|
||||
#define ANOMALY_05000465 (0)
|
||||
#define ANOMALY_05000467 (0)
|
||||
#define ANOMALY_05000474 (0)
|
||||
#define ANOMALY_05000485 (0)
|
||||
|
||||
#endif
|
||||
5
u-boot/arch/blackfin/include/asm/mach-bf537/def_local.h
Normal file
5
u-boot/arch/blackfin/include/asm/mach-bf537/def_local.h
Normal file
@@ -0,0 +1,5 @@
|
||||
#include "gpio.h"
|
||||
#include "portmux.h"
|
||||
#include "ports.h"
|
||||
|
||||
#define BF537_FAMILY 1 /* Linux glue */
|
||||
65
u-boot/arch/blackfin/include/asm/mach-bf537/gpio.h
Normal file
65
u-boot/arch/blackfin/include/asm/mach-bf537/gpio.h
Normal file
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACH_GPIO_H_
|
||||
#define _MACH_GPIO_H_
|
||||
|
||||
#define MAX_BLACKFIN_GPIOS 48
|
||||
|
||||
#define GPIO_PF0 0
|
||||
#define GPIO_PF1 1
|
||||
#define GPIO_PF2 2
|
||||
#define GPIO_PF3 3
|
||||
#define GPIO_PF4 4
|
||||
#define GPIO_PF5 5
|
||||
#define GPIO_PF6 6
|
||||
#define GPIO_PF7 7
|
||||
#define GPIO_PF8 8
|
||||
#define GPIO_PF9 9
|
||||
#define GPIO_PF10 10
|
||||
#define GPIO_PF11 11
|
||||
#define GPIO_PF12 12
|
||||
#define GPIO_PF13 13
|
||||
#define GPIO_PF14 14
|
||||
#define GPIO_PF15 15
|
||||
#define GPIO_PG0 16
|
||||
#define GPIO_PG1 17
|
||||
#define GPIO_PG2 18
|
||||
#define GPIO_PG3 19
|
||||
#define GPIO_PG4 20
|
||||
#define GPIO_PG5 21
|
||||
#define GPIO_PG6 22
|
||||
#define GPIO_PG7 23
|
||||
#define GPIO_PG8 24
|
||||
#define GPIO_PG9 25
|
||||
#define GPIO_PG10 26
|
||||
#define GPIO_PG11 27
|
||||
#define GPIO_PG12 28
|
||||
#define GPIO_PG13 29
|
||||
#define GPIO_PG14 30
|
||||
#define GPIO_PG15 31
|
||||
#define GPIO_PH0 32
|
||||
#define GPIO_PH1 33
|
||||
#define GPIO_PH2 34
|
||||
#define GPIO_PH3 35
|
||||
#define GPIO_PH4 36
|
||||
#define GPIO_PH5 37
|
||||
#define GPIO_PH6 38
|
||||
#define GPIO_PH7 39
|
||||
#define GPIO_PH8 40
|
||||
#define GPIO_PH9 41
|
||||
#define GPIO_PH10 42
|
||||
#define GPIO_PH11 43
|
||||
#define GPIO_PH12 44
|
||||
#define GPIO_PH13 45
|
||||
#define GPIO_PH14 46
|
||||
#define GPIO_PH15 47
|
||||
|
||||
#define PORT_F GPIO_PF0
|
||||
#define PORT_G GPIO_PG0
|
||||
#define PORT_H GPIO_PH0
|
||||
|
||||
#endif /* _MACH_GPIO_H_ */
|
||||
152
u-boot/arch/blackfin/include/asm/mach-bf537/portmux.h
Normal file
152
u-boot/arch/blackfin/include/asm/mach-bf537/portmux.h
Normal file
@@ -0,0 +1,152 @@
|
||||
/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later
|
||||
*/
|
||||
|
||||
#ifndef _MACH_PORTMUX_H_
|
||||
#define _MACH_PORTMUX_H_
|
||||
|
||||
#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
|
||||
|
||||
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
|
||||
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
|
||||
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
|
||||
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
|
||||
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
|
||||
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
|
||||
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
|
||||
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
|
||||
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
|
||||
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
|
||||
#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
|
||||
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
|
||||
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
|
||||
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
|
||||
#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
|
||||
#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
|
||||
#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
|
||||
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
|
||||
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
|
||||
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
|
||||
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
|
||||
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
|
||||
#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
|
||||
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
|
||||
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
|
||||
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
|
||||
|
||||
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
|
||||
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
|
||||
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
|
||||
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
|
||||
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
|
||||
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
|
||||
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
|
||||
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
|
||||
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
|
||||
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
|
||||
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
|
||||
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
|
||||
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
|
||||
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
|
||||
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
|
||||
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
|
||||
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
|
||||
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
|
||||
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
|
||||
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
|
||||
#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
|
||||
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
|
||||
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
|
||||
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
|
||||
|
||||
#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
|
||||
#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
|
||||
#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
|
||||
#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
|
||||
#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
|
||||
#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
|
||||
#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
|
||||
#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
|
||||
#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
|
||||
#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
|
||||
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
|
||||
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
|
||||
#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
|
||||
#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
|
||||
#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
|
||||
|
||||
#define PORT_PJ0 (GPIO_PH15 + 1)
|
||||
#define PORT_PJ1 (GPIO_PH15 + 2)
|
||||
#define PORT_PJ2 (GPIO_PH15 + 3)
|
||||
#define PORT_PJ3 (GPIO_PH15 + 4)
|
||||
#define PORT_PJ4 (GPIO_PH15 + 5)
|
||||
#define PORT_PJ5 (GPIO_PH15 + 6)
|
||||
#define PORT_PJ6 (GPIO_PH15 + 7)
|
||||
#define PORT_PJ7 (GPIO_PH15 + 8)
|
||||
#define PORT_PJ8 (GPIO_PH15 + 9)
|
||||
#define PORT_PJ9 (GPIO_PH15 + 10)
|
||||
#define PORT_PJ10 (GPIO_PH15 + 11)
|
||||
#define PORT_PJ11 (GPIO_PH15 + 12)
|
||||
|
||||
#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
|
||||
#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
|
||||
#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
|
||||
#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
|
||||
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
|
||||
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
|
||||
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
|
||||
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
|
||||
#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
|
||||
#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
|
||||
|
||||
#define P_MII0 {\
|
||||
P_MII0_ETxD0, \
|
||||
P_MII0_ETxD1, \
|
||||
P_MII0_ETxD2, \
|
||||
P_MII0_ETxD3, \
|
||||
P_MII0_ETxEN, \
|
||||
P_MII0_TxCLK, \
|
||||
P_MII0_PHYINT, \
|
||||
P_MII0_COL, \
|
||||
P_MII0_ERxD0, \
|
||||
P_MII0_ERxD1, \
|
||||
P_MII0_ERxD2, \
|
||||
P_MII0_ERxD3, \
|
||||
P_MII0_ERxDV, \
|
||||
P_MII0_ERxCLK, \
|
||||
P_MII0_ERxER, \
|
||||
P_MII0_CRS, \
|
||||
P_MDC, \
|
||||
P_MDIO, 0}
|
||||
|
||||
#define P_RMII0 {\
|
||||
P_MII0_ETxD0, \
|
||||
P_MII0_ETxD1, \
|
||||
P_MII0_ETxEN, \
|
||||
P_MII0_ERxD0, \
|
||||
P_MII0_ERxD1, \
|
||||
P_MII0_ERxER, \
|
||||
P_RMII0_REF_CLK, \
|
||||
P_RMII0_MDINT, \
|
||||
P_RMII0_CRS_DV, \
|
||||
P_MDC, \
|
||||
P_MDIO, 0}
|
||||
|
||||
#endif /* _MACH_PORTMUX_H_ */
|
||||
28
u-boot/arch/blackfin/include/asm/mach-bf537/ports.h
Normal file
28
u-boot/arch/blackfin/include/asm/mach-bf537/ports.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Port Masks
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_PERIPHERAL_PORT__
|
||||
#define __BFIN_PERIPHERAL_PORT__
|
||||
|
||||
/* PORT_MUX Masks */
|
||||
#define PJSE 0x0001
|
||||
#define PJCE_MASK 0x0006
|
||||
#define PJCE_SPORT 0x0000
|
||||
#define PJCE_CAN 0x0001
|
||||
#define PJCE_SPI 0x0002
|
||||
#define PFDE 0x0008
|
||||
#define PFTE 0x0010
|
||||
#define PFS6E 0x0020
|
||||
#define PFS5E 0x0040
|
||||
#define PFS4E 0x0080
|
||||
#define PFFE 0x0100
|
||||
#define PGSE 0x0200
|
||||
#define PGRE 0x0400
|
||||
#define PGTE 0x0800
|
||||
|
||||
#include "../mach-common/bits/ports-f.h"
|
||||
#include "../mach-common/bits/ports-g.h"
|
||||
#include "../mach-common/bits/ports-h.h"
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user