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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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23
u-boot/arch/arm/mach-uniphier/dram/Makefile Normal file
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#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \
ddrphy-training.o ddrphy-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += umc-pro4.o \
ddrphy-training.o ddrphy-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \
ddrphy-training.o ddrphy-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += umc-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o
else
obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o
endif

315
u-boot/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c Normal file
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/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include "../init.h"
#include "ddrmphy-regs.h"
/* Select either decimal or hexadecimal */
#if 1
#define PRINTF_FORMAT "%2d"
#else
#define PRINTF_FORMAT "%02x"
#endif
/* field separator */
#define FS " "
static void __iomem *get_phy_base(int ch)
{
return (void __iomem *)(0x5b830000 + ch * 0x00200000);
}
static int get_nr_ch(void)
{
const struct uniphier_board_data *bd = uniphier_get_board_param();
return bd->dram_ch[2].size ? 3 : 2;
}
static int get_nr_datx8(int ch)
{
const struct uniphier_board_data *bd = uniphier_get_board_param();
return bd->dram_ch[ch].width / 8;
}
static void print_bdl(void __iomem *reg, int n)
{
u32 val = readl(reg);
int i;
for (i = 0; i < n; i++)
printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
}
static void dump_loop(void (*callback)(void __iomem *))
{
int ch, dx, nr_ch, nr_dx;
void __iomem *dx_base;
nr_ch = get_nr_ch();
for (ch = 0; ch < nr_ch; ch++) {
dx_base = get_phy_base(ch) + DMPHY_DX_BASE;
nr_dx = get_nr_datx8(ch);
for (dx = 0; dx < nr_dx; dx++) {
printf("CH%dDX%d:", ch, dx);
(*callback)(dx_base);
dx_base += DMPHY_DX_STRIDE;
printf("\n");
}
}
}
static void zq_dump(void)
{
int ch, zq, nr_ch, nr_zq, i;
void __iomem *zq_base;
u32 dr, pr;
printf("\n--- Impedance Data ---\n");
printf(" ZPD ZPU OPD OPU ZDV ODV\n");
nr_ch = get_nr_ch();
for (ch = 0; ch < nr_ch; ch++) {
zq_base = get_phy_base(ch) + DMPHY_ZQ_BASE;
nr_zq = 3;
for (zq = 0; zq < nr_zq; zq++) {
printf("CH%dZQ%d:", ch, zq);
dr = readl(zq_base + DMPHY_ZQ_DR);
for (i = 0; i < 4; i++) {
printf(FS PRINTF_FORMAT, dr & 0x7f);
dr >>= 7;
}
pr = readl(zq_base + DMPHY_ZQ_PR);
for (i = 0; i < 2; i++) {
printf(FS PRINTF_FORMAT, pr & 0xf);
pr >>= 4;
}
zq_base += DMPHY_ZQ_STRIDE;
printf("\n");
}
}
}
static void __wbdl_dump(void __iomem *dx_base)
{
print_bdl(dx_base + DMPHY_DX_BDLR0, 4);
print_bdl(dx_base + DMPHY_DX_BDLR1, 4);
print_bdl(dx_base + DMPHY_DX_BDLR2, 2);
printf(FS "(+" PRINTF_FORMAT ")",
readl(dx_base + DMPHY_DX_LCDLR1) & 0xff);
}
static void wbdl_dump(void)
{
printf("\n--- Write Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
dump_loop(&__wbdl_dump);
}
static void __rbdl_dump(void __iomem *dx_base)
{
print_bdl(dx_base + DMPHY_DX_BDLR3, 4);
print_bdl(dx_base + DMPHY_DX_BDLR4, 4);
print_bdl(dx_base + DMPHY_DX_BDLR5, 1);
printf(FS "(+" PRINTF_FORMAT ")",
(readl(dx_base + DMPHY_DX_LCDLR1) >> 8) & 0xff);
printf(FS "(+" PRINTF_FORMAT ")",
(readl(dx_base + DMPHY_DX_LCDLR1) >> 16) & 0xff);
}
static void rbdl_dump(void)
{
printf("\n--- Read Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
dump_loop(&__rbdl_dump);
}
static void __wld_dump(void __iomem *dx_base)
{
int rank;
u32 lcdlr0 = readl(dx_base + DMPHY_DX_LCDLR0);
u32 gtr = readl(dx_base + DMPHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
printf(FS PRINTF_FORMAT "%sT", wld,
wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
}
}
static void wld_dump(void)
{
printf("\n--- Write Leveling Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
dump_loop(&__wld_dump);
}
static void __dqsgd_dump(void __iomem *dx_base)
{
int rank;
u32 lcdlr2 = readl(dx_base + DMPHY_DX_LCDLR2);
u32 gtr = readl(dx_base + DMPHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
}
}
static void dqsgd_dump(void)
{
printf("\n--- DQS Gating Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
dump_loop(&__dqsgd_dump);
}
static void __mdl_dump(void __iomem *dx_base)
{
int i;
u32 mdl = readl(dx_base + DMPHY_DX_MDLR);
for (i = 0; i < 3; i++)
printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
}
static void mdl_dump(void)
{
printf("\n--- Master Delay Line ---\n");
printf(" IPRD TPRD MDLD\n");
dump_loop(&__mdl_dump);
}
#define REG_DUMP(x) \
{ int ofst = DMPHY_ ## x; void __iomem *reg = phy_base + ofst; \
printf("%3d: %-10s: %p : %08x\n", \
ofst >> DMPHY_SHIFT, #x, reg, readl(reg)); }
#define DX_REG_DUMP(dx, x) \
{ int ofst = DMPHY_DX_BASE + DMPHY_DX_STRIDE * (dx) + \
DMPHY_DX_## x; \
void __iomem *reg = phy_base + ofst; \
printf("%3d: DX%d%-7s: %p : %08x\n", \
ofst >> DMPHY_SHIFT, (dx), #x, reg, readl(reg)); }
static void reg_dump(void)
{
int ch, dx, nr_ch, nr_dx;
void __iomem *phy_base;
printf("\n--- DDR PHY registers ---\n");
nr_ch = get_nr_ch();
for (ch = 0; ch < nr_ch; ch++) {
phy_base = get_phy_base(ch);
nr_dx = get_nr_datx8(ch);
printf("== Ch%d ==\n", ch);
printf(" No: Name : Address : Data\n");
REG_DUMP(RIDR);
REG_DUMP(PIR);
REG_DUMP(PGCR0);
REG_DUMP(PGCR1);
REG_DUMP(PGCR2);
REG_DUMP(PGCR3);
REG_DUMP(PGSR0);
REG_DUMP(PGSR1);
REG_DUMP(PLLCR);
REG_DUMP(PTR0);
REG_DUMP(PTR1);
REG_DUMP(PTR2);
REG_DUMP(PTR3);
REG_DUMP(PTR4);
REG_DUMP(ACMDLR);
REG_DUMP(ACBDLR0);
REG_DUMP(DXCCR);
REG_DUMP(DSGCR);
REG_DUMP(DCR);
REG_DUMP(DTPR0);
REG_DUMP(DTPR1);
REG_DUMP(DTPR2);
REG_DUMP(DTPR3);
REG_DUMP(MR0);
REG_DUMP(MR1);
REG_DUMP(MR2);
REG_DUMP(MR3);
for (dx = 0; dx < nr_dx; dx++) {
DX_REG_DUMP(dx, GCR0);
DX_REG_DUMP(dx, GCR1);
DX_REG_DUMP(dx, GCR2);
DX_REG_DUMP(dx, GCR3);
DX_REG_DUMP(dx, GTR);
}
}
}
static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *cmd = argv[1];
if (argc == 1)
cmd = "all";
if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
zq_dump();
if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
wbdl_dump();
if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
rbdl_dump();
if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
wld_dump();
if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
dqsgd_dump();
if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
mdl_dump();
if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
reg_dump();
return 0;
}
U_BOOT_CMD(
ddrm, 2, 1, do_ddrm,
"UniPhier DDR PHY parameters dumper",
"- dump all of the followings\n"
"ddrm zq - dump Impedance Data\n"
"ddrm wbdl - dump Write Bit Delay\n"
"ddrm rbdl - dump Read Bit Delay\n"
"ddrm wld - dump Write Leveling\n"
"ddrm dqsgd - dump DQS Gating Delay\n"
"ddrm mdl - dump Master Delay Line\n"
"ddrm reg - dump registers\n"
);

267
u-boot/arch/arm/mach-uniphier/dram/cmd_ddrphy.c Normal file
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/*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mapmem.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include "../soc-info.h"
#include "ddrphy-regs.h"
/* Select either decimal or hexadecimal */
#if 1
#define PRINTF_FORMAT "%2d"
#else
#define PRINTF_FORMAT "%02x"
#endif
/* field separator */
#define FS " "
static unsigned long uniphier_ld4_base[] = {
0x5bc01000,
0x5be01000,
0 /* sentinel */
};
static unsigned long uniphier_pro4_base[] = {
0x5bc01000,
0x5be01000,
0 /* sentinel */
};
static unsigned long uniphier_sld8_base[] = {
0x5bc01000,
0x5be01000,
0 /* sentinel */
};
static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
{
return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
}
static void dump_loop(unsigned long *base,
void (*callback)(struct ddrphy_datx8 __iomem *))
{
struct ddrphy __iomem *phy;
int p, dx;
for (p = 0; *base; base++, p++) {
phy = map_sysmem(*base, SZ_4K);
for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
printf("PHY%dDX%d:", p, dx);
(*callback)(&phy->dx[dx]);
printf("\n");
}
unmap_sysmem(phy);
}
}
static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
{
int i;
for (i = 0; i < 10; i++)
printf(FS PRINTF_FORMAT, read_bdl(dx, i));
printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
}
static void wbdl_dump(unsigned long *base)
{
printf("\n--- Write Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
dump_loop(base, &__wbdl_dump);
}
static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
{
int i;
for (i = 15; i < 24; i++)
printf(FS PRINTF_FORMAT, read_bdl(dx, i));
printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
}
static void rbdl_dump(unsigned long *base)
{
printf("\n--- Read Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
dump_loop(base, &__rbdl_dump);
}
static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
{
int rank;
u32 lcdlr0 = readl(&dx->lcdlr[0]);
u32 gtr = readl(&dx->gtr);
for (rank = 0; rank < 4; rank++) {
u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
printf(FS PRINTF_FORMAT "%sT", wld,
wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
}
}
static void wld_dump(unsigned long *base)
{
printf("\n--- Write Leveling Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
dump_loop(base, &__wld_dump);
}
static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
{
int rank;
u32 lcdlr2 = readl(&dx->lcdlr[2]);
u32 gtr = readl(&dx->gtr);
for (rank = 0; rank < 4; rank++) {
u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
}
}
static void dqsgd_dump(unsigned long *base)
{
printf("\n--- DQS Gating Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
dump_loop(base, &__dqsgd_dump);
}
static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
{
int i;
u32 mdl = readl(&dx->mdlr);
for (i = 0; i < 3; i++)
printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
}
static void mdl_dump(unsigned long *base)
{
printf("\n--- Master Delay Line ---\n");
printf(" IPRD TPRD MDLD\n");
dump_loop(base, &__mdl_dump);
}
#define REG_DUMP(x) \
{ u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
p - (u32 *)phy, #x, p, readl(p)); }
static void reg_dump(unsigned long *base)
{
struct ddrphy __iomem *phy;
int p;
printf("\n--- DDR PHY registers ---\n");
for (p = 0; *base; base++, p++) {
phy = map_sysmem(*base, SZ_4K);
printf("== PHY%d (base: %p) ==\n", p, phy);
printf(" No: Name : Address : Data\n");
REG_DUMP(ridr);
REG_DUMP(pir);
REG_DUMP(pgcr[0]);
REG_DUMP(pgcr[1]);
REG_DUMP(pgsr[0]);
REG_DUMP(pgsr[1]);
REG_DUMP(pllcr);
REG_DUMP(ptr[0]);
REG_DUMP(ptr[1]);
REG_DUMP(ptr[2]);
REG_DUMP(ptr[3]);
REG_DUMP(ptr[4]);
REG_DUMP(acmdlr);
REG_DUMP(acbdlr);
REG_DUMP(dxccr);
REG_DUMP(dsgcr);
REG_DUMP(dcr);
REG_DUMP(dtpr[0]);
REG_DUMP(dtpr[1]);
REG_DUMP(dtpr[2]);
REG_DUMP(mr0);
REG_DUMP(mr1);
REG_DUMP(mr2);
REG_DUMP(mr3);
REG_DUMP(dx[0].gcr);
REG_DUMP(dx[0].gtr);
REG_DUMP(dx[1].gcr);
REG_DUMP(dx[1].gtr);
unmap_sysmem(phy);
}
}
static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *cmd = argv[1];
unsigned long *base;
switch (uniphier_get_soc_type()) {
case SOC_UNIPHIER_LD4:
base = uniphier_ld4_base;
break;
case SOC_UNIPHIER_PRO4:
base = uniphier_pro4_base;
break;
case SOC_UNIPHIER_SLD8:
base = uniphier_sld8_base;
break;
default:
printf("unsupported SoC\n");
return CMD_RET_FAILURE;
}
if (argc == 1)
cmd = "all";
if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
wbdl_dump(base);
if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
rbdl_dump(base);
if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
wld_dump(base);
if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
dqsgd_dump(base);
if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
mdl_dump(base);
if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
reg_dump(base);
return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
ddr, 2, 1, do_ddr,
"UniPhier DDR PHY parameters dumper",
"- dump all of the followings\n"
"ddr wbdl - dump Write Bit Delay\n"
"ddr rbdl - dump Read Bit Delay\n"
"ddr wld - dump Write Leveling\n"
"ddr dqsgd - dump DQS Gating Delay\n"
"ddr mdl - dump Master Delay Line\n"
"ddr reg - dump registers\n"
);

146
u-boot/arch/arm/mach-uniphier/dram/ddrmphy-regs.h Normal file
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@@ -0,0 +1,146 @@
/*
* UniPhier DDR MultiPHY registers
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_DDRMPHY_REGS_H
#define ARCH_DDRMPHY_REGS_H
#include <linux/bitops.h>
#define DMPHY_SHIFT 2
#define DMPHY_RIDR (0x000 << DMPHY_SHIFT)
#define DMPHY_PIR (0x001 << DMPHY_SHIFT)
#define DMPHY_PIR_INIT BIT(0) /* Initialization Trigger */
#define DMPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
#define DMPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
#define DMPHY_PIR_DCAL BIT(5) /* DDL Calibration */
#define DMPHY_PIR_PHYRST BIT(6) /* PHY Reset */
#define DMPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
#define DMPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
#define DMPHY_PIR_WL BIT(9) /* Write Leveling */
#define DMPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
#define DMPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
#define DMPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
#define DMPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
#define DMPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
#define DMPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
#define DMPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
#define DMPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
#define DMPHY_PGCR0 (0x002 << DMPHY_SHIFT)
#define DMPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */
#define DMPHY_PGCR1 (0x003 << DMPHY_SHIFT)
#define DMPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
#define DMPHY_PGCR2 (0x004 << DMPHY_SHIFT)
#define DMPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/
#define DMPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/
#define DMPHY_PGCR3 (0x005 << DMPHY_SHIFT)
#define DMPHY_PGSR0 (0x006 << DMPHY_SHIFT)
#define DMPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
#define DMPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
#define DMPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
#define DMPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
#define DMPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
#define DMPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
#define DMPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
#define DMPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
#define DMPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
#define DMPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
#define DMPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
#define DMPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
#define DMPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */
#define DMPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
#define DMPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
#define DMPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
#define DMPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
#define DMPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
#define DMPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
#define DMPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
#define DMPHY_PGSR1 (0x007 << DMPHY_SHIFT)
#define DMPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */
#define DMPHY_PLLCR (0x008 << DMPHY_SHIFT)
#define DMPHY_PTR0 (0x009 << DMPHY_SHIFT)
#define DMPHY_PTR1 (0x00A << DMPHY_SHIFT)
#define DMPHY_PTR2 (0x00B << DMPHY_SHIFT)
#define DMPHY_PTR3 (0x00C << DMPHY_SHIFT)
#define DMPHY_PTR4 (0x00D << DMPHY_SHIFT)
#define DMPHY_ACMDLR (0x00E << DMPHY_SHIFT)
#define DMPHY_ACLCDLR (0x00F << DMPHY_SHIFT)
#define DMPHY_ACBDLR0 (0x010 << DMPHY_SHIFT)
#define DMPHY_ACBDLR1 (0x011 << DMPHY_SHIFT)
#define DMPHY_ACBDLR2 (0x012 << DMPHY_SHIFT)
#define DMPHY_ACBDLR3 (0x013 << DMPHY_SHIFT)
#define DMPHY_ACBDLR4 (0x014 << DMPHY_SHIFT)
#define DMPHY_ACBDLR5 (0x015 << DMPHY_SHIFT)
#define DMPHY_ACBDLR6 (0x016 << DMPHY_SHIFT)
#define DMPHY_ACBDLR7 (0x017 << DMPHY_SHIFT)
#define DMPHY_ACBDLR8 (0x018 << DMPHY_SHIFT)
#define DMPHY_ACBDLR9 (0x019 << DMPHY_SHIFT)
#define DMPHY_ACIOCR0 (0x01A << DMPHY_SHIFT)
#define DMPHY_ACIOCR1 (0x01B << DMPHY_SHIFT)
#define DMPHY_ACIOCR2 (0x01C << DMPHY_SHIFT)
#define DMPHY_ACIOCR3 (0x01D << DMPHY_SHIFT)
#define DMPHY_ACIOCR4 (0x01E << DMPHY_SHIFT)
#define DMPHY_ACIOCR5 (0x01F << DMPHY_SHIFT)
#define DMPHY_DXCCR (0x020 << DMPHY_SHIFT)
#define DMPHY_DSGCR (0x021 << DMPHY_SHIFT)
#define DMPHY_DCR (0x022 << DMPHY_SHIFT)
#define DMPHY_DTPR0 (0x023 << DMPHY_SHIFT)
#define DMPHY_DTPR1 (0x024 << DMPHY_SHIFT)
#define DMPHY_DTPR2 (0x025 << DMPHY_SHIFT)
#define DMPHY_DTPR3 (0x026 << DMPHY_SHIFT)
#define DMPHY_MR0 (0x027 << DMPHY_SHIFT)
#define DMPHY_MR1 (0x028 << DMPHY_SHIFT)
#define DMPHY_MR2 (0x029 << DMPHY_SHIFT)
#define DMPHY_MR3 (0x02A << DMPHY_SHIFT)
#define DMPHY_ODTCR (0x02B << DMPHY_SHIFT)
#define DMPHY_DTCR (0x02C << DMPHY_SHIFT)
#define DMPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
#define DMPHY_DTCR_RANKEN_MASK (0xf << (DMPHY_DTCR_RANKEN_SHIFT))
#define DMPHY_DTAR0 (0x02D << DMPHY_SHIFT)
#define DMPHY_DTAR1 (0x02E << DMPHY_SHIFT)
#define DMPHY_DTAR2 (0x02F << DMPHY_SHIFT)
#define DMPHY_DTAR3 (0x030 << DMPHY_SHIFT)
#define DMPHY_DTDR0 (0x031 << DMPHY_SHIFT)
#define DMPHY_DTDR1 (0x032 << DMPHY_SHIFT)
#define DMPHY_DTEDR0 (0x033 << DMPHY_SHIFT)
#define DMPHY_DTEDR1 (0x034 << DMPHY_SHIFT)
#define DMPHY_ZQCR (0x090 << DMPHY_SHIFT)
#define DMPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */
#define DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */
/* ZQ */
#define DMPHY_ZQ_BASE (0x091 << DMPHY_SHIFT)
#define DMPHY_ZQ_STRIDE (0x004 << DMPHY_SHIFT)
#define DMPHY_ZQ_PR (0x000 << DMPHY_SHIFT)
#define DMPHY_ZQ_DR (0x001 << DMPHY_SHIFT)
#define DMPHY_ZQ_SR (0x002 << DMPHY_SHIFT)
/* DATX8 */
#define DMPHY_DX_BASE (0x0A0 << DMPHY_SHIFT)
#define DMPHY_DX_STRIDE (0x020 << DMPHY_SHIFT)
#define DMPHY_DX_GCR0 (0x000 << DMPHY_SHIFT)
#define DMPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
#define DMPHY_DX_GCR0_WLRKEN_MASK (0xf << (DMPHY_DX_GCR0_WLRKEN_SHIFT))
#define DMPHY_DX_GCR1 (0x001 << DMPHY_SHIFT)
#define DMPHY_DX_GCR2 (0x002 << DMPHY_SHIFT)
#define DMPHY_DX_GCR3 (0x003 << DMPHY_SHIFT)
#define DMPHY_DX_GSR0 (0x004 << DMPHY_SHIFT)
#define DMPHY_DX_GSR1 (0x005 << DMPHY_SHIFT)
#define DMPHY_DX_GSR2 (0x006 << DMPHY_SHIFT)
#define DMPHY_DX_BDLR0 (0x007 << DMPHY_SHIFT)
#define DMPHY_DX_BDLR1 (0x008 << DMPHY_SHIFT)
#define DMPHY_DX_BDLR2 (0x009 << DMPHY_SHIFT)
#define DMPHY_DX_BDLR3 (0x00A << DMPHY_SHIFT)
#define DMPHY_DX_BDLR4 (0x00B << DMPHY_SHIFT)
#define DMPHY_DX_BDLR5 (0x00C << DMPHY_SHIFT)
#define DMPHY_DX_BDLR6 (0x00D << DMPHY_SHIFT)
#define DMPHY_DX_LCDLR0 (0x00E << DMPHY_SHIFT)
#define DMPHY_DX_LCDLR1 (0x00F << DMPHY_SHIFT)
#define DMPHY_DX_LCDLR2 (0x010 << DMPHY_SHIFT)
#define DMPHY_DX_MDLR (0x011 << DMPHY_SHIFT)
#define DMPHY_DX_GTR (0x012 << DMPHY_SHIFT)
#endif /* ARCH_DDRMPHY_REGS_H */

41
u-boot/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h Normal file
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/*
* Copyright (C) 2016 Socionext Inc.
*/
#ifndef _DDRPHY_LD20_REGS_H
#define _DDRPHY_LD20_REGS_H
#define PHY_SCL_DATA_0 0x00000104
#define PHY_SCL_DATA_1 0x00000108
#define PHY_SCL_LATENCY 0x0000010C
#define PHY_SCL_START 0x00000100
#define PHY_SCL_CONFIG_1 0x00000118
#define PHY_SCL_CONFIG_2 0x0000011C
#define PHY_PAD_CTRL 0x00000120
#define PHY_DLL_RECALIB 0x00000124
#define PHY_DLL_ADRCTRL 0x00000128
#define PHY_LANE_SEL 0x0000012C
#define PHY_DLL_TRIM_1 0x00000130
#define PHY_DLL_TRIM_2 0x00000134
#define PHY_DLL_TRIM_3 0x00000138
#define PHY_SCL_MAIN_CLK_DELTA 0x00000140
#define PHY_WRLVL_AUTOINC_TRIM 0x0000014C
#define PHY_WRLVL_DYN_ODT 0x00000150
#define PHY_WRLVL_ON_OFF 0x00000154
#define PHY_UNQ_ANALOG_DLL_1 0x0000015C
#define PHY_DLL_INCR_TRIM_1 0x00000164
#define PHY_DLL_INCR_TRIM_3 0x00000168
#define PHY_SCL_CONFIG_3 0x0000016C
#define PHY_UNIQUIFY_TSMC_IO_1 0x00000170
#define PHY_SCL_START_ADDR 0x00000188
#define PHY_DSCL_CNT 0x0000019C
#define PHY_DLL_TRIM_CLK 0x000001A4
#define PHY_DYNAMIC_BIT_LVL 0x000001AC
#define PHY_SCL_WINDOW_TRIM 0x000001B4
#define PHY_DISABLE_GATING_FOR_SCL 0x000001B8
#define PHY_SCL_CONFIG_4 0x000001BC
#define PHY_DYNAMIC_WRITE_BIT_LVL 0x000001C0
#define PHY_VREF_TRAINING 0x000001C8
#define PHY_SCL_GATE_TIMING 0x000001E0
#endif /* _DDRPHY_LD20_REGS_H */

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u-boot/arch/arm/mach-uniphier/dram/ddrphy-ld4.c Normal file
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/*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/types.h>
#include <linux/io.h>
#include "ddrphy-regs.h"
enum dram_freq {
DRAM_FREQ_1333M,
DRAM_FREQ_1600M,
DRAM_FREQ_NR,
};
static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04};
static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E};
static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80};
static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100};
static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66};
static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400};
static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
bool ddr3plus)
{
enum dram_freq freq_e;
u32 tmp;
switch (freq) {
case 1333:
freq_e = DRAM_FREQ_1333M;
break;
case 1600:
freq_e = DRAM_FREQ_1600M;
break;
default:
printf("unsupported DRAM frequency %d MHz\n", freq);
return -EINVAL;
}
writel(0x0300c473, &phy->pgcr[1]);
writel(ddrphy_ptr0[freq_e], &phy->ptr[0]);
writel(ddrphy_ptr1[freq_e], &phy->ptr[1]);
writel(0x00083DEF, &phy->ptr[2]);
writel(ddrphy_ptr3[freq_e], &phy->ptr[3]);
writel(ddrphy_ptr4[freq_e], &phy->ptr[4]);
writel(0xF004001A, &phy->dsgcr);
/* change the value of the on-die pull-up/pull-down registors */
tmp = readl(&phy->dxccr);
tmp &= ~0x0ee0;
tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
writel(tmp, &phy->dxccr);
writel(0x0000040B, &phy->dcr);
writel(ddrphy_dtpr0[freq_e], &phy->dtpr[0]);
writel(ddrphy_dtpr1[freq_e], &phy->dtpr[1]);
writel(ddrphy_dtpr2[freq_e], &phy->dtpr[2]);
writel(ddrphy_mr0[freq_e], &phy->mr0);
writel(0x00000006, &phy->mr1);
writel(ddrphy_mr2[freq_e], &phy->mr2);
writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
;
writel(0x0300C473, &phy->pgcr[1]);
writel(0x0000005D, &phy->zq[0].cr[1]);
return 0;
}

168
u-boot/arch/arm/mach-uniphier/dram/ddrphy-regs.h Normal file
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/*
* UniPhier DDR PHY registers
*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_DDRPHY_REGS_H
#define ARCH_DDRPHY_REGS_H
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/types.h>
#ifndef __ASSEMBLY__
struct ddrphy {
u32 ridr; /* Revision Identification Register */
u32 pir; /* PHY Initialixation Register */
u32 pgcr[2]; /* PHY General Configuration Register */
u32 pgsr[2]; /* PHY General Status Register */
u32 pllcr; /* PLL Control Register */
u32 ptr[5]; /* PHY Timing Register */
u32 acmdlr; /* AC Master Delay Line Register */
u32 acbdlr; /* AC Bit Delay Line Register */
u32 aciocr; /* AC I/O Configuration Register */
u32 dxccr; /* DATX8 Common Configuration Register */
u32 dsgcr; /* DDR System General Configuration Register */
u32 dcr; /* DRAM Configuration Register */
u32 dtpr[3]; /* DRAM Timing Parameters Register */
u32 mr0; /* Mode Register 0 */
u32 mr1; /* Mode Register 1 */
u32 mr2; /* Mode Register 2 */
u32 mr3; /* Mode Register 3 */
u32 odtcr; /* ODT Configuration Register */
u32 dtcr; /* Data Training Configuration Register */
u32 dtar[4]; /* Data Training Address Register */
u32 dtdr[2]; /* Data Training Data Register */
u32 dtedr[2]; /* Data Training Eye Data Register */
u32 pgcr2; /* PHY General Configuration Register 2 */
u32 rsv0[8]; /* Reserved */
u32 rdimmgcr[2]; /* RDIMM General Configuration Register */
u32 rdimmcr0[2]; /* RDIMM Control Register */
u32 dcuar; /* DCU Address Register */
u32 dcudr; /* DCU Data Register */
u32 dcurr; /* DCU Run Register */
u32 dculr; /* DCU Loop Register */
u32 dcugcr; /* DCU General Configuration Register */
u32 dcutpr; /* DCU Timing Parameters Register */
u32 dcusr[2]; /* DCU Status Register */
u32 rsv1[8]; /* Reserved */
u32 bistrr; /* BIST Run Register */
u32 bistwcr; /* BIST Word Count Register */
u32 bistmskr[3]; /* BIST Mask Register */
u32 bistlsr; /* BIST LFSR Sed Register */
u32 bistar[3]; /* BIST Address Register */
u32 bistudpr; /* BIST User Data Pattern Register */
u32 bistgsr; /* BIST General Status Register */
u32 bistwer; /* BIST Word Error Register */
u32 bistber[4]; /* BIST Bit Error Register */
u32 bistwcsr; /* BIST Word Count Status Register */
u32 bistfwr[3]; /* BIST Fail Word Register */
u32 rsv2[10]; /* Reserved */
u32 gpr[2]; /* General Purpose Register */
struct ddrphy_zq { /* ZQ */
u32 cr[2]; /* Impedance Control Register */
u32 sr[2]; /* Impedance Status Register */
} zq[4];
struct ddrphy_datx8 { /* DATX8 */
u32 gcr; /* General Configuration Register */
u32 gsr[2]; /* General Status Register */
u32 bdlr[5]; /* Bit Delay Line Register */
u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
u32 mdlr; /* Master Delay Line Register */
u32 gtr; /* General Timing Register */
u32 gsr2; /* General Status Register 2 */
u32 rsv[2]; /* Reserved */
} dx[9];
};
#endif /* __ASSEMBLY__ */
#define PIR_INIT BIT(0) /* Initialization Trigger */
#define PIR_ZCAL BIT(1) /* Impedance Calibration */
#define PIR_PLLINIT BIT(4) /* PLL Initialization */
#define PIR_DCAL BIT(5) /* DDL Calibration */
#define PIR_PHYRST BIT(6) /* PHY Reset */
#define PIR_DRAMRST BIT(7) /* DRAM Reset */
#define PIR_DRAMINIT BIT(8) /* DRAM Initialization */
#define PIR_WL BIT(9) /* Write Leveling */
#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */
#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */
#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
#define PIR_RDEYE BIT(14) /* Read Data Eye Training */
#define PIR_WREYE BIT(15) /* Write Data Eye Training */
#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
#define PIR_INITBYP BIT(31) /* Initialization Bypass */
#define PGSR0_IDONE BIT(0) /* Initialization Done */
#define PGSR0_PLDONE BIT(1) /* PLL Lock Done */
#define PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
#define PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
#define PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
#define PGSR0_WLDONE BIT(5) /* Write Leveling Done */
#define PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
#define PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
#define PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
#define PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */
#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
#define PGSR0_IERR BIT(16) /* Initialization Error */
#define PGSR0_PLERR BIT(17) /* PLL Lock Error */
#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */
#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */
#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
#define PGSR0_WLERR BIT(21) /* Write Leveling Error */
#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
#define PGSR0_REERR BIT(26) /* Read Eye Training Error */
#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */
#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */
#define DXCCR_DQSRES_OPEN (0 << 5)
#define DXCCR_DQSRES_688_OHM (1 << 5)
#define DXCCR_DQSRES_611_OHM (2 << 5)
#define DXCCR_DQSRES_550_OHM (3 << 5)
#define DXCCR_DQSRES_500_OHM (4 << 5)
#define DXCCR_DQSRES_458_OHM (5 << 5)
#define DXCCR_DQSRES_393_OHM (6 << 5)
#define DXCCR_DQSRES_344_OHM (7 << 5)
#define DXCCR_DQSNRES_OPEN (0 << 9)
#define DXCCR_DQSNRES_688_OHM (1 << 9)
#define DXCCR_DQSNRES_611_OHM (2 << 9)
#define DXCCR_DQSNRES_550_OHM (3 << 9)
#define DXCCR_DQSNRES_500_OHM (4 << 9)
#define DXCCR_DQSNRES_458_OHM (5 << 9)
#define DXCCR_DQSNRES_393_OHM (6 << 9)
#define DXCCR_DQSNRES_344_OHM (7 << 9)
#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
#define DTCR_DTMPR BIT(6) /* Data Training using MPR */
#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */
#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT))
#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
/* SoC-specific parameters */
#define NR_DATX8_PER_DDRPHY 2
#ifndef __ASSEMBLY__
int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
bool ddr3plus);
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
int ddrphy_training(struct ddrphy __iomem *phy);
#endif
#endif /* ARCH_DDRPHY_REGS_H */

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u-boot/arch/arm/mach-uniphier/dram/ddrphy-training.c Normal file
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/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include "ddrphy-regs.h"
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
{
int dx;
u32 __iomem tmp, *p;
for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
p = &phy->dx[dx].gcr;
tmp = readl(p);
/* Specify the rank that should be write leveled */
tmp &= ~DXGCR_WLRKEN_MASK;
tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
writel(tmp, p);
}
p = &phy->dtcr;
tmp = readl(p);
/* Specify the rank used during data bit deskew and eye centering */
tmp &= ~DTCR_DTRANK_MASK;
tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
/* Use Multi-Purpose Register for DQS gate training */
tmp |= DTCR_DTMPR;
/* Specify the rank enabled for data-training */
tmp &= ~DTCR_RANKEN_MASK;
tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK;
writel(tmp, p);
}
struct ddrphy_init_sequence {
char *description;
u32 init_flag;
u32 done_flag;
u32 err_flag;
};
static const struct ddrphy_init_sequence init_sequence[] = {
{
"DRAM Initialization",
PIR_DRAMRST | PIR_DRAMINIT,
PGSR0_DIDONE,
PGSR0_DIERR
},
{
"Write Leveling",
PIR_WL,
PGSR0_WLDONE,
PGSR0_WLERR
},
{
"Read DQS Gate Training",
PIR_QSGATE,
PGSR0_QSGDONE,
PGSR0_QSGERR
},
{
"Write Leveling Adjustment",
PIR_WLADJ,
PGSR0_WLADONE,
PGSR0_WLAERR
},
{
"Read Bit Deskew",
PIR_RDDSKW,
PGSR0_RDDONE,
PGSR0_RDERR
},
{
"Write Bit Deskew",
PIR_WRDSKW,
PGSR0_WDDONE,
PGSR0_WDERR
},
{
"Read Eye Training",
PIR_RDEYE,
PGSR0_REDONE,
PGSR0_REERR
},
{
"Write Eye Training",
PIR_WREYE,
PGSR0_WEDONE,
PGSR0_WEERR
}
};
int ddrphy_training(struct ddrphy __iomem *phy)
{
int i;
u32 pgsr0;
u32 init_flag = PIR_INIT;
u32 done_flag = PGSR0_IDONE;
int timeout = 50000; /* 50 msec is long enough */
#ifdef DISPLAY_ELAPSED_TIME
ulong start = get_timer(0);
#endif
for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
init_flag |= init_sequence[i].init_flag;
done_flag |= init_sequence[i].done_flag;
}
writel(init_flag, &phy->pir);
do {
if (--timeout < 0) {
printf("%s: error: timeout during DDR training\n",
__func__);
return -ETIMEDOUT;
}
udelay(1);
pgsr0 = readl(&phy->pgsr[0]);
} while ((pgsr0 & done_flag) != done_flag);
for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
if (pgsr0 & init_sequence[i].err_flag) {
printf("%s: error: %s failed\n", __func__,
init_sequence[i].description);
return -EIO;
}
}
#ifdef DISPLAY_ELAPSED_TIME
printf("%s: info: elapsed time %ld msec\n", get_timer(start));
#endif
return 0;
}

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u-boot/arch/arm/mach-uniphier/dram/umc-ld11.c Normal file
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/*
* Copyright (C) 2016 Socionext Inc.
*/
#include <common.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <asm/processor.h>
#include "../init.h"
#include "umc64-regs.h"
#define CONFIG_DDR_FREQ 1866
#define DRAM_CH_NR 2
enum dram_freq {
DRAM_FREQ_1600M,
DRAM_FREQ_NR,
};
enum dram_size {
DRAM_SZ_256M,
DRAM_SZ_512M,
DRAM_SZ_NR,
};
/* umc */
static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D};
static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810};
static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810};
static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004};
static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004};
static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
unsigned long size, int ch)
{
writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
writel(0x00000003, dc_base + UMC_ACSSETA);
writel(0x00000103, dc_base + UMC_FLOWCTLG);
writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
writel(0x02020200, dc_base + UMC_SPCSETB);
writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
return 0;
}
static int umc_ch_init(void __iomem *umc_ch_base,
enum dram_freq freq, unsigned long size, int ch)
{
void __iomem *dc_base = umc_ch_base;
return umc_dc_init(dc_base, freq, size, ch);
}
static void um_init(void __iomem *um_base)
{
writel(0x00000001, um_base + UMC_SIORST);
writel(0x00000001, um_base + UMC_VO0RST);
writel(0x00000001, um_base + UMC_VPERST);
writel(0x00000001, um_base + UMC_RGLRST);
writel(0x00000001, um_base + UMC_A2DRST);
writel(0x00000001, um_base + UMC_DMDRST);
}
int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *um_base = (void __iomem *)0x5B800000;
void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
enum dram_freq freq;
int ch, ret;
switch (bd->dram_freq) {
case 1600:
freq = DRAM_FREQ_1600M;
break;
default:
pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
return -EINVAL;
}
for (ch = 0; ch < bd->dram_nr_ch; ch++) {
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
if (ret) {
pr_err("failed to initialize UMC ch%d\n", ch);
return ret;
}
umc_ch_base += 0x00200000;
}
um_init(um_base);
return 0;
}

306
u-boot/arch/arm/mach-uniphier/dram/umc-ld20.c Normal file
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/*
* Copyright (C) 2016 Socionext Inc.
*
* based on commit f7a4c9efe333fb1536efa86f9e96dc0ee109fedd of Diag
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <asm/processor.h>
#include "../init.h"
#include "ddrphy-ld20-regs.h"
#include "umc64-regs.h"
#define DRAM_CH_NR 3
enum dram_freq {
DRAM_FREQ_1866M,
DRAM_FREQ_NR,
};
enum dram_size {
DRAM_SZ_256M,
DRAM_SZ_512M,
DRAM_SZ_NR,
};
/* umc */
static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
static u32 umc_memconf0a[DRAM_FREQ_NR] = {0x00000801};
static u32 umc_memconf0b[DRAM_FREQ_NR] = {0x00000130};
static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00033803};
static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
{0x0049071D, 0x0078071D},
};
static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610};
static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610};
static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204};
static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204};
static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
static u32 umc_directbusctrla[DRAM_CH_NR] = {
0x00000000, 0x00000001, 0x00000001
};
/* DDR PHY */
static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
{
writel(0x00000001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
while ((readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
cpu_relax();
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
writel(0x00000000, phy_base + PHY_LANE_SEL);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
writel(0x00000006, phy_base + PHY_LANE_SEL);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
writel(0x0000000c, phy_base + PHY_LANE_SEL);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
writel(0x00000012, phy_base + PHY_LANE_SEL);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM);
writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1);
writel(0x50bb40b1, phy_base + PHY_PAD_CTRL);
writel(0x00000070, phy_base + PHY_VREF_TRAINING);
writel(0x01000075, phy_base + PHY_SCL_CONFIG_1);
writel(0x00000501, phy_base + PHY_SCL_CONFIG_2);
writel(0x00000000, phy_base + PHY_SCL_CONFIG_3);
writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
writel(0x00000000, phy_base + PHY_SCL_CONFIG_4);
writel(0x000000a0, phy_base + PHY_SCL_GATE_TIMING);
writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT);
writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF);
writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL);
writel(0x00000000, phy_base + PHY_LANE_SEL);
writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK);
writel(0xa800100d, phy_base + PHY_DLL_RECALIB);
writel(0x00005076, phy_base + PHY_SCL_LATENCY);
}
static int ddrphy_training(void __iomem *phy_base)
{
writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM);
writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
writel(0x50000000, phy_base + PHY_SCL_START);
while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
cpu_relax();
writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
writel(0xff00ff00, phy_base + PHY_SCL_DATA_0);
writel(0xff00ff00, phy_base + PHY_SCL_DATA_1);
writel(0x00080000, phy_base + PHY_SCL_START_ADDR);
writel(0x11000000, phy_base + PHY_SCL_START);
while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
cpu_relax();
writel(0x00000000, phy_base + PHY_SCL_START_ADDR);
writel(0x30500000, phy_base + PHY_SCL_START);
while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
cpu_relax();
writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA);
writel(0x789b3de0, phy_base + PHY_SCL_DATA_0);
writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
writel(0x11000000, phy_base + PHY_SCL_START);
while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
cpu_relax();
writel(0x34000000, phy_base + PHY_SCL_START);
while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
cpu_relax();
writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
return 0;
}
static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
unsigned long size, int ch)
{
enum dram_size size_e;
switch (size) {
case 0:
return 0;
case SZ_256M:
size_e = DRAM_SZ_256M;
break;
case SZ_512M:
size_e = DRAM_SZ_512M;
break;
default:
pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
size, ch);
return -EINVAL;
}
/* Wait for PHY Init Complete */
while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
cpu_relax();
writel(0x00000001, dc_base + UMC_DFICSOVRRD);
writel(0x00000000, dc_base + UMC_DFITURNOFF);
writel(umc_initctla[freq], dc_base + UMC_INITCTLA);
writel(umc_initctlb[freq], dc_base + UMC_INITCTLB);
writel(umc_initctlc[freq], dc_base + UMC_INITCTLC);
writel(umc_drmmr0[freq], dc_base + UMC_DRMMR0);
writel(0x00000004, dc_base + UMC_DRMMR1);
writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2);
writel(0x00000000, dc_base + UMC_DRMMR3);
writel(umc_memconf0a[freq], dc_base + UMC_MEMCONF0A);
writel(umc_memconf0b[freq], dc_base + UMC_MEMCONF0B);
writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
writel(0x00000008, dc_base + UMC_MEMMAPSET);
writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
writel(umc_cmdctle[freq][size_e], dc_base + UMC_CMDCTLE);
writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
writel(umc_dataset[freq], dc_base + UMC_DATASET);
writel(0x00400020, dc_base + UMC_DCCGCTL);
writel(0x00000003, dc_base + UMC_ACSSETA);
writel(0x00000103, dc_base + UMC_FLOWCTLG);
writel(0x00010200, dc_base + UMC_ACSSETB);
writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
writel(0x00004444, dc_base + UMC_FLOWCTLC);
writel(0x00000000, dc_base + UMC_DFICUPDCTLA);
writel(0x00202000, dc_base + UMC_FLOWCTLB);
writel(0x00000000, dc_base + UMC_BSICMAPSET);
writel(0x00000000, dc_base + UMC_ERRMASKA);
writel(0x00000000, dc_base + UMC_ERRMASKB);
writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA);
writel(0x00000001, dc_base + UMC_INITSET);
/* Wait for PHY Init Complete */
while (readl(dc_base + UMC_INITSTAT) & BIT(0))
cpu_relax();
writel(0x2A0A0A00, dc_base + UMC_SPCSETB);
writel(0x00000000, dc_base + UMC_DFICSOVRRD);
return 0;
}
static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
enum dram_freq freq, unsigned long size, int ch)
{
void __iomem *dc_base = umc_ch_base + 0x00011000;
void __iomem *phy_base = phy_ch_base;
int ret;
/* PHY Update Mode (ON) */
writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA);
/* deassert PHY reset signals */
writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
dc_base + UMC_DIOCTLA);
ddrphy_init(phy_base, freq);
ret = umc_dc_init(dc_base, freq, size, ch);
if (ret)
return ret;
ret = ddrphy_training(phy_base);
if (ret)
return ret;
return 0;
}
static void um_init(void __iomem *um_base)
{
writel(0x000000ff, um_base + UMC_MBUS0);
writel(0x000000ff, um_base + UMC_MBUS1);
writel(0x000000ff, um_base + UMC_MBUS2);
writel(0x00000001, um_base + UMC_MBUS3);
writel(0x00000001, um_base + UMC_MBUS4);
writel(0x00000001, um_base + UMC_MBUS5);
writel(0x00000001, um_base + UMC_MBUS6);
writel(0x00000001, um_base + UMC_MBUS7);
writel(0x00000001, um_base + UMC_MBUS8);
writel(0x00000001, um_base + UMC_MBUS9);
writel(0x00000001, um_base + UMC_MBUS10);
}
int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *um_base = (void __iomem *)0x5b600000;
void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
void __iomem *phy_ch_base = (void __iomem *)0x6e200000;
enum dram_freq freq;
int ch, ret;
switch (bd->dram_freq) {
case 1866:
freq = DRAM_FREQ_1866M;
break;
default:
pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
return -EINVAL;
}
for (ch = 0; ch < bd->dram_nr_ch; ch++) {
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
ret = umc_ch_init(umc_ch_base, phy_ch_base, freq,
size / (width / 16), ch);
if (ret) {
pr_err("failed to initialize UMC ch%d\n", ch);
return ret;
}
umc_ch_base += 0x00200000;
phy_ch_base += 0x00004000;
}
um_init(um_base);
return 0;
}

191
u-boot/arch/arm/mach-uniphier/dram/umc-ld4.c Normal file
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/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <asm/processor.h>
#include "../init.h"
#include "ddrphy-regs.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
enum dram_freq {
DRAM_FREQ_1333M,
DRAM_FREQ_1600M,
DRAM_FREQ_NR,
};
enum dram_size {
DRAM_SZ_128M,
DRAM_SZ_256M,
DRAM_SZ_NR,
};
static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17};
static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24};
static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
{0x00240512, 0x00350512},
{0x002b0617, 0x003f0617},
};
static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};
static int umc_get_rank(int ch)
{
return ch; /* ch0: rank0, ch1: rank1 for this SoC */
}
static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
writel(0x000fffcf, ssif_base + 0x0000c008);
writel(0x00000001, ssif_base + 0x0000b000);
writel(0x00000001, ssif_base + 0x0000c000);
writel(0x03010101, ssif_base + UMC_MDMCHSEL);
writel(0x03010100, ssif_base + UMC_DMDCHSEL);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
writel(0x00000001, ssif_base + UMC_CPURST);
writel(0x00000001, ssif_base + UMC_IDSRST);
writel(0x00000001, ssif_base + UMC_IXMRST);
writel(0x00000001, ssif_base + UMC_MDMRST);
writel(0x00000001, ssif_base + UMC_MDDRST);
writel(0x00000001, ssif_base + UMC_SIORST);
writel(0x00000001, ssif_base + UMC_VIORST);
writel(0x00000001, ssif_base + UMC_FRCRST);
writel(0x00000001, ssif_base + UMC_RGLRST);
writel(0x00000001, ssif_base + UMC_AIORST);
writel(0x00000001, ssif_base + UMC_DMDRST);
}
static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
int freq, unsigned long size, bool ddr3plus)
{
enum dram_freq freq_e;
enum dram_size size_e;
if (!ddr3plus) {
pr_err("DDR3 standard is not supported\n");
return -EINVAL;
}
switch (freq) {
case 1333:
freq_e = DRAM_FREQ_1333M;
break;
case 1600:
freq_e = DRAM_FREQ_1600M;
break;
default:
pr_err("unsupported DRAM frequency %d MHz\n", freq);
return -EINVAL;
}
switch (size) {
case 0:
return 0;
case SZ_128M:
size_e = DRAM_SZ_128M;
break;
case SZ_256M:
size_e = DRAM_SZ_256M;
break;
default:
pr_err("unsupported DRAM size 0x%08lx\n", size);
return -EINVAL;
}
writel(umc_cmdctla_plus[freq_e], dc_base + UMC_CMDCTLA);
writel(umc_cmdctlb_plus[freq_e], dc_base + UMC_CMDCTLB);
writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
writel(0x04060806, dc_base + UMC_WDATACTL_D0);
writel(0x04a02000, dc_base + UMC_DATASET);
writel(0x00000000, ca_base + 0x2300);
writel(0x00400020, dc_base + UMC_DCCGCTL);
writel(0x00000003, dc_base + 0x7000);
writel(0x0000000f, dc_base + 0x8000);
writel(0x000000c3, dc_base + 0x8004);
writel(0x00000071, dc_base + 0x8008);
writel(0x0000003b, dc_base + UMC_DICGCTLA);
writel(0x020a0808, dc_base + UMC_DICGCTLB);
writel(0x00000004, dc_base + UMC_FLOWCTLG);
writel(0x80000201, ca_base + 0xc20);
writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
writel(0x00200000, dc_base + UMC_FLOWCTLB);
writel(0x00004444, dc_base + UMC_FLOWCTLC);
writel(0x200a0a00, dc_base + UMC_SPCSETB);
writel(0x00000000, dc_base + UMC_SPCSETD);
writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
return 0;
}
static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
int freq, unsigned long size, bool ddr3plus, int ch)
{
void __iomem *phy_base = dc_base + 0x00001000;
int ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
cpu_relax();
writel(0x00000101, dc_base + UMC_DIOCTLA);
ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
if (ret)
return ret;
ddrphy_prepare_training(phy_base, umc_get_rank(ch));
ret = ddrphy_training(phy_base);
if (ret)
return ret;
return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
}
int uniphier_ld4_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *umc_base = (void __iomem *)0x5b800000;
void __iomem *ca_base = umc_base + 0x00001000;
void __iomem *dc_base = umc_base + 0x00400000;
void __iomem *ssif_base = umc_base;
int ch, ret;
for (ch = 0; ch < DRAM_CH_NR; ch++) {
ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
bd->dram_ch[ch].size,
bd->dram_ddr3plus, ch);
if (ret) {
pr_err("failed to initialize UMC ch%d\n", ch);
return ret;
}
ca_base += 0x00001000;
dc_base += 0x00200000;
}
umc_start_ssif(ssif_base);
return 0;
}

186
u-boot/arch/arm/mach-uniphier/dram/umc-pro4.c Normal file
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/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <asm/processor.h>
#include "../init.h"
#include "ddrphy-regs.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
enum dram_size {
DRAM_SZ_128M,
DRAM_SZ_256M,
DRAM_SZ_512M,
DRAM_SZ_NR,
};
static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
writel(0x000fffcf, ssif_base + 0x0000c008);
writel(0x00000001, ssif_base + 0x0000b000);
writel(0x00000001, ssif_base + 0x0000c000);
writel(0x03010100, ssif_base + UMC_HDMCHSEL);
writel(0x03010101, ssif_base + UMC_MDMCHSEL);
writel(0x03010100, ssif_base + UMC_DVCCHSEL);
writel(0x03010100, ssif_base + UMC_DMDCHSEL);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
writel(0x00000001, ssif_base + UMC_CPURST);
writel(0x00000001, ssif_base + UMC_IDSRST);
writel(0x00000001, ssif_base + UMC_IXMRST);
writel(0x00000001, ssif_base + UMC_HDMRST);
writel(0x00000001, ssif_base + UMC_MDMRST);
writel(0x00000001, ssif_base + UMC_HDDRST);
writel(0x00000001, ssif_base + UMC_MDDRST);
writel(0x00000001, ssif_base + UMC_SIORST);
writel(0x00000001, ssif_base + UMC_GIORST);
writel(0x00000001, ssif_base + UMC_HD2RST);
writel(0x00000001, ssif_base + UMC_VIORST);
writel(0x00000001, ssif_base + UMC_DVCRST);
writel(0x00000001, ssif_base + UMC_RGLRST);
writel(0x00000001, ssif_base + UMC_VPERST);
writel(0x00000001, ssif_base + UMC_AIORST);
writel(0x00000001, ssif_base + UMC_DMDRST);
}
static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
int freq, unsigned long size, bool ddr3plus)
{
enum dram_size size_e;
if (freq != 1600) {
pr_err("Unsupported DDR frequency %d MHz\n", freq);
return -EINVAL;
}
if (ddr3plus) {
pr_err("DDR3+ is not supported\n");
return -EINVAL;
}
switch (size) {
case SZ_128M:
size_e = DRAM_SZ_128M;
break;
case SZ_256M:
size_e = DRAM_SZ_256M;
break;
case SZ_512M:
size_e = DRAM_SZ_512M;
break;
default:
pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size);
return -EINVAL;
}
writel(0x66bb0f17, dc_base + UMC_CMDCTLA);
writel(0x18c6aa44, dc_base + UMC_CMDCTLB);
writel(umc_spcctla[size_e], dc_base + UMC_SPCCTLA);
writel(0x00ff0008, dc_base + UMC_SPCCTLB);
writel(0x000c00ae, dc_base + UMC_RDATACTL_D0);
writel(0x000c00ae, dc_base + UMC_RDATACTL_D1);
writel(0x04060802, dc_base + UMC_WDATACTL_D0);
writel(0x04060802, dc_base + UMC_WDATACTL_D1);
writel(0x04a02000, dc_base + UMC_DATASET);
writel(0x00000000, ca_base + 0x2300);
writel(0x00400020, dc_base + UMC_DCCGCTL);
writel(0x0000000f, dc_base + 0x7000);
writel(0x0000000f, dc_base + 0x8000);
writel(0x000000c3, dc_base + 0x8004);
writel(0x00000071, dc_base + 0x8008);
writel(0x00000004, dc_base + UMC_FLOWCTLG);
writel(0x00000000, dc_base + 0x0060);
writel(0x80000201, ca_base + 0xc20);
writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
writel(0x00200000, dc_base + UMC_FLOWCTLB);
writel(0x00004444, dc_base + UMC_FLOWCTLC);
writel(0x200a0a00, dc_base + UMC_SPCSETB);
writel(0x00010000, dc_base + UMC_SPCSETD);
writel(0x80000020, dc_base + UMC_DFICUPDCTLA);
return 0;
}
static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
int freq, unsigned long size, unsigned int width,
bool ddr3plus)
{
void __iomem *phy_base = dc_base + 0x00001000;
int nr_phy = width / 16;
int phy, ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
cpu_relax();
for (phy = 0; phy < nr_phy; phy++) {
writel(0x00000100 | ((1 << (phy + 1)) - 1),
dc_base + UMC_DIOCTLA);
ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
if (ret)
return ret;
ddrphy_prepare_training(phy_base, phy);
ret = ddrphy_training(phy_base);
if (ret)
return ret;
phy_base += 0x00001000;
}
return umc_dramcont_init(dc_base, ca_base, freq, size / (width / 16),
ddr3plus);
}
int uniphier_pro4_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *umc_base = (void __iomem *)0x5b800000;
void __iomem *ca_base = umc_base + 0x00001000;
void __iomem *dc_base = umc_base + 0x00400000;
void __iomem *ssif_base = umc_base;
int ch, ret;
for (ch = 0; ch < DRAM_CH_NR; ch++) {
ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
bd->dram_ch[ch].size,
bd->dram_ch[ch].width,
bd->dram_ddr3plus);
if (ret) {
pr_err("failed to initialize UMC ch%d\n", ch);
return ret;
}
ca_base += 0x00001000;
dc_base += 0x00200000;
}
umc_start_ssif(ssif_base);
return 0;
}

637
u-boot/arch/arm/mach-uniphier/dram/umc-pxs2.c Normal file
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/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by:
* Copyright (C) 2015 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <asm/processor.h>
#include "../init.h"
#include "../soc-info.h"
#include "ddrmphy-regs.h"
#include "umc-regs.h"
#define DRAM_CH_NR 3
enum dram_freq {
DRAM_FREQ_1866M,
DRAM_FREQ_2133M,
DRAM_FREQ_NR,
};
enum dram_size {
DRAM_SZ_256M,
DRAM_SZ_512M,
DRAM_SZ_NR,
};
static u32 ddrphy_pgcr2[DRAM_FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x15171e45, 0x18182357};
static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x0e9ad8e9, 0x10b34157};
static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x35a00d88, 0x39e40e88};
static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x2288cc2c, 0x228a04d0};
static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x50005e00, 0x50006a00};
static u32 ddrphy_dtpr3[DRAM_FREQ_NR] = {0x0010cb49, 0x0010ec89};
static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000115, 0x00000125};
static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x000002a0, 0x000002a8};
/* dependent on package and board design */
static u32 ddrphy_acbdlr0[DRAM_CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};
static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722};
/*
* The ch2 is a different generation UMC core.
* The register spec is different, unfortunately.
*/
static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44};
static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
{0x004A071D, 0x0078071D},
{0x0055081E, 0x0089081E},
};
static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
/* The ch2 is different for some reason only hardware guys know... */
static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
/* DDR multiPHY */
static inline int ddrphy_get_rank(int dx)
{
return dx / 2;
}
static void ddrphy_fifo_reset(void __iomem *phy_base)
{
u32 tmp;
tmp = readl(phy_base + DMPHY_PGCR0);
tmp &= ~DMPHY_PGCR0_PHYFRST;
writel(tmp, phy_base + DMPHY_PGCR0);
udelay(1);
tmp |= DMPHY_PGCR0_PHYFRST;
writel(tmp, phy_base + DMPHY_PGCR0);
udelay(1);
}
static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
{
u32 tmp;
tmp = readl(phy_base + DMPHY_PGCR1);
if (enable)
tmp &= ~DMPHY_PGCR1_INHVT;
else
tmp |= DMPHY_PGCR1_INHVT;
writel(tmp, phy_base + DMPHY_PGCR1);
if (!enable) {
while (!(readl(phy_base + DMPHY_PGSR1) & DMPHY_PGSR1_VTSTOP))
cpu_relax();
}
}
static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
{
int dx;
u32 lcdlr1, rdqsd;
void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
ddrphy_vt_ctrl(phy_base, 0);
for (dx = 0; dx < nr_dx; dx++) {
lcdlr1 = readl(dx_base + DMPHY_DX_LCDLR1);
rdqsd = (lcdlr1 >> 8) & 0xff;
rdqsd = clamp(rdqsd + step, 0U, 0xffU);
lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
writel(lcdlr1, dx_base + DMPHY_DX_LCDLR1);
readl(dx_base + DMPHY_DX_LCDLR1); /* relax */
dx_base += DMPHY_DX_STRIDE;
}
ddrphy_vt_ctrl(phy_base, 1);
}
static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
{
void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
const int nr_dx = width / 8;
int dx, rank;
u32 gtr;
int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
for (dx = 0; dx < nr_dx; dx++) {
gtr = readl(dx_base + DMPHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
dgsl = gtr & 0x7;
/* if dgsl is zero, this rank was not trained. skip. */
if (dgsl) {
dgsl_min = min(dgsl_min, dgsl);
dgsl_max = max(dgsl_max, dgsl);
}
gtr >>= 3;
}
dx_base += DMPHY_DX_STRIDE;
}
if (dgsl_min != dgsl_max)
printf("DQS Gateing System Latencies are not all leveled.\n");
return dgsl_max;
}
static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width,
int ch)
{
u32 tmp;
void __iomem *zq_base, *dx_base;
int zq, dx;
int nr_dx;
nr_dx = width / 8;
writel(DMPHY_PIR_ZCALBYP, phy_base + DMPHY_PIR);
/*
* Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
* to avoid read error issue.
*/
writel(0x07d81e37, phy_base + DMPHY_PGCR0);
writel(0x0200c4e0, phy_base + DMPHY_PGCR1);
tmp = ddrphy_pgcr2[freq];
if (width >= 32)
tmp |= DMPHY_PGCR2_DUALCHN | DMPHY_PGCR2_ACPDDC;
writel(tmp, phy_base + DMPHY_PGCR2);
writel(ddrphy_ptr0[freq], phy_base + DMPHY_PTR0);
writel(ddrphy_ptr1[freq], phy_base + DMPHY_PTR1);
writel(0x00083def, phy_base + DMPHY_PTR2);
writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3);
writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4);
writel(ddrphy_acbdlr0[ch], phy_base + DMPHY_ACBDLR0);
writel(0x55555555, phy_base + DMPHY_ACIOCR1);
writel(0x00000000, phy_base + DMPHY_ACIOCR2);
writel(0x55555555, phy_base + DMPHY_ACIOCR3);
writel(0x00000000, phy_base + DMPHY_ACIOCR4);
writel(0x00000055, phy_base + DMPHY_ACIOCR5);
writel(0x00181aa4, phy_base + DMPHY_DXCCR);
writel(0x0024641e, phy_base + DMPHY_DSGCR);
writel(0x0000040b, phy_base + DMPHY_DCR);
writel(ddrphy_dtpr0[freq], phy_base + DMPHY_DTPR0);
writel(ddrphy_dtpr1[freq], phy_base + DMPHY_DTPR1);
writel(ddrphy_dtpr2[freq], phy_base + DMPHY_DTPR2);
writel(ddrphy_dtpr3[freq], phy_base + DMPHY_DTPR3);
writel(ddrphy_mr0[freq], phy_base + DMPHY_MR0);
writel(0x00000006, phy_base + DMPHY_MR1);
writel(ddrphy_mr2[freq], phy_base + DMPHY_MR2);
writel(0x00000000, phy_base + DMPHY_MR3);
tmp = 0;
for (dx = 0; dx < nr_dx; dx++)
tmp |= BIT(DMPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
writel(0x90003087 | tmp, phy_base + DMPHY_DTCR);
writel(0x00000000, phy_base + DMPHY_DTAR0);
writel(0x00000008, phy_base + DMPHY_DTAR1);
writel(0x00000010, phy_base + DMPHY_DTAR2);
writel(0x00000018, phy_base + DMPHY_DTAR3);
writel(0xdd22ee11, phy_base + DMPHY_DTDR0);
writel(0x7788bb44, phy_base + DMPHY_DTDR1);
/* impedance control settings */
writel(0x04048900, phy_base + DMPHY_ZQCR);
zq_base = phy_base + DMPHY_ZQ_BASE;
for (zq = 0; zq < 4; zq++) {
/*
* board-dependent
* PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
*/
writel(0x0007BB5D, zq_base + DMPHY_ZQ_PR);
zq_base += DMPHY_ZQ_STRIDE;
}
/* DATX8 settings */
dx_base = phy_base + DMPHY_DX_BASE;
for (dx = 0; dx < 4; dx++) {
tmp = readl(dx_base + DMPHY_DX_GCR0);
tmp &= ~DMPHY_DX_GCR0_WLRKEN_MASK;
tmp |= BIT(DMPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
DMPHY_DX_GCR0_WLRKEN_MASK;
writel(tmp, dx_base + DMPHY_DX_GCR0);
writel(0x00000000, dx_base + DMPHY_DX_GCR1);
writel(0x00000000, dx_base + DMPHY_DX_GCR2);
writel(0x00000000, dx_base + DMPHY_DX_GCR3);
dx_base += DMPHY_DX_STRIDE;
}
while (!(readl(phy_base + DMPHY_PGSR0) & DMPHY_PGSR0_IDONE))
cpu_relax();
ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
}
struct ddrphy_init_sequence {
char *description;
u32 init_flag;
u32 done_flag;
u32 err_flag;
};
static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
{
"Impedance Calibration",
DMPHY_PIR_ZCAL,
DMPHY_PGSR0_ZCDONE,
DMPHY_PGSR0_ZCERR,
},
{ /* sentinel */ }
};
static const struct ddrphy_init_sequence dram_init_sequence[] = {
{
"DRAM Initialization",
DMPHY_PIR_DRAMRST | DMPHY_PIR_DRAMINIT,
DMPHY_PGSR0_DIDONE,
0,
},
{ /* sentinel */ }
};
static const struct ddrphy_init_sequence training_sequence[] = {
{
"Write Leveling",
DMPHY_PIR_WL,
DMPHY_PGSR0_WLDONE,
DMPHY_PGSR0_WLERR,
},
{
"Read DQS Gate Training",
DMPHY_PIR_QSGATE,
DMPHY_PGSR0_QSGDONE,
DMPHY_PGSR0_QSGERR,
},
{
"Write Leveling Adjustment",
DMPHY_PIR_WLADJ,
DMPHY_PGSR0_WLADONE,
DMPHY_PGSR0_WLAERR,
},
{
"Read Bit Deskew",
DMPHY_PIR_RDDSKW,
DMPHY_PGSR0_RDDONE,
DMPHY_PGSR0_RDERR,
},
{
"Write Bit Deskew",
DMPHY_PIR_WRDSKW,
DMPHY_PGSR0_WDDONE,
DMPHY_PGSR0_WDERR,
},
{
"Read Eye Training",
DMPHY_PIR_RDEYE,
DMPHY_PGSR0_REDONE,
DMPHY_PGSR0_REERR,
},
{
"Write Eye Training",
DMPHY_PIR_WREYE,
DMPHY_PGSR0_WEDONE,
DMPHY_PGSR0_WEERR,
},
{ /* sentinel */ }
};
static int __ddrphy_training(void __iomem *phy_base,
const struct ddrphy_init_sequence *seq)
{
const struct ddrphy_init_sequence *s;
u32 pgsr0;
u32 init_flag = DMPHY_PIR_INIT;
u32 done_flag = DMPHY_PGSR0_IDONE;
int timeout = 50000; /* 50 msec is long enough */
#ifdef DISPLAY_ELAPSED_TIME
ulong start = get_timer(0);
#endif
for (s = seq; s->description; s++) {
init_flag |= s->init_flag;
done_flag |= s->done_flag;
}
writel(init_flag, phy_base + DMPHY_PIR);
do {
if (--timeout < 0) {
pr_err("%s: error: timeout during DDR training\n",
__func__);
return -ETIMEDOUT;
}
udelay(1);
pgsr0 = readl(phy_base + DMPHY_PGSR0);
} while ((pgsr0 & done_flag) != done_flag);
for (s = seq; s->description; s++) {
if (pgsr0 & s->err_flag) {
pr_err("%s: error: %s failed\n", __func__,
s->description);
return -EIO;
}
}
#ifdef DISPLAY_ELAPSED_TIME
printf("%s: info: elapsed time %ld msec\n", get_timer(start));
#endif
return 0;
}
static int ddrphy_impedance_calibration(void __iomem *phy_base)
{
int ret;
u32 tmp;
ret = __ddrphy_training(phy_base, impedance_calibration_sequence);
if (ret)
return ret;
/*
* Because of a hardware bug, IDONE flag is set when the first ZQ block
* is calibrated. The flag does not guarantee the completion for all
* the ZQ blocks. Wait a little more just in case.
*/
udelay(1);
/* reflect ZQ settings and enable average algorithm*/
tmp = readl(phy_base + DMPHY_ZQCR);
tmp |= DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
writel(tmp, phy_base + DMPHY_ZQCR);
tmp &= ~DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
tmp |= DMPHY_ZQCR_AVGEN;
writel(tmp, phy_base + DMPHY_ZQCR);
return 0;
}
static int ddrphy_dram_init(void __iomem *phy_base)
{
return __ddrphy_training(phy_base, dram_init_sequence);
}
static int ddrphy_training(void __iomem *phy_base)
{
return __ddrphy_training(phy_base, training_sequence);
}
/* UMC */
static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
{
u32 val;
int latency;
val = readl(dc_base + UMC_RDATACTL_D0);
latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT;
latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >>
UMC_RDATACTL_RAD2LTY_SHIFT;
/*
* UMC works at the half clock rate of the PHY.
* The LSB of latency is ignored
*/
latency += phy_latency & ~1;
val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK);
if (latency > 0xf) {
val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
} else {
val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
}
writel(val, dc_base + UMC_RDATACTL_D0);
writel(val, dc_base + UMC_RDATACTL_D1);
readl(dc_base + UMC_RDATACTL_D1); /* relax */
}
/* enable/disable auto refresh */
void umc_refresh_ctrl(void __iomem *dc_base, int enable)
{
u32 tmp;
tmp = readl(dc_base + UMC_SPCSETB);
tmp &= ~UMC_SPCSETB_AREFMD_MASK;
if (enable)
tmp |= UMC_SPCSETB_AREFMD_ARB;
else
tmp |= UMC_SPCSETB_AREFMD_REG;
writel(tmp, dc_base + UMC_SPCSETB);
udelay(1);
}
static void umc_ud_init(void __iomem *umc_base, int ch)
{
writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0);
if (ch == 2)
writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);
}
static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
unsigned long size, int width, int ch)
{
enum dram_size size_e;
int latency;
u32 val;
switch (size) {
case 0:
return 0;
case SZ_256M:
size_e = DRAM_SZ_256M;
break;
case SZ_512M:
size_e = DRAM_SZ_512M;
break;
default:
pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
size, ch);
return -EINVAL;
}
writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq],
dc_base + UMC_CMDCTLB);
writel(umc_spcctla[freq][size_e], dc_base + UMC_SPCCTLA);
writel(umc_spcctlb[freq], dc_base + UMC_SPCCTLB);
val = 0x000e000e;
latency = 12;
/* ES2 inserted one more FF to the logic. */
if (uniphier_get_soc_model() >= 2)
latency += 2;
if (latency > 0xf) {
val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
} else {
val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
}
writel(val, dc_base + UMC_RDATACTL_D0);
if (width >= 32)
writel(val, dc_base + UMC_RDATACTL_D1);
writel(0x04060A02, dc_base + UMC_WDATACTL_D0);
if (width >= 32)
writel(0x04060A02, dc_base + UMC_WDATACTL_D1);
writel(0x04000000, dc_base + UMC_DATASET);
writel(0x00400020, dc_base + UMC_DCCGCTL);
writel(0x00000084, dc_base + UMC_FLOWCTLG);
writel(0x00000000, dc_base + UMC_ACSSETA);
writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq],
dc_base + UMC_FLOWCTLA);
writel(0x00004400, dc_base + UMC_FLOWCTLC);
writel(0x200A0A00, dc_base + UMC_SPCSETB);
writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
writel(0x0000000D, dc_base + UMC_RESPCTL);
if (ch != 2) {
writel(0x00202000, dc_base + UMC_FLOWCTLB);
writel(0xFDBFFFFF, dc_base + UMC_FLOWCTLOB0);
writel(0xFFFFFFFF, dc_base + UMC_FLOWCTLOB1);
writel(0x00080700, dc_base + UMC_BSICMAPSET);
} else {
writel(0x00200000, dc_base + UMC_FLOWCTLB);
writel(0x00000000, dc_base + UMC_BSICMAPSET);
}
writel(0x00000000, dc_base + UMC_ERRMASKA);
writel(0x00000000, dc_base + UMC_ERRMASKB);
return 0;
}
static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq,
unsigned long size, unsigned int width, int ch)
{
void __iomem *dc_base = umc_ch_base + 0x00011000;
void __iomem *phy_base = umc_ch_base + 0x00030000;
int ret;
writel(0x00000002, dc_base + UMC_INITSET);
while (readl(dc_base + UMC_INITSTAT) & BIT(2))
cpu_relax();
/* deassert PHY reset signals */
writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
dc_base + UMC_DIOCTLA);
ddrphy_init(phy_base, freq, width, ch);
ret = ddrphy_impedance_calibration(phy_base);
if (ret)
return ret;
ddrphy_dram_init(phy_base);
if (ret)
return ret;
ret = umc_dc_init(dc_base, freq, size, width, ch);
if (ret)
return ret;
umc_ud_init(umc_ch_base, ch);
ret = ddrphy_training(phy_base);
if (ret)
return ret;
udelay(1);
/* match the system latency between UMC and PHY */
umc_set_system_latency(dc_base,
ddrphy_get_system_latency(phy_base, width));
udelay(1);
/* stop auto refresh before clearing FIFO in PHY */
umc_refresh_ctrl(dc_base, 0);
ddrphy_fifo_reset(phy_base);
umc_refresh_ctrl(dc_base, 1);
udelay(10);
return 0;
}
static void um_init(void __iomem *um_base)
{
writel(0x000000ff, um_base + UMC_MBUS0);
writel(0x000000ff, um_base + UMC_MBUS1);
writel(0x000000ff, um_base + UMC_MBUS2);
writel(0x000000ff, um_base + UMC_MBUS3);
}
int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *um_base = (void __iomem *)0x5b600000;
void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
enum dram_freq freq;
int ch, ret;
switch (bd->dram_freq) {
case 1866:
freq = DRAM_FREQ_1866M;
break;
case 2133:
freq = DRAM_FREQ_2133M;
break;
default:
pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
return -EINVAL;
}
for (ch = 0; ch < bd->dram_nr_ch; ch++) {
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
ret = umc_ch_init(umc_ch_base, freq, size / (width / 16),
width, ch);
if (ret) {
pr_err("failed to initialize UMC ch%d\n", ch);
return ret;
}
umc_ch_base += 0x00200000;
}
um_init(um_base);
return 0;
}

107
u-boot/arch/arm/mach-uniphier/dram/umc-regs.h Normal file
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/*
* UniPhier UMC (Universal Memory Controller) registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_UMC_REGS_H
#define ARCH_UMC_REGS_H
#include <linux/bitops.h>
#define UMC_CPURST 0x00000700
#define UMC_IDSRST 0x0000070C
#define UMC_IXMRST 0x00000714
#define UMC_HDMRST 0x00000718
#define UMC_MDMRST 0x0000071C
#define UMC_HDDRST 0x00000720
#define UMC_MDDRST 0x00000724
#define UMC_SIORST 0x00000728
#define UMC_GIORST 0x0000072C
#define UMC_HD2RST 0x00000734
#define UMC_VIORST 0x0000073C
#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
#define UMC_DVCRST 0x00000748 /* Pro4 */
#define UMC_RGLRST 0x00000750
#define UMC_VPERST 0x00000758
#define UMC_AIORST 0x00000764
#define UMC_DMDRST 0x00000770
#define UMC_HDMCHSEL 0x00000898
#define UMC_MDMCHSEL 0x0000089C
#define UMC_DVCCHSEL 0x000008C8
#define UMC_DMDCHSEL 0x000008F0
#define UMC_CLKEN_SSIF_FETCH 0x0000C060
#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
#define UMC_CLKEN_SSIF_WC 0x0000C07C
#define UMC_CLKEN_SSIF_RC 0x0000C080
#define UMC_CLKEN_SSIF_DST 0x0000C084
#define UMC_CMDCTLA 0x00000000
#define UMC_CMDCTLB 0x00000004
#define UMC_INITSET 0x00000014
#define UMC_INITSET_INIT1EN BIT(1) /* init without power-on wait */
#define UMC_INITSET_INIT0EN BIT(0) /* init with power-on wait */
#define UMC_INITSTAT 0x00000018
#define UMC_INITSTAT_INIT1ST BIT(1) /* init without power-on wait */
#define UMC_INITSTAT_INIT0ST BIT(0) /* init with power-on wait */
#define UMC_SPCCTLA 0x00000030
#define UMC_SPCCTLB 0x00000034
#define UMC_SPCSETA 0x00000038
#define UMC_SPCSETB 0x0000003C
#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
#define UMC_SPCSETC 0x00000040
#define UMC_SPCSETD 0x00000044
#define UMC_SPCSTATA 0x00000050
#define UMC_SPCSTATB 0x00000054
#define UMC_SPCSTATC 0x00000058
#define UMC_ACSSETA 0x00000060
#define UMC_FLOWCTLA 0x00000400
#define UMC_FLOWCTLB 0x00000404
#define UMC_FLOWCTLC 0x00000408
#define UMC_FLOWCTLG 0x00000508
#define UMC_FLOWCTLOB0 0x00000520
#define UMC_FLOWCTLOB1 0x00000524
#define UMC_RDATACTL_D0 0x00000600
#define UMC_RDATACTL_RADLTY_SHIFT 4
#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
#define UMC_RDATACTL_RAD2LTY_SHIFT 8
#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
#define UMC_WDATACTL_D0 0x00000604
#define UMC_RDATACTL_D1 0x00000608
#define UMC_WDATACTL_D1 0x0000060C
#define UMC_DATASET 0x00000610
#define UMC_RESPCTL 0x00000624
#define UMC_DCCGCTL 0x00000720
#define UMC_DICGCTLA 0x00000724
#define UMC_DICGCTLB 0x00000728
#define UMC_ERRMASKA 0x00000958
#define UMC_ERRMASKB 0x0000095c
#define UMC_BSICMAPSET 0x00000988
#define UMC_DIOCTLA 0x00000C00
#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
#define UMC_DFICUPDCTLA 0x00000C20
/* UM registers */
#define UMC_MBUS0 0x00080004
#define UMC_MBUS1 0x00081004
#define UMC_MBUS2 0x00082004
#define UMC_MBUS3 0x00083004
/* UD registers */
#define UMC_BITPERPIXELMODE_D0 0x010
#define UMC_PAIR1DOFF_D0 0x054
#endif

194
u-boot/arch/arm/mach-uniphier/dram/umc-sld8.c Normal file
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/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <asm/processor.h>
#include "../init.h"
#include "ddrphy-regs.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
enum dram_freq {
DRAM_FREQ_1333M,
DRAM_FREQ_1600M,
DRAM_FREQ_NR,
};
enum dram_size {
DRAM_SZ_128M,
DRAM_SZ_256M,
DRAM_SZ_512M,
DRAM_SZ_NR,
};
static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17};
static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17};
static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44};
static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24};
static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
{0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */
{0x002b0617, 0x003f0617, 0x00670617},
};
static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};
static int umc_get_rank(int ch)
{
return ch; /* ch0: rank0, ch1: rank1 for this SoC */
}
static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
writel(0x000fffcf, ssif_base + 0x0000c008);
writel(0x00000001, ssif_base + 0x0000b000);
writel(0x00000001, ssif_base + 0x0000c000);
writel(0x03010101, ssif_base + UMC_MDMCHSEL);
writel(0x03010100, ssif_base + UMC_DMDCHSEL);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
writel(0x00000001, ssif_base + UMC_CPURST);
writel(0x00000001, ssif_base + UMC_IDSRST);
writel(0x00000001, ssif_base + UMC_IXMRST);
writel(0x00000001, ssif_base + UMC_MDMRST);
writel(0x00000001, ssif_base + UMC_MDDRST);
writel(0x00000001, ssif_base + UMC_SIORST);
writel(0x00000001, ssif_base + UMC_VIORST);
writel(0x00000001, ssif_base + UMC_FRCRST);
writel(0x00000001, ssif_base + UMC_RGLRST);
writel(0x00000001, ssif_base + UMC_AIORST);
writel(0x00000001, ssif_base + UMC_DMDRST);
}
static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
int freq, unsigned long size, bool ddr3plus)
{
enum dram_freq freq_e;
enum dram_size size_e;
switch (freq) {
case 1333:
freq_e = DRAM_FREQ_1333M;
break;
case 1600:
freq_e = DRAM_FREQ_1600M;
break;
default:
pr_err("unsupported DRAM frequency %d MHz\n", freq);
return -EINVAL;
}
switch (size) {
case 0:
return 0;
case SZ_128M:
size_e = DRAM_SZ_128M;
break;
case SZ_256M:
size_e = DRAM_SZ_256M;
break;
case SZ_512M:
size_e = DRAM_SZ_512M;
break;
default:
pr_err("unsupported DRAM size 0x%08lx\n", size);
return -EINVAL;
}
writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e],
dc_base + UMC_CMDCTLA);
writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e],
dc_base + UMC_CMDCTLB);
writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
writel(0x04060806, dc_base + UMC_WDATACTL_D0);
writel(0x04a02000, dc_base + UMC_DATASET);
writel(0x00000000, ca_base + 0x2300);
writel(0x00400020, dc_base + UMC_DCCGCTL);
writel(0x00000003, dc_base + 0x7000);
writel(0x0000004f, dc_base + 0x8000);
writel(0x000000c3, dc_base + 0x8004);
writel(0x00000077, dc_base + 0x8008);
writel(0x0000003b, dc_base + UMC_DICGCTLA);
writel(0x020a0808, dc_base + UMC_DICGCTLB);
writel(0x00000004, dc_base + UMC_FLOWCTLG);
writel(0x80000201, ca_base + 0xc20);
writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
writel(0x00200000, dc_base + UMC_FLOWCTLB);
writel(0x00004444, dc_base + UMC_FLOWCTLC);
writel(0x200a0a00, dc_base + UMC_SPCSETB);
writel(0x00000000, dc_base + UMC_SPCSETD);
writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
return 0;
}
static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
int freq, unsigned long size, bool ddr3plus, int ch)
{
void __iomem *phy_base = dc_base + 0x00001000;
int ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
cpu_relax();
writel(0x00000101, dc_base + UMC_DIOCTLA);
ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
if (ret)
return ret;
ddrphy_prepare_training(phy_base, umc_get_rank(ch));
ret = ddrphy_training(phy_base);
if (ret)
return ret;
return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
}
int uniphier_sld8_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *umc_base = (void __iomem *)0x5b800000;
void __iomem *ca_base = umc_base + 0x00001000;
void __iomem *dc_base = umc_base + 0x00400000;
void __iomem *ssif_base = umc_base;
int ch, ret;
for (ch = 0; ch < DRAM_CH_NR; ch++) {
ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
bd->dram_ch[ch].size,
bd->dram_ddr3plus, ch);
if (ret) {
pr_err("failed to initialize UMC ch%d\n", ch);
return ret;
}
ca_base += 0x00001000;
dc_base += 0x00200000;
}
umc_start_ssif(ssif_base);
return 0;
}

85
u-boot/arch/arm/mach-uniphier/dram/umc64-regs.h Normal file
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/*
* Copyright (C) 2016 Socionext Inc.
*/
#ifndef UMC_LD20_REGS_H
#define UMC_LD20_REGS_H
#define UMC_CMDCTLA 0x00000000
#define UMC_CMDCTLB 0x00000004
#define UMC_CMDCTLC 0x00000008
#define UMC_INITCTLA 0x00000020
#define UMC_INITCTLB 0x00000024
#define UMC_INITCTLC 0x00000028
#define UMC_DRMMR0 0x00000030
#define UMC_DRMMR1 0x00000034
#define UMC_DRMMR2 0x00000038
#define UMC_DRMMR3 0x0000003C
#define UMC_INITSET 0x00000040
#define UMC_INITSTAT 0x00000044
#define UMC_CMDCTLE 0x00000050
#define UMC_CMDCTLF 0x00000054
#define UMC_CMDCTLG 0x00000058
#define UMC_SPCSETB 0x00000084
#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
#define UMC_ACSSETA 0x000000C0
#define UMC_ACSSETB 0x000000C4
#define UMC_MEMCONF0A 0x00000200
#define UMC_MEMCONF0B 0x00000204
#define UMC_MEMCONFCH 0x00000240
#define UMC_MEMMAPSET 0x00000250
#define UMC_FLOWCTLA 0x00000400
#define UMC_FLOWCTLB 0x00000404
#define UMC_FLOWCTLC 0x00000408
#define UMC_ACFETCHCTRL 0x00000460
#define UMC_FLOWCTLG 0x00000508
#define UMC_RDATACTL_D0 0x00000600
#define UMC_WDATACTL_D0 0x00000604
#define UMC_RDATACTL_D1 0x00000608
#define UMC_WDATACTL_D1 0x0000060C
#define UMC_DATASET 0x00000610
#define UMC_ODTCTL_D0 0x00000618
#define UMC_ODTCTL_D1 0x0000061C
#define UMC_RESPCTL 0x00000624
#define UMC_DIRECTBUSCTRLA 0x00000680
#define UMC_DEBUGC 0x00000718
#define UMC_DCCGCTL 0x00000720
#define UMC_DICGCTLA 0x00000724
#define UMC_DICGCTLB 0x00000728
#define UMC_ERRMASKA 0x00000958
#define UMC_ERRMASKB 0x0000095C
#define UMC_BSICMAPSET 0x00000988
#define UMC_DIOCTLA 0x00000C00
#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
#define UMC_DFISTCTLC 0x00000C18
#define UMC_DFICUPDCTLA 0x00000C20
#define UMC_DFIPUPDCTLA 0x00000C30
#define UMC_DFICSOVRRD 0x00000C84
#define UMC_DFITURNOFF 0x00000C88
/* UM registers */
#define UMC_MBUS0 0x00080004
#define UMC_MBUS1 0x00081004
#define UMC_MBUS2 0x00082004
#define UMC_MBUS3 0x00000C78
#define UMC_MBUS4 0x00000CF8
#define UMC_MBUS5 0x00000E78
#define UMC_MBUS6 0x00000EF8
#define UMC_MBUS7 0x00001278
#define UMC_MBUS8 0x000012F8
#define UMC_MBUS9 0x00002478
#define UMC_MBUS10 0x000024F8
/* UMC1 register */
#define UMC_SIORST 0x00000728
#define UMC_VO0RST 0x0000073c
#define UMC_VPERST 0x00000744
#define UMC_RGLRST 0x00000750
#define UMC_A2DRST 0x00000764
#define UMC_DMDRST 0x00000770
#endif /* UMC_LD20_REGS_H */