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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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44
u-boot/arch/arm/mach-tegra/tegra210/Kconfig Normal file
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if TEGRA210
choice
prompt "Tegra210 board select"
config TARGET_E2220_1170
bool "NVIDIA Tegra210 E2220-1170 board"
help
E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM,
eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various
expansion modules.
config TARGET_P2371_0000
bool "NVIDIA Tegra210 P2371-0000 board"
help
P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O
board. The combination contains SoC, DRAM, eMMC, SD card slot,
HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA,
a GPIO expansion header, and an analog audio jack.
config TARGET_P2371_2180
bool "NVIDIA Tegra210 P2371-2180 (Jetson TX1) board"
help
P2371-2180 (Jetson TX1 developer kit) is a P2180 CPU board married
to a P2597 I/O board. The combination contains SoC, DRAM, eMMC, SD
card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host
port, SATA, PCIe, and two GPIO expansion headers.
config TARGET_P2571
bool "NVIDIA Tegra210 P2571 base board"
help
P2571 is a P2530 married to a P1963 I/O board
endchoice
config SYS_SOC
default "tegra210"
source "board/nvidia/e2220-1170/Kconfig"
source "board/nvidia/p2371-0000/Kconfig"
source "board/nvidia/p2371-2180/Kconfig"
source "board/nvidia/p2571/Kconfig"
endif

12
u-boot/arch/arm/mach-tegra/tegra210/Makefile Normal file
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#
# (C) Copyright 2013-2015
# NVIDIA Corporation <www.nvidia.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += clock.o
obj-y += funcmux.o
obj-y += pinmux.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o

1227
u-boot/arch/arm/mach-tegra/tegra210/clock.c Normal file
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40
u-boot/arch/arm/mach-tegra/tegra210/funcmux.c Normal file
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/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra210 high-level function multiplexing */
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
int funcmux_select(enum periph_id id, int config)
{
int bad_config = config != FUNCMUX_DEFAULT;
switch (id) {
/*
* Add other periph IDs here as needed.
* Note that all pinmux/pads should have already
* been set up in the board pinmux table in
* pinmux-config-<board>.h for all periphs.
* Leave this in for the odd case where a mux
* needs to be changed on-the-fly.
*/
default:
debug("%s: invalid periph_id %d", __func__, id);
return -1;
}
if (bad_config) {
debug("%s: invalid config %d for periph_id %d", __func__,
config, id);
return -1;
}
return 0;
}

195
u-boot/arch/arm/mach-tegra/tegra210/pinmux.c Normal file
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/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/pinmux.h>
#define PIN(pin, f0, f1, f2, f3) \
{ \
.funcs = { \
PMUX_FUNC_##f0, \
PMUX_FUNC_##f1, \
PMUX_FUNC_##f2, \
PMUX_FUNC_##f3, \
}, \
}
#define PIN_RESERVED {}
static const struct pmux_pingrp_desc tegra210_pingroups[] = {
/* pin, f0, f1, f2, f3 */
/* Offset 0x3000 */
PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
PIN_RESERVED,
/* Offset 0x301c */
PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN_RESERVED,
/* Offset 0x3038 */
PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3),
PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3),
PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3),
PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3),
PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3),
PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3),
PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3),
PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3),
PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3),
PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3),
PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3),
PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3),
PIN_RESERVED,
/* Offset 0x30a4 */
PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3),
PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3),
PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3),
PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3),
PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3),
PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3),
PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3),
PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3),
PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3),
PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3),
PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3),
PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3),
PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3),
PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3),
PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3),
PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3),
PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART),
PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART),
PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART),
PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART),
PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3),
PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3),
PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3),
PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3),
PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3),
PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3),
PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3),
PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3),
PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3),
PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3),
PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3),
PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3),
PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3),
PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3),
PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3),
PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3),
PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3),
PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3),
PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3),
PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3),
PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3),
PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3),
PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3),
PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3),
PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3),
PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3),
PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3),
PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3),
PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3),
PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3),
PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3),
PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3),
PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3),
PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3),
PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3),
PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3),
PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1),
PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3),
PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(PA6, SATA, RSVD1, RSVD2, RSVD3),
PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3),
PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3),
PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(PL1, SOC, RSVD1, RSVD2, RSVD3),
PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3),
PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3),
PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3),
PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3),
PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3),
};
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;

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u-boot/arch/arm/mach-tegra/tegra210/xusb-padctl.c Normal file
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/*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0
*/
#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
#include <common.h>
#include <errno.h>
#include "../xusb-padctl-common.h"
#include <asm/arch/clock.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
enum tegra210_function {
TEGRA210_FUNC_SNPS,
TEGRA210_FUNC_XUSB,
TEGRA210_FUNC_UART,
TEGRA210_FUNC_PCIE_X1,
TEGRA210_FUNC_PCIE_X4,
TEGRA210_FUNC_USB3,
TEGRA210_FUNC_SATA,
TEGRA210_FUNC_RSVD,
};
static const char *const tegra210_functions[] = {
"snps",
"xusb",
"uart",
"pcie-x1",
"pcie-x4",
"usb3",
"sata",
"rsvd",
};
static const unsigned int tegra210_otg_functions[] = {
TEGRA210_FUNC_SNPS,
TEGRA210_FUNC_XUSB,
TEGRA210_FUNC_UART,
TEGRA210_FUNC_RSVD,
};
static const unsigned int tegra210_usb_functions[] = {
TEGRA210_FUNC_SNPS,
TEGRA210_FUNC_XUSB,
};
static const unsigned int tegra210_pci_functions[] = {
TEGRA210_FUNC_PCIE_X1,
TEGRA210_FUNC_USB3,
TEGRA210_FUNC_SATA,
TEGRA210_FUNC_PCIE_X4,
};
#define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
{ \
.name = _name, \
.offset = _offset, \
.shift = _shift, \
.mask = _mask, \
.iddq = _iddq, \
.num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions), \
.funcs = tegra210_##_funcs##_functions, \
}
static const struct tegra_xusb_padctl_lane tegra210_lanes[] = {
TEGRA210_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
TEGRA210_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
TEGRA210_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
TEGRA210_LANE("otg-3", 0x004, 6, 0x3, 0, otg),
TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
TEGRA210_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, 1, pci),
TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, 2, pci),
TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, 3, pci),
TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, 4, pci),
TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, 5, pci),
TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, 6, pci),
TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, 7, pci),
TEGRA210_LANE("sata-0", 0x028, 30, 0x3, 8, pci),
};
#define XUSB_PADCTL_ELPG_PROGRAM 0x024
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
{
u32 value;
if (padctl->enable++ > 0)
return 0;
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
return 0;
}
static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
{
u32 value;
if (padctl->enable == 0) {
error("unbalanced enable/disable");
return 0;
}
if (--padctl->enable > 0)
return 0;
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
return 0;
}
static int phy_prepare(struct tegra_xusb_phy *phy)
{
int err;
err = tegra_xusb_padctl_enable(phy->padctl);
if (err < 0)
return err;
reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
return 0;
}
static int phy_unprepare(struct tegra_xusb_phy *phy)
{
reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
return tegra_xusb_padctl_disable(phy->padctl);
}
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
#define CLK_RST_XUSBIO_PLL_CFG0 0x51c
#define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
#define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
static int pcie_phy_enable(struct tegra_xusb_phy *phy)
{
struct tegra_xusb_padctl *padctl = phy->padctl;
unsigned long start;
u32 value;
debug("> %s(phy=%p)\n", __func__, phy);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
udelay(1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
debug(" waiting for calibration\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
break;
}
if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
debug(" timeout\n");
return -ETIMEDOUT;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
debug(" waiting for calibration to stop\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
break;
}
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
debug(" timeout\n");
return -ETIMEDOUT;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
debug(" waiting for PLL to lock...\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
break;
}
if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
debug(" timeout\n");
return -ETIMEDOUT;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
debug(" waiting for register calibration...\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
break;
}
if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
debug(" timeout\n");
return -ETIMEDOUT;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
debug(" waiting for register calibration to stop...\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
break;
}
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
debug(" timeout\n");
return -ETIMEDOUT;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
udelay(1);
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
debug("< %s()\n", __func__);
return 0;
}
static int pcie_phy_disable(struct tegra_xusb_phy *phy)
{
return 0;
}
static const struct tegra_xusb_phy_ops pcie_phy_ops = {
.prepare = phy_prepare,
.enable = pcie_phy_enable,
.disable = pcie_phy_disable,
.unprepare = phy_unprepare,
};
static struct tegra_xusb_phy tegra210_phys[] = {
{
.type = TEGRA_XUSB_PADCTL_PCIE,
.ops = &pcie_phy_ops,
.padctl = &padctl,
},
};
static const struct tegra_xusb_padctl_soc tegra210_socdata = {
.lanes = tegra210_lanes,
.num_lanes = ARRAY_SIZE(tegra210_lanes),
.functions = tegra210_functions,
.num_functions = ARRAY_SIZE(tegra210_functions),
.phys = tegra210_phys,
.num_phys = ARRAY_SIZE(tegra210_phys),
};
void tegra_xusb_padctl_init(const void *fdt)
{
int count, nodes[1];
debug("> %s(fdt=%p)\n", __func__, fdt);
count = fdtdec_find_aliases_for_id(fdt, "padctl",
COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
nodes, ARRAY_SIZE(nodes));
if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra210_socdata))
return;
debug("< %s()\n", __func__);
}