avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/arch/arm/mach-socfpga/include/mach/base_addr_a10.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
+#define _SOCFPGA_A10_BASE_HARDWARE_H_
+
+#define SOCFPGA_EMAC0_ADDRESS			0xff800000
+#define SOCFPGA_EMAC1_ADDRESS			0xff802000
+#define SOCFPGA_EMAC2_ADDRESS			0xff804000
+#define SOCFPGA_SDMMC_ADDRESS			0xff808000
+#define SOCFPGA_QSPIREGS_ADDRESS		0xff809000
+#define SOCFPGA_QSPIDATA_ADDRESS		0xffa00000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xffcfa000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS		0xffcfe400
+#define SOCFPGA_FPGAMGRREGS_ADDRESS		0xffd03000
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd06000
+#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS	0xffd07000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd07200
+#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS	0xffd07300
+#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS	0xffd07400
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_MPUSCU_ADDRESS			0xffffc000
+#define SOCFPGA_MPUL2_ADDRESS			0xfffff000
+#define SOCFPGA_I2C0_ADDRESS			0xffc02200
+#define SOCFPGA_I2C1_ADDRESS			0xffc02300
+
+#define SOCFPGA_ECC_OCRAM_ADDRESS		0xff8c3000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_OSC1TIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd05000
+
+#define SOCFPGA_SDR_ADDRESS			0xffcfb000
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xffd12400
+#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS	0xffd13200
+#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS	0xffd13300
+#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS		0xffd13400
+
+#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */

u-boot/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h

@@ -0,0 +1,62 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_STM_ADDRESS		0xfc000000
+#define SOCFPGA_DAP_ADDRESS		0xff000000
+#define SOCFPGA_EMAC0_ADDRESS		0xff700000
+#define SOCFPGA_EMAC1_ADDRESS		0xff702000
+#define SOCFPGA_SDMMC_ADDRESS		0xff704000
+#define SOCFPGA_QSPI_ADDRESS		0xff705000
+#define SOCFPGA_GPIO0_ADDRESS		0xff708000
+#define SOCFPGA_GPIO1_ADDRESS		0xff709000
+#define SOCFPGA_GPIO2_ADDRESS		0xff70a000
+#define SOCFPGA_L3REGS_ADDRESS		0xff800000
+#define SOCFPGA_USB0_ADDRESS		0xffb00000
+#define SOCFPGA_USB1_ADDRESS		0xffb40000
+#define SOCFPGA_CAN0_ADDRESS		0xffc00000
+#define SOCFPGA_CAN1_ADDRESS		0xffc01000
+#define SOCFPGA_UART0_ADDRESS		0xffc02000
+#define SOCFPGA_UART1_ADDRESS		0xffc03000
+#define SOCFPGA_I2C0_ADDRESS		0xffc04000
+#define SOCFPGA_I2C1_ADDRESS		0xffc05000
+#define SOCFPGA_I2C2_ADDRESS		0xffc06000
+#define SOCFPGA_I2C3_ADDRESS		0xffc07000
+#define SOCFPGA_SDR_ADDRESS		0xffc20000
+#define SOCFPGA_L4WD0_ADDRESS		0xffd02000
+#define SOCFPGA_L4WD1_ADDRESS		0xffd03000
+#define SOCFPGA_CLKMGR_ADDRESS		0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS		0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS		0xffd08000
+#define SOCFPGA_SPIS0_ADDRESS		0xffe02000
+#define SOCFPGA_SPIS1_ADDRESS		0xffe03000
+#define SOCFPGA_SPIM0_ADDRESS		0xfff00000
+#define SOCFPGA_SPIM1_ADDRESS		0xfff01000
+#define SOCFPGA_SCANMGR_ADDRESS		0xfff02000
+#define SOCFPGA_ROM_ADDRESS		0xfffd0000
+#define SOCFPGA_MPUSCU_ADDRESS		0xfffec000
+#define SOCFPGA_MPUL2_ADDRESS		0xfffef000
+#define SOCFPGA_OCRAM_ADDRESS		0xffff0000
+#define SOCFPGA_LWFPGASLAVES_ADDRESS	0xff200000
+#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS	0xff400000
+#define SOCFPGA_HPS2FPGAREGS_ADDRESS	0xff500000
+#define SOCFPGA_FPGA2HPSREGS_ADDRESS	0xff600000
+#define SOCFPGA_FPGAMGRREGS_ADDRESS	0xff706000
+#define SOCFPGA_ACPIDMAP_ADDRESS	0xff707000
+#define SOCFPGA_NANDDATA_ADDRESS	0xff900000
+#define SOCFPGA_QSPIDATA_ADDRESS	0xffa00000
+#define SOCFPGA_NANDREGS_ADDRESS	0xffb80000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS	0xffb90000
+#define SOCFPGA_SPTIMER0_ADDRESS	0xffc08000
+#define SOCFPGA_SPTIMER1_ADDRESS	0xffc09000
+#define SOCFPGA_OSC1TIMER0_ADDRESS	0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS	0xffd01000
+#define SOCFPGA_DMANONSECURE_ADDRESS	0xffe00000
+#define SOCFPGA_DMASECURE_ADDRESS	0xffe01000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */

u-boot/arch/arm/mach-socfpga/include/mach/clock_manager.h

@@ -0,0 +1,314 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_CLOCK_MANAGER_H_
+#define	_CLOCK_MANAGER_H_
+
+#ifndef __ASSEMBLER__
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+const unsigned int cm_get_osc_clk_hz(const int osc);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+#endif
+
+struct cm_config {
+	/* main group */
+	uint32_t main_vco_base;
+	uint32_t mpuclk;
+	uint32_t mainclk;
+	uint32_t dbgatclk;
+	uint32_t mainqspiclk;
+	uint32_t mainnandsdmmcclk;
+	uint32_t cfg2fuser0clk;
+	uint32_t maindiv;
+	uint32_t dbgdiv;
+	uint32_t tracediv;
+	uint32_t l4src;
+
+	/* peripheral group */
+	uint32_t peri_vco_base;
+	uint32_t emac0clk;
+	uint32_t emac1clk;
+	uint32_t perqspiclk;
+	uint32_t pernandsdmmcclk;
+	uint32_t perbaseclk;
+	uint32_t s2fuser1clk;
+	uint32_t perdiv;
+	uint32_t gpiodiv;
+	uint32_t persrc;
+
+	/* sdram pll group */
+	uint32_t sdram_vco_base;
+	uint32_t ddrdqsclk;
+	uint32_t ddr2xdqsclk;
+	uint32_t ddrdqclk;
+	uint32_t s2fuser2clk;
+};
+
+void cm_basic_init(const struct cm_config * const cfg);
+
+struct socfpga_clock_manager_main_pll {
+	u32	vco;
+	u32	misc;
+	u32	mpuclk;
+	u32	mainclk;
+	u32	dbgatclk;
+	u32	mainqspiclk;
+	u32	mainnandsdmmcclk;
+	u32	cfgs2fuser0clk;
+	u32	en;
+	u32	maindiv;
+	u32	dbgdiv;
+	u32	tracediv;
+	u32	l4src;
+	u32	stat;
+	u32	_pad_0x38_0x40[2];
+};
+
+struct socfpga_clock_manager_per_pll {
+	u32	vco;
+	u32	misc;
+	u32	emac0clk;
+	u32	emac1clk;
+	u32	perqspiclk;
+	u32	pernandsdmmcclk;
+	u32	perbaseclk;
+	u32	s2fuser1clk;
+	u32	en;
+	u32	div;
+	u32	gpiodiv;
+	u32	src;
+	u32	stat;
+	u32	_pad_0x34_0x40[3];
+};
+
+struct socfpga_clock_manager_sdr_pll {
+	u32	vco;
+	u32	ctrl;
+	u32	ddrdqsclk;
+	u32	ddr2xdqsclk;
+	u32	ddrdqclk;
+	u32	s2fuser2clk;
+	u32	en;
+	u32	stat;
+};
+
+struct socfpga_clock_manager_altera {
+	u32	mpuclk;
+	u32	mainclk;
+};
+
+struct socfpga_clock_manager {
+	u32	ctrl;
+	u32	bypass;
+	u32	inter;
+	u32	intren;
+	u32	dbctrl;
+	u32	stat;
+	u32	_pad_0x18_0x3f[10];
+	struct socfpga_clock_manager_main_pll main_pll;
+	struct socfpga_clock_manager_per_pll per_pll;
+	struct socfpga_clock_manager_sdr_pll sdr_pll;
+	struct socfpga_clock_manager_altera altera;
+	u32	_pad_0xe8_0x200[70];
+};
+
+#define CLKMGR_CTRL_SAFEMODE				(1 << 0)
+#define CLKMGR_CTRL_SAFEMODE_OFFSET			0
+
+#define CLKMGR_BYPASS_PERPLLSRC				(1 << 4)
+#define CLKMGR_BYPASS_PERPLLSRC_OFFSET			4
+#define CLKMGR_BYPASS_PERPLL				(1 << 3)
+#define CLKMGR_BYPASS_PERPLL_OFFSET			3
+#define CLKMGR_BYPASS_SDRPLLSRC				(1 << 2)
+#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET			2
+#define CLKMGR_BYPASS_SDRPLL				(1 << 1)
+#define CLKMGR_BYPASS_SDRPLL_OFFSET			1
+#define CLKMGR_BYPASS_MAINPLL				(1 << 0)
+#define CLKMGR_BYPASS_MAINPLL_OFFSET			0
+
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK			0x00000100
+#define CLKMGR_INTER_PERPLLLOCKED_MASK			0x00000080
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK			0x00000040
+#define CLKMGR_INTER_PERPLLLOST_MASK			0x00000010
+#define CLKMGR_INTER_SDRPLLLOST_MASK			0x00000020
+#define CLKMGR_INTER_MAINPLLLOST_MASK			0x00000008
+
+#define CLKMGR_STAT_BUSY				(1 << 0)
+
+/* Main PLL */
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN			(1 << 0)
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET		0
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK		0x003f0000
+#define CLKMGR_MAINPLLGRP_VCO_EN			(1 << 1)
+#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET			1
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK		0x0000fff8
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN			(1 << 2)
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET		2
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE		0x8001000d
+
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK		0x00000010
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK		0x00000020
+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK		0x00000080
+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK		0x00000040
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK		0x00000004
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK		0x00000200
+
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK		0x00000003
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET	2
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK		0x0000000c
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET	4
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK		0x00000070
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET	7
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK		0x00000380
+
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK		0x00000003
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET		2
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK		0x0000000c
+
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK	0x00000007
+
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP			(1 << 0)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET		0
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP			(1 << 1)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET		1
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE		0x00000000
+#define CLKMGR_L4_SP_CLK_SRC_MAINPLL			0x0
+#define CLKMGR_L4_SP_CLK_SRC_PERPLL			0x1
+
+/* Per PLL */
+#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK			0x003f0000
+#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK			0x0000fff8
+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
+#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET		22
+#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK			0x00c00000
+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE		0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET		22
+#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK			0x00c00000
+
+#define CLKMGR_VCO_SSRC_EOSC1				0x0
+#define CLKMGR_VCO_SSRC_EOSC2				0x1
+#define CLKMGR_VCO_SSRC_F2S				0x2
+
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET	0
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK		0x00000400
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000100
+
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET		6
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK		0x000001c0
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET		9
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK		0x00000e00
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET		0
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK		0x00000007
+
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET	0
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK		0x00ffffff
+
+#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET		2
+#define CLKMGR_PERPLLGRP_SRC_NAND_MASK			0x0000000c
+#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET		4
+#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK			0x00000030
+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE		0x00000015
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET		0
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK			0x00000003
+#define CLKMGR_SDMMC_CLK_SRC_F2S			0x0
+#define CLKMGR_SDMMC_CLK_SRC_MAIN			0x1
+#define CLKMGR_SDMMC_CLK_SRC_PER			0x2
+#define CLKMGR_QSPI_CLK_SRC_F2S				0x0
+#define CLKMGR_QSPI_CLK_SRC_MAIN			0x1
+#define CLKMGR_QSPI_CLK_SRC_PER				0x2
+
+/* SDR PLL */
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK			0x003f0000
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK			0x0000fff8
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL		(1 << 24)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET		24
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET		25
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK		0x7e000000
+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE		0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET		22
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK			0x00c00000
+
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET		9
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET	9
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET		9
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET	9
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK		0x00000e00
+
+#endif /* _CLOCK_MANAGER_H_ */

u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ */
+
+#ifndef	_FPGA_MANAGER_H_
+#define	_FPGA_MANAGER_H_
+
+#include <altera.h>
+
+struct socfpga_fpga_manager {
+	/* FPGA Manager Module */
+	u32	stat;			/* 0x00 */
+	u32	ctrl;
+	u32	dclkcnt;
+	u32	dclkstat;
+	u32	gpo;			/* 0x10 */
+	u32	gpi;
+	u32	misci;			/* 0x18 */
+	u32	_pad_0x1c_0x82c[517];
+
+	/* Configuration Monitor (MON) Registers */
+	u32	gpio_inten;		/* 0x830 */
+	u32	gpio_intmask;
+	u32	gpio_inttype_level;
+	u32	gpio_int_polarity;
+	u32	gpio_intstatus;		/* 0x840 */
+	u32	gpio_raw_intstatus;
+	u32	_pad_0x848;
+	u32	gpio_porta_eoi;
+	u32	gpio_ext_porta;		/* 0x850 */
+	u32	_pad_0x854_0x85c[3];
+	u32	gpio_1s_sync;		/* 0x860 */
+	u32	_pad_0x864_0x868[2];
+	u32	gpio_ver_id_code;
+	u32	gpio_config_reg2;	/* 0x870 */
+	u32	gpio_config_reg1;
+};
+
+#define FPGAMGRREGS_STAT_MODE_MASK		0x7
+#define FPGAMGRREGS_STAT_MSEL_MASK		0xf8
+#define FPGAMGRREGS_STAT_MSEL_LSB		3
+
+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK		0x200
+#define FPGAMGRREGS_CTRL_AXICFGEN_MASK		0x100
+#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK	0x4
+#define FPGAMGRREGS_CTRL_NCE_MASK		0x2
+#define FPGAMGRREGS_CTRL_EN_MASK		0x1
+#define FPGAMGRREGS_CTRL_CDRATIO_LSB		6
+
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK	0x8
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK	0x4
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK	0x2
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK	0x1
+
+/* FPGA Mode */
+#define FPGAMGRREGS_MODE_FPGAOFF		0x0
+#define FPGAMGRREGS_MODE_RESETPHASE		0x1
+#define FPGAMGRREGS_MODE_CFGPHASE		0x2
+#define FPGAMGRREGS_MODE_INITPHASE		0x3
+#define FPGAMGRREGS_MODE_USERMODE		0x4
+#define FPGAMGRREGS_MODE_UNKNOWN		0x5
+
+/* FPGA CD Ratio Value */
+#define CDRATIO_x1				0x0
+#define CDRATIO_x2				0x1
+#define CDRATIO_x4				0x2
+#define CDRATIO_x8				0x3
+
+/* SoCFPGA support functions */
+int fpgamgr_test_fpga_ready(void);
+int fpgamgr_poll_fpga_ready(void);
+int fpgamgr_get_mode(void);
+
+#endif /* _FPGA_MANAGER_H_ */

u-boot/arch/arm/mach-socfpga/include/mach/freeze_controller.h

@@ -0,0 +1,49 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_FREEZE_CONTROLLER_H_
+#define	_FREEZE_CONTROLLER_H_
+
+struct socfpga_freeze_controller {
+	u32	vioctrl;
+	u32	padding[3];
+	u32	hioctrl;
+	u32	src;
+	u32	hwctrl;
+};
+
+#define FREEZE_CHANNEL_NUM		(4)
+
+typedef enum {
+	FREEZE_CTRL_FROZEN = 0,
+	FREEZE_CTRL_THAWED = 1
+} FREEZE_CTRL_CHAN_STATE;
+
+#define SYSMGR_FRZCTRL_ADDRESS 0x40
+#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
+#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
+#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
+#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
+#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
+#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
+#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
+#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
+#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
+#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
+#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
+#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
+#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
+#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
+
+void sys_mgr_frzctrl_freeze_req(void);
+void sys_mgr_frzctrl_thaw_req(void);
+
+#endif /* _FREEZE_CONTROLLER_H_ */

u-boot/arch/arm/mach-socfpga/include/mach/gpio.h

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_GPIO_H
+#define _SOCFPGA_GPIO_H
+
+#endif /* _SOCFPGA_GPIO_H */

u-boot/arch/arm/mach-socfpga/include/mach/nic301.h

@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_NIC301_REGISTERS_H_
+#define	_NIC301_REGISTERS_H_
+
+struct nic301_registers {
+	u32	remap;				/* 0x0 */
+	/* Security Register Group */
+	u32	_pad_0x4_0x8[1];
+	u32	l4main;
+	u32	l4sp;
+	u32	l4mp;				/* 0x10 */
+	u32	l4osc1;
+	u32	l4spim;
+	u32	stm;
+	u32	lwhps2fpgaregs;			/* 0x20 */
+	u32	_pad_0x24_0x28[1];
+	u32	usb1;
+	u32	nanddata;
+	u32	_pad_0x30_0x80[20];
+	u32	usb0;				/* 0x80 */
+	u32	nandregs;
+	u32	qspidata;
+	u32	fpgamgrdata;
+	u32	hps2fpgaregs;			/* 0x90 */
+	u32	acp;
+	u32	rom;
+	u32	ocram;
+	u32	sdrdata;			/* 0xA0 */
+	u32	_pad_0xa4_0x1fd0[1995];
+	/* ID Register Group */
+	u32	periph_id_4;			/* 0x1FD0 */
+	u32	_pad_0x1fd4_0x1fe0[3];
+	u32	periph_id_0;			/* 0x1FE0 */
+	u32	periph_id_1;
+	u32	periph_id_2;
+	u32	periph_id_3;
+	u32	comp_id_0;			/* 0x1FF0 */
+	u32	comp_id_1;
+	u32	comp_id_2;
+	u32	comp_id_3;
+	u32	_pad_0x2000_0x2008[2];
+	/* L4 MAIN */
+	u32	l4main_fn_mod_bm_iss;
+	u32	_pad_0x200c_0x3008[1023];
+	/* L4 SP */
+	u32	l4sp_fn_mod_bm_iss;
+	u32	_pad_0x300c_0x4008[1023];
+	/* L4 MP */
+	u32	l4mp_fn_mod_bm_iss;
+	u32	_pad_0x400c_0x5008[1023];
+	/* L4 OSC1 */
+	u32	l4osc_fn_mod_bm_iss;
+	u32	_pad_0x500c_0x6008[1023];
+	/* L4 SPIM */
+	u32	l4spim_fn_mod_bm_iss;
+	u32	_pad_0x600c_0x7008[1023];
+	/* STM */
+	u32	stm_fn_mod_bm_iss;
+	u32	_pad_0x700c_0x7108[63];
+	u32	stm_fn_mod;
+	u32	_pad_0x710c_0x8008[959];
+	/* LWHPS2FPGA */
+	u32	lwhps2fpga_fn_mod_bm_iss;
+	u32	_pad_0x800c_0x8108[63];
+	u32	lwhps2fpga_fn_mod;
+	u32	_pad_0x810c_0xa008[1983];
+	/* USB1 */
+	u32	usb1_fn_mod_bm_iss;
+	u32	_pad_0xa00c_0xa044[14];
+	u32	usb1_ahb_cntl;
+	u32	_pad_0xa048_0xb008[1008];
+	/* NANDDATA */
+	u32	nanddata_fn_mod_bm_iss;
+	u32	_pad_0xb00c_0xb108[63];
+	u32	nanddata_fn_mod;
+	u32	_pad_0xb10c_0x20008[21439];
+	/* USB0 */
+	u32	usb0_fn_mod_bm_iss;
+	u32	_pad_0x2000c_0x20044[14];
+	u32	usb0_ahb_cntl;
+	u32	_pad_0x20048_0x21008[1008];
+	/* NANDREGS */
+	u32	nandregs_fn_mod_bm_iss;
+	u32	_pad_0x2100c_0x21108[63];
+	u32	nandregs_fn_mod;
+	u32	_pad_0x2110c_0x22008[959];
+	/* QSPIDATA */
+	u32	qspidata_fn_mod_bm_iss;
+	u32	_pad_0x2200c_0x22044[14];
+	u32	qspidata_ahb_cntl;
+	u32	_pad_0x22048_0x23008[1008];
+	/* FPGAMGRDATA */
+	u32	fpgamgrdata_fn_mod_bm_iss;
+	u32	_pad_0x2300c_0x23040[13];
+	u32	fpgamgrdata_wr_tidemark;	/* 0x23040 */
+	u32	_pad_0x23044_0x23108[49];
+	u32	fn_mod;
+	u32	_pad_0x2310c_0x24008[959];
+	/* HPS2FPGA */
+	u32	hps2fpga_fn_mod_bm_iss;
+	u32	_pad_0x2400c_0x24040[13];
+	u32	hps2fpga_wr_tidemark;		/* 0x24040 */
+	u32	_pad_0x24044_0x24108[49];
+	u32	hps2fpga_fn_mod;
+	u32	_pad_0x2410c_0x25008[959];
+	/* ACP */
+	u32	acp_fn_mod_bm_iss;
+	u32	_pad_0x2500c_0x25108[63];
+	u32	acp_fn_mod;
+	u32	_pad_0x2510c_0x26008[959];
+	/* Boot ROM */
+	u32	bootrom_fn_mod_bm_iss;
+	u32	_pad_0x2600c_0x26108[63];
+	u32	bootrom_fn_mod;
+	u32	_pad_0x2610c_0x27008[959];
+	/* On-chip RAM */
+	u32	ocram_fn_mod_bm_iss;
+	u32	_pad_0x2700c_0x27040[13];
+	u32	ocram_wr_tidemark;		/* 0x27040 */
+	u32	_pad_0x27044_0x27108[49];
+	u32	ocram_fn_mod;
+	u32	_pad_0x2710c_0x42024[27590];
+	/* DAP */
+	u32	dap_fn_mod2;
+	u32	dap_fn_mod_ahb;
+	u32	_pad_0x4202c_0x42100[53];
+	u32	dap_read_qos;			/* 0x42100 */
+	u32	dap_write_qos;
+	u32	dap_fn_mod;
+	u32	_pad_0x4210c_0x43100[1021];
+	/* MPU */
+	u32	mpu_read_qos;			/* 0x43100 */
+	u32	mpu_write_qos;
+	u32	mpu_fn_mod;
+	u32	_pad_0x4310c_0x44028[967];
+	/* SDMMC */
+	u32	sdmmc_fn_mod_ahb;
+	u32	_pad_0x4402c_0x44100[53];
+	u32	sdmmc_read_qos;			/* 0x44100 */
+	u32	sdmmc_write_qos;
+	u32	sdmmc_fn_mod;
+	u32	_pad_0x4410c_0x45100[1021];
+	/* DMA */
+	u32	dma_read_qos;			/* 0x45100 */
+	u32	dma_write_qos;
+	u32	dma_fn_mod;
+	u32	_pad_0x4510c_0x46040[973];
+	/* FPGA2HPS */
+	u32	fpga2hps_wr_tidemark;		/* 0x46040 */
+	u32	_pad_0x46044_0x46100[47];
+	u32	fpga2hps_read_qos;		/* 0x46100 */
+	u32	fpga2hps_write_qos;
+	u32	fpga2hps_fn_mod;
+	u32	_pad_0x4610c_0x47100[1021];
+	/* ETR */
+	u32	etr_read_qos;			/* 0x47100 */
+	u32	etr_write_qos;
+	u32	etr_fn_mod;
+	u32	_pad_0x4710c_0x48100[1021];
+	/* EMAC0 */
+	u32	emac0_read_qos;			/* 0x48100 */
+	u32	emac0_write_qos;
+	u32	emac0_fn_mod;
+	u32	_pad_0x4810c_0x49100[1021];
+	/* EMAC1 */
+	u32	emac1_read_qos;			/* 0x49100 */
+	u32	emac1_write_qos;
+	u32	emac1_fn_mod;
+	u32	_pad_0x4910c_0x4a028[967];
+	/* USB0 */
+	u32	usb0_fn_mod_ahb;
+	u32	_pad_0x4a02c_0x4a100[53];
+	u32	usb0_read_qos;			/* 0x4A100 */
+	u32	usb0_write_qos;
+	u32	usb0_fn_mod;
+	u32	_pad_0x4a10c_0x4b100[1021];
+	/* NAND */
+	u32	nand_read_qos;			/* 0x4B100 */
+	u32	nand_write_qos;
+	u32	nand_fn_mod;
+	u32	_pad_0x4b10c_0x4c028[967];
+	/* USB1 */
+	u32	usb1_fn_mod_ahb;
+	u32	_pad_0x4c02c_0x4c100[53];
+	u32	usb1_read_qos;			/* 0x4C100 */
+	u32	usb1_write_qos;
+	u32	usb1_fn_mod;
+};
+
+#endif	/* _NIC301_REGISTERS_H_ */

u-boot/arch/arm/mach-socfpga/include/mach/reset_manager.h

@@ -0,0 +1,82 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_RESET_MANAGER_H_
+#define	_RESET_MANAGER_H_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+void socfpga_bridges_reset(int enable);
+
+void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
+
+struct socfpga_reset_manager {
+	u32	status;
+	u32	ctrl;
+	u32	counts;
+	u32	padding1;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+	u32	misc_mod_reset;
+	u32	padding2[12];
+	u32	tstscratch;
+};
+
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
+#else
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+#endif
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET	8
+#define RSTMGR_BANK_MASK	0x7
+#define RSTMGR_RESET_OFFSET	0
+#define RSTMGR_RESET_MASK	0x1f
+#define RSTMGR_DEFINE(_bank, _offset)		\
+	((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset)			\
+	(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset)			\
+	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+
+/*
+ * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... permodrst
+ * 2 ... per2modrst
+ * 3 ... brgmodrst
+ * 4 ... miscmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_NAND		RSTMGR_DEFINE(1, 4)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
+#define RSTMGR_L4WD0		RSTMGR_DEFINE(1, 6)
+#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(1, 8)
+#define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
+#define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
+
+/* Create a human-readable reference to SoCFPGA reset. */
+#define SOCFPGA_RESET(_name)	RSTMGR_##_name
+
+#endif /* _RESET_MANAGER_H_ */

u-boot/arch/arm/mach-socfpga/include/mach/scan_manager.h

@@ -0,0 +1,26 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_SCAN_MANAGER_H_
+#define	_SCAN_MANAGER_H_
+
+struct socfpga_scan_manager {
+	u32	stat;
+	u32	en;
+	u32	padding[2];
+	u32	fifo_single_byte;
+	u32	fifo_double_byte;
+	u32	fifo_triple_byte;
+	u32	fifo_quad_byte;
+};
+
+int scan_mgr_configure_iocsr(void);
+u32 scan_mgr_get_fpga_id(void);
+int iocsr_get_config_table(const unsigned int chain_id,
+			   const unsigned long **table,
+			   unsigned int *table_len);
+
+#endif /* _SCAN_MANAGER_H_ */

u-boot/arch/arm/mach-socfpga/include/mach/scu.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SOCFPGA_SCU_H__
+#define __SOCFPGA_SCU_H__
+
+struct scu_registers {
+	u32	ctrl;			/* 0x00 */
+	u32	cfg;
+	u32	cpsr;
+	u32	iassr;
+	u32	_pad_0x10_0x3c[12];	/* 0x10 */
+	u32	fsar;			/* 0x40 */
+	u32	fear;
+	u32	_pad_0x48_0x50[2];
+	u32	acr;			/* 0x54 */
+	u32	sacr;
+};
+
+#endif	/* __SOCFPGA_SCU_H__ */

u-boot/arch/arm/mach-socfpga/include/mach/sdram.h

@@ -0,0 +1,436 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2015
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_SDRAM_H_
+#define	_SDRAM_H_
+
+#ifndef __ASSEMBLY__
+
+unsigned long sdram_calculate_size(void);
+int sdram_mmr_init_full(unsigned int sdr_phy_reg);
+int sdram_calibration_full(void);
+
+const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
+
+void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
+void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
+const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
+
+#define SDR_CTRLGRP_ADDRESS	(SOCFPGA_SDR_ADDRESS | 0x5000)
+
+struct socfpga_sdr_ctrl {
+	u32	ctrl_cfg;
+	u32	dram_timing1;
+	u32	dram_timing2;
+	u32	dram_timing3;
+	u32	dram_timing4;	/* 0x10 */
+	u32	lowpwr_timing;
+	u32	dram_odt;
+	u32	__padding0[4];
+	u32	dram_addrw;	/* 0x2c */
+	u32	dram_if_width;	/* 0x30 */
+	u32	dram_dev_width;
+	u32	dram_sts;
+	u32	dram_intr;
+	u32	sbe_count;	/* 0x40 */
+	u32	dbe_count;
+	u32	err_addr;
+	u32	drop_count;
+	u32	drop_addr;	/* 0x50 */
+	u32	lowpwr_eq;
+	u32	lowpwr_ack;
+	u32	static_cfg;
+	u32	ctrl_width;	/* 0x60 */
+	u32	cport_width;
+	u32	cport_wmap;
+	u32	cport_rmap;
+	u32	rfifo_cmap;	/* 0x70 */
+	u32	wfifo_cmap;
+	u32	cport_rdwr;
+	u32	port_cfg;
+	u32	fpgaport_rst;	/* 0x80 */
+	u32	__padding1;
+	u32	fifo_cfg;
+	u32	protport_default;
+	u32	prot_rule_addr;	/* 0x90 */
+	u32	prot_rule_id;
+	u32	prot_rule_data;
+	u32	prot_rule_rdwr;
+	u32	__padding2[3];
+	u32	mp_priority;	/* 0xac */
+	u32	mp_weight0;	/* 0xb0 */
+	u32	mp_weight1;
+	u32	mp_weight2;
+	u32	mp_weight3;
+	u32	mp_pacing0;	/* 0xc0 */
+	u32	mp_pacing1;
+	u32	mp_pacing2;
+	u32	mp_pacing3;
+	u32	mp_threshold0;	/* 0xd0 */
+	u32	mp_threshold1;
+	u32	mp_threshold2;
+	u32	__padding3[29];
+	u32	phy_ctrl0;	/* 0x150 */
+	u32	phy_ctrl1;
+	u32	phy_ctrl2;
+};
+
+/* SDRAM configuration structure for the SPL. */
+struct socfpga_sdram_config {
+	u32	ctrl_cfg;
+	u32	dram_timing1;
+	u32	dram_timing2;
+	u32	dram_timing3;
+	u32	dram_timing4;
+	u32	lowpwr_timing;
+	u32	dram_odt;
+	u32	dram_addrw;
+	u32	dram_if_width;
+	u32	dram_dev_width;
+	u32	dram_intr;
+	u32	lowpwr_eq;
+	u32	static_cfg;
+	u32	ctrl_width;
+	u32	cport_width;
+	u32	cport_wmap;
+	u32	cport_rmap;
+	u32	rfifo_cmap;
+	u32	wfifo_cmap;
+	u32	cport_rdwr;
+	u32	port_cfg;
+	u32	fpgaport_rst;
+	u32	fifo_cfg;
+	u32	mp_priority;
+	u32	mp_weight0;
+	u32	mp_weight1;
+	u32	mp_weight2;
+	u32	mp_weight3;
+	u32	mp_pacing0;
+	u32	mp_pacing1;
+	u32	mp_pacing2;
+	u32	mp_pacing3;
+	u32	mp_threshold0;
+	u32	mp_threshold1;
+	u32	mp_threshold2;
+	u32	phy_ctrl0;
+};
+
+struct socfpga_sdram_rw_mgr_config {
+	u8	activate_0_and_1;
+	u8	activate_0_and_1_wait1;
+	u8	activate_0_and_1_wait2;
+	u8	activate_1;
+	u8	clear_dqs_enable;
+	u8	guaranteed_read;
+	u8	guaranteed_read_cont;
+	u8	guaranteed_write;
+	u8	guaranteed_write_wait0;
+	u8	guaranteed_write_wait1;
+	u8	guaranteed_write_wait2;
+	u8	guaranteed_write_wait3;
+	u8	idle;
+	u8	idle_loop1;
+	u8	idle_loop2;
+	u8	init_reset_0_cke_0;
+	u8	init_reset_1_cke_0;
+	u8	lfsr_wr_rd_bank_0;
+	u8	lfsr_wr_rd_bank_0_data;
+	u8	lfsr_wr_rd_bank_0_dqs;
+	u8	lfsr_wr_rd_bank_0_nop;
+	u8	lfsr_wr_rd_bank_0_wait;
+	u8	lfsr_wr_rd_bank_0_wl_1;
+	u8	lfsr_wr_rd_dm_bank_0;
+	u8	lfsr_wr_rd_dm_bank_0_data;
+	u8	lfsr_wr_rd_dm_bank_0_dqs;
+	u8	lfsr_wr_rd_dm_bank_0_nop;
+	u8	lfsr_wr_rd_dm_bank_0_wait;
+	u8	lfsr_wr_rd_dm_bank_0_wl_1;
+	u8	mrs0_dll_reset;
+	u8	mrs0_dll_reset_mirr;
+	u8	mrs0_user;
+	u8	mrs0_user_mirr;
+	u8	mrs1;
+	u8	mrs1_mirr;
+	u8	mrs2;
+	u8	mrs2_mirr;
+	u8	mrs3;
+	u8	mrs3_mirr;
+	u8	precharge_all;
+	u8	read_b2b;
+	u8	read_b2b_wait1;
+	u8	read_b2b_wait2;
+	u8	refresh_all;
+	u8	rreturn;
+	u8	sgle_read;
+	u8	zqcl;
+
+	u8	true_mem_data_mask_width;
+	u8	mem_address_mirroring;
+	u8	mem_data_mask_width;
+	u8	mem_data_width;
+	u8	mem_dq_per_read_dqs;
+	u8	mem_dq_per_write_dqs;
+	u8	mem_if_read_dqs_width;
+	u8	mem_if_write_dqs_width;
+	u8	mem_number_of_cs_per_dimm;
+	u8	mem_number_of_ranks;
+	u8	mem_virtual_groups_per_read_dqs;
+	u8	mem_virtual_groups_per_write_dqs;
+};
+
+struct socfpga_sdram_io_config {
+	u16	delay_per_opa_tap;
+	u8	delay_per_dchain_tap;
+	u8	delay_per_dqs_en_dchain_tap;
+	u8	dll_chain_length;
+	u8	dqdqs_out_phase_max;
+	u8	dqs_en_delay_max;
+	u8	dqs_en_delay_offset;
+	u8	dqs_en_phase_max;
+	u8	dqs_in_delay_max;
+	u8	dqs_in_reserve;
+	u8	dqs_out_reserve;
+	u8	io_in_delay_max;
+	u8	io_out1_delay_max;
+	u8	io_out2_delay_max;
+	u8	shift_dqs_en_when_shift_dqs;
+};
+
+struct socfpga_sdram_misc_config {
+	u32	reg_file_init_seq_signature;
+	u8	afi_rate_ratio;
+	u8	calib_lfifo_offset;
+	u8	calib_vfifo_offset;
+	u8	enable_super_quick_calibration;
+	u8	max_latency_count_width;
+	u8	read_valid_fifo_size;
+	u8	tinit_cntr0_val;
+	u8	tinit_cntr1_val;
+	u8	tinit_cntr2_val;
+	u8	treset_cntr0_val;
+	u8	treset_cntr1_val;
+	u8	treset_cntr2_val;
+};
+
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
+/* Register template: sdr::ctrlgrp::dramtiming1                            */
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming2                            */
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
+/* Register template: sdr::ctrlgrp::dramtiming3                            */
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming4                            */
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::lowpwrtiming                           */
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
+/* Register template: sdr::ctrlgrp::dramaddrw                              */
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
+/* Register template: sdr::ctrlgrp::dramifwidth                            */
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::dramdevwidth                           */
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramintr                               */
+#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
+#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
+/* Register template: sdr::ctrlgrp::staticcfg                              */
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
+#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
+#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::ctrlwidth                              */
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::cportwidth                             */
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::cportwmap                              */
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::cportrmap                              */
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::rfifocmap                              */
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::wfifocmap                              */
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::cportrdwr                              */
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::portcfg                                */
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::fifocfg                                */
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::mppriority                             */
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_0                   */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_1                   */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_2                   */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_3                   */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_0                   */
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_1                   */
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_2                   */
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_3                   */
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0       */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
+#define  \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1       */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2       */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
+0x0000ffff
+/* Register template: sdr::ctrlgrp::remappriority                          */
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0                     */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
+ (((x) << 10) & 0x00000c00)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
+ (((x) << 6) & 0x000000c0)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
+ (((x) << 8) & 0x00000100)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
+ (((x) << 9) & 0x00000200)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
+ (((x) << 4) & 0x00000030)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
+ (((x) << 2) & 0x0000000c)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
+ (((x) << 0) & 0x00000003)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1                     */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2                     */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::dramodt                                */
+#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
+#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
+#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
+#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
+/* Field instance: sdr::ctrlgrp::dramsts                                   */
+#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
+#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
+
+/* SDRAM width macro for configuration with ECC */
+#define SDRAM_WIDTH_32BIT_WITH_ECC	40
+#define SDRAM_WIDTH_16BIT_WITH_ECC	24
+
+#endif
+#endif /* _SDRAM_H_ */

u-boot/arch/arm/mach-socfpga/include/mach/system_manager.h

@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_SYSTEM_MANAGER_H_
+#define	_SYSTEM_MANAGER_H_
+
+#ifndef __ASSEMBLY__
+
+void sysmgr_pinmux_init(void);
+void sysmgr_config_warmrstcfgio(int enable);
+
+void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
+#endif
+
+struct socfpga_system_manager {
+	/* System Manager Module */
+	u32	siliconid1;			/* 0x00 */
+	u32	siliconid2;
+	u32	_pad_0x8_0xf[2];
+	u32	wddbg;				/* 0x10 */
+	u32	bootinfo;
+	u32	hpsinfo;
+	u32	parityinj;
+	/* FPGA Interface Group */
+	u32	fpgaintfgrp_gbl;		/* 0x20 */
+	u32	fpgaintfgrp_indiv;
+	u32	fpgaintfgrp_module;
+	u32	_pad_0x2c_0x2f;
+	/* Scan Manager Group */
+	u32	scanmgrgrp_ctrl;		/* 0x30 */
+	u32	_pad_0x34_0x3f[3];
+	/* Freeze Control Group */
+	u32	frzctrl_vioctrl;		/* 0x40 */
+	u32	_pad_0x44_0x4f[3];
+	u32	frzctrl_hioctrl;		/* 0x50 */
+	u32	frzctrl_src;
+	u32	frzctrl_hwctrl;
+	u32	_pad_0x5c_0x5f;
+	/* EMAC Group */
+	u32	emacgrp_ctrl;			/* 0x60 */
+	u32	emacgrp_l3master;
+	u32	_pad_0x68_0x6f[2];
+	/* DMA Controller Group */
+	u32	dmagrp_ctrl;			/* 0x70 */
+	u32	dmagrp_persecurity;
+	u32	_pad_0x78_0x7f[2];
+	/* Preloader (initial software) Group */
+	u32	iswgrp_handoff[8];		/* 0x80 */
+	u32	_pad_0xa0_0xbf[8];		/* 0xa0 */
+	/* Boot ROM Code Register Group */
+	u32	romcodegrp_ctrl;		/* 0xc0 */
+	u32	romcodegrp_cpu1startaddr;
+	u32	romcodegrp_initswstate;
+	u32	romcodegrp_initswlastld;
+	u32	romcodegrp_bootromswstate;	/* 0xd0 */
+	u32	__pad_0xd4_0xdf[3];
+	/* Warm Boot from On-Chip RAM Group */
+	u32	romcodegrp_warmramgrp_enable;	/* 0xe0 */
+	u32	romcodegrp_warmramgrp_datastart;
+	u32	romcodegrp_warmramgrp_length;
+	u32	romcodegrp_warmramgrp_execution;
+	u32	romcodegrp_warmramgrp_crc;	/* 0xf0 */
+	u32	__pad_0xf4_0xff[3];
+	/* Boot ROM Hardware Register Group */
+	u32	romhwgrp_ctrl;			/* 0x100 */
+	u32	_pad_0x104_0x107;
+	/* SDMMC Controller Group */
+	u32	sdmmcgrp_ctrl;
+	u32	sdmmcgrp_l3master;
+	/* NAND Flash Controller Register Group */
+	u32	nandgrp_bootstrap;		/* 0x110 */
+	u32	nandgrp_l3master;
+	/* USB Controller Group */
+	u32	usbgrp_l3master;
+	u32	_pad_0x11c_0x13f[9];
+	/* ECC Management Register Group */
+	u32	eccgrp_l2;			/* 0x140 */
+	u32	eccgrp_ocram;
+	u32	eccgrp_usb0;
+	u32	eccgrp_usb1;
+	u32	eccgrp_emac0;			/* 0x150 */
+	u32	eccgrp_emac1;
+	u32	eccgrp_dma;
+	u32	eccgrp_can0;
+	u32	eccgrp_can1;			/* 0x160 */
+	u32	eccgrp_nand;
+	u32	eccgrp_qspi;
+	u32	eccgrp_sdmmc;
+	u32	_pad_0x170_0x3ff[164];
+	/* Pin Mux Control Group */
+	u32	emacio[20];			/* 0x400 */
+	u32	flashio[12];			/* 0x450 */
+	u32	generalio[28];			/* 0x480 */
+	u32	_pad_0x4f0_0x4ff[4];
+	u32	mixed1io[22];			/* 0x500 */
+	u32	mixed2io[8];			/* 0x558 */
+	u32	gplinmux[23];			/* 0x578 */
+	u32	gplmux[71];			/* 0x5d4 */
+	u32	nandusefpga;			/* 0x6f0 */
+	u32	_pad_0x6f4;
+	u32	rgmii1usefpga;			/* 0x6f8 */
+	u32	_pad_0x6fc_0x700[2];
+	u32	i2c0usefpga;			/* 0x704 */
+	u32	sdmmcusefpga;			/* 0x708 */
+	u32	_pad_0x70c_0x710[2];
+	u32	rgmii0usefpga;			/* 0x714 */
+	u32	_pad_0x718_0x720[3];
+	u32	i2c3usefpga;			/* 0x724 */
+	u32	i2c2usefpga;			/* 0x728 */
+	u32	i2c1usefpga;			/* 0x72c */
+	u32	spim1usefpga;			/* 0x730 */
+	u32	_pad_0x734;
+	u32	spim0usefpga;			/* 0x738 */
+};
+
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	(1 << 0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	(1 << 1)
+#define SYSMGR_ECC_OCRAM_EN	(1 << 0)
+#define SYSMGR_ECC_OCRAM_SERR	(1 << 3)
+#define SYSMGR_ECC_OCRAM_DERR	(1 << 4)
+#define SYSMGR_FPGAINTF_USEFPGA	0x1
+#define SYSMGR_FPGAINTF_SPIM0	(1 << 0)
+#define SYSMGR_FPGAINTF_SPIM1	(1 << 1)
+#define SYSMGR_FPGAINTF_EMAC0	(1 << 2)
+#define SYSMGR_FPGAINTF_EMAC1	(1 << 3)
+#define SYSMGR_FPGAINTF_NAND	(1 << 4)
+#define SYSMGR_FPGAINTF_SDMMC	(1 << 5)
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	3
+#else
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
+#endif
+
+#define SYSMGR_SDMMC_DRVSEL_SHIFT	0
+
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
+
+#endif /* _SYSTEM_MANAGER_H_ */

u-boot/arch/arm/mach-socfpga/include/mach/timer.h

@@ -0,0 +1,18 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_TIMER_H_
+#define _SOCFPGA_TIMER_H_
+
+struct socfpga_timer {
+	u32	load_val;
+	u32	curr_val;
+	u32	ctrl;
+	u32	eoi;
+	u32	int_stat;
+};
+
+#endif