avionic design with actual uboot and tooling

submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md

u-boot/arch/arm/mach-mvebu/include/mach/config.h

@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for MVEBU platforms
+ */
+
+#ifndef _MVEBU_CONFIG_H
+#define _MVEBU_CONFIG_H
+
+#include <asm/arch/soc.h>
+
+#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
+	|| defined(CONFIG_ARMADA_38X)
+/*
+ * Set this for the common xor register definitions needed in dram.c
+ * for A38x as well here.
+ */
+#define MV88F78X60 /* for the DDR training bin_hdr code */
+#endif
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#define CONFIG_SYS_L2_PL310
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#endif
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define	CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Add target to build it automatically upon "make" */
+#ifdef CONFIG_SPL
+#define CONFIG_BUILD_TARGET	"u-boot-spl.kwb"
+#endif
+
+/* end of 16M scrubbed by training in bootrom */
+#define CONFIG_SYS_INIT_SP_ADDR		0x00FF0000
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+#define MV_UART_CONSOLE_BASE		MVEBU_UART0_BASE
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_KIRKWOOD_SPI
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS		0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS		0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ		50000000
+#endif
+#endif
+
+/* Needed for SPI NOR booting in SPL */
+#define CONFIG_DM_SEQ_ALIAS		1
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MII		/* expose smi ove miiphy interface */
+#if !defined(CONFIG_ARMADA_375)
+#define CONFIG_MVNETA		/* Enable Marvell Gbe Controller Driver */
+#define CONFIG_PHYLIB
+#endif
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_PHY_GIGE		/* GbE speed/duplex detect */
+#define CONFIG_ARP_TIMEOUT	200
+#define CONFIG_NET_RETRY_COUNT	50
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#ifndef CONFIG_SYS_I2C_SOFT
+#define CONFIG_I2C_MVTWSI
+#endif
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+/* Use common timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER	(MVEBU_TIMER_BASE + 0x14)
+#define CONFIG_SYS_TIMER_RATE		25000000
+
+#endif /* __MVEBU_CONFIG_H */

u-boot/arch/arm/mach-mvebu/include/mach/cpu.h

@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MVEBU_CPU_H
+#define _MVEBU_CPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define MVEBU_REG_PCIE_DEVID		(MVEBU_REG_PCIE_BASE + 0x00)
+#define MVEBU_REG_PCIE_REVID		(MVEBU_REG_PCIE_BASE + 0x08)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+	BANK2,
+	BANK3
+};
+
+enum cpu_winen {
+	CPU_WIN_DISABLE,
+	CPU_WIN_ENABLE
+};
+
+enum cpu_target {
+	CPU_TARGET_DRAM = 0x0,
+	CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
+	CPU_TARGET_ETH23 = 0x3,
+	CPU_TARGET_PCIE02 = 0x4,
+	CPU_TARGET_ETH01 = 0x7,
+	CPU_TARGET_PCIE13 = 0x8,
+	CPU_TARGET_SASRAM = 0x9,
+	CPU_TARGET_NAND = 0xd,
+};
+
+enum cpu_attrib {
+	CPU_ATTR_SASRAM = 0x01,
+	CPU_ATTR_DRAM_CS0 = 0x0e,
+	CPU_ATTR_DRAM_CS1 = 0x0d,
+	CPU_ATTR_DRAM_CS2 = 0x0b,
+	CPU_ATTR_DRAM_CS3 = 0x07,
+	CPU_ATTR_NANDFLASH = 0x2f,
+	CPU_ATTR_SPIFLASH = 0x1e,
+	CPU_ATTR_SPI0_CS0 = 0x1e,
+	CPU_ATTR_SPI0_CS1 = 0x5e,
+	CPU_ATTR_SPI1_CS2 = 0x9a,
+	CPU_ATTR_BOOTROM = 0x1d,
+	CPU_ATTR_PCIE_IO = 0xe0,
+	CPU_ATTR_PCIE_MEM = 0xe8,
+	CPU_ATTR_DEV_CS0 = 0x3e,
+	CPU_ATTR_DEV_CS1 = 0x3d,
+	CPU_ATTR_DEV_CS2 = 0x3b,
+	CPU_ATTR_DEV_CS3 = 0x37,
+};
+
+enum {
+	MVEBU_SOC_AXP,
+	MVEBU_SOC_A375,
+	MVEBU_SOC_A38X,
+	MVEBU_SOC_UNKNOWN,
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define MBUS_PCI_MEM_BASE	0xE8000000
+#define MBUS_PCI_MEM_SIZE	(128 << 20)
+#define MBUS_PCI_IO_BASE	0xF1100000
+#define MBUS_PCI_IO_SIZE	(64 << 10)
+#define MBUS_SPI_BASE		0xF4000000
+#define MBUS_SPI_SIZE		(8 << 20)
+#define MBUS_BOOTROM_BASE	0xF8000000
+#define MBUS_BOOTROM_SIZE	(8 << 20)
+
+struct mbus_win {
+	u32 base;
+	u32 size;
+	u8 target;
+	u8 attr;
+};
+
+/*
+ * System registers
+ * Ref: Datasheet sec:A.28
+ */
+struct mvebu_system_registers {
+#if defined(CONFIG_ARMADA_375)
+	u8 pad1[0x54];
+#else
+	u8 pad1[0x60];
+#endif
+	u32 rstoutn_mask; /* 0x60 */
+	u32 sys_soft_rst; /* 0x64 */
+};
+
+/*
+ * GPIO Registers
+ * Ref: Datasheet sec:A.19
+ */
+struct kwgpio_registers {
+	u32 dout;
+	u32 oe;
+	u32 blink_en;
+	u32 din_pol;
+	u32 din;
+	u32 irq_cause;
+	u32 irq_mask;
+	u32 irq_level;
+};
+
+struct sar_freq_modes {
+	u8 val;
+	u8 ffc;		/* Fabric Frequency Configuration */
+	u32 p_clk;
+	u32 nb_clk;
+	u32 d_clk;
+};
+
+/* Needed for dynamic (board-specific) mbus configuration */
+extern struct mvebu_mbus_state mbus_state;
+
+/*
+ * functions
+ */
+unsigned int mvebu_sdram_bar(enum memory_bank bank);
+unsigned int mvebu_sdram_bs(enum memory_bank bank);
+void mvebu_sdram_size_adjust(enum memory_bank bank);
+int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_soc_family(void);
+u32 mvebu_get_nand_clock(void);
+
+void return_to_bootrom(void);
+
+int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
+void get_sar_freq(struct sar_freq_modes *sar_freq);
+
+/*
+ * Highspeed SERDES PHY config init, ported from bin_hdr
+ * to mainline U-Boot
+ */
+int serdes_phy_config(void);
+
+/*
+ * DDR3 init / training code ported from Marvell bin_hdr. Now
+ * available in mainline U-Boot in:
+ * drivers/ddr/marvell
+ */
+int ddr3_init(void);
+
+struct mvebu_lcd_info {
+	u32 fb_base;
+	int x_res;
+	int y_res;
+	int x_fp;		/* frontporch */
+	int y_fp;
+	int x_bp;		/* backporch */
+	int y_bp;
+};
+
+int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _MVEBU_CPU_H */

u-boot/arch/arm/mach-mvebu/include/mach/gpio.h

@@ -0,0 +1,10 @@
+/*
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __MACH_MVEBU_GPIO_H
+#define __MACH_MVEBU_GPIO_H
+
+/* Empty file - sdhci requires this. */
+
+#endif

u-boot/arch/arm/mach-mvebu/include/mach/soc.h

@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for the Marvell's Feroceon CPU core.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MVEBU_SOC_H
+#define _MVEBU_SOC_H
+
+#define SOC_MV78230_ID		0x7823
+#define SOC_MV78260_ID		0x7826
+#define SOC_MV78460_ID		0x7846
+#define SOC_88F6720_ID		0x6720
+#define SOC_88F6810_ID		0x6810
+#define SOC_88F6820_ID		0x6820
+#define SOC_88F6828_ID		0x6828
+
+/* A375 revisions */
+#define MV_88F67XX_A0_ID	0x3
+
+/* A38x revisions */
+#define MV_88F68XX_Z1_ID	0x0
+#define MV_88F68XX_A0_ID	0x4
+
+/* TCLK Core Clock definition */
+#ifndef CONFIG_SYS_TCLK
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+#endif
+
+/* Armada XP PLL frequency (used for NAND clock generation) */
+#define CONFIG_SYS_MVEBU_PLL_CLOCK	2000000000
+
+/* SOC specific definations */
+#define INTREG_BASE		0xd0000000
+#define INTREG_BASE_ADDR_REG	(INTREG_BASE + 0x20080)
+#if defined(CONFIG_SPL_BUILD)
+/*
+ * The SPL U-Boot version still runs with the default
+ * address for the internal registers, configured by
+ * the BootROM. Only the main U-Boot version uses the
+ * new internal register base address, that also is
+ * required for the Linux kernel.
+ */
+#define SOC_REGS_PHY_BASE	0xd0000000
+#else
+#define SOC_REGS_PHY_BASE	0xf1000000
+#endif
+#define MVEBU_REGISTER(x)	(SOC_REGS_PHY_BASE + x)
+
+#define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
+#define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
+#define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
+#define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
+#define MVEBU_TWSI1_BASE	(MVEBU_REGISTER(0x11100))
+#define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
+#define MVEBU_GPIO0_BASE	(MVEBU_REGISTER(0x18100))
+#define MVEBU_GPIO1_BASE	(MVEBU_REGISTER(0x18140))
+#define MVEBU_GPIO2_BASE	(MVEBU_REGISTER(0x18180))
+#define MVEBU_SYSTEM_REG_BASE	(MVEBU_REGISTER(0x18200))
+#define MVEBU_CLOCK_BASE	(MVEBU_REGISTER(0x18700))
+#define MVEBU_CPU_WIN_BASE	(MVEBU_REGISTER(0x20000))
+#define MVEBU_SDRAM_BASE	(MVEBU_REGISTER(0x20180))
+#define MVEBU_TIMER_BASE	(MVEBU_REGISTER(0x20300))
+#define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
+#define MVEBU_AXP_USB_BASE      (MVEBU_REGISTER(0x50000))
+#define MVEBU_USB20_BASE	(MVEBU_REGISTER(0x58000))
+#define MVEBU_AXP_SATA_BASE	(MVEBU_REGISTER(0xa0000))
+#define MVEBU_SATA0_BASE	(MVEBU_REGISTER(0xa8000))
+#define MVEBU_NAND_BASE		(MVEBU_REGISTER(0xd0000))
+#define MVEBU_SDIO_BASE		(MVEBU_REGISTER(0xd8000))
+#define MVEBU_LCD_BASE		(MVEBU_REGISTER(0xe0000))
+
+#define SOC_COHERENCY_FABRIC_CTRL_REG	(MVEBU_REGISTER(0x20200))
+#define MBUS_ERR_PROP_EN	(1 << 8)
+
+#define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
+#define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
+
+#define MVEBU_SOC_DEV_MUX_REG	(MVEBU_SYSTEM_REG_BASE + 0x08)
+#define NAND_EN			BIT(0)
+#define NAND_ARBITER_EN		BIT(27)
+
+#define ARMADA_XP_PUP_ENABLE	(MVEBU_SYSTEM_REG_BASE + 0x44c)
+#define GE0_PUP_EN		BIT(0)
+#define GE1_PUP_EN		BIT(1)
+#define LCD_PUP_EN		BIT(2)
+#define NAND_PUP_EN		BIT(4)
+#define SPI_PUP_EN		BIT(5)
+
+#define MVEBU_CORE_DIV_CLK_CTRL(i)	(MVEBU_CLOCK_BASE + ((i) * 0x8))
+#define NAND_ECC_DIVCKL_RATIO_OFFS	8
+#define NAND_ECC_DIVCKL_RATIO_MASK	(0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
+
+#define SDRAM_MAX_CS		4
+#define SDRAM_ADDR_MASK		0xFF000000
+
+/* MVEBU CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA	CPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE	CPU_WIN_ENABLE
+#define MVCPU_WIN_DISABLE	CPU_WIN_DISABLE
+
+#define COMPHY_REFCLK_ALIGNMENT	(MVEBU_REGISTER(0x182f8))
+
+/* BootROM error register (also includes some status infos) */
+#define CONFIG_BOOTROM_ERR_REG	(MVEBU_REGISTER(0x182d0))
+#define BOOTROM_ERR_MODE_OFFS	28
+#define BOOTROM_ERR_MODE_MASK	(0xf << BOOTROM_ERR_MODE_OFFS)
+#define BOOTROM_ERR_MODE_UART	0x6
+
+#if defined(CONFIG_ARMADA_375)
+/* SAR values for Armada 375 */
+#define CONFIG_SAR_REG		(MVEBU_REGISTER(0xe8200))
+#define CONFIG_SAR2_REG		(MVEBU_REGISTER(0xe8204))
+
+#define SAR_CPU_FREQ_OFFS	17
+#define SAR_CPU_FREQ_MASK	(0x1f << SAR_CPU_FREQ_OFFS)
+
+#define BOOT_DEV_SEL_OFFS	3
+#define BOOT_DEV_SEL_MASK	(0x3f << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART		0x30
+#define BOOT_FROM_SPI		0x38
+#elif defined(CONFIG_ARMADA_38X)
+/* SAR values for Armada 38x */
+#define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18600))
+
+#define SAR_CPU_FREQ_OFFS	10
+#define SAR_CPU_FREQ_MASK	(0x1f << SAR_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS	4
+#define SAR_BOOT_DEVICE_MASK	(0x1f << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS	4
+#define BOOT_DEV_SEL_MASK	(0x3f << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART		0x28
+#define BOOT_FROM_SPI		0x32
+#define BOOT_FROM_MMC		0x30
+#define BOOT_FROM_MMC_ALT	0x31
+#else
+/* SAR values for Armada XP */
+#define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18230))
+#define CONFIG_SAR2_REG		(MVEBU_REGISTER(0x18234))
+
+#define SAR_CPU_FREQ_OFFS	21
+#define SAR_CPU_FREQ_MASK	(0x7 << SAR_CPU_FREQ_OFFS)
+#define SAR_FFC_FREQ_OFFS	24
+#define SAR_FFC_FREQ_MASK	(0xf << SAR_FFC_FREQ_OFFS)
+#define SAR2_CPU_FREQ_OFFS	20
+#define SAR2_CPU_FREQ_MASK	(0x1 << SAR2_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS	5
+#define SAR_BOOT_DEVICE_MASK	(0xf << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS	5
+#define BOOT_DEV_SEL_MASK	(0xf << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART		0x2
+#define BOOT_FROM_SPI		0x3
+#endif
+
+#endif /* _MVEBU_SOC_H */