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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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70
u-boot/arch/arm/mach-exynos/include/mach/adc.h Normal file
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/*
* Copyright (C) 2010 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* MyungJoo Ham <myungjoo.ham@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_ARCH_ADC_H_
#define __ASM_ARM_ARCH_ADC_H_
#define ADC_V2_CON1_SOFT_RESET (0x2 << 1)
#define ADC_V2_CON1_STC_EN 0x1
#define ADC_V2_CON2_OSEL(x) (((x) & 0x1) << 10)
#define OSEL_2S 0x0
#define OSEL_BINARY 0x1
#define ADC_V2_CON2_ESEL(x) (((x) & 0x1) << 9)
#define ESEL_ADC_EVAL_TIME_40CLK 0x0
#define ESEL_ADC_EVAL_TIME_20CLK 0x1
#define ADC_V2_CON2_HIGHF(x) (((x) & 0x1) << 8)
#define HIGHF_CONV_RATE_30KSPS 0x0
#define HIGHF_CONV_RATE_600KSPS 0x1
#define ADC_V2_CON2_C_TIME(x) (((x) & 0x7) << 4)
#define ADC_V2_CON2_CHAN_SEL_MASK 0xf
#define ADC_V2_CON2_CHAN_SEL(x) ((x) & ADC_V2_CON2_CHAN_SEL_MASK)
#define ADC_V2_GET_STATUS_FLAG(x) (((x) >> 2) & 0x1)
#define FLAG_CONV_END 0x1
#define ADC_V2_INT_DISABLE 0x0
#define ADC_V2_INT_ENABLE 0x1
#define INT_NOT_GENERATED 0x0
#define INT_GENERATED 0x1
#define ADC_V2_VERSION 0x80000008
#define ADC_V2_MAX_CHANNEL 9
/* For default 8 time convertion with sample rate 600 kSPS - 15us timeout */
#define ADC_V2_CONV_TIMEOUT_US 15
#define ADC_V2_DAT_MASK 0xfff
#ifndef __ASSEMBLY__
struct s5p_adc {
unsigned int adccon;
unsigned int adctsc;
unsigned int adcdly;
unsigned int adcdat0;
unsigned int adcdat1;
unsigned int adcupdn;
unsigned int adcclrint;
unsigned int adcmux;
unsigned int adcclrintpndnup;
};
struct exynos_adc_v2 {
unsigned int con1;
unsigned int con2;
unsigned int status;
unsigned int dat;
unsigned int int_en;
unsigned int int_status;
unsigned int reserved[2];
unsigned int version;
};
#endif
#endif /* __ASM_ARM_ARCH_ADC_H_ */

29
u-boot/arch/arm/mach-exynos/include/mach/board.h Normal file
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/*
* (C) Copyright 2013 Samsung Electronics
* Rajeshwari Shinde <rajeshwari.s@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EXYNOS_BOARD_H
#define _EXYNOS_BOARD_H
/*
* Exynos baord specific changes for
* board_init
*/
int exynos_init(void);
/*
* Exynos board specific changes for
* board_early_init_f
*/
int exynos_early_init_f(void);
/*
* Exynos board specific changes for
* board_power_init
*/
int exynos_power_init(void);
#endif /* EXYNOS_BOARD_H */

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u-boot/arch/arm/mach-exynos/include/mach/clk.h Normal file
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/*
* (C) Copyright 2010 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_ARCH_CLK_H_
#define __ASM_ARM_ARCH_CLK_H_
#define APLL 0
#define MPLL 1
#define EPLL 2
#define HPLL 3
#define VPLL 4
#define BPLL 5
#define RPLL 6
#define SPLL 7
#define CPLL 8
#define DPLL 9
#define IPLL 10
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
#define MASK_RATIO(x) (0xf << (x << 4))
#define SET_PRE_RATIO(x, y) ((y & 0xff) << ((x << 4) + 8))
#define SET_RATIO(x, y) ((y & 0xf) << (x << 4))
enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,
EXYNOS_SRC_EPLL,
EXYNOS_SRC_VPLL,
EXYNOS542X_SRC_MPLL = 3,
EXYNOS542X_SRC_SPLL,
EXYNOS542X_SRC_EPLL = 6,
EXYNOS542X_SRC_RPLL,
};
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned long get_i2c_clk(void);
unsigned long get_pwm_clk(void);
unsigned long get_uart_clk(int dev_index);
unsigned long get_mmc_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);
unsigned long get_lcd_clk(void);
void set_lcd_clk(void);
void set_mipi_clk(void);
int set_i2s_clk_source(unsigned int i2s_id);
int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
unsigned int i2s_id);
int set_epll_clk(unsigned long rate);
int set_spi_clk(int periph_id, unsigned int rate);
/**
* get the clk frequency of the required peripheral
*
* @param peripheral Peripheral id
*
* @return frequency of the peripheral clk
*/
unsigned long clock_get_periph_rate(int peripheral);
#endif

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u-boot/arch/arm/mach-exynos/include/mach/clock.h Normal file
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u-boot/arch/arm/mach-exynos/include/mach/cpu.h Normal file
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/*
* (C) Copyright 2010 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EXYNOS4_CPU_H
#define _EXYNOS4_CPU_H
#define DEVICE_NOT_AVAILABLE 0
#define EXYNOS_CPU_NAME "Exynos"
#define EXYNOS4_ADDR_BASE 0x10000000
/* EXYNOS4 Common*/
#define EXYNOS4_I2C_SPACING 0x10000
#define EXYNOS4_GPIO_PART3_BASE 0x03860000
#define EXYNOS4_PRO_ID 0x10000000
#define EXYNOS4_SYSREG_BASE 0x10010000
#define EXYNOS4_POWER_BASE 0x10020000
#define EXYNOS4_SWRESET 0x10020400
#define EXYNOS4_CLOCK_BASE 0x10030000
#define EXYNOS4_SYSTIMER_BASE 0x10050000
#define EXYNOS4_WATCHDOG_BASE 0x10060000
#define EXYNOS4_TZPC_BASE 0x10110000
#define EXYNOS4_DMC_CTRL_BASE 0x10400000
#define EXYNOS4_MIU_BASE 0x10600000
#define EXYNOS4_ACE_SFR_BASE 0x10830000
#define EXYNOS4_GPIO_PART2_BASE 0x11000000
#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */
#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */
#define EXYNOS4_GPIO_PART1_BASE 0x11400000
#define EXYNOS4_FIMD_BASE 0x11C00000
#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
#define EXYNOS4_USBOTG_BASE 0x12480000
#define EXYNOS4_MMC_BASE 0x12510000
#define EXYNOS4_SROMC_BASE 0x12570000
#define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000
#define EXYNOS4_USBPHY_BASE 0x125B0000
#define EXYNOS4_UART_BASE 0x13800000
#define EXYNOS4_I2C_BASE 0x13860000
#define EXYNOS4_ADC_BASE 0x13910000
#define EXYNOS4_SPI_BASE 0x13920000
#define EXYNOS4_PWMTIMER_BASE 0x139D0000
#define EXYNOS4_MODEM_BASE 0x13A00000
#define EXYNOS4_USBPHY_CONTROL 0x10020704
#define EXYNOS4_I2S_BASE 0xE2100000
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS4X12 */
#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
#define EXYNOS4X12_PRO_ID 0x10000000
#define EXYNOS4X12_SYSREG_BASE 0x10010000
#define EXYNOS4X12_POWER_BASE 0x10020000
#define EXYNOS4X12_SWRESET 0x10020400
#define EXYNOS4X12_USBPHY_CONTROL 0x10020704
#define EXYNOS4X12_CLOCK_BASE 0x10030000
#define EXYNOS4X12_SYSTIMER_BASE 0x10050000
#define EXYNOS4X12_WATCHDOG_BASE 0x10060000
#define EXYNOS4X12_TZPC_BASE 0x10110000
#define EXYNOS4X12_DMC_CTRL_BASE 0x10600000
#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
#define EXYNOS4X12_ACE_SFR_BASE 0x10830000
#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
#define EXYNOS4X12_GPIO_PART2_0 0x11000000
#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */
#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */
#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */
#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */
#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */
#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */
#define EXYNOS4X12_FIMD_BASE 0x11C00000
#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
#define EXYNOS4X12_USBOTG_BASE 0x12480000
#define EXYNOS4X12_MMC_BASE 0x12510000
#define EXYNOS4X12_SROMC_BASE 0x12570000
#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000
#define EXYNOS4X12_USBPHY_BASE 0x125B0000
#define EXYNOS4X12_UART_BASE 0x13800000
#define EXYNOS4X12_I2C_BASE 0x13860000
#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000
#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5 */
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_AUDIOSS_BASE 0x03810000
#define EXYNOS5_GPIO_PART8_BASE 0x03860000
#define EXYNOS5_PRO_ID 0x10000000
#define EXYNOS5_CLOCK_BASE 0x10010000
#define EXYNOS5_POWER_BASE 0x10040000
#define EXYNOS5_SWRESET 0x10040400
#define EXYNOS5_SYSREG_BASE 0x10050000
#define EXYNOS5_TZPC_BASE 0x10100000
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_DMC_PHY_BASE 0x10C00000
#define EXYNOS5_GPIO_PART5_BASE 0x10D10000
#define EXYNOS5_GPIO_PART6_BASE 0x10D10060
#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
#define EXYNOS5_GPIO_PART2_BASE 0x114002E0
#define EXYNOS5_GPIO_PART3_BASE 0x11400C00
#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000
#define EXYNOS5_USB3PHY_BASE 0x12100000
#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
#define EXYNOS5_USBPHY_BASE 0x12130000
#define EXYNOS5_USBOTG_BASE 0x12140000
#define EXYNOS5_MMC_BASE 0x12200000
#define EXYNOS5_SROMC_BASE 0x12250000
#define EXYNOS5_UART_BASE 0x12C00000
#define EXYNOS5_I2C_BASE 0x12C60000
#define EXYNOS5_SPI_BASE 0x12D20000
#define EXYNOS5_I2S_BASE 0x12D60000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5_SPI_ISP_BASE 0x131A0000
#define EXYNOS5_GPIO_PART4_BASE 0x13400000
#define EXYNOS5_FIMD_BASE 0x14400000
#define EXYNOS5_DP_BASE 0x145B0000
#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5420 */
#define EXYNOS5420_AUDIOSS_BASE 0x03810000
#define EXYNOS5420_GPIO_PART6_BASE 0x03860000
#define EXYNOS5420_PRO_ID 0x10000000
#define EXYNOS5420_CLOCK_BASE 0x10010000
#define EXYNOS5420_POWER_BASE 0x10040000
#define EXYNOS5420_SWRESET 0x10040400
#define EXYNOS5420_INFORM_BASE 0x10040800
#define EXYNOS5420_SPARE_BASE 0x10040900
#define EXYNOS5420_CPU_CONFIG_BASE 0x10042000
#define EXYNOS5420_CPU_STATUS_BASE 0x10042004
#define EXYNOS5420_SYSREG_BASE 0x10050000
#define EXYNOS5420_TZPC_BASE 0x100E0000
#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
#define EXYNOS5420_ACE_SFR_BASE 0x10830000
#define EXYNOS5420_DMC_PHY_BASE 0x10C00000
#define EXYNOS5420_DMC_CTRL_BASE 0x10C20000
#define EXYNOS5420_DMC_TZASC_BASE 0x10D40000
#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000
#define EXYNOS5420_MMC_BASE 0x12200000
#define EXYNOS5420_SROMC_BASE 0x12250000
#define EXYNOS5420_USB3PHY_BASE 0x12500000
#define EXYNOS5420_UART_BASE 0x12C00000
#define EXYNOS5420_I2C_BASE 0x12C60000
#define EXYNOS5420_I2C_8910_BASE 0x12E00000
#define EXYNOS5420_SPI_BASE 0x12D20000
#define EXYNOS5420_I2S_BASE 0x12D60000
#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
#define EXYNOS5420_GPIO_PART4_BASE 0x13410000
#define EXYNOS5420_GPIO_PART5_BASE 0x14000000
#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
#define EXYNOS5420_DP_BASE 0x145B0000
#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
#ifndef __ASSEMBLY__
#include <asm/io.h>
/* CPU detection macros */
extern unsigned int s5p_cpu_id;
extern unsigned int s5p_cpu_rev;
static inline int s5p_get_cpu_rev(void)
{
return s5p_cpu_rev;
}
static inline void s5p_set_cpu_id(void)
{
unsigned int pro_id = readl(EXYNOS4_PRO_ID);
unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12;
unsigned int cpu_rev = pro_id & 0x000000FF;
switch (cpu_id) {
case 0x200:
/* Exynos4210 EVT0 */
s5p_cpu_id = 0x4210;
s5p_cpu_rev = 0;
break;
case 0x210:
/* Exynos4210 EVT1 */
s5p_cpu_id = 0x4210;
s5p_cpu_rev = cpu_rev;
break;
case 0x412:
/* Exynos4412 */
s5p_cpu_id = 0x4412;
s5p_cpu_rev = cpu_rev;
break;
case 0x520:
/* Exynos5250 */
s5p_cpu_id = 0x5250;
break;
case 0x420:
/* Exynos5420 */
s5p_cpu_id = 0x5420;
break;
case 0x422:
/*
* Exynos5800 is a variant of Exynos5420
* and has product id 0x5422
*/
s5p_cpu_id = 0x5422;
break;
}
}
static inline char *s5p_get_cpu_name(void)
{
return EXYNOS_CPU_NAME;
}
#define IS_SAMSUNG_TYPE(type, id) \
static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \
{ \
return (s5p_cpu_id >> 12) == id; \
}
IS_SAMSUNG_TYPE(exynos4, 0x4)
IS_SAMSUNG_TYPE(exynos5, 0x5)
#define IS_EXYNOS_TYPE(type, id) \
static inline int __attribute__((no_instrument_function)) \
proid_is_##type(void) \
{ \
return s5p_cpu_id == id; \
}
IS_EXYNOS_TYPE(exynos4210, 0x4210)
IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
IS_EXYNOS_TYPE(exynos5420, 0x5420)
IS_EXYNOS_TYPE(exynos5422, 0x5422)
#define SAMSUNG_BASE(device, base) \
static inline unsigned long __attribute__((no_instrument_function)) \
samsung_get_base_##device(void) \
{ \
if (cpu_is_exynos4()) { \
if (proid_is_exynos4412()) \
return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
} else if (cpu_is_exynos5()) { \
if (proid_is_exynos5420() || proid_is_exynos5422()) \
return EXYNOS5420_##base; \
return EXYNOS5_##base; \
} \
return 0; \
}
SAMSUNG_BASE(adc, ADC_BASE)
SAMSUNG_BASE(clock, CLOCK_BASE)
SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
SAMSUNG_BASE(sysreg, SYSREG_BASE)
SAMSUNG_BASE(i2c, I2C_BASE)
SAMSUNG_BASE(i2s, I2S_BASE)
SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
SAMSUNG_BASE(pro_id, PRO_ID)
SAMSUNG_BASE(mmc, MMC_BASE)
SAMSUNG_BASE(modem, MODEM_BASE)
SAMSUNG_BASE(sromc, SROMC_BASE)
SAMSUNG_BASE(swreset, SWRESET)
SAMSUNG_BASE(timer, PWMTIMER_BASE)
SAMSUNG_BASE(uart, UART_BASE)
SAMSUNG_BASE(usb_phy, USBPHY_BASE)
SAMSUNG_BASE(usb3_phy, USB3PHY_BASE)
SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE)
SAMSUNG_BASE(usb_otg, USBOTG_BASE)
SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
SAMSUNG_BASE(power, POWER_BASE)
SAMSUNG_BASE(spi, SPI_BASE)
SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
SAMSUNG_BASE(tzpc, TZPC_BASE)
SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE)
SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
#endif
#endif /* _EXYNOS4_CPU_H */

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u-boot/arch/arm/mach-exynos/include/mach/dmc.h Normal file
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#ifndef __DMC_H__
#define __DMC_H__
#ifndef __ASSEMBLY__
struct exynos4_dmc {
unsigned int concontrol;
unsigned int memcontrol;
unsigned int memconfig0;
unsigned int memconfig1;
unsigned int directcmd;
unsigned int prechconfig;
unsigned int phycontrol0;
unsigned int phycontrol1;
unsigned int phycontrol2;
unsigned int phycontrol3;
unsigned int pwrdnconfig;
unsigned char res1[0x4];
unsigned int timingref;
unsigned int timingrow;
unsigned int timingdata;
unsigned int timingpower;
unsigned int phystatus;
unsigned int phyzqcontrol;
unsigned int chip0status;
unsigned int chip1status;
unsigned int arefstatus;
unsigned int mrstatus;
unsigned int phytest0;
unsigned int phytest1;
unsigned int qoscontrol0;
unsigned int qosconfig0;
unsigned int qoscontrol1;
unsigned int qosconfig1;
unsigned int qoscontrol2;
unsigned int qosconfig2;
unsigned int qoscontrol3;
unsigned int qosconfig3;
unsigned int qoscontrol4;
unsigned int qosconfig4;
unsigned int qoscontrol5;
unsigned int qosconfig5;
unsigned int qoscontrol6;
unsigned int qosconfig6;
unsigned int qoscontrol7;
unsigned int qosconfig7;
unsigned int qoscontrol8;
unsigned int qosconfig8;
unsigned int qoscontrol9;
unsigned int qosconfig9;
unsigned int qoscontrol10;
unsigned int qosconfig10;
unsigned int qoscontrol11;
unsigned int qosconfig11;
unsigned int qoscontrol12;
unsigned int qosconfig12;
unsigned int qoscontrol13;
unsigned int qosconfig13;
unsigned int qoscontrol14;
unsigned int qosconfig14;
unsigned int qoscontrol15;
unsigned int qosconfig15;
unsigned int qostimeout0;
unsigned int qostimeout1;
unsigned char res2[0x8];
unsigned int ivcontrol;
unsigned char res3[0x8];
unsigned int perevconfig;
unsigned char res4[0xDF00];
unsigned int pmnc_ppc_a;
unsigned char res5[0xC];
unsigned int cntens_ppc_a;
unsigned char res6[0xC];
unsigned int cntenc_ppc_a;
unsigned char res7[0xC];
unsigned int intens_ppc_a;
unsigned char res8[0xC];
unsigned int intenc_ppc_a;
unsigned char res9[0xC];
unsigned int flag_ppc_a;
unsigned char res10[0xAC];
unsigned int ccnt_ppc_a;
unsigned char res11[0xC];
unsigned int pmcnt0_ppc_a;
unsigned char res12[0xC];
unsigned int pmcnt1_ppc_a;
unsigned char res13[0xC];
unsigned int pmcnt2_ppc_a;
unsigned char res14[0xC];
unsigned int pmcnt3_ppc_a;
unsigned char res15[0xEBC];
unsigned int pmnc_ppc_m;
unsigned char res16[0xC];
unsigned int cntens_ppc_m;
unsigned char res17[0xC];
unsigned int cntenc_ppc_m;
unsigned char res18[0xC];
unsigned int intens_ppc_m;
unsigned char res19[0xC];
unsigned int intenc_ppc_m;
unsigned char res20[0xC];
unsigned int flag_ppc_m;
unsigned char res21[0xAC];
unsigned int ccnt_ppc_m;
unsigned char res22[0xC];
unsigned int pmcnt0_ppc_m;
unsigned char res23[0xC];
unsigned int pmcnt1_ppc_m;
unsigned char res24[0xC];
unsigned int pmcnt2_ppc_m;
unsigned char res25[0xC];
unsigned int pmcnt3_ppc_m;
};
struct exynos5_dmc {
unsigned int concontrol;
unsigned int memcontrol;
unsigned int memconfig0;
unsigned int memconfig1;
unsigned int directcmd;
unsigned int prechconfig;
unsigned int phycontrol0;
unsigned char res1[0xc];
unsigned int pwrdnconfig;
unsigned int timingpzq;
unsigned int timingref;
unsigned int timingrow;
unsigned int timingdata;
unsigned int timingpower;
unsigned int phystatus;
unsigned char res2[0x4];
unsigned int chipstatus_ch0;
unsigned int chipstatus_ch1;
unsigned char res3[0x4];
unsigned int mrstatus;
unsigned char res4[0x8];
unsigned int qoscontrol0;
unsigned char resr5[0x4];
unsigned int qoscontrol1;
unsigned char res6[0x4];
unsigned int qoscontrol2;
unsigned char res7[0x4];
unsigned int qoscontrol3;
unsigned char res8[0x4];
unsigned int qoscontrol4;
unsigned char res9[0x4];
unsigned int qoscontrol5;
unsigned char res10[0x4];
unsigned int qoscontrol6;
unsigned char res11[0x4];
unsigned int qoscontrol7;
unsigned char res12[0x4];
unsigned int qoscontrol8;
unsigned char res13[0x4];
unsigned int qoscontrol9;
unsigned char res14[0x4];
unsigned int qoscontrol10;
unsigned char res15[0x4];
unsigned int qoscontrol11;
unsigned char res16[0x4];
unsigned int qoscontrol12;
unsigned char res17[0x4];
unsigned int qoscontrol13;
unsigned char res18[0x4];
unsigned int qoscontrol14;
unsigned char res19[0x4];
unsigned int qoscontrol15;
unsigned char res20[0x14];
unsigned int ivcontrol;
unsigned int wrtra_config;
unsigned int rdlvl_config;
unsigned char res21[0x8];
unsigned int brbrsvconfig;
unsigned int brbqosconfig;
unsigned int membaseconfig0;
unsigned int membaseconfig1;
unsigned char res22[0xc];
unsigned int wrlvl_config;
unsigned char res23[0xc];
unsigned int perevcontrol;
unsigned int perev0config;
unsigned int perev1config;
unsigned int perev2config;
unsigned int perev3config;
unsigned char res24[0xdebc];
unsigned int pmnc_ppc_a;
unsigned char res25[0xc];
unsigned int cntens_ppc_a;
unsigned char res26[0xc];
unsigned int cntenc_ppc_a;
unsigned char res27[0xc];
unsigned int intens_ppc_a;
unsigned char res28[0xc];
unsigned int intenc_ppc_a;
unsigned char res29[0xc];
unsigned int flag_ppc_a;
unsigned char res30[0xac];
unsigned int ccnt_ppc_a;
unsigned char res31[0xc];
unsigned int pmcnt0_ppc_a;
unsigned char res32[0xc];
unsigned int pmcnt1_ppc_a;
unsigned char res33[0xc];
unsigned int pmcnt2_ppc_a;
unsigned char res34[0xc];
unsigned int pmcnt3_ppc_a;
};
struct exynos5420_dmc {
unsigned int concontrol;
unsigned int memcontrol;
unsigned int cgcontrol;
unsigned char res500[0x4];
unsigned int directcmd;
unsigned int prechconfig0;
unsigned int phycontrol0;
unsigned int prechconfig1;
unsigned char res1[0x8];
unsigned int pwrdnconfig;
unsigned int timingpzq;
unsigned int timingref;
unsigned int timingrow0;
unsigned int timingdata0;
unsigned int timingpower0;
unsigned int phystatus;
unsigned int etctiming;
unsigned int chipstatus;
unsigned char res3[0x8];
unsigned int mrstatus;
unsigned char res4[0x8];
unsigned int qoscontrol0;
unsigned char resr5[0x4];
unsigned int qoscontrol1;
unsigned char res6[0x4];
unsigned int qoscontrol2;
unsigned char res7[0x4];
unsigned int qoscontrol3;
unsigned char res8[0x4];
unsigned int qoscontrol4;
unsigned char res9[0x4];
unsigned int qoscontrol5;
unsigned char res10[0x4];
unsigned int qoscontrol6;
unsigned char res11[0x4];
unsigned int qoscontrol7;
unsigned char res12[0x4];
unsigned int qoscontrol8;
unsigned char res13[0x4];
unsigned int qoscontrol9;
unsigned char res14[0x4];
unsigned int qoscontrol10;
unsigned char res15[0x4];
unsigned int qoscontrol11;
unsigned char res16[0x4];
unsigned int qoscontrol12;
unsigned char res17[0x4];
unsigned int qoscontrol13;
unsigned char res18[0x4];
unsigned int qoscontrol14;
unsigned char res19[0x4];
unsigned int qoscontrol15;
unsigned char res20[0x4];
unsigned int timing_set_sw;
unsigned int timingrow1;
unsigned int timingdata1;
unsigned int timingpower1;
unsigned char res300[0x4];
unsigned int wrtra_config;
unsigned int rdlvl_config;
unsigned char res21[0x4];
unsigned int brbrsvcontrol;
unsigned int brbrsvconfig;
unsigned int brbqosconfig;
unsigned char res301[0x14];
unsigned int wrlvl_config0;
unsigned int wrlvl_config1;
unsigned int wrlvl_status;
unsigned char res23[0x4];
unsigned int ppcclockon;
unsigned int perevconfig0;
unsigned int perevconfig1;
unsigned int perevconfig2;
unsigned int perevconfig3;
unsigned char res24[0xc];
unsigned int control_io_rdata;
unsigned char res240[0xc];
unsigned int cacal_config0;
unsigned int cacal_config1;
unsigned int cacal_status;
unsigned char res302[0xa4];
unsigned int bp_control0;
unsigned int bp_config0_r;
unsigned int bp_config0_w;
unsigned char res303[0x4];
unsigned int bp_control1;
unsigned int bp_config1_r;
unsigned int bp_config1_w;
unsigned char res304[0x4];
unsigned int bp_control2;
unsigned int bp_config2_r;
unsigned int bp_config2_w;
unsigned char res305[0x4];
unsigned int bp_control3;
unsigned int bp_config3_r;
unsigned int bp_config3_w;
unsigned char res306[0xddb4];
unsigned int pmnc_ppc;
unsigned char res25[0xc];
unsigned int cntens_ppc;
unsigned char res26[0xc];
unsigned int cntenc_ppc;
unsigned char res27[0xc];
unsigned int intens_ppc;
unsigned char res28[0xc];
unsigned int intenc_ppc;
unsigned char res29[0xc];
unsigned int flag_ppc;
unsigned char res30[0xac];
unsigned int ccnt_ppc;
unsigned char res31[0xc];
unsigned int pmcnt0_ppc;
unsigned char res32[0xc];
unsigned int pmcnt1_ppc;
unsigned char res33[0xc];
unsigned int pmcnt2_ppc;
unsigned char res34[0xc];
unsigned int pmcnt3_ppc;
};
struct exynos5_phy_control {
unsigned int phy_con0;
unsigned int phy_con1;
unsigned int phy_con2;
unsigned int phy_con3;
unsigned int phy_con4;
unsigned char res1[4];
unsigned int phy_con6;
unsigned char res2[4];
unsigned int phy_con8;
unsigned int phy_con9;
unsigned int phy_con10;
unsigned char res3[4];
unsigned int phy_con12;
unsigned int phy_con13;
unsigned int phy_con14;
unsigned int phy_con15;
unsigned int phy_con16;
unsigned char res4[4];
unsigned int phy_con17;
unsigned int phy_con18;
unsigned int phy_con19;
unsigned int phy_con20;
unsigned int phy_con21;
unsigned int phy_con22;
unsigned int phy_con23;
unsigned int phy_con24;
unsigned int phy_con25;
unsigned int phy_con26;
unsigned int phy_con27;
unsigned int phy_con28;
unsigned int phy_con29;
unsigned int phy_con30;
unsigned int phy_con31;
unsigned int phy_con32;
unsigned int phy_con33;
unsigned int phy_con34;
unsigned int phy_con35;
unsigned int phy_con36;
unsigned int phy_con37;
unsigned int phy_con38;
unsigned int phy_con39;
unsigned int phy_con40;
unsigned int phy_con41;
unsigned int phy_con42;
};
struct exynos5420_phy_control {
unsigned int phy_con0;
unsigned int phy_con1;
unsigned int phy_con2;
unsigned int phy_con3;
unsigned int phy_con4;
unsigned int phy_con5;
unsigned int phy_con6;
unsigned char res2[0x4];
unsigned int phy_con8;
unsigned char res5[0x4];
unsigned int phy_con10;
unsigned int phy_con11;
unsigned int phy_con12;
unsigned int phy_con13;
unsigned int phy_con14;
unsigned int phy_con15;
unsigned int phy_con16;
unsigned char res4[0x4];
unsigned int phy_con17;
unsigned int phy_con18;
unsigned int phy_con19;
unsigned int phy_con20;
unsigned int phy_con21;
unsigned int phy_con22;
unsigned int phy_con23;
unsigned int phy_con24;
unsigned int phy_con25;
unsigned int phy_con26;
unsigned int phy_con27;
unsigned int phy_con28;
unsigned int phy_con29;
unsigned int phy_con30;
unsigned int phy_con31;
unsigned int phy_con32;
unsigned int phy_con33;
unsigned int phy_con34;
unsigned char res6[0x8];
unsigned int phy_con37;
unsigned char res7[0x4];
unsigned int phy_con39;
unsigned int phy_con40;
unsigned int phy_con41;
unsigned int phy_con42;
};
struct exynos5420_tzasc {
unsigned char res1[0xf00];
unsigned int membaseconfig0;
unsigned int membaseconfig1;
unsigned char res2[0x8];
unsigned int memconfig0;
unsigned int memconfig1;
};
enum ddr_mode {
DDR_MODE_DDR2,
DDR_MODE_DDR3,
DDR_MODE_LPDDR2,
DDR_MODE_LPDDR3,
DDR_MODE_COUNT,
};
enum mem_manuf {
MEM_MANUF_AUTODETECT,
MEM_MANUF_ELPIDA,
MEM_MANUF_SAMSUNG,
MEM_MANUF_COUNT,
};
/* CONCONTROL register fields */
#define CONCONTROL_DFI_INIT_START_SHIFT 28
#define CONCONTROL_RD_FETCH_SHIFT 12
#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
#define CONCONTROL_AREF_EN_SHIFT 5
#define CONCONTROL_UPDATE_MODE (1 << 3)
/* PRECHCONFIG register field */
#define PRECHCONFIG_TP_CNT_SHIFT 24
/* PWRDNCONFIG register field */
#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
#define PWRDNCONFIG_DSREF_CYC_SHIFT 16
/* PHY_CON0 register fields */
#define PHY_CON0_T_WRRDCMD_SHIFT 17
#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3
/* PHY_CON1 register fields */
#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
/* PHY_CON4 rgister fields */
#define PHY_CON10_CTRL_OFFSETR3 (1 << 24)
/* PHY_CON12 register fields */
#define PHY_CON12_CTRL_START_POINT_SHIFT 24
#define PHY_CON12_CTRL_INC_SHIFT 16
#define PHY_CON12_CTRL_FORCE_SHIFT 8
#define PHY_CON12_CTRL_START_SHIFT 6
#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
#define PHY_CON12_CTRL_DLL_ON_SHIFT 5
#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
#define PHY_CON12_CTRL_REF_SHIFT 1
/* PHY_CON16 register fields */
#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24
#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
/* PHY_CON42 register fields */
#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
#define PHY_CON42_CTRL_RDLAT_SHIFT 0
#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
#endif
#endif

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u-boot/arch/arm/mach-exynos/include/mach/dp.h Normal file
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/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_ARCH_DP_H_
#define __ASM_ARM_ARCH_DP_H_
#ifndef __ASSEMBLY__
struct exynos_dp {
unsigned char res1[0x10];
unsigned int tx_version;
unsigned int tx_sw_reset;
unsigned int func_en1;
unsigned int func_en2;
unsigned int video_ctl1;
unsigned int video_ctl2;
unsigned int video_ctl3;
unsigned int video_ctl4;
unsigned int color_blue_cb;
unsigned int color_green_y;
unsigned int color_red_cr;
unsigned int video_ctl8;
unsigned char res2[0x4];
unsigned int video_ctl10;
unsigned int total_ln_cfg_l;
unsigned int total_ln_cfg_h;
unsigned int active_ln_cfg_l;
unsigned int active_ln_cfg_h;
unsigned int vfp_cfg;
unsigned int vsw_cfg;
unsigned int vbp_cfg;
unsigned int total_pix_cfg_l;
unsigned int total_pix_cfg_h;
unsigned int active_pix_cfg_l;
unsigned int active_pix_cfg_h;
unsigned int hfp_cfg_l;
unsigned int hfp_cfg_h;
unsigned int hsw_cfg_l;
unsigned int hsw_cfg_h;
unsigned int hbp_cfg_l;
unsigned int hbp_cfg_h;
unsigned int video_status;
unsigned int total_ln_sta_l;
unsigned int total_ln_sta_h;
unsigned int active_ln_sta_l;
unsigned int active_ln_sta_h;
unsigned int vfp_sta;
unsigned int vsw_sta;
unsigned int vbp_sta;
unsigned int total_pix_sta_l;
unsigned int total_pix_sta_h;
unsigned int active_pix_sta_l;
unsigned int active_pix_sta_h;
unsigned int hfp_sta_l;
unsigned int hfp_sta_h;
unsigned int hsw_sta_l;
unsigned int hsw_sta_h;
unsigned int hbp_sta_l;
unsigned int hbp_sta_h;
unsigned char res3[0x288];
unsigned int lane_map;
unsigned char res4[0x10];
unsigned int analog_ctl1;
unsigned int analog_ctl2;
unsigned int analog_ctl3;
unsigned int pll_filter_ctl1;
unsigned int amp_tuning_ctl;
unsigned char res5[0xc];
unsigned int aux_hw_retry_ctl;
unsigned char res6[0x2c];
unsigned int int_state;
unsigned int common_int_sta1;
unsigned int common_int_sta2;
unsigned int common_int_sta3;
unsigned int common_int_sta4;
unsigned char res7[0x8];
unsigned int int_sta;
unsigned char res8[0x1c];
unsigned int int_ctl;
unsigned char res9[0x200];
unsigned int sys_ctl1;
unsigned int sys_ctl2;
unsigned int sys_ctl3;
unsigned int sys_ctl4;
unsigned int vid_ctl;
unsigned char res10[0x2c];
unsigned int pkt_send_ctl;
unsigned char res[0x4];
unsigned int hdcp_ctl;
unsigned char res11[0x34];
unsigned int link_bw_set;
unsigned int lane_count_set;
unsigned int training_ptn_set;
unsigned int ln0_link_training_ctl;
unsigned int ln1_link_training_ctl;
unsigned int ln2_link_training_ctl;
unsigned int ln3_link_training_ctl;
unsigned int dn_spread_ctl;
unsigned int hw_link_training_ctl;
unsigned char res12[0x1c];
unsigned int debug_ctl;
unsigned int hpd_deglitch_l;
unsigned int hpd_deglitch_h;
unsigned char res13[0x14];
unsigned int link_debug_ctl;
unsigned char res14[0x1c];
unsigned int m_vid0;
unsigned int m_vid1;
unsigned int m_vid2;
unsigned int n_vid0;
unsigned int n_vid1;
unsigned int n_vid2;
unsigned int m_vid_mon;
unsigned int pll_ctl;
unsigned int phy_pd;
unsigned int phy_test;
unsigned char res15[0x8];
unsigned int video_fifo_thrd;
unsigned char res16[0x8];
unsigned int audio_margin;
unsigned int dn_spread_ctl1;
unsigned int dn_spread_ctl2;
unsigned char res17[0x18];
unsigned int m_cal_ctl;
unsigned int m_vid_gen_filter_th;
unsigned char res18[0x10];
unsigned int m_aud_gen_filter_th;
unsigned char res50[0x4];
unsigned int aux_ch_sta;
unsigned int aux_err_num;
unsigned int aux_ch_defer_ctl;
unsigned int aux_rx_comm;
unsigned int buffer_data_ctl;
unsigned int aux_ch_ctl1;
unsigned int aux_addr_7_0;
unsigned int aux_addr_15_8;
unsigned int aux_addr_19_16;
unsigned int aux_ch_ctl2;
unsigned char res19[0x18];
unsigned int buf_data0;
unsigned char res20[0x3c];
unsigned int soc_general_ctl;
unsigned char res21[0x8c];
unsigned int crc_con;
unsigned int crc_result;
unsigned char res22[0x8];
unsigned int common_int_mask1;
unsigned int common_int_mask2;
unsigned int common_int_mask3;
unsigned int common_int_mask4;
unsigned int int_sta_mask1;
unsigned int int_sta_mask2;
unsigned int int_sta_mask3;
unsigned int int_sta_mask4;
unsigned int int_sta_mask;
unsigned int crc_result2;
unsigned int scrambler_reset_cnt;
unsigned int pn_inv;
unsigned int psr_config;
unsigned int psr_command0;
unsigned int psr_command1;
unsigned int psr_crc_mon0;
unsigned int psr_crc_mon1;
unsigned char res24[0x30];
unsigned int phy_bist_ctrl;
unsigned char res25[0xc];
unsigned int phy_ctrl;
unsigned char res26[0x1c];
unsigned int test_pattern_gen_en;
unsigned int test_pattern_gen_ctrl;
};
#endif /* __ASSEMBLY__ */
/* For DP VIDEO CTL 1 */
#define VIDEO_EN_MASK (0x01 << 7)
#define VIDEO_MUTE_MASK (0x01 << 6)
/* For DP VIDEO CTL 4 */
#define VIDEO_BIST_MASK (0x1 << 3)
/* EXYNOS_DP_ANALOG_CTL_1 */
#define SEL_BG_NEW_BANDGAP (0x0 << 6)
#define SEL_BG_INTERNAL_RESISTOR (0x1 << 6)
#define TX_TERMINAL_CTRL_73_OHM (0x0 << 4)
#define TX_TERMINAL_CTRL_61_OHM (0x1 << 4)
#define TX_TERMINAL_CTRL_50_OHM (0x2 << 4)
#define TX_TERMINAL_CTRL_45_OHM (0x3 << 4)
#define SWING_A_30PER_G_INCREASE (0x1 << 3)
#define SWING_A_30PER_G_NORMAL (0x0 << 3)
/* EXYNOS_DP_ANALOG_CTL_2 */
#define CPREG_BLEED (0x1 << 4)
#define SEL_24M (0x1 << 3)
#define TX_DVDD_BIT_1_0000V (0x3 << 0)
#define TX_DVDD_BIT_1_0625V (0x4 << 0)
#define TX_DVDD_BIT_1_1250V (0x5 << 0)
/* EXYNOS_DP_ANALOG_CTL_3 */
#define DRIVE_DVDD_BIT_1_0000V (0x3 << 5)
#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
#define DRIVE_DVDD_BIT_1_1250V (0x5 << 5)
#define SEL_CURRENT_DEFAULT (0x0 << 3)
#define VCO_BIT_000_MICRO (0x0 << 0)
#define VCO_BIT_200_MICRO (0x1 << 0)
#define VCO_BIT_300_MICRO (0x2 << 0)
#define VCO_BIT_400_MICRO (0x3 << 0)
#define VCO_BIT_500_MICRO (0x4 << 0)
#define VCO_BIT_600_MICRO (0x5 << 0)
#define VCO_BIT_700_MICRO (0x6 << 0)
#define VCO_BIT_900_MICRO (0x7 << 0)
/* EXYNOS_DP_PLL_FILTER_CTL_1 */
#define PD_RING_OSC (0x1 << 6)
#define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4)
#define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4)
#define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4)
#define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4)
#define TX_CUR1_1X (0x0 << 2)
#define TX_CUR1_2X (0x1 << 2)
#define TX_CUR1_3X (0x2 << 2)
#define TX_CUR_1_MA (0x0 << 0)
#define TX_CUR_2_MA (0x1 << 0)
#define TX_CUR_3_MA (0x2 << 0)
#define TX_CUR_4_MA (0x3 << 0)
/* EXYNOS_DP_PLL_FILTER_CTL_2 */
#define CH3_AMP_0_MV (0x3 << 12)
#define CH2_AMP_0_MV (0x3 << 8)
#define CH1_AMP_0_MV (0x3 << 4)
#define CH0_AMP_0_MV (0x3 << 0)
/* EXYNOS_DP_PLL_CTL */
#define DP_PLL_PD (0x1 << 7)
#define DP_PLL_RESET (0x1 << 6)
#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
#define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
#define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
/* EXYNOS_DP_INT_CTL */
#define SOFT_INT_CTRL (0x1 << 2)
#define INT_POL (0x1 << 0)
/* DP TX SW RESET */
#define RESET_DP_TX (0x01 << 0)
/* DP FUNC_EN_1 */
#define MASTER_VID_FUNC_EN_N (0x1 << 7)
#define SLAVE_VID_FUNC_EN_N (0x1 << 5)
#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
#define AUD_FUNC_EN_N (0x1 << 3)
#define HDCP_FUNC_EN_N (0x1 << 2)
#define CRC_FUNC_EN_N (0x1 << 1)
#define SW_FUNC_EN_N (0x1 << 0)
/* DP FUNC_EN_2 */
#define SSC_FUNC_EN_N (0x1 << 7)
#define AUX_FUNC_EN_N (0x1 << 2)
#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
/* EXYNOS_DP_PHY_PD */
#define PHY_PD (0x1 << 5)
#define AUX_PD (0x1 << 4)
#define CH3_PD (0x1 << 3)
#define CH2_PD (0x1 << 2)
#define CH1_PD (0x1 << 1)
#define CH0_PD (0x1 << 0)
/* EXYNOS_DP_COMMON_INT_STA_1 */
#define VSYNC_DET (0x1 << 7)
#define PLL_LOCK_CHG (0x1 << 6)
#define SPDIF_ERR (0x1 << 5)
#define SPDIF_UNSTBL (0x1 << 4)
#define VID_FORMAT_CHG (0x1 << 3)
#define AUD_CLK_CHG (0x1 << 2)
#define VID_CLK_CHG (0x1 << 1)
#define SW_INT (0x1 << 0)
/* EXYNOS_DP_DEBUG_CTL */
#define PLL_LOCK (0x1 << 4)
#define F_PLL_LOCK (0x1 << 3)
#define PLL_LOCK_CTRL (0x1 << 2)
/* EXYNOS_DP_FUNC_EN_2 */
#define SSC_FUNC_EN_N (0x1 << 7)
#define AUX_FUNC_EN_N (0x1 << 2)
#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
/* EXYNOS_DP_COMMON_INT_STA_4 */
#define PSR_ACTIVE (0x1 << 7)
#define PSR_INACTIVE (0x1 << 6)
#define SPDIF_BI_PHASE_ERR (0x1 << 5)
#define HOTPLUG_CHG (0x1 << 2)
#define HPD_LOST (0x1 << 1)
#define PLUG (0x1 << 0)
/* EXYNOS_DP_INT_STA */
#define INT_HPD (0x1 << 6)
#define HW_TRAINING_FINISH (0x1 << 5)
#define RPLY_RECEIV (0x1 << 1)
#define AUX_ERR (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_3 */
#define HPD_STATUS (0x1 << 6)
#define F_HPD (0x1 << 5)
#define HPD_CTRL (0x1 << 4)
#define HDCP_RDY (0x1 << 3)
#define STRM_VALID (0x1 << 2)
#define F_VALID (0x1 << 1)
#define VALID_CTRL (0x1 << 0)
/* EXYNOS_DP_AUX_HW_RETRY_CTL */
#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
/* EXYNOS_DP_AUX_CH_DEFER_CTL */
#define DEFER_CTRL_EN (0x1 << 7)
#define DEFER_COUNT(x) (((x) & 0x7f) << 0)
#define COMMON_INT_MASK_1 (0)
#define COMMON_INT_MASK_2 (0)
#define COMMON_INT_MASK_3 (0)
#define COMMON_INT_MASK_4 (0)
#define INT_STA_MASK (0)
/* EXYNOS_DP_BUFFER_DATA_CTL */
#define BUF_CLR (0x1 << 7)
#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
/* EXYNOS_DP_AUX_ADDR_7_0 */
#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
/* EXYNOS_DP_AUX_ADDR_15_8 */
#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
/* EXYNOS_DP_AUX_ADDR_19_16 */
#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
/* EXYNOS_DP_AUX_CH_CTL_1 */
#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
#define AUX_TX_COMM_MASK (0xf << 0)
#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
#define AUX_TX_COMM_MOT (0x1 << 2)
#define AUX_TX_COMM_WRITE (0x0 << 0)
#define AUX_TX_COMM_READ (0x1 << 0)
/* EXYNOS_DP_AUX_CH_CTL_2 */
#define ADDR_ONLY (0x1 << 1)
#define AUX_EN (0x1 << 0)
/* EXYNOS_DP_AUX_CH_STA */
#define AUX_BUSY (0x1 << 4)
#define AUX_STATUS_MASK (0xf << 0)
/* EXYNOS_DP_AUX_RX_COMM */
#define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
#define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
/* EXYNOS_DP_PHY_TEST */
#define MACRO_RST (0x1 << 5)
#define CH1_TEST (0x1 << 1)
#define CH0_TEST (0x1 << 0)
/* EXYNOS_DP_TRAINING_PTN_SET */
#define SCRAMBLER_TYPE (0x1 << 9)
#define HW_LINK_TRAINING_PATTERN (0x1 << 8)
#define SCRAMBLING_DISABLE (0x1 << 5)
#define SCRAMBLING_ENABLE (0x0 << 5)
#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
/* EXYNOS_DP_TOTAL_LINE_CFG */
#define TOTAL_LINE_CFG_L(x) ((x) & 0xff)
#define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff)
#define ACTIVE_LINE_CFG_L(x) ((x) & 0xff)
#define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff)
#define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff)
#define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
#define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff)
#define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
#define H_F_PORCH_CFG_L(x) ((x) & 0xff)
#define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
#define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff)
#define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
#define H_B_PORCH_CFG_L(x) ((x) & 0xff)
#define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
#define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5)
#define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3)
#define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3)
#define PRE_EMPHASIS_SET_0_MASK (0x3 << 3)
#define PRE_EMPHASIS_SET_0_SHIFT (3)
#define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3)
#define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3)
#define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3)
#define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3)
#define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2)
#define DRIVE_CURRENT_SET_0_MASK (0x3 << 0)
#define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0)
#define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3)
#define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0)
#define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0)
#define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0)
#define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0)
/* EXYNOS_DP_LN1_LINK_TRAINING_CTL */
#define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5)
#define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3)
#define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3)
#define PRE_EMPHASIS_SET_1_MASK (0x3 << 3)
#define PRE_EMPHASIS_SET_1_SHIFT (3)
#define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3)
#define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3)
#define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3)
#define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3)
#define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2)
#define DRIVE_CURRENT_SET_1_MASK (0x3 << 0)
#define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0)
#define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3)
#define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0)
#define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0)
#define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0)
#define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0)
/* EXYNOS_DP_LN2_LINK_TRAINING_CTL */
#define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5)
#define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3)
#define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3)
#define PRE_EMPHASIS_SET_2_MASK (0x3 << 3)
#define PRE_EMPHASIS_SET_2_SHIFT (3)
#define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3)
#define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3)
#define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3)
#define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3)
#define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2)
#define DRIVE_CURRENT_SET_2_MASK (0x3 << 0)
#define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0)
#define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3)
#define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0)
#define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0)
#define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0)
#define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0)
/* EXYNOS_DP_LN3_LINK_TRAINING_CTL */
#define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5)
#define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3)
#define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3)
#define PRE_EMPHASIS_SET_3_MASK (0x3 << 3)
#define PRE_EMPHASIS_SET_3_SHIFT (3)
#define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3)
#define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3)
#define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3)
#define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3)
#define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2)
#define DRIVE_CURRENT_SET_3_MASK (0x3 << 0)
#define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0)
#define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3)
#define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0)
#define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0)
#define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0)
#define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0)
/* EXYNOS_DP_VIDEO_CTL_10 */
#define FORMAT_SEL (0x1 << 4)
#define INTERACE_SCAN_CFG (0x1 << 2)
#define INTERACE_SCAN_CFG_SHIFT (2)
#define VSYNC_POLARITY_CFG (0x1 << 1)
#define V_S_POLARITY_CFG_SHIFT (1)
#define HSYNC_POLARITY_CFG (0x1 << 0)
#define H_S_POLARITY_CFG_SHIFT (0)
/* EXYNOS_DP_SOC_GENERAL_CTL */
#define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
#define AUDIO_MODE_MASTER_MODE (0x0 << 8)
#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
#define VIDEO_MASTER_CLK_SEL (0x1 << 2)
#define VIDEO_MASTER_MODE_EN (0x1 << 1)
#define VIDEO_MODE_MASK (0x1 << 0)
#define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
#define VIDEO_MODE_MASTER_MODE (0x0 << 0)
/* EXYNOS_DP_VIDEO_CTL_1 */
#define VIDEO_EN (0x1 << 7)
#define HDCP_VIDEO_MUTE (0x1 << 6)
/* EXYNOS_DP_VIDEO_CTL_2 */
#define IN_D_RANGE_MASK (0x1 << 7)
#define IN_D_RANGE_SHIFT (7)
#define IN_D_RANGE_CEA (0x1 << 7)
#define IN_D_RANGE_VESA (0x0 << 7)
#define IN_BPC_MASK (0x7 << 4)
#define IN_BPC_SHIFT (4)
#define IN_BPC_12_BITS (0x3 << 4)
#define IN_BPC_10_BITS (0x2 << 4)
#define IN_BPC_8_BITS (0x1 << 4)
#define IN_BPC_6_BITS (0x0 << 4)
#define IN_COLOR_F_MASK (0x3 << 0)
#define IN_COLOR_F_SHIFT (0)
#define IN_COLOR_F_YCBCR444 (0x2 << 0)
#define IN_COLOR_F_YCBCR422 (0x1 << 0)
#define IN_COLOR_F_RGB (0x0 << 0)
/* EXYNOS_DP_VIDEO_CTL_3 */
#define IN_YC_COEFFI_MASK (0x1 << 7)
#define IN_YC_COEFFI_SHIFT (7)
#define IN_YC_COEFFI_ITU709 (0x1 << 7)
#define IN_YC_COEFFI_ITU601 (0x0 << 7)
#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
#define VID_CHK_UPDATE_TYPE_SHIFT (4)
#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
/* EXYNOS_DP_TEST_PATTERN_GEN_EN */
#define TEST_PATTERN_GEN_EN (0x1 << 0)
#define TEST_PATTERN_GEN_DIS (0x0 << 0)
/* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */
#define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0)
#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0)
#define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0)
/* EXYNOS_DP_VIDEO_CTL_4 */
#define BIST_EN (0x1 << 3)
#define BIST_WIDTH_MASK (0x1 << 2)
#define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2)
#define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2)
#define BIST_TYPE_MASK (0x3 << 0)
#define BIST_TYPE_COLOR_BAR (0x0 << 0)
#define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0)
#define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0)
/* EXYNOS_DP_SYS_CTL_1 */
#define DET_STA (0x1 << 2)
#define FORCE_DET (0x1 << 1)
#define DET_CTRL (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_2 */
#define CHA_CRI(x) (((x) & 0xf) << 4)
#define CHA_STA (0x1 << 2)
#define FORCE_CHA (0x1 << 1)
#define CHA_CTRL (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_3 */
#define HPD_STATUS (0x1 << 6)
#define F_HPD (0x1 << 5)
#define HPD_CTRL (0x1 << 4)
#define HDCP_RDY (0x1 << 3)
#define STRM_VALID (0x1 << 2)
#define F_VALID (0x1 << 1)
#define VALID_CTRL (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_4 */
#define FIX_M_AUD (0x1 << 4)
#define ENHANCED (0x1 << 3)
#define FIX_M_VID (0x1 << 2)
#define M_VID_UPDATE_CTRL (0x3 << 0)
/* EXYNOS_M_VID_X */
#define M_VID0_CFG(x) ((x) & 0xff)
#define M_VID1_CFG(x) (((x) >> 8) & 0xff)
#define M_VID2_CFG(x) (((x) >> 16) & 0xff)
/* EXYNOS_M_VID_X */
#define N_VID0_CFG(x) ((x) & 0xff)
#define N_VID1_CFG(x) (((x) >> 8) & 0xff)
#define N_VID2_CFG(x) (((x) >> 16) & 0xff)
/* DPCD_TRAINING_PATTERN_SET */
#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
/* Definition for DPCD Register */
#define DPCD_DPCD_REV (0x0000)
#define DPCD_MAX_LINK_RATE (0x0001)
#define DPCD_MAX_LANE_COUNT (0x0002)
#define DPCD_LINK_BW_SET (0x0100)
#define DPCD_LANE_COUNT_SET (0x0101)
#define DPCD_TRAINING_PATTERN_SET (0x0102)
#define DPCD_TRAINING_LANE0_SET (0x0103)
#define DPCD_LANE0_1_STATUS (0x0202)
#define DPCD_LN_ALIGN_UPDATED (0x0204)
#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206)
#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207)
#define DPCD_TEST_REQUEST (0x0218)
#define DPCD_TEST_RESPONSE (0x0260)
#define DPCD_TEST_EDID_CHECKSUM (0x0261)
#define DPCD_SINK_POWER_STATE (0x0600)
/* DPCD_TEST_REQUEST */
#define DPCD_TEST_EDID_READ (0x1 << 2)
/* DPCD_TEST_RESPONSE */
#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
/* DPCD_SINK_POWER_STATE */
#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
/* I2C EDID Chip ID, Slave Address */
#define I2C_EDID_DEVICE_ADDR (0x50)
#define I2C_E_EDID_DEVICE_ADDR (0x30)
#define EDID_BLOCK_LENGTH (0x80)
#define EDID_HEADER_PATTERN (0x00)
#define EDID_EXTENSION_FLAG (0x7e)
#define EDID_CHECKSUM (0x7f)
/* DPCD_LANE0_1_STATUS */
#define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6)
#define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5)
#define DPCD_LANE1_CR_DONE (0x1 << 4)
#define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2)
#define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1)
#define DPCD_LANE0_CR_DONE (0x1 << 0)
/* DPCD_ADJUST_REQUEST_LANE0_1 */
#define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6)
#define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3)
#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6)
#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6)
#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6)
#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6)
#define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4)
#define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3)
#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4)
#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4)
#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4)
#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4)
#define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2)
#define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3)
#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2)
#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2)
#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2)
#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2)
#define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0)
#define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3)
#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0)
#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0)
#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0)
#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0)
/* DPCD_ADJUST_REQUEST_LANE2_3 */
#define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6)
#define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3)
#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6)
#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6)
#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6)
#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6)
#define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4)
#define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3)
#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4)
#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4)
#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4)
#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4)
#define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2)
#define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3)
#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2)
#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2)
#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2)
#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2)
#define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0)
#define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3)
#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0)
#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0)
#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0)
#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0)
/* DPCD_LANE_COUNT_SET */
#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
#define DPCD_LN_COUNT_SET(x) ((x) & 0x1f)
/* DPCD_LANE_ALIGN__STATUS_UPDATED */
#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
/* DPCD_TRAINING_LANE0_SET */
#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3)
#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3)
#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3)
#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3)
#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0)
#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0)
#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0)
#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0)
#define DPCD_REQ_ADJ_SWING (0x00)
#define DPCD_REQ_ADJ_EMPHASIS (0x01)
#define DP_LANE_STAT_CR_DONE (0x01 << 0)
#define DP_LANE_STAT_CE_DONE (0x01 << 1)
#define DP_LANE_STAT_SYM_LOCK (0x01 << 2)
#endif

201
u-boot/arch/arm/mach-exynos/include/mach/dp_info.h Normal file
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@@ -0,0 +1,201 @@
/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DP_INFO_H
#define _DP_INFO_H
#define msleep(a) udelay(a * 1000)
#define DP_TIMEOUT_LOOP_COUNT 100
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 4
#define EXYNOS_DP_SUCCESS 0
enum {
DP_DISABLE,
DP_ENABLE,
};
struct edp_disp_info {
char *name;
unsigned int h_total;
unsigned int h_res;
unsigned int h_sync_width;
unsigned int h_back_porch;
unsigned int h_front_porch;
unsigned int v_total;
unsigned int v_res;
unsigned int v_sync_width;
unsigned int v_back_porch;
unsigned int v_front_porch;
unsigned int v_sync_rate;
};
struct edp_link_train_info {
unsigned int lt_status;
unsigned int ep_loop;
unsigned int cr_loop[4];
};
struct edp_video_info {
unsigned int master_mode;
unsigned int bist_mode;
unsigned int bist_pattern;
unsigned int h_sync_polarity;
unsigned int v_sync_polarity;
unsigned int interlaced;
unsigned int color_space;
unsigned int dynamic_range;
unsigned int ycbcr_coeff;
unsigned int color_depth;
};
struct exynos_dp_priv {
struct edp_disp_info disp_info;
struct edp_link_train_info lt_info;
struct edp_video_info video_info;
/*below info get from panel during training*/
unsigned char lane_bw;
unsigned char lane_cnt;
unsigned char dpcd_rev;
/*support enhanced frame cap */
unsigned char dpcd_efc;
struct exynos_dp *regs;
};
enum analog_power_block {
AUX_BLOCK,
CH0_BLOCK,
CH1_BLOCK,
CH2_BLOCK,
CH3_BLOCK,
ANALOG_TOTAL,
POWER_ALL
};
enum pll_status {
PLL_UNLOCKED = 0,
PLL_LOCKED
};
enum {
COLOR_RGB,
COLOR_YCBCR422,
COLOR_YCBCR444
};
enum {
VESA,
CEA
};
enum {
COLOR_YCBCR601,
COLOR_YCBCR709
};
enum {
COLOR_6,
COLOR_8,
COLOR_10,
COLOR_12
};
enum {
DP_LANE_BW_1_62 = 0x06,
DP_LANE_BW_2_70 = 0x0a,
};
enum {
DP_LANE_CNT_1 = 1,
DP_LANE_CNT_2 = 2,
DP_LANE_CNT_4 = 4,
};
enum {
DP_DPCD_REV_10 = 0x10,
DP_DPCD_REV_11 = 0x11,
};
enum {
DP_LT_NONE,
DP_LT_START,
DP_LT_CR,
DP_LT_ET,
DP_LT_FINISHED,
DP_LT_FAIL,
};
enum {
PRE_EMPHASIS_LEVEL_0,
PRE_EMPHASIS_LEVEL_1,
PRE_EMPHASIS_LEVEL_2,
PRE_EMPHASIS_LEVEL_3,
};
enum {
PRBS7,
D10_2,
TRAINING_PTN1,
TRAINING_PTN2,
DP_NONE
};
enum {
VOLTAGE_LEVEL_0,
VOLTAGE_LEVEL_1,
VOLTAGE_LEVEL_2,
VOLTAGE_LEVEL_3,
};
enum pattern_type {
NO_PATTERN,
COLOR_RAMP,
BALCK_WHITE_V_LINES,
COLOR_SQUARE,
INVALID_PATTERN,
COLORBAR_32,
COLORBAR_64,
WHITE_GRAY_BALCKBAR_32,
WHITE_GRAY_BALCKBAR_64,
MOBILE_WHITEBAR_32,
MOBILE_WHITEBAR_64
};
enum {
CALCULATED_M,
REGISTER_M
};
enum {
VIDEO_TIMING_FROM_CAPTURE,
VIDEO_TIMING_FROM_REGISTER
};
struct exynos_dp_platform_data {
struct exynos_dp_priv *edp_dev_info;
};
#ifdef CONFIG_EXYNOS_DP
unsigned int exynos_init_dp(void);
#else
unsigned int exynos_init_dp(void)
{
return 0;
}
#endif
#endif /* _DP_INFO_H */

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u-boot/arch/arm/mach-exynos/include/mach/dsim.h Normal file
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/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: InKi Dae <inki.dae@samsung.com>
* Author: Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_ARCH_DSIM_H_
#define __ASM_ARM_ARCH_DSIM_H_
#ifndef __ASSEMBLY__
struct exynos_mipi_dsim {
unsigned int status;
unsigned int swrst;
unsigned int clkctrl;
unsigned int timeout;
unsigned int config;
unsigned int escmode;
unsigned int mdresol;
unsigned int mvporch;
unsigned int mhporch;
unsigned int msync;
unsigned int sdresol;
unsigned int intsrc;
unsigned int intmsk;
unsigned int pkthdr;
unsigned int payload;
unsigned int rxfifo;
unsigned int fifothld;
unsigned int fifoctrl;
unsigned int memacchr;
unsigned int pllctrl;
unsigned int plltmr;
unsigned int phyacchr;
unsigned int phyacchr1;
};
#endif /* __ASSEMBLY__ */
/*
* Bit Definitions
*/
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
#define DSIM_STOP_STATE_CLK (1 << 8)
#define DSIM_TX_READY_HS_CLK (1 << 10)
#define DSIM_PLL_STABLE (1 << 31)
/* DSIM_SWRST */
#define DSIM_FUNCRST (1 << 16)
#define DSIM_SWRST (1 << 0)
/* EXYNOS_DSIM_TIMEOUT */
#define DSIM_LPDR_TOUT_SHIFT (0)
#define DSIM_BTA_TOUT_SHIFT (16)
/* EXYNOS_DSIM_CLKCTRL */
#define DSIM_LANE_ESC_CLKEN_SHIFT (19)
#define DSIM_BYTE_CLKEN_SHIFT (24)
#define DSIM_BYTE_CLK_SRC_SHIFT (25)
#define DSIM_PLL_BYPASS_SHIFT (27)
#define DSIM_ESC_CLKEN_SHIFT (28)
#define DSIM_TX_REQUEST_HSCLK_SHIFT (31)
#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << \
DSIM_LANE_ESC_CLKEN_SHIFT)
#define DSIM_BYTE_CLK_ENABLE (1 << DSIM_BYTE_CLKEN_SHIFT)
#define DSIM_BYTE_CLK_DISABLE (0 << DSIM_BYTE_CLKEN_SHIFT)
#define DSIM_PLL_BYPASS_EXTERNAL (1 << DSIM_PLL_BYPASS_SHIFT)
#define DSIM_ESC_CLKEN_ENABLE (1 << DSIM_ESC_CLKEN_SHIFT)
#define DSIM_ESC_CLKEN_DISABLE (0 << DSIM_ESC_CLKEN_SHIFT)
/* EXYNOS_DSIM_CONFIG */
#define DSIM_NUM_OF_DATALANE_SHIFT (5)
#define DSIM_SUBPIX_SHIFT (8)
#define DSIM_MAINPIX_SHIFT (12)
#define DSIM_SUBVC_SHIFT (16)
#define DSIM_MAINVC_SHIFT (18)
#define DSIM_HSA_MODE_SHIFT (20)
#define DSIM_HBP_MODE_SHIFT (21)
#define DSIM_HFP_MODE_SHIFT (22)
#define DSIM_HSE_MODE_SHIFT (23)
#define DSIM_AUTO_MODE_SHIFT (24)
#define DSIM_VIDEO_MODE_SHIFT (25)
#define DSIM_BURST_MODE_SHIFT (26)
#define DSIM_EOT_PACKET_SHIFT (28)
#define DSIM_AUTO_FLUSH_SHIFT (29)
#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0)
#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT)
/* EXYNOS_DSIM_ESCMODE */
#define DSIM_TX_LPDT_SHIFT (6)
#define DSIM_CMD_LPDT_SHIFT (7)
#define DSIM_TX_LPDT_LP (1 << DSIM_TX_LPDT_SHIFT)
#define DSIM_CMD_LPDT_LP (1 << DSIM_CMD_LPDT_SHIFT)
#define DSIM_STOP_STATE_CNT_SHIFT (21)
#define DSIM_FORCE_STOP_STATE_SHIFT (20)
/* EXYNOS_DSIM_MDRESOL */
#define DSIM_MAIN_STAND_BY (1 << 31)
#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
/* EXYNOS_DSIM_MVPORCH */
#define DSIM_CMD_ALLOW_SHIFT (28)
#define DSIM_STABLE_VFP_SHIFT (16)
#define DSIM_MAIN_VBP_SHIFT (0)
#define DSIM_CMD_ALLOW_MASK (0xf << DSIM_CMD_ALLOW_SHIFT)
#define DSIM_STABLE_VFP_MASK (0x7ff << DSIM_STABLE_VFP_SHIFT)
#define DSIM_MAIN_VBP_MASK (0x7ff << DSIM_MAIN_VBP_SHIFT)
/* EXYNOS_DSIM_MHPORCH */
#define DSIM_MAIN_HFP_SHIFT (16)
#define DSIM_MAIN_HBP_SHIFT (0)
#define DSIM_MAIN_HFP_MASK ((0xffff) << DSIM_MAIN_HFP_SHIFT)
#define DSIM_MAIN_HBP_MASK ((0xffff) << DSIM_MAIN_HBP_SHIFT)
/* EXYNOS_DSIM_MSYNC */
#define DSIM_MAIN_VSA_SHIFT (22)
#define DSIM_MAIN_HSA_SHIFT (0)
#define DSIM_MAIN_VSA_MASK ((0x3ff) << DSIM_MAIN_VSA_SHIFT)
#define DSIM_MAIN_HSA_MASK ((0xffff) << DSIM_MAIN_HSA_SHIFT)
/* EXYNOS_DSIM_SDRESOL */
#define DSIM_SUB_STANDY_SHIFT (31)
#define DSIM_SUB_VRESOL_SHIFT (16)
#define DSIM_SUB_HRESOL_SHIFT (0)
#define DSIM_SUB_STANDY_MASK ((0x1) << DSIM_SUB_STANDY_SHIFT)
#define DSIM_SUB_VRESOL_MASK ((0x7ff) << DSIM_SUB_VRESOL_SHIFT)
#define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT)
/* EXYNOS_DSIM_INTSRC */
#define INTSRC_FRAME_DONE (1 << 24)
#define INTSRC_PLL_STABLE (1 << 31)
#define INTSRC_SWRST_RELEASE (1 << 30)
/* EXYNOS_DSIM_INTMSK */
#define INTMSK_FRAME_DONE (1 << 24)
/* EXYNOS_DSIM_FIFOCTRL */
#define SFR_HEADER_EMPTY (1 << 22)
/* EXYNOS_DSIM_PKTHDR */
#define DSIM_PKTHDR_DI(x) (((x) & 0x3f) << 0)
#define DSIM_PKTHDR_DAT0(x) ((x) << 8)
#define DSIM_PKTHDR_DAT1(x) ((x) << 16)
/* EXYNOS_DSIM_PHYACCHR */
#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
#define DSIM_AFC_CTL_SHIFT (5)
#define DSIM_AFC_EN (1 << 14)
/* EXYNOS_DSIM_PHYACCHR1 */
#define DSIM_DPDN_SWAP_DATA_SHIFT (0)
/* EXYNOS_DSIM_PLLCTRL */
#define DSIM_SCALER_SHIFT (1)
#define DSIM_MAIN_SHIFT (4)
#define DSIM_PREDIV_SHIFT (13)
#define DSIM_PRECTRL_SHIFT (20)
#define DSIM_PLL_EN_SHIFT (23)
#define DSIM_FREQ_BAND_SHIFT (24)
#define DSIM_ZEROCTRL_SHIFT (28)
#endif

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u-boot/arch/arm/mach-exynos/include/mach/dwmmc.h Normal file
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/*
* (C) Copyright 2012 SAMSUNG Electronics
* Jaehoon Chung <jh80.chung@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define DWMCI_CLKSEL 0x09C
#define DWMCI_SET_SAMPLE_CLK(x) (x)
#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
#define EMMCP_MPSBEGIN0 0x1200
#define EMMCP_SEND0 0x1204
#define EMMCP_CTRL0 0x120C
#define MPSCTRL_SECURE_READ_BIT (0x1<<7)
#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6)
#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5)
#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4)
#define MPSCTRL_USE_FUSE_KEY (0x1<<3)
#define MPSCTRL_ECB_MODE (0x1<<2)
#define MPSCTRL_ENCRYPTION (0x1<<1)
#define MPSCTRL_VALID (0x1<<0)
/* CLKSEL Register */
#define DWMCI_DIVRATIO_BIT 24
#define DWMCI_DIVRATIO_MASK 0x7
int exynos_dwmmc_init(const void *blob);
int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);

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u-boot/arch/arm/mach-exynos/include/mach/ehci.h Normal file
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/*
* SAMSUNG EXYNOS USB HOST EHCI Controller
*
* Copyright (C) 2012 Samsung Electronics Co.Ltd
* Vivek Gautam <gautam.vivek@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_ARCH_EHCI_H__
#define __ASM_ARM_ARCH_EHCI_H__
#define CLK_24MHZ 5
#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6)
#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
#define RSTCON_HOSTPHY_SWRST (0xf << 3)
#define RSTCON_SWRST (0x1 << 0)
#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
#define HOST_CTRL0_COMMONON_N (1 << 9)
#define HOST_CTRL0_SIDDQ (1 << 6)
#define HOST_CTRL0_FORCESLEEP (1 << 5)
#define HOST_CTRL0_FORCESUSPEND (1 << 4)
#define HOST_CTRL0_WORDINTERFACE (1 << 3)
#define HOST_CTRL0_UTMISWRST (1 << 2)
#define HOST_CTRL0_LINKSWRST (1 << 1)
#define HOST_CTRL0_PHYSWRST (1 << 0)
#define HOST_CTRL0_FSEL_MASK (7 << 16)
#define EHCICTRL_ENAINCRXALIGN (1 << 29)
#define EHCICTRL_ENAINCR4 (1 << 28)
#define EHCICTRL_ENAINCR8 (1 << 27)
#define EHCICTRL_ENAINCR16 (1 << 26)
#define HSIC_CTRL_REFCLKSEL (0x2)
#define HSIC_CTRL_REFCLKSEL_MASK (0x3)
#define HSIC_CTRL_REFCLKSEL_SHIFT (23)
#define HSIC_CTRL_REFCLKDIV_12 (0x24)
#define HSIC_CTRL_REFCLKDIV_MASK (0x7f)
#define HSIC_CTRL_REFCLKDIV_SHIFT (16)
#define HSIC_CTRL_SIDDQ (0x1 << 6)
#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
#define HSIC_CTRL_UTMISWRST (0x1 << 2)
#define HSIC_CTRL_PHYSWRST (0x1 << 0)
/* Register map for PHY control */
struct exynos_usb_phy {
unsigned int usbphyctrl0;
unsigned int usbphytune0;
unsigned int reserved1[2];
unsigned int hsicphyctrl1;
unsigned int hsicphytune1;
unsigned int reserved2[2];
unsigned int hsicphyctrl2;
unsigned int hsicphytune2;
unsigned int reserved3[2];
unsigned int ehcictrl;
unsigned int ohcictrl;
unsigned int usbotgsys;
unsigned int reserved4;
unsigned int usbotgtune;
};
struct exynos4412_usb_phy {
unsigned int usbphyctrl;
unsigned int usbphyclk;
unsigned int usbphyrstcon;
};
/* Switch on the VBUS power. */
int board_usb_vbus_init(void);
#endif /* __ASM_ARM_ARCH_EHCI_H__ */

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u-boot/arch/arm/mach-exynos/include/mach/fb.h Normal file
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/*
* (C) Copyright 2012 Samsung Electronics
* Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_ARCH_FB_H_
#define __ASM_ARM_ARCH_FB_H_
#ifndef __ASSEMBLY__
struct exynos_fb {
unsigned int vidcon0;
unsigned int vidcon1;
unsigned int vidcon2;
unsigned int vidcon3;
unsigned int vidtcon0;
unsigned int vidtcon1;
unsigned int vidtcon2;
unsigned int vidtcon3;
unsigned int wincon0;
unsigned int wincon1;
unsigned int wincon2;
unsigned int wincon3;
unsigned int wincon4;
unsigned int winshmap;
unsigned int res1;
unsigned int winchmap2;
unsigned int vidosd0a;
unsigned int vidosd0b;
unsigned int vidosd0c;
unsigned int res2;
unsigned int vidosd1a;
unsigned int vidosd1b;
unsigned int vidosd1c;
unsigned int vidosd1d;
unsigned int vidosd2a;
unsigned int vidosd2b;
unsigned int vidosd2c;
unsigned int vidosd2d;
unsigned int vidosd3a;
unsigned int vidosd3b;
unsigned int vidosd3c;
unsigned int res3;
unsigned int vidosd4a;
unsigned int vidosd4b;
unsigned int vidosd4c;
unsigned int res4[5];
unsigned int vidw00add0b0;
unsigned int vidw00add0b1;
unsigned int vidw01add0b0;
unsigned int vidw01add0b1;
unsigned int vidw02add0b0;
unsigned int vidw02add0b1;
unsigned int vidw03add0b0;
unsigned int vidw03add0b1;
unsigned int vidw04add0b0;
unsigned int vidw04add0b1;
unsigned int res5[2];
unsigned int vidw00add1b0;
unsigned int vidw00add1b1;
unsigned int vidw01add1b0;
unsigned int vidw01add1b1;
unsigned int vidw02add1b0;
unsigned int vidw02add1b1;
unsigned int vidw03add1b0;
unsigned int vidw03add1b1;
unsigned int vidw04add1b0;
unsigned int vidw04add1b1;
unsigned int res7[2];
unsigned int vidw00add2;
unsigned int vidw01add2;
unsigned int vidw02add2;
unsigned int vidw03add2;
unsigned int vidw04add2;
unsigned int res8[7];
unsigned int vidintcon0;
unsigned int vidintcon1;
unsigned int res9[1];
unsigned int w1keycon0;
unsigned int w1keycon1;
unsigned int w2keycon0;
unsigned int w2keycon1;
unsigned int w3keycon0;
unsigned int w3keycon1;
unsigned int w4keycon0;
unsigned int w4keycon1;
unsigned int w1keyalpha;
unsigned int w2keyalpha;
unsigned int w3keyalpha;
unsigned int w4keyalpha;
unsigned int dithmode;
unsigned int res10[2];
unsigned int win0map;
unsigned int win1map;
unsigned int win2map;
unsigned int win3map;
unsigned int win4map;
unsigned int res11[1];
unsigned int wpalcon_h;
unsigned int wpalcon_l;
unsigned int trigcon;
unsigned int res12[2];
unsigned int i80ifcona0;
unsigned int i80ifcona1;
unsigned int i80ifconb0;
unsigned int i80ifconb1;
unsigned int colorgaincon;
unsigned int res13[2];
unsigned int ldi_cmdcon0;
unsigned int ldi_cmdcon1;
unsigned int res14[1];
/* To be updated */
unsigned char res15[156];
unsigned int dualrgb;
unsigned char res16[16];
unsigned int dp_mie_clkcon;
};
#endif
/* LCD IF register offset */
#define EXYNOS4_LCD_IF_BASE_OFFSET 0x0
#define EXYNOS5_LCD_IF_BASE_OFFSET 0x20000
static inline unsigned int exynos_fimd_get_base_offset(void)
{
if (cpu_is_exynos5())
return EXYNOS5_LCD_IF_BASE_OFFSET;
else
return EXYNOS4_LCD_IF_BASE_OFFSET;
}
/*
* Register offsets
*/
#define EXYNOS_WINCON(x) (x * 0x04)
#define EXYNOS_VIDOSD(x) (x * 0x10)
#define EXYNOS_BUFFER_OFFSET(x) (x * 0x08)
#define EXYNOS_BUFFER_SIZE(x) (x * 0x04)
/*
* Bit Definitions
*/
/* VIDCON0 */
#define EXYNOS_VIDCON0_DSI_DISABLE (0 << 30)
#define EXYNOS_VIDCON0_DSI_ENABLE (1 << 30)
#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE (0 << 29)
#define EXYNOS_VIDCON0_SCAN_INTERLACE (1 << 29)
#define EXYNOS_VIDCON0_SCAN_MASK (1 << 29)
#define EXYNOS_VIDCON0_VIDOUT_RGB (0 << 26)
#define EXYNOS_VIDCON0_VIDOUT_ITU (1 << 26)
#define EXYNOS_VIDCON0_VIDOUT_I80LDI0 (2 << 26)
#define EXYNOS_VIDCON0_VIDOUT_I80LDI1 (3 << 26)
#define EXYNOS_VIDCON0_VIDOUT_WB_RGB (4 << 26)
#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0 (6 << 26)
#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26)
#define EXYNOS_VIDCON0_VIDOUT_MASK (7 << 26)
#define EXYNOS_VIDCON0_PNRMODE_RGB_P (0 << 17)
#define EXYNOS_VIDCON0_PNRMODE_BGR_P (1 << 17)
#define EXYNOS_VIDCON0_PNRMODE_RGB_S (2 << 17)
#define EXYNOS_VIDCON0_PNRMODE_BGR_S (3 << 17)
#define EXYNOS_VIDCON0_PNRMODE_MASK (3 << 17)
#define EXYNOS_VIDCON0_PNRMODE_SHIFT (17)
#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS (0 << 16)
#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME (1 << 16)
#define EXYNOS_VIDCON0_CLKVALUP_MASK (1 << 16)
#define EXYNOS_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6)
#define EXYNOS_VIDCON0_VCLKEN_NORMAL (0 << 5)
#define EXYNOS_VIDCON0_VCLKEN_FREERUN (1 << 5)
#define EXYNOS_VIDCON0_VCLKEN_MASK (1 << 5)
#define EXYNOS_VIDCON0_CLKDIR_DIRECTED (0 << 4)
#define EXYNOS_VIDCON0_CLKDIR_DIVIDED (1 << 4)
#define EXYNOS_VIDCON0_CLKDIR_MASK (1 << 4)
#define EXYNOS_VIDCON0_CLKSEL_HCLK (0 << 2)
#define EXYNOS_VIDCON0_CLKSEL_SCLK (1 << 2)
#define EXYNOS_VIDCON0_CLKSEL_MASK (1 << 2)
#define EXYNOS_VIDCON0_ENVID_ENABLE (1 << 1)
#define EXYNOS_VIDCON0_ENVID_DISABLE (0 << 1)
#define EXYNOS_VIDCON0_ENVID_F_ENABLE (1 << 0)
#define EXYNOS_VIDCON0_ENVID_F_DISABLE (0 << 0)
/* VIDCON1 */
#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE (0 << 7)
#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE (1 << 7)
#define EXYNOS_VIDCON1_IHSYNC_NORMAL (0 << 6)
#define EXYNOS_VIDCON1_IHSYNC_INVERT (1 << 6)
#define EXYNOS_VIDCON1_IVSYNC_NORMAL (0 << 5)
#define EXYNOS_VIDCON1_IVSYNC_INVERT (1 << 5)
#define EXYNOS_VIDCON1_IVDEN_NORMAL (0 << 4)
#define EXYNOS_VIDCON1_IVDEN_INVERT (1 << 4)
/* VIDCON2 */
#define EXYNOS_VIDCON2_EN601_DISABLE (0 << 23)
#define EXYNOS_VIDCON2_EN601_ENABLE (1 << 23)
#define EXYNOS_VIDCON2_EN601_MASK (1 << 23)
#define EXYNOS_VIDCON2_WB_DISABLE (0 << 15)
#define EXYNOS_VIDCON2_WB_ENABLE (1 << 15)
#define EXYNOS_VIDCON2_WB_MASK (1 << 15)
#define EXYNOS_VIDCON2_TVFORMATSEL_HW (0 << 14)
#define EXYNOS_VIDCON2_TVFORMATSEL_SW (1 << 14)
#define EXYNOS_VIDCON2_TVFORMATSEL_MASK (1 << 14)
#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422 (1 << 12)
#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444 (2 << 12)
#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12)
#define EXYNOS_VIDCON2_ORGYUV_YCBCR (0 << 8)
#define EXYNOS_VIDCON2_ORGYUV_CBCRY (1 << 8)
#define EXYNOS_VIDCON2_ORGYUV_MASK (1 << 8)
#define EXYNOS_VIDCON2_YUVORD_CBCR (0 << 7)
#define EXYNOS_VIDCON2_YUVORD_CRCB (1 << 7)
#define EXYNOS_VIDCON2_YUVORD_MASK (1 << 7)
/* PRTCON */
#define EXYNOS_PRTCON_UPDATABLE (0 << 11)
#define EXYNOS_PRTCON_PROTECT (1 << 11)
/* VIDTCON0 */
#define EXYNOS_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24)
#define EXYNOS_VIDTCON0_VBPD(x) (((x) & 0xff) << 16)
#define EXYNOS_VIDTCON0_VFPD(x) (((x) & 0xff) << 8)
#define EXYNOS_VIDTCON0_VSPW(x) (((x) & 0xff) << 0)
/* VIDTCON1 */
#define EXYNOS_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24)
#define EXYNOS_VIDTCON1_HBPD(x) (((x) & 0xff) << 16)
#define EXYNOS_VIDTCON1_HFPD(x) (((x) & 0xff) << 8)
#define EXYNOS_VIDTCON1_HSPW(x) (((x) & 0xff) << 0)
/* VIDTCON2 */
#define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11)
#define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0)
#define EXYNOS_VIDTCON2_LINEVAL_E(x) ((((x) & 0x800) >> 11) << 23)
#define EXYNOS_VIDTCON2_HOZVAL_E(x) ((((x) & 0x800) >> 11) << 22)
/* Window 0~4 Control - WINCONx */
#define EXYNOS_WINCON_DATAPATH_DMA (0 << 22)
#define EXYNOS_WINCON_DATAPATH_LOCAL (1 << 22)
#define EXYNOS_WINCON_DATAPATH_MASK (1 << 22)
#define EXYNOS_WINCON_BUFSEL_0 (0 << 20)
#define EXYNOS_WINCON_BUFSEL_1 (1 << 20)
#define EXYNOS_WINCON_BUFSEL_MASK (1 << 20)
#define EXYNOS_WINCON_BUFSEL_SHIFT (20)
#define EXYNOS_WINCON_BUFAUTO_DISABLE (0 << 19)
#define EXYNOS_WINCON_BUFAUTO_ENABLE (1 << 19)
#define EXYNOS_WINCON_BUFAUTO_MASK (1 << 19)
#define EXYNOS_WINCON_BITSWP_DISABLE (0 << 18)
#define EXYNOS_WINCON_BITSWP_ENABLE (1 << 18)
#define EXYNOS_WINCON_BITSWP_SHIFT (18)
#define EXYNOS_WINCON_BYTESWP_DISABLE (0 << 17)
#define EXYNOS_WINCON_BYTESWP_ENABLE (1 << 17)
#define EXYNOS_WINCON_BYTESWP_SHIFT (17)
#define EXYNOS_WINCON_HAWSWP_DISABLE (0 << 16)
#define EXYNOS_WINCON_HAWSWP_ENABLE (1 << 16)
#define EXYNOS_WINCON_HAWSWP_SHIFT (16)
#define EXYNOS_WINCON_WSWP_DISABLE (0 << 15)
#define EXYNOS_WINCON_WSWP_ENABLE (1 << 15)
#define EXYNOS_WINCON_WSWP_SHIFT (15)
#define EXYNOS_WINCON_INRGB_RGB (0 << 13)
#define EXYNOS_WINCON_INRGB_YUV (1 << 13)
#define EXYNOS_WINCON_INRGB_MASK (1 << 13)
#define EXYNOS_WINCON_BURSTLEN_16WORD (0 << 9)
#define EXYNOS_WINCON_BURSTLEN_8WORD (1 << 9)
#define EXYNOS_WINCON_BURSTLEN_4WORD (2 << 9)
#define EXYNOS_WINCON_BURSTLEN_MASK (3 << 9)
#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE (0 << 7)
#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE (1 << 7)
#define EXYNOS_WINCON_BLD_PLANE (0 << 6)
#define EXYNOS_WINCON_BLD_PIXEL (1 << 6)
#define EXYNOS_WINCON_BLD_MASK (1 << 6)
#define EXYNOS_WINCON_BPPMODE_1BPP (0 << 2)
#define EXYNOS_WINCON_BPPMODE_2BPP (1 << 2)
#define EXYNOS_WINCON_BPPMODE_4BPP (2 << 2)
#define EXYNOS_WINCON_BPPMODE_8BPP_PAL (3 << 2)
#define EXYNOS_WINCON_BPPMODE_8BPP (4 << 2)
#define EXYNOS_WINCON_BPPMODE_16BPP_565 (5 << 2)
#define EXYNOS_WINCON_BPPMODE_16BPP_A555 (6 << 2)
#define EXYNOS_WINCON_BPPMODE_18BPP_666 (8 << 2)
#define EXYNOS_WINCON_BPPMODE_18BPP_A665 (9 << 2)
#define EXYNOS_WINCON_BPPMODE_24BPP_888 (0xb << 2)
#define EXYNOS_WINCON_BPPMODE_24BPP_A887 (0xc << 2)
#define EXYNOS_WINCON_BPPMODE_32BPP (0xd << 2)
#define EXYNOS_WINCON_BPPMODE_16BPP_A444 (0xe << 2)
#define EXYNOS_WINCON_BPPMODE_15BPP_555 (0xf << 2)
#define EXYNOS_WINCON_BPPMODE_MASK (0xf << 2)
#define EXYNOS_WINCON_BPPMODE_SHIFT (2)
#define EXYNOS_WINCON_ALPHA0_SEL (0 << 1)
#define EXYNOS_WINCON_ALPHA1_SEL (1 << 1)
#define EXYNOS_WINCON_ALPHA_SEL_MASK (1 << 1)
#define EXYNOS_WINCON_ENWIN_DISABLE (0 << 0)
#define EXYNOS_WINCON_ENWIN_ENABLE (1 << 0)
/* WINCON1 special */
#define EXYNOS_WINCON1_VP_DISABLE (0 << 24)
#define EXYNOS_WINCON1_VP_ENABLE (1 << 24)
#define EXYNOS_WINCON1_LOCALSEL_FIMC1 (0 << 23)
#define EXYNOS_WINCON1_LOCALSEL_VP (1 << 23)
#define EXYNOS_WINCON1_LOCALSEL_MASK (1 << 23)
/* WINSHMAP */
#define EXYNOS_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10)
#define EXYNOS_WINSHMAP_CH_ENABLE(x) (1 << (x))
#define EXYNOS_WINSHMAP_CH_DISABLE(x) (1 << (x))
#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x) (0x20 << (x))
#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x) (0x20 << (x))
/* VIDOSDxA, VIDOSDxB */
#define EXYNOS_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11)
#define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0)
#define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11)
#define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0)
#define EXYNOS_VIDOSD_RIGHT_X_E(x) (((x) & 0x1) << 23)
#define EXYNOS_VIDOSD_BOTTOM_Y_E(x) (((x) & 0x1) << 22)
/* VIDOSD0C, VIDOSDxD */
#define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0)
/* VIDOSDxC (1~4) */
#define EXYNOS_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20)
#define EXYNOS_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16)
#define EXYNOS_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12)
#define EXYNOS_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8)
#define EXYNOS_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4)
#define EXYNOS_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0)
#define EXYNOS_VIDOSD_ALPHA0_SHIFT (12)
#define EXYNOS_VIDOSD_ALPHA1_SHIFT (0)
/* Start Address */
#define EXYNOS_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24)
#define EXYNOS_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0)
/* End Address */
#define EXYNOS_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0)
/* Buffer Size */
#define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13)
#define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0)
#define EXYNOS_VIDADDR_OFFSIZE_E(x) ((((x) & 0x2000) >> 13) << 27)
#define EXYNOS_VIDADDR_PAGEWIDTH_E(x) ((((x) & 0x2000) >> 13) << 26)
/* WIN Color Map */
#define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff)
/* VIDINTCON0 */
#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19)
#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19)
#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18)
#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18)
#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17)
#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17)
#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK (0 << 15)
#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15)
#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15)
#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT (3 << 15)
#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK (3 << 15)
#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE (0 << 13)
#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK (1 << 13)
#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13)
#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT (3 << 13)
#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE (0 << 12)
#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE (1 << 12)
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4 (1 << 11)
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3 (1 << 10)
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2 (1 << 9)
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1 (1 << 6)
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0 (1 << 5)
#define EXYNOS_VIDINTCON0_FIFOSEL_ALL (0x73 << 5)
#define EXYNOS_VIDINTCON0_FIFOSEL_MASK (0x73 << 5)
#define EXYNOS_VIDINTCON0_FIFOLEVEL_25 (0 << 2)
#define EXYNOS_VIDINTCON0_FIFOLEVEL_50 (1 << 2)
#define EXYNOS_VIDINTCON0_FIFOLEVEL_75 (2 << 2)
#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2)
#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL (4 << 2)
#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK (7 << 2)
#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE (0 << 1)
#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE (1 << 1)
#define EXYNOS_VIDINTCON0_INT_DISABLE (0 << 0)
#define EXYNOS_VIDINTCON0_INT_ENABLE (1 << 0)
#define EXYNOS_VIDINTCON0_INT_MASK (1 << 0)
/* VIDINTCON1 */
#define EXYNOS_VIDINTCON1_INTVPPEND (1 << 5)
#define EXYNOS_VIDINTCON1_INTI80PEND (1 << 2)
#define EXYNOS_VIDINTCON1_INTFRMPEND (1 << 1)
#define EXYNOS_VIDINTCON1_INTFIFOPEND (1 << 0)
/* WINMAP */
#define EXYNOS_WINMAP_ENABLE (1 << 24)
/* WxKEYCON0 (1~4) */
#define EXYNOS_KEYCON0_KEYBLEN_DISABLE (0 << 26)
#define EXYNOS_KEYCON0_KEYBLEN_ENABLE (1 << 26)
#define EXYNOS_KEYCON0_KEY_DISABLE (0 << 25)
#define EXYNOS_KEYCON0_KEY_ENABLE (1 << 25)
#define EXYNOS_KEYCON0_DIRCON_MATCH_FG (0 << 24)
#define EXYNOS_KEYCON0_DIRCON_MATCH_BG (1 << 24)
#define EXYNOS_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0)
/* WxKEYCON1 (1~4) */
#define EXYNOS_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0)
/* DUALRGB */
#define EXYNOS_DUALRGB_BYPASS_SINGLE (0x00 << 0)
#define EXYNOS_DUALRGB_BYPASS_DUAL (0x01 << 0)
#define EXYNOS_DUALRGB_MIE_DUAL (0x10 << 0)
#define EXYNOS_DUALRGB_MIE_SINGLE (0x11 << 0)
#define EXYNOS_DUALRGB_LINESPLIT (0x0 << 2)
#define EXYNOS_DUALRGB_FRAMESPLIT (0x1 << 2)
#define EXYNOS_DUALRGB_SUB_CNT(x) ((x & 0xfff) << 4)
#define EXYNOS_DUALRGB_VDEN_EN_DISABLE (0x0 << 16)
#define EXYNOS_DUALRGB_VDEN_EN_ENABLE (0x1 << 16)
#define EXYNOS_DUALRGB_MAIN_CNT(x) ((x & 0xfff) << 18)
/* I80IFCONA0 and I80IFCONA1 */
#define EXYNOS_LCD_CS_SETUP(x) (((x) & 0xf) << 16)
#define EXYNOS_LCD_WR_SETUP(x) (((x) & 0xf) << 12)
#define EXYNOS_LCD_WR_ACT(x) (((x) & 0xf) << 8)
#define EXYNOS_LCD_WR_HOLD(x) (((x) & 0xf) << 4)
#define EXYNOS_RSPOL_LOW (0 << 2)
#define EXYNOS_RSPOL_HIGH (1 << 2)
#define EXYNOS_I80IFEN_DISABLE (0 << 0)
#define EXYNOS_I80IFEN_ENABLE (1 << 0)
/* TRIGCON */
#define EXYNOS_I80SOFT_TRIG_EN (1 << 0)
#define EXYNOS_I80START_TRIG (1 << 1)
#define EXYNOS_I80STATUS_TRIG_DONE (1 << 2)
/* DP_MIE_CLKCON */
#define EXYNOS_DP_MIE_DISABLE (0 << 0)
#define EXYNOS_DP_CLK_ENABLE (1 << 1)
#define EXYNOS_MIE_CLK_ENABLE (3 << 0)
#endif /* _REGS_FB_H */

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u-boot/arch/arm/mach-exynos/include/mach/gpio.h Normal file
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u-boot/arch/arm/mach-exynos/include/mach/i2s-regs.h Normal file
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/*
* Copyright (C) 2012 Samsung Electronics
* R. Chandrasekar <rcsekar@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __I2S_REGS_H__
#define __I2S_REGS_H__
#define CON_RESET (1 << 31)
#define CON_TXFIFO_FULL (1 << 8)
#define CON_TXCH_PAUSE (1 << 4)
#define CON_ACTIVE (1 << 0)
#define MOD_OP_CLK (3 << 30)
#define MOD_BLCP_SHIFT 24
#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT)
#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT)
#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT)
#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT)
#define MOD_BLC_16BIT (0 << 13)
#define MOD_BLC_8BIT (1 << 13)
#define MOD_BLC_24BIT (2 << 13)
#define MOD_BLC_MASK (3 << 13)
#define MOD_SLAVE (1 << 11)
#define MOD_RCLKSRC (0 << 10)
#define MOD_MASK (3 << 8)
#define MOD_LR_LLOW (0 << 7)
#define MOD_LR_RLOW (1 << 7)
#define MOD_SDF_IIS (0 << 5)
#define MOD_SDF_MSB (1 << 5)
#define MOD_SDF_LSB (2 << 5)
#define MOD_SDF_MASK (3 << 5)
#define MOD_RCLK_256FS (0 << 3)
#define MOD_RCLK_512FS (1 << 3)
#define MOD_RCLK_384FS (2 << 3)
#define MOD_RCLK_768FS (3 << 3)
#define MOD_RCLK_MASK (3 << 3)
#define MOD_BCLK_32FS (0 << 1)
#define MOD_BCLK_48FS (1 << 1)
#define MOD_BCLK_16FS (2 << 1)
#define MOD_BCLK_24FS (3 << 1)
#define MOD_BCLK_MASK (3 << 1)
#define MOD_CDCLKCON (1 << 12)
#define FIC_TXFLUSH (1 << 15)
#define FIC_RXFLUSH (1 << 7)
#define PSREN (1 << 15)
#define PSVAL (3 << 8)
#endif /* __I2S_REGS_H__ */

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u-boot/arch/arm/mach-exynos/include/mach/mipi_dsim.h Normal file
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/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: InKi Dae <inki.dae@samsung.com>
* Author: Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DSIM_H
#define _DSIM_H
#include <linux/list.h>
#include <linux/fb.h>
#include <lcd.h>
#define PANEL_NAME_SIZE (32)
enum mipi_dsim_interface_type {
DSIM_COMMAND,
DSIM_VIDEO
};
enum mipi_dsim_virtual_ch_no {
DSIM_VIRTUAL_CH_0,
DSIM_VIRTUAL_CH_1,
DSIM_VIRTUAL_CH_2,
DSIM_VIRTUAL_CH_3
};
enum mipi_dsim_burst_mode_type {
DSIM_NON_BURST_SYNC_EVENT,
DSIM_BURST_SYNC_EVENT,
DSIM_NON_BURST_SYNC_PULSE,
DSIM_BURST,
DSIM_NON_VIDEO_MODE
};
enum mipi_dsim_no_of_data_lane {
DSIM_DATA_LANE_1,
DSIM_DATA_LANE_2,
DSIM_DATA_LANE_3,
DSIM_DATA_LANE_4
};
enum mipi_dsim_byte_clk_src {
DSIM_PLL_OUT_DIV8,
DSIM_EXT_CLK_DIV8,
DSIM_EXT_CLK_BYPASS
};
enum mipi_dsim_pixel_format {
DSIM_CMD_3BPP,
DSIM_CMD_8BPP,
DSIM_CMD_12BPP,
DSIM_CMD_16BPP,
DSIM_VID_16BPP_565,
DSIM_VID_18BPP_666PACKED,
DSIM_18BPP_666LOOSELYPACKED,
DSIM_24BPP_888
};
/* MIPI DSI Processor-to-Peripheral transaction types */
enum {
MIPI_DSI_V_SYNC_START = 0x01,
MIPI_DSI_V_SYNC_END = 0x11,
MIPI_DSI_H_SYNC_START = 0x21,
MIPI_DSI_H_SYNC_END = 0x31,
MIPI_DSI_COLOR_MODE_OFF = 0x02,
MIPI_DSI_COLOR_MODE_ON = 0x12,
MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
MIPI_DSI_DCS_SHORT_WRITE = 0x05,
MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
MIPI_DSI_DCS_READ = 0x06,
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
MIPI_DSI_END_OF_TRANSMISSION = 0x08,
MIPI_DSI_NULL_PACKET = 0x09,
MIPI_DSI_BLANKING_PACKET = 0x19,
MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
MIPI_DSI_DCS_LONG_WRITE = 0x39,
MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
};
/*
* struct mipi_dsim_config - interface for configuring mipi-dsi controller.
*
* @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.
* @eot_disable: enable or disable EoT packet in HS mode.
* @auto_vertical_cnt: specifies auto vertical count mode.
* in Video mode, the vertical line transition uses line counter
* configured by VSA, VBP, and Vertical resolution.
* If this bit is set to '1', the line counter does not use VSA and VBP
* registers.(in command mode, this variable is ignored)
* @hse: set horizontal sync event mode.
* In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
* start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
* this bit transfers HSYNC end packet in VSYNC pulse and Vporch area
* (in mommand mode, this variable is ignored)
* @hfp: specifies HFP disable mode.
* if this variable is set, DSI master ignores HFP area in VIDEO mode.
* (in command mode, this variable is ignored)
* @hbp: specifies HBP disable mode.
* if this variable is set, DSI master ignores HBP area in VIDEO mode.
* (in command mode, this variable is ignored)
* @hsa: specifies HSA disable mode.
* if this variable is set, DSI master ignores HSA area in VIDEO mode.
* (in command mode, this variable is ignored)
* @e_interface: specifies interface to be used.(CPU or RGB interface)
* @e_virtual_ch: specifies virtual channel number that main or
* sub diaplsy uses.
* @e_pixel_format: specifies pixel stream format for main or sub display.
* @e_burst_mode: selects Burst mode in Video mode.
* in Non-burst mode, RGB data area is filled with RGB data and NULL
* packets, according to input bandwidth of RGB interface.
* In Burst mode, RGB data area is filled with RGB data only.
* @e_no_data_lane: specifies data lane count to be used by Master.
* @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
* DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
* @pll_stable_time: specifies the PLL Timer for stability of the ganerated
* clock(System clock cycle base)
* if the timer value goes to 0x00000000, the clock stable bit of status
* and interrupt register is set.
* @esc_clk: specifies escape clock frequency for getting the escape clock
* prescaler value.
* @stop_holding_cnt: specifies the interval value between transmitting
* read packet(or write "set_tear_on" command) and BTA request.
* after transmitting read packet or write "set_tear_on" command,
* BTA requests to D-PHY automatically. this counter value specifies
* the interval between them.
* @bta_timeout: specifies the timer for BTA.
* this register specifies time out from BTA request to change
* the direction with respect to Tx escape clock.
* @rx_timeout: specifies the timer for LP Rx mode timeout.
* this register specifies time out on how long RxValid deasserts,
* after RxLpdt asserts with respect to Tx escape clock.
* - RxValid specifies Rx data valid indicator.
* - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
* - RxValid and RxLpdt specifies signal from D-PHY.
*/
struct mipi_dsim_config {
unsigned char auto_flush;
unsigned char eot_disable;
unsigned char auto_vertical_cnt;
unsigned char hse;
unsigned char hfp;
unsigned char hbp;
unsigned char hsa;
enum mipi_dsim_interface_type e_interface;
enum mipi_dsim_virtual_ch_no e_virtual_ch;
enum mipi_dsim_pixel_format e_pixel_format;
enum mipi_dsim_burst_mode_type e_burst_mode;
enum mipi_dsim_no_of_data_lane e_no_data_lane;
enum mipi_dsim_byte_clk_src e_byte_clk;
/*
* ===========================================
* | P | M | S | MHz |
* -------------------------------------------
* | 3 | 100 | 3 | 100 |
* | 3 | 100 | 2 | 200 |
* | 3 | 63 | 1 | 252 |
* | 4 | 100 | 1 | 300 |
* | 4 | 110 | 1 | 330 |
* | 12 | 350 | 1 | 350 |
* | 3 | 100 | 1 | 400 |
* | 4 | 150 | 1 | 450 |
* | 6 | 118 | 1 | 472 |
* | 3 | 120 | 1 | 480 |
* | 12 | 250 | 0 | 500 |
* | 4 | 100 | 0 | 600 |
* | 3 | 81 | 0 | 648 |
* | 3 | 88 | 0 | 704 |
* | 3 | 90 | 0 | 720 |
* | 3 | 100 | 0 | 800 |
* | 12 | 425 | 0 | 850 |
* | 4 | 150 | 0 | 900 |
* | 12 | 475 | 0 | 950 |
* | 6 | 250 | 0 | 1000 |
* -------------------------------------------
*/
/*
* pms could be calculated as the following.
* M * 24 / P * 2 ^ S = MHz
*/
unsigned char p;
unsigned short m;
unsigned char s;
unsigned int pll_stable_time;
unsigned long esc_clk;
unsigned short stop_holding_cnt;
unsigned char bta_timeout;
unsigned short rx_timeout;
};
/*
* struct mipi_dsim_device - global interface for mipi-dsi driver.
*
* @dsim_config: infomation for configuring mipi-dsi controller.
* @master_ops: callbacks to mipi-dsi operations.
* @dsim_lcd_dev: pointer to activated ddi device.
* (it would be registered by mipi-dsi driver.)
* @dsim_lcd_drv: pointer to activated_ddi driver.
* (it would be registered by mipi-dsi driver.)
* @state: specifies status of MIPI-DSI controller.
* the status could be RESET, INIT, STOP, HSCLKEN and ULPS.
* @data_lane: specifiec enabled data lane number.
* this variable would be set by driver according to e_no_data_lane
* automatically.
* @e_clk_src: select byte clock source.
* @pd: pointer to MIPI-DSI driver platform data.
*/
struct mipi_dsim_device {
struct mipi_dsim_config *dsim_config;
struct mipi_dsim_master_ops *master_ops;
struct mipi_dsim_lcd_device *dsim_lcd_dev;
struct mipi_dsim_lcd_driver *dsim_lcd_drv;
unsigned int state;
unsigned int data_lane;
enum mipi_dsim_byte_clk_src e_clk_src;
struct exynos_platform_mipi_dsim *pd;
};
/*
* struct exynos_platform_mipi_dsim - interface to platform data
* for mipi-dsi driver.
*
* @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.
* lcd panel driver searched would be actived.
* @dsim_config: pointer of structure for configuring mipi-dsi controller.
* @lcd_panel_info: pointer for lcd panel specific structure.
* this structure specifies width, height, timing and polarity and so on.
* @lcd_power: callback pointer for enabling or disabling lcd power.
* @mipi_power: callback pointer for enabling or disabling mipi power.
* @phy_enable: pointer to a callback controlling D-PHY enable/reset
*/
struct exynos_platform_mipi_dsim {
char lcd_panel_name[PANEL_NAME_SIZE];
struct mipi_dsim_config *dsim_config;
void *lcd_panel_info;
int (*lcd_power)(void);
int (*mipi_power)(void);
void (*phy_enable)(unsigned int dev_index, unsigned int enable);
};
/*
* struct mipi_dsim_master_ops - callbacks to mipi-dsi operations.
*
* @cmd_write: transfer command to lcd panel at LP mode.
* @cmd_read: read command from rx register.
* @get_dsim_frame_done: get the status that all screen data have been
* transferred to mipi-dsi.
* @clear_dsim_frame_done: clear frame done status.
* @get_fb_frame_done: get frame done status of display controller.
* @trigger: trigger display controller.
* - this one would be used only in case of CPU mode.
*/
struct mipi_dsim_master_ops {
int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
const unsigned char *data0, unsigned int data1);
int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
unsigned int data0, unsigned int data1);
int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim);
int (*get_fb_frame_done)(void);
void (*trigger)(struct fb_info *info);
};
/*
* device structure for mipi-dsi based lcd panel.
*
* @name: name of the device to use with this device, or an
* alias for that name.
* @id: id of device to be registered.
* @bus_id: bus id for identifing connected bus
* and this bus id should be same as id of mipi_dsim_device.
* @master: pointer to mipi-dsi master device object.
* @platform_data: lcd panel specific platform data.
*/
struct mipi_dsim_lcd_device {
char *name;
int id;
int bus_id;
int reverse_panel;
struct mipi_dsim_device *master;
struct exynos_platform_mipi_dsim *platform_data;
};
/*
* driver structure for mipi-dsi based lcd panel.
*
* this structure should be registered by lcd panel driver.
* mipi-dsi driver seeks lcd panel registered through name field
* and calls these callback functions in appropriate time.
*
* @name: name of the driver to use with this device, or an
* alias for that name.
* @id: id of driver to be registered.
* this id would be used for finding device object registered.
* @mipi_panel_init: callback pointer for initializing lcd panel based on mipi
* dsi interface.
* @mipi_display_on: callback pointer for lcd panel display on.
*/
struct mipi_dsim_lcd_driver {
char *name;
int id;
int (*mipi_panel_init)(struct mipi_dsim_device *dsim_dev);
void (*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
};
#ifdef CONFIG_EXYNOS_MIPI_DSIM
int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd);
#else
static inline int exynos_mipi_dsi_init(
struct exynos_platform_mipi_dsim *dsim_pd)
{
return 0;
}
#endif
/*
* register mipi_dsim_lcd_driver object defined by lcd panel driver
* to mipi-dsi driver.
*/
int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver
*lcd_drv);
/*
* register mipi_dsim_lcd_device to mipi-dsi master.
*/
int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
*lcd_dev);
void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
struct vidinfo;
void exynos_init_dsim_platform_data(struct vidinfo *vid);
/* panel driver init based on mipi dsi interface */
void s6e8ax0_init(void);
extern int mipi_power(void);
#endif /* _DSIM_H */

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/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MMC_H_
#define __ASM_ARCH_MMC_H_
#define S5P_MMC_DEV_OFFSET 0x10000
#define SDHCI_CONTROL2 0x80
#define SDHCI_CONTROL3 0x84
#define SDHCI_CONTROL4 0x8C
#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
#define SDHCI_CTRL2_CDINVRXD3 (1 << 29)
#define SDHCI_CTRL2_SLCARDOUT (1 << 28)
#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
#define SDHCI_CTRL2_LVLDAT_SHIFT (16)
#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
#define SDHCI_CTRL2_ENFBCLKTX (1 << 15)
#define SDHCI_CTRL2_ENFBCLKRX (1 << 14)
#define SDHCI_CTRL2_SDCDSEL (1 << 13)
#define SDHCI_CTRL2_SDSIGPC (1 << 12)
#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9)
#define SDHCI_CTRL2_DFCNT_SHIFT (9)
#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
#define SDHCI_CTRL2_RWAITMODE (1 << 7)
#define SDHCI_CTRL2_DISBUFRD (1 << 6)
#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4)
#define SDHCI_CTRL2_SELBASECLK_SHIFT (4)
#define SDHCI_CTRL2_PWRSYNC (1 << 3)
#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
#define SDHCI_CTRL2_HWINITFIN (1 << 0)
#define SDHCI_CTRL3_FCSEL3 (1 << 31)
#define SDHCI_CTRL3_FCSEL2 (1 << 23)
#define SDHCI_CTRL3_FCSEL1 (1 << 15)
#define SDHCI_CTRL3_FCSEL0 (1 << 7)
#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
#define SDHCI_CTRL4_DRIVE_SHIFT (16)
#define SDHCI_MAX_HOSTS 4
int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline int s5p_mmc_init(int index, int bus_width)
{
unsigned int base = samsung_get_base_mmc() +
(S5P_MMC_DEV_OFFSET * index);
return s5p_sdhci_init(base, index, bus_width);
}
int exynos_mmc_init(const void *blob);
#endif

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/*
* Copyright (C) 2012 Samsung Electronics
* Rajeshwari Shinde <rajeshwari.s@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_ARCH_PERIPH_H
#define __ASM_ARM_ARCH_PERIPH_H
/*
* Peripherals required for pinmux configuration. List will
* grow with support for more devices getting added.
* Numbering based on interrupt table.
*
*/
enum periph_id {
PERIPH_ID_UART0 = 51,
PERIPH_ID_UART1,
PERIPH_ID_UART2,
PERIPH_ID_UART3,
PERIPH_ID_I2C0 = 56,
PERIPH_ID_I2C1,
PERIPH_ID_I2C2,
PERIPH_ID_I2C3,
PERIPH_ID_I2C4,
PERIPH_ID_I2C5,
PERIPH_ID_I2C6,
PERIPH_ID_I2C7,
PERIPH_ID_SPI0 = 68,
PERIPH_ID_SPI1,
PERIPH_ID_SPI2,
PERIPH_ID_SDMMC0 = 75,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
PERIPH_ID_SDMMC3,
PERIPH_ID_I2C8 = 87,
PERIPH_ID_I2C9,
PERIPH_ID_I2S0 = 98,
PERIPH_ID_I2S1 = 99,
/* Since following peripherals do
* not have shared peripheral interrupts (SPIs)
* they are numbered arbitiraly after the maximum
* SPIs Exynos has (128)
*/
PERIPH_ID_SROMC = 128,
PERIPH_ID_SPI3,
PERIPH_ID_SPI4,
PERIPH_ID_SDMMC4,
PERIPH_ID_PWM0,
PERIPH_ID_PWM1,
PERIPH_ID_PWM2,
PERIPH_ID_PWM3,
PERIPH_ID_PWM4,
PERIPH_ID_DPHPD,
PERIPH_ID_I2C10 = 203,
PERIPH_ID_NONE = -1,
};
#endif /* __ASM_ARM_ARCH_PERIPH_H */

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/*
* Copyright (C) 2012 Samsung Electronics
* Abhilash Kesavan <a.kesavan@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_ARCH_PINMUX_H
#define __ASM_ARM_ARCH_PINMUX_H
#include "periph.h"
/*
* Flags for setting specific configarations of peripherals.
* List will grow with support for more devices getting added.
*/
enum {
PINMUX_FLAG_NONE = 0x00000000,
/* Flags for eMMC */
PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
/* Flags for SROM controller */
PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
/* Flags for I2C */
PINMUX_FLAG_HS_MODE = 1 << 1, /* I2C High Speed Mode */
};
/**
* Configures the pinmux for a particular peripheral.
*
* Each gpio can be configured in many different ways (4 bits on exynos)
* such as "input", "output", "special function", "external interrupt"
* etc. This function will configure the peripheral pinmux along with
* pull-up/down and drive strength.
*
* @param peripheral peripheral to be configured
* @param flags configure flags
* @return 0 if ok, -1 on error (e.g. unsupported peripheral)
*/
int exynos_pinmux_config(int peripheral, int flags);
/**
* Decode the peripheral id using the interrpt numbers.
*
* @param blob Device tree blob
* @param node FDT I2C node to find
* @return peripheral id if ok, PERIPH_ID_NONE on error
*/
int pinmux_decode_periph_id(const void *blob, int node);
#endif

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u-boot/arch/arm/mach-exynos/include/mach/pwm.h Normal file
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/*
* Copyright (C) 2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
* Minkyu Kang <mk7.kang@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_ARCH_PWM_H_
#define __ASM_ARM_ARCH_PWM_H_
#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
/* Divider MUX */
#define MUX_DIV_1 0 /* 1/1 period */
#define MUX_DIV_2 1 /* 1/2 period */
#define MUX_DIV_4 2 /* 1/4 period */
#define MUX_DIV_8 3 /* 1/8 period */
#define MUX_DIV_16 4 /* 1/16 period */
#define MUX_DIV_SHIFT(x) (x * 4)
#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
#define TCON_START(x) (1 << TCON_OFFSET(x))
#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
#define TCON4_AUTO_RELOAD (1 << 22)
#ifndef __ASSEMBLY__
struct s5p_timer {
unsigned int tcfg0;
unsigned int tcfg1;
unsigned int tcon;
unsigned int tcntb0;
unsigned int tcmpb0;
unsigned int tcnto0;
unsigned int tcntb1;
unsigned int tcmpb1;
unsigned int tcnto1;
unsigned int tcntb2;
unsigned int tcmpb2;
unsigned int tcnto2;
unsigned int tcntb3;
unsigned int tcmpb3;
unsigned int tcnto3;
unsigned int tcntb4;
unsigned int tcnto4;
unsigned int tintcstat;
};
#endif /* __ASSEMBLY__ */
#endif

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u-boot/arch/arm/mach-exynos/include/mach/pwm_backlight.h Normal file
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/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PWM_BACKLIGHT_H_
#define _PWM_BACKLIGHT_H_
struct pwm_backlight_data {
int pwm_id;
int period;
int max_brightness;
int brightness;
};
extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd);
#endif /* _PWM_BACKLIGHT_H_ */

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u-boot/arch/arm/mach-exynos/include/mach/sound.h Normal file
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/*
* Copyright (C) 2012 Samsung Electronics
* Rajeshwari Shinde <rajeshwari.s@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SOUND_ARCH_H__
#define __SOUND_ARCH_H__
/* I2S values */
#define I2S_PLL_CLK 192000000
#define I2S_SAMPLING_RATE 48000
#define I2S_BITS_PER_SAMPLE 16
#define I2S_CHANNELS 2
#define I2S_RFS 256
#define I2S_BFS 32
/* I2C values */
#define AUDIO_I2C_BUS 1
#define AUDIO_I2C_REG 0x1a
/* Audio Codec */
#define AUDIO_CODEC "wm8994"
#define AUDIO_COMPAT 1
#endif

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u-boot/arch/arm/mach-exynos/include/mach/spi.h Normal file
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/*
* (C) Copyright 2012 SAMSUNG Electronics
* Padmavathi Venna <padma.v@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
#ifndef __ASSEMBLY__
/* SPI peripheral register map; padded to 64KB */
struct exynos_spi {
unsigned int ch_cfg; /* 0x00 */
unsigned char reserved0[4];
unsigned int mode_cfg; /* 0x08 */
unsigned int cs_reg; /* 0x0c */
unsigned char reserved1[4];
unsigned int spi_sts; /* 0x14 */
unsigned int tx_data; /* 0x18 */
unsigned int rx_data; /* 0x1c */
unsigned int pkt_cnt; /* 0x20 */
unsigned char reserved2[4];
unsigned int swap_cfg; /* 0x28 */
unsigned int fb_clk; /* 0x2c */
unsigned char padding[0xffd0];
};
#define EXYNOS_SPI_MAX_FREQ 50000000
#define SPI_TIMEOUT_MS 10
#define SF_READ_DATA_CMD 0x3
/* SPI_CHCFG */
#define SPI_CH_HS_EN (1 << 6)
#define SPI_CH_RST (1 << 5)
#define SPI_SLAVE_MODE (1 << 4)
#define SPI_CH_CPOL_L (1 << 3)
#define SPI_CH_CPHA_B (1 << 2)
#define SPI_RX_CH_ON (1 << 1)
#define SPI_TX_CH_ON (1 << 0)
/* SPI_MODECFG */
#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29)
#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17)
/* SPI_CSREG */
#define SPI_SLAVE_SIG_INACT (1 << 0)
/* SPI_STS */
#define SPI_ST_TX_DONE (1 << 25)
#define SPI_FIFO_LVL_MASK 0x1ff
#define SPI_TX_LVL_OFFSET 6
#define SPI_RX_LVL_OFFSET 15
/* Feedback Delay */
#define SPI_CLK_BYPASS (0 << 0)
#define SPI_FB_DELAY_90 (1 << 0)
#define SPI_FB_DELAY_180 (2 << 0)
#define SPI_FB_DELAY_270 (3 << 0)
/* Packet Count */
#define SPI_PACKET_CNT_EN (1 << 16)
/* Swap config */
#define SPI_TX_SWAP_EN (1 << 0)
#define SPI_TX_BYTE_SWAP (1 << 2)
#define SPI_TX_HWORD_SWAP (1 << 3)
#define SPI_TX_BYTE_SWAP (1 << 2)
#define SPI_RX_SWAP_EN (1 << 4)
#define SPI_RX_BYTE_SWAP (1 << 6)
#define SPI_RX_HWORD_SWAP (1 << 7)
#endif /* __ASSEMBLY__ */
#endif

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u-boot/arch/arm/mach-exynos/include/mach/spl.h Normal file
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/*
* Copyright (c) 2012 The Chromium OS Authors.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_EXYNOS_SPL_H__
#define __ASM_ARCH_EXYNOS_SPL_H__
#include <asm/arch/dmc.h>
#include <asm/arch/power.h>
#ifndef __ASSEMBLY__
/* Parameters of early board initialization in SPL */
struct spl_machine_param {
/* Add fields as and when required */
u32 signature;
u32 version; /* Version number */
u32 size; /* Size of block */
/**
* Parameters we expect, in order, terminated with \0. Each parameter
* is a single character representing one 32-bit word in this
* structure.
*
* Valid characters in this string are:
*
* Code Name
* v mem_iv_size
* m mem_type
* u uboot_size
* b boot_source
* f frequency_mhz (memory frequency in MHz)
* a ARM clock frequency in MHz
* s serial base address
* i i2c base address for early access (meant for PMIC)
* r board rev GPIO numbers used to read board revision
* (lower halfword=bit 0, upper=bit 1)
* M Memory Manufacturer name
* \0 termination
*/
char params[12]; /* Length must be word-aligned */
u32 mem_iv_size; /* Memory channel interleaving size */
enum ddr_mode mem_type; /* Type of on-board memory */
/*
* U-Boot size - The iROM mmc copy function used by the SPL takes a
* block count paramter to describe the U-Boot size unlike the spi
* boot copy function which just uses the U-Boot size directly. Align
* the U-Boot size to block size (512 bytes) when populating the SPL
* table only for mmc boot.
*/
u32 uboot_size;
unsigned boot_source; /* Boot device */
unsigned frequency_mhz; /* Frequency of memory in MHz */
unsigned arm_freq_mhz; /* ARM Frequency in MHz */
u32 serial_base; /* Serial base address */
u32 i2c_base; /* i2c base address */
u32 board_rev_gpios; /* Board revision GPIOs */
enum mem_manuf mem_manuf; /* Memory Manufacturer */
} __attribute__((__packed__));
#endif
/**
* Validate signature and return a pointer to the parameter table. If the
* signature is invalid, call panic() and never return.
*
* @return pointer to the parameter table if signature matched or never return.
*/
struct spl_machine_param *spl_get_machine_params(void);
#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */

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u-boot/arch/arm/mach-exynos/include/mach/sromc.h Normal file
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/*
* (C) Copyright 2010 Samsung Electronics
* Naveen Krishna Ch <ch.naveen@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Note: This file contains the register description for SROMC
*/
#ifndef __ASM_ARCH_SROMC_H_
#define __ASM_ARCH_SROMC_H_
#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
/* 1-> Byte base address*/
#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
#define SROMC_BC_TAH(x) (x << 8) /* address holding time */
#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
#ifndef __ASSEMBLY__
struct s5p_sromc {
unsigned int bw;
unsigned int bc[4];
};
#endif /* __ASSEMBLY__ */
/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
enum {
FDT_SROM_PMC,
FDT_SROM_TACP,
FDT_SROM_TAH,
FDT_SROM_TCOH,
FDT_SROM_TACC,
FDT_SROM_TCOS,
FDT_SROM_TACS,
FDT_SROM_TIMING_COUNT,
};
struct fdt_sromc {
u8 bank; /* srom bank number */
u8 width; /* bus width in bytes */
unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
};
#endif /* __ASM_ARCH_SROMC_H_ */

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/*
* Copyright (C) 2010 Samsung Electrnoics
* Minkyu Kang <mk7.kang@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
u32 get_device_type(void);
void invalidate_dcache(u32);
void l2_cache_disable(void);
void l2_cache_enable(void);
#endif

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/*
* (C) Copyright 2012 Samsung Electronics
* Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_ARCH_SYSTEM_H_
#define __ASM_ARM_ARCH_SYSTEM_H_
#ifndef __ASSEMBLY__
struct exynos4_sysreg {
unsigned char res1[0x210];
unsigned int display_ctrl;
unsigned int display_ctrl2;
unsigned int camera_control;
unsigned int audio_endian;
unsigned int jtag_con;
};
struct exynos5_sysreg {
unsigned char res1[0x214];
unsigned int disp1blk_cfg;
unsigned int disp2blk_cfg;
unsigned int hdcp_e_fuse;
unsigned int gsclblk_cfg0;
unsigned int gsclblk_cfg1;
unsigned int reserved;
unsigned int ispblk_cfg;
unsigned int usb20phy_cfg;
unsigned char res2[0x29c];
unsigned int mipi_dphy;
unsigned int dptx_dphy;
unsigned int phyclk_sel;
};
#endif
#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
/*
* Data Synchronization Barrier acts as a special kind of memory barrier.
* No instruction in program order after this instruction executes until
* this instruction completes. This instruction completes when:
* - All explicit memory accesses before this instruction complete.
* - All Cache, Branch predictor and TLB maintenance operations before
* this instruction complete.
*/
#define dsb() __asm__ __volatile__ ("dsb\n\t" : : );
/*
* This instruction causes an event to be signaled to all cores
* within a multiprocessor system. If SEV is implemented,
* WFE must also be implemented.
*/
#define sev() __asm__ __volatile__ ("sev\n\t" : : );
/*
* If the Event Register is not set, WFE suspends execution until
* one of the following events occurs:
* - an IRQ interrupt, unless masked by the CPSR I-bit
* - an FIQ interrupt, unless masked by the CPSR F-bit
* - an Imprecise Data abort, unless masked by the CPSR A-bit
* - a Debug Entry request, if Debug is enabled
* - an Event signaled by another processor using the SEV instruction.
* If the Event Register is set, WFE clears it and returns immediately.
* If WFE is implemented, SEV must also be implemented.
*/
#define wfe() __asm__ __volatile__ ("wfe\n\t" : : );
/* Move 0xd3 value to CPSR register to enable SVC mode */
#define svc32_mode_en() __asm__ __volatile__ \
("@ I&F disable, Mode: 0x13 - SVC\n\t" \
"msr cpsr_c, #0x13|0xC0\n\t" : : )
/* Set program counter with the given value */
#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x))
/* Branch to the given location */
#define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x))
/* Read Main Id register */
#define mrc_midr(x) __asm__ __volatile__ \
("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
/* Read Multiprocessor Affinity Register */
#define mrc_mpafr(x) __asm__ __volatile__ \
("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : )
/* Read System Control Register */
#define mrc_sctlr(x) __asm__ __volatile__ \
("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : )
/* Read Auxiliary Control Register */
#define mrc_auxr(x) __asm__ __volatile__ \
("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : )
/* Read L2 Control register */
#define mrc_l2_ctlr(x) __asm__ __volatile__ \
("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : )
/* Read L2 Auxilliary Control register */
#define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \
("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : )
/* Write System Control Register */
#define mcr_sctlr(x) __asm__ __volatile__ \
("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x))
/* Write Auxiliary Control Register */
#define mcr_auxr(x) __asm__ __volatile__ \
("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x))
/* Invalidate all instruction caches to PoU */
#define mcr_icache(x) __asm__ __volatile__ \
("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x))
/* Invalidate unified TLB */
#define mcr_tlb(x) __asm__ __volatile__ \
("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x))
/* Write L2 Control register */
#define mcr_l2_ctlr(x) __asm__ __volatile__ \
("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x))
/* Write L2 Auxilliary Control register */
#define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \
("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x))
void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
int exynos_lcd_early_init(const void *blob);
#endif /* _EXYNOS4_SYSTEM_H */

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/*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Akshay Saraswat <akshay.s@samsung.com>
*
* EXYNOS - Thermal Management Unit
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_TMU_H
#define __ASM_ARCH_TMU_H
struct exynos5_tmu_reg {
u32 triminfo;
u32 rsvd1[4];
u32 triminfo_control;
u32 rsvd5[2];
u32 tmu_control;
u32 rsvd7;
u32 tmu_status;
u32 sampling_internal;
u32 counter_value0;
u32 counter_value1;
u32 rsvd8[2];
u32 current_temp;
u32 rsvd10[3];
u32 threshold_temp_rise;
u32 threshold_temp_fall;
u32 rsvd13[2];
u32 past_temp3_0;
u32 past_temp7_4;
u32 past_temp11_8;
u32 past_temp15_12;
u32 inten;
u32 intstat;
u32 intclear;
u32 rsvd15;
u32 emul_con;
};
#endif /* __ASM_ARCH_TMU_H */

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/*
* (C) Copyright 2012 Samsung Electronics
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __TZPC_H_
#define __TZPC_H_
#ifndef __ASSEMBLY__
struct exynos_tzpc {
unsigned int r0size;
char res1[0x7FC];
unsigned int decprot0stat;
unsigned int decprot0set;
unsigned int decprot0clr;
unsigned int decprot1stat;
unsigned int decprot1set;
unsigned int decprot1clr;
unsigned int decprot2stat;
unsigned int decprot2set;
unsigned int decprot2clr;
unsigned int decprot3stat;
unsigned int decprot3set;
unsigned int decprot3clr;
char res2[0x7B0];
unsigned int periphid0;
unsigned int periphid1;
unsigned int periphid2;
unsigned int periphid3;
unsigned int pcellid0;
unsigned int pcellid1;
unsigned int pcellid2;
unsigned int pcellid3;
};
#define EXYNOS4_NR_TZPC_BANKS 6
#define EXYNOS5_NR_TZPC_BANKS 10
/* TZPC : Register Offsets */
#define TZPC_BASE_OFFSET 0x10000
/*
* TZPC Register Value :
* R0SIZE: 0x0 : Size of secured ram
*/
#define R0SIZE 0x0
/*
* TZPC Decode Protection Register Value :
* DECPROTXSET: 0xFF : Set Decode region to non-secure
*/
#define DECPROTXSET 0xFF
void tzpc_init(void);
#endif
#endif

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/*
* (C) Copyright 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Heungjun Kim <riverful.kim@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_UART_H_
#define __ASM_ARCH_UART_H_
#ifndef __ASSEMBLY__
/* baudrate rest value */
union br_rest {
unsigned short slot; /* udivslot */
unsigned char value; /* ufracval */
};
struct s5p_uart {
unsigned int ulcon;
unsigned int ucon;
unsigned int ufcon;
unsigned int umcon;
unsigned int utrstat;
unsigned int uerstat;
unsigned int ufstat;
unsigned int umstat;
unsigned char utxh;
unsigned char res1[3];
unsigned char urxh;
unsigned char res2[3];
unsigned int ubrdiv;
union br_rest rest;
unsigned char res3[0xffd0];
};
static inline int s5p_uart_divslot(void)
{
return 0;
}
#endif /* __ASSEMBLY__ */
#endif

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/*
* Copyright (C) 2011 Samsung Electronics
* Heungjun Kim <riverful.kim@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_ARCH_WATCHDOG_H_
#define __ASM_ARM_ARCH_WATCHDOG_H_
#define WTCON_RESET_OFFSET 0
#define WTCON_INTEN_OFFSET 2
#define WTCON_CLKSEL_OFFSET 3
#define WTCON_EN_OFFSET 5
#define WTCON_PRE_OFFSET 8
#define WTCON_CLK_16 0x0
#define WTCON_CLK_32 0x1
#define WTCON_CLK_64 0x2
#define WTCON_CLK_128 0x3
#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET)
#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET)
#define WTCON_EN (0x1 << WTCON_EN_OFFSET)
#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
#ifndef __ASSEMBLY__
struct s5p_watchdog {
unsigned int wtcon;
unsigned int wtdat;
unsigned int wtcnt;
unsigned int wtclrint;
};
/* functions */
void wdt_stop(void);
void wdt_start(unsigned int timeout);
#endif /* __ASSEMBLY__ */
#endif

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/* Copyright (c) 2012 Samsung Electronics Co. Ltd
*
* Exynos Phy register definitions
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_XHCI_EXYNOS_H_
#define _ASM_ARCH_XHCI_EXYNOS_H_
/* Phy register MACRO definitions */
#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
#define PHYUTMI_OTGDISABLE (1 << 6)
#define PHYUTMI_FORCESUSPEND (1 << 1)
#define PHYUTMI_FORCESLEEP (1 << 0)
#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
#define PHYCLKRST_SSC_EN (0x1 << 20)
#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
#define PHYCLKRST_FSEL_MASK (0x3f << 5)
#define PHYCLKRST_FSEL(_x) ((_x) << 5)
#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
#define PHYCLKRST_RETENABLEN (0x1 << 4)
#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
#define PHYCLKRST_PORTRESET (0x1 << 1)
#define PHYCLKRST_COMMONONN (0x1 << 0)
#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
#define FSEL_CLKSEL_24M (0x5)
/* XHCI PHY register structure */
struct exynos_usb3_phy {
unsigned int reserve1;
unsigned int link_system;
unsigned int phy_utmi;
unsigned int phy_pipe;
unsigned int phy_clk_rst;
unsigned int phy_reg0;
unsigned int phy_reg1;
unsigned int phy_param0;
unsigned int phy_param1;
unsigned int phy_term;
unsigned int phy_test;
unsigned int phy_adp;
unsigned int phy_batchg;
unsigned int phy_resume;
unsigned int reserve2[3];
unsigned int link_port;
};
#endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */