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avionic design with actual uboot and tooling

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submodule of avionic design uboot bootloader and with included tools to
get you started , read readme.md and readme-tk1-loader.md
This commit is contained in:
Kevin
2026-03-03 21:46:32 +02:00
parent fe3ba02c96
commit 68d74d3181
11967 changed files with 2221897 additions and 0 deletions
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41
u-boot/arch/arm/include/asm/imx-common/boot_mode.h Normal file
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/*
* Copyright (C) 2012 Boundary Devices Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_BOOT_MODE_H
#define _ASM_BOOT_MODE_H
#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
enum boot_device {
WEIM_NOR_BOOT,
ONE_NAND_BOOT,
PATA_BOOT,
SATA_BOOT,
I2C_BOOT,
SPI_NOR_BOOT,
SD1_BOOT,
SD2_BOOT,
SD3_BOOT,
SD4_BOOT,
MMC1_BOOT,
MMC2_BOOT,
MMC3_BOOT,
MMC4_BOOT,
NAND_BOOT,
QSPI_BOOT,
UNKNOWN_BOOT,
BOOT_DEV_NUM = UNKNOWN_BOOT,
};
struct boot_mode {
const char *name;
unsigned cfg_val;
};
void add_board_boot_modes(const struct boot_mode *p);
void boot_mode_apply(unsigned cfg_val);
extern const struct boot_mode soc_boot_modes[];
#endif

166
u-boot/arch/arm/include/asm/imx-common/dma.h Normal file
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/*
* Freescale i.MX28 APBH DMA
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DMA_H__
#define __DMA_H__
#include <linux/list.h>
#include <linux/compiler.h>
#ifndef CONFIG_ARCH_DMA_PIO_WORDS
#define DMA_PIO_WORDS 15
#else
#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
#endif
#define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN
/*
* MXS DMA channels
*/
#if defined(CONFIG_MX23)
enum {
MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
MXS_DMA_CHANNEL_AHB_APBH_SSP0,
MXS_DMA_CHANNEL_AHB_APBH_SSP1,
MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
MXS_MAX_DMA_CHANNELS,
};
#elif defined(CONFIG_MX28)
enum {
MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_SSP1,
MXS_DMA_CHANNEL_AHB_APBH_SSP2,
MXS_DMA_CHANNEL_AHB_APBH_SSP3,
MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
MXS_DMA_CHANNEL_AHB_APBH_HSADC,
MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
MXS_MAX_DMA_CHANNELS,
};
#endif
/*
* MXS DMA hardware command.
*
* This structure describes the in-memory layout of an entire DMA command,
* including space for the maximum number of PIO accesses. See the appropriate
* reference manual for a detailed description of what these fields mean to the
* DMA hardware.
*/
#define MXS_DMA_DESC_COMMAND_MASK 0x3
#define MXS_DMA_DESC_COMMAND_OFFSET 0
#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
#define MXS_DMA_DESC_CHAIN (1 << 2)
#define MXS_DMA_DESC_IRQ (1 << 3)
#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
#define MXS_DMA_DESC_DEC_SEM (1 << 6)
#define MXS_DMA_DESC_WAIT4END (1 << 7)
#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
#define MXS_DMA_DESC_BYTES_OFFSET 16
struct mxs_dma_cmd {
unsigned long next;
unsigned long data;
union {
dma_addr_t address;
unsigned long alternate;
};
unsigned long pio_words[DMA_PIO_WORDS];
};
/*
* MXS DMA command descriptor.
*
* This structure incorporates an MXS DMA hardware command structure, along
* with metadata.
*/
#define MXS_DMA_DESC_FIRST (1 << 0)
#define MXS_DMA_DESC_LAST (1 << 1)
#define MXS_DMA_DESC_READY (1 << 31)
struct mxs_dma_desc {
struct mxs_dma_cmd cmd;
unsigned int flags;
dma_addr_t address;
void *buffer;
struct list_head node;
} __aligned(MXS_DMA_ALIGNMENT);
/**
* MXS DMA channel
*
* This structure represents a single DMA channel. The MXS platform code
* maintains an array of these structures to represent every DMA channel in the
* system (see mxs_dma_channels).
*/
#define MXS_DMA_FLAGS_IDLE 0
#define MXS_DMA_FLAGS_BUSY (1 << 0)
#define MXS_DMA_FLAGS_FREE 0
#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
#define MXS_DMA_FLAGS_VALID (1 << 31)
struct mxs_dma_chan {
const char *name;
unsigned long dev;
struct mxs_dma_device *dma;
unsigned int flags;
unsigned int active_num;
unsigned int pending_num;
struct list_head active;
struct list_head done;
};
struct mxs_dma_desc *mxs_dma_desc_alloc(void);
void mxs_dma_desc_free(struct mxs_dma_desc *);
int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
int mxs_dma_go(int chan);
void mxs_dma_init(void);
int mxs_dma_init_channel(int chan);
int mxs_dma_release(int chan);
void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
#endif /* __DMA_H__ */

23
u-boot/arch/arm/include/asm/imx-common/gpio.h Normal file
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/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_IMX_GPIO_H
#define __ASM_ARCH_IMX_GPIO_H
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr; /* data */
u32 gpio_dir; /* direction */
u32 gpio_psr; /* pad satus */
};
#endif
#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31))
#endif

148
u-boot/arch/arm/include/asm/imx-common/hab.h Normal file
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/*
* Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
#ifndef __SECURE_MX6Q_H__
#define __SECURE_MX6Q_H__
#include <linux/types.h>
/* -------- start of HAB API updates ------------*/
/* The following are taken from HAB4 SIS */
/* Status definitions */
enum hab_status {
HAB_STS_ANY = 0x00,
HAB_FAILURE = 0x33,
HAB_WARNING = 0x69,
HAB_SUCCESS = 0xf0
};
/* Security Configuration definitions */
enum hab_config {
HAB_CFG_RETURN = 0x33, /* < Field Return IC */
HAB_CFG_OPEN = 0xf0, /* < Non-secure IC */
HAB_CFG_CLOSED = 0xcc /* < Secure IC */
};
/* State definitions */
enum hab_state {
HAB_STATE_INITIAL = 0x33, /* Initialising state (transitory) */
HAB_STATE_CHECK = 0x55, /* Check state (non-secure) */
HAB_STATE_NONSECURE = 0x66, /* Non-secure state */
HAB_STATE_TRUSTED = 0x99, /* Trusted state */
HAB_STATE_SECURE = 0xaa, /* Secure state */
HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */
HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */
HAB_STATE_NONE = 0xf0, /* No security state machine */
HAB_STATE_MAX
};
enum hab_reason {
HAB_RSN_ANY = 0x00, /* Match any reason */
HAB_ENG_FAIL = 0x30, /* Engine failure */
HAB_INV_ADDRESS = 0x22, /* Invalid address: access denied */
HAB_INV_ASSERTION = 0x0c, /* Invalid assertion */
HAB_INV_CALL = 0x28, /* Function called out of sequence */
HAB_INV_CERTIFICATE = 0x21, /* Invalid certificate */
HAB_INV_COMMAND = 0x06, /* Invalid command: command malformed */
HAB_INV_CSF = 0x11, /* Invalid csf */
HAB_INV_DCD = 0x27, /* Invalid dcd */
HAB_INV_INDEX = 0x0f, /* Invalid index: access denied */
HAB_INV_IVT = 0x05, /* Invalid ivt */
HAB_INV_KEY = 0x1d, /* Invalid key */
HAB_INV_RETURN = 0x1e, /* Failed callback function */
HAB_INV_SIGNATURE = 0x18, /* Invalid signature */
HAB_INV_SIZE = 0x17, /* Invalid data size */
HAB_MEM_FAIL = 0x2e, /* Memory failure */
HAB_OVR_COUNT = 0x2b, /* Expired poll count */
HAB_OVR_STORAGE = 0x2d, /* Exhausted storage region */
HAB_UNS_ALGORITHM = 0x12, /* Unsupported algorithm */
HAB_UNS_COMMAND = 0x03, /* Unsupported command */
HAB_UNS_ENGINE = 0x0a, /* Unsupported engine */
HAB_UNS_ITEM = 0x24, /* Unsupported configuration item */
HAB_UNS_KEY = 0x1b, /* Unsupported key type/parameters */
HAB_UNS_PROTOCOL = 0x14, /* Unsupported protocol */
HAB_UNS_STATE = 0x09, /* Unsuitable state */
HAB_RSN_MAX
};
enum hab_context {
HAB_CTX_ANY = 0x00, /* Match any context */
HAB_CTX_FAB = 0xff, /* Event logged in hab_fab_test() */
HAB_CTX_ENTRY = 0xe1, /* Event logged in hab_rvt.entry() */
HAB_CTX_TARGET = 0x33, /* Event logged in hab_rvt.check_target() */
HAB_CTX_AUTHENTICATE = 0x0a,/* Logged in hab_rvt.authenticate_image() */
HAB_CTX_DCD = 0xdd, /* Event logged in hab_rvt.run_dcd() */
HAB_CTX_CSF = 0xcf, /* Event logged in hab_rvt.run_csf() */
HAB_CTX_COMMAND = 0xc0, /* Event logged executing csf/dcd command */
HAB_CTX_AUT_DAT = 0xdb, /* Authenticated data block */
HAB_CTX_ASSERT = 0xa0, /* Event logged in hab_rvt.assert() */
HAB_CTX_EXIT = 0xee, /* Event logged in hab_rvt.exit() */
HAB_CTX_MAX
};
struct imx_sec_config_fuse_t {
int bank;
int word;
};
#if defined(CONFIG_SECURE_BOOT)
extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
#endif
/*Function prototype description*/
typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
uint8_t* , size_t*);
typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
enum hab_state *);
typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
typedef enum hab_status hab_rvt_entry_t(void);
typedef enum hab_status hab_rvt_exit_t(void);
typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
typedef void hapi_clock_init_t(void);
#define HAB_ENG_ANY 0x00 /* Select first compatible engine */
#define HAB_ENG_SCC 0x03 /* Security controller */
#define HAB_ENG_RTIC 0x05 /* Run-time integrity checker */
#define HAB_ENG_SAHARA 0x06 /* Crypto accelerator */
#define HAB_ENG_CSU 0x0a /* Central Security Unit */
#define HAB_ENG_SRTC 0x0c /* Secure clock */
#define HAB_ENG_DCP 0x1b /* Data Co-Processor */
#define HAB_ENG_CAAM 0x1d /* CAAM */
#define HAB_ENG_SNVS 0x1e /* Secure Non-Volatile Storage */
#define HAB_ENG_OCOTP 0x21 /* Fuse controller */
#define HAB_ENG_DTCP 0x22 /* DTCP co-processor */
#define HAB_ENG_ROM 0x36 /* Protected ROM area */
#define HAB_ENG_HDCP 0x24 /* HDCP co-processor */
#define HAB_ENG_RTL 0x77 /* RTL simulation engine */
#define HAB_ENG_SW 0xff /* Software engine */
#ifdef CONFIG_ROM_UNIFIED_SECTIONS
#define HAB_RVT_BASE 0x00000100
#else
#define HAB_RVT_BASE 0x00000094
#endif
#define HAB_RVT_ENTRY (*(uint32_t *)(HAB_RVT_BASE + 0x04))
#define HAB_RVT_EXIT (*(uint32_t *)(HAB_RVT_BASE + 0x08))
#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
#define HAB_RVT_REPORT_EVENT (*(uint32_t *)(HAB_RVT_BASE + 0x20))
#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24))
#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8)
#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC)
#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x000000A8)
#define HAB_RVT_ENTRY_NEW (*(uint32_t *)0x0000009C)
#define HAB_RVT_EXIT_NEW (*(uint32_t *)0x000000A0)
#define HAB_CID_ROM 0 /**< ROM Caller ID */
#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
/* ----------- end of HAB API updates ------------*/
#endif

24
u-boot/arch/arm/include/asm/imx-common/imximage.cfg Normal file
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/*
* i.MX image header offset values
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* NOTE: This file must be kept in sync with tools/imximage.h because
* tools/imximage.c can not cross-include headers from arch/arm/
* and vice-versa.
*/
#ifndef __ASM_IMX_COMMON_IMXIMAGE_CFG__
#define __ASM_IMX_COMMON_IMXIMAGE_CFG__
/* Standard image header offset for NAND, SATA, SD, SPI flash. */
#define FLASH_OFFSET_STANDARD 0x400
/* Specific image header offset for booting from OneNAND. */
#define FLASH_OFFSET_ONENAND 0x100
/* Specific image header offset for booting from memory-mapped NOR. */
#define FLASH_OFFSET_NOR 0x1000
#endif /* __ASM_IMX_COMMON_IMXIMAGE_CFG__ */

260
u-boot/arch/arm/include/asm/imx-common/iomux-v3.h Normal file
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/*
* Based on Linux i.MX iomux-v3.h file:
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
* <armlinux@phytec.de>
*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MACH_IOMUX_V3_H__
#define __MACH_IOMUX_V3_H__
#include <common.h>
/*
* build IOMUX_PAD structure
*
* This iomux scheme is based around pads, which are the physical balls
* on the processor.
*
* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
* things like driving strength and pullup/pulldown.
* - Each pad can have but not necessarily does have an output routing register
* (IOMUXC_SW_MUX_CTL_PAD_x).
* - Each pad can have but not necessarily does have an input routing register
* (IOMUXC_x_SELECT_INPUT)
*
* The three register sets do not have a fixed offset to each other,
* hence we order this table by pad control registers (which all pads
* have) and put the optional i/o routing registers into additional
* fields.
*
* The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
*
* IOMUX/PAD Bit field definitions
*
* MUX_CTRL_OFS: 0..11 (12)
* PAD_CTRL_OFS: 12..23 (12)
* SEL_INPUT_OFS: 24..35 (12)
* MUX_MODE + SION: 36..40 (5)
* PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
* SEL_INP: 59..62 (4)
* reserved: 63 (1)
*/
typedef u64 iomux_v3_cfg_t;
#define MUX_CTRL_OFS_SHIFT 0
#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
#define MUX_PAD_CTRL_OFS_SHIFT 12
#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
MUX_PAD_CTRL_OFS_SHIFT)
#define MUX_SEL_INPUT_OFS_SHIFT 24
#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
MUX_SEL_INPUT_OFS_SHIFT)
#define MUX_MODE_SHIFT 36
#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
#define MUX_PAD_CTRL_SHIFT 41
#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
#define MUX_SEL_INPUT_SHIFT 59
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
MUX_MODE_SHIFT)
#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
sel_input, pad_ctrl) \
(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
MUX_PAD_CTRL(pad))
#define __NA_ 0x000
#define NO_MUX_I 0
#define NO_PAD_I 0
#define NO_PAD_CTRL (1 << 17)
#ifdef CONFIG_MX7
#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
#define IOMUX_CONFIG_LPSR 0x8
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0)
#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0)
#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0)
#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0)
#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0)
#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0)
#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0)
#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0)
#define PAD_CTL_SRE_FAST (0 << 2)
#define PAD_CTL_SRE_SLOW (0x1 << 2)
#define PAD_CTL_HYS (0x1 << 3)
#define PAD_CTL_PUE (0x1 << 4)
#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE)
#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE)
#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE)
#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE)
#else
#ifdef CONFIG_MX6
#define PAD_CTL_HYS (1 << 16)
#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE)
#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)
#define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE)
#define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE)
#define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE)
#define PAD_CTL_PKE (1 << 12)
#define PAD_CTL_ODE (1 << 11)
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
#define PAD_CTL_SPEED_LOW (0 << 6)
#else
#define PAD_CTL_SPEED_LOW (1 << 6)
#endif
#define PAD_CTL_SPEED_MED (2 << 6)
#define PAD_CTL_SPEED_HIGH (3 << 6)
#define PAD_CTL_DSE_DISABLE (0 << 3)
#define PAD_CTL_DSE_240ohm (1 << 3)
#define PAD_CTL_DSE_120ohm (2 << 3)
#define PAD_CTL_DSE_80ohm (3 << 3)
#define PAD_CTL_DSE_60ohm (4 << 3)
#define PAD_CTL_DSE_48ohm (5 << 3)
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
#if defined CONFIG_MX6SL
#define PAD_CTL_LVE (1 << 1)
#define PAD_CTL_LVE_BIT (1 << 22)
#endif
#elif defined(CONFIG_VF610)
#define PAD_MUX_MODE_SHIFT 20
#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
#define PAD_CTL_SPEED_MED (1 << 12)
#define PAD_CTL_SPEED_HIGH (3 << 12)
#define PAD_CTL_SRE (1 << 11)
#define PAD_CTL_ODE (1 << 10)
#define PAD_CTL_DSE_150ohm (1 << 6)
#define PAD_CTL_DSE_50ohm (3 << 6)
#define PAD_CTL_DSE_25ohm (6 << 6)
#define PAD_CTL_DSE_20ohm (7 << 6)
#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PKE (1 << 3)
#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
#define PAD_CTL_OBE_ENABLE (1 << 1)
#define PAD_CTL_IBE_ENABLE (1 << 0)
#else
#define PAD_CTL_DVS (1 << 13)
#define PAD_CTL_INPUT_DDR (1 << 9)
#define PAD_CTL_HYS (1 << 8)
#define PAD_CTL_PKE (1 << 7)
#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
#define PAD_CTL_ODE (1 << 3)
#define PAD_CTL_DSE_LOW (0 << 1)
#define PAD_CTL_DSE_MED (1 << 1)
#define PAD_CTL_DSE_HIGH (2 << 1)
#define PAD_CTL_DSE_MAX (3 << 1)
#endif
#define PAD_CTL_SRE_SLOW (0 << 0)
#define PAD_CTL_SRE_FAST (1 << 0)
#endif
#define IOMUX_CONFIG_SION 0x10
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_SHIFT 5
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
/*
* Set bits for general purpose registers
*/
void imx_iomux_set_gpr_register(int group, int start_bit,
int num_bits, int value);
#ifdef CONFIG_IOMUX_SHARE_CONF_REG
void imx_iomux_gpio_set_direction(unsigned int gpio,
unsigned int direction);
void imx_iomux_gpio_get_function(unsigned int gpio,
u32 *gpio_state);
#endif
/* macros for declaring and using pinmux array */
#if defined(CONFIG_MX6QDL)
#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
#define SETUP_IOMUX_PAD(def) \
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \
imx_iomux_v3_setup_pad(MX6Q_##def); \
} else { \
imx_iomux_v3_setup_pad(MX6DL_##def); \
}
#define SETUP_IOMUX_PADS(x) \
imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
#define IOMUX_PADS(x) MX6Q_##x
#define SETUP_IOMUX_PAD(def) \
imx_iomux_v3_setup_pad(MX6Q_##def);
#define SETUP_IOMUX_PADS(x) \
imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
#else
#define IOMUX_PADS(x) MX6DL_##x
#define SETUP_IOMUX_PAD(def) \
imx_iomux_v3_setup_pad(MX6DL_##def);
#define SETUP_IOMUX_PADS(x) \
imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
#endif
#endif /* __MACH_IOMUX_V3_H__*/

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u-boot/arch/arm/include/asm/imx-common/mx5_video.h Normal file
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/*
* Copyright (C) 2012
* Anatolij Gustschin, DENX Software Engineering, <agust@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX5_VIDEO_H
#define __MX5_VIDEO_H
#ifdef CONFIG_VIDEO
void lcd_enable(void);
void setup_iomux_lcd(void);
#else
static inline void lcd_enable(void) { }
static inline void setup_iomux_lcd(void) { }
#endif
#endif

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u-boot/arch/arm/include/asm/imx-common/mxc_i2c.h Normal file
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/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MXC_MXC_I2C_H__
#define __ASM_ARCH_MXC_MXC_I2C_H__
#include <asm-generic/gpio.h>
#include <asm/imx-common/iomux-v3.h>
struct i2c_pin_ctrl {
iomux_v3_cfg_t i2c_mode;
iomux_v3_cfg_t gpio_mode;
unsigned char gp;
unsigned char spare;
};
struct i2c_pads_info {
struct i2c_pin_ctrl scl;
struct i2c_pin_ctrl sda;
};
/*
* Information about i2c controller
* struct mxc_i2c_bus - information about the i2c[x] bus
* @index: i2c bus index
* @base: Address of I2C bus controller
* @driver_data: Flags for different platforms, such as I2C_QUIRK_FLAG.
* @speed: Speed of I2C bus
* @pads_info: pinctrl info for this i2c bus, will be used when pinctrl is ok.
* The following two is only to be compatible with non-DM part.
* @idle_bus_fn: function to force bus idle
* @idle_bus_data: parameter for idle_bus_fun
* For DM:
* bus: The device structure for i2c bus controller
* scl-gpio: specify the gpio related to SCL pin
* sda-gpio: specify the gpio related to SDA pin
*/
struct mxc_i2c_bus {
/*
* board file can use this index to locate which i2c_pads_info is for
* i2c_idle_bus. When pinmux is implement, this entry can be
* discarded. Here we do not use dev->seq, because we do not want to
* export device to board file.
*/
int index;
ulong base;
ulong driver_data;
int speed;
struct i2c_pads_info *pads_info;
#ifndef CONFIG_DM_I2C
int (*idle_bus_fn)(void *p);
void *idle_bus_data;
#else
struct udevice *bus;
/* Use gpio to force bus idle when bus state is abnormal */
struct gpio_desc scl_gpio;
struct gpio_desc sda_gpio;
#endif
};
#if defined(CONFIG_MX6QDL)
#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
struct i2c_pads_info mx6q_##name = { \
.scl = { \
.i2c_mode = MX6Q_##scl_i2c, \
.gpio_mode = MX6Q_##scl_gpio, \
.gp = scl_gp, \
}, \
.sda = { \
.i2c_mode = MX6Q_##sda_i2c, \
.gpio_mode = MX6Q_##sda_gpio, \
.gp = sda_gp, \
} \
}; \
struct i2c_pads_info mx6s_##name = { \
.scl = { \
.i2c_mode = MX6DL_##scl_i2c, \
.gpio_mode = MX6DL_##scl_gpio, \
.gp = scl_gp, \
}, \
.sda = { \
.i2c_mode = MX6DL_##sda_i2c, \
.gpio_mode = MX6DL_##sda_gpio, \
.gp = sda_gp, \
} \
};
#define I2C_PADS_INFO(name) \
(is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \
&mx6q_##name : &mx6s_##name
#endif
int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
struct i2c_pads_info *p);
void bus_i2c_init(int index, int speed, int slave_addr,
int (*idle_bus_fn)(void *p), void *p);
int force_idle_bus(void *priv);
int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus);
#endif

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u-boot/arch/arm/include/asm/imx-common/rdc-sema.h Normal file
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/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __RDC_SEMA_H__
#define __RDC_SEMA_H__
/*
* rdc_peri_cfg_t and rdc_ma_cft_t use the same layout.
*
* [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]
* d3 d2 d1 d0 | master id | peri id
* d[x] means domain[x], x can be [3 - 0].
*/
typedef u32 rdc_peri_cfg_t;
typedef u32 rdc_ma_cfg_t;
#define RDC_PERI_SHIFT 0
#define RDC_PERI_MASK 0xFF
#define RDC_DOMAIN_SHIFT_BASE 16
#define RDC_DOMAIN_MASK 0xFF0000
#define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
#define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
#define RDC_MASTER_SHIFT 8
#define RDC_MASTER_MASK 0xFF00
#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \
(domain_id << RDC_DOMAIN_SHIFT_BASE))
/* The Following macro definitions are common to i.MX6SX and i.MX7D */
#define SEMA_GATES_NUM 64
#define RDC_MDA_DID_SHIFT 0
#define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT)
#define RDC_MDA_LCK_SHIFT 31
#define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT)
#define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1)
#define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain))
#define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain))
#define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain))
#define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \
RDC_PDAP_DR_MASK(domain))
#define RDC_PDAP_SREQ_SHIFT 30
#define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT)
#define RDC_PDAP_LCK_SHIFT 31
#define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT)
#define RDC_MRSA_SADR_SHIFT 7
#define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT)
#define RDC_MREA_EADR_SHIFT 7
#define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT)
#define RDC_MRC_DW_SHIFT(domain) (domain)
#define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain))
#define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain))
#define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain))
#define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \
RDC_MRC_DR_MASK(domain))
#define RDC_MRC_ENA_SHIFT 30
#define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT)
#define RDC_MRC_LCK_SHIFT 31
#define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT)
#define RDC_MRVS_VDID_SHIFT 0
#define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT)
#define RDC_MRVS_AD_SHIFT 4
#define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT)
#define RDC_MRVS_VADDR_SHIFT 5
#define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT)
#define RDC_SEMA_GATE_GTFSM_SHIFT 0
#define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT)
#define RDC_SEMA_GATE_LDOM_SHIFT 5
#define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT)
#define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0
#define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT)
#define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2
#define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT)
#define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4
#define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT)
#define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8
#define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)
int imx_rdc_check_permission(int per_id, int dom_id);
int imx_rdc_sema_lock(int per_id);
int imx_rdc_sema_unlock(int per_id);
int imx_rdc_setup_peri(rdc_peri_cfg_t p);
int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
unsigned count);
int imx_rdc_setup_ma(rdc_ma_cfg_t p);
int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);
#endif /* __RDC_SEMA_H__*/

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u-boot/arch/arm/include/asm/imx-common/regs-apbh.h Normal file
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/*
* Freescale i.MX28 APBH Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __REGS_APBH_H__
#define __REGS_APBH_H__
#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
#if defined(CONFIG_MX23)
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
mxs_reg_32(hw_apbh_ctrl2)
mxs_reg_32(hw_apbh_channel_ctrl)
union {
struct {
mxs_reg_32(hw_apbh_ch_curcmdar)
mxs_reg_32(hw_apbh_ch_nxtcmdar)
mxs_reg_32(hw_apbh_ch_cmd)
mxs_reg_32(hw_apbh_ch_bar)
mxs_reg_32(hw_apbh_ch_sema)
mxs_reg_32(hw_apbh_ch_debug1)
mxs_reg_32(hw_apbh_ch_debug2)
} ch[8];
struct {
mxs_reg_32(hw_apbh_ch0_curcmdar)
mxs_reg_32(hw_apbh_ch0_nxtcmdar)
mxs_reg_32(hw_apbh_ch0_cmd)
mxs_reg_32(hw_apbh_ch0_bar)
mxs_reg_32(hw_apbh_ch0_sema)
mxs_reg_32(hw_apbh_ch0_debug1)
mxs_reg_32(hw_apbh_ch0_debug2)
mxs_reg_32(hw_apbh_ch1_curcmdar)
mxs_reg_32(hw_apbh_ch1_nxtcmdar)
mxs_reg_32(hw_apbh_ch1_cmd)
mxs_reg_32(hw_apbh_ch1_bar)
mxs_reg_32(hw_apbh_ch1_sema)
mxs_reg_32(hw_apbh_ch1_debug1)
mxs_reg_32(hw_apbh_ch1_debug2)
mxs_reg_32(hw_apbh_ch2_curcmdar)
mxs_reg_32(hw_apbh_ch2_nxtcmdar)
mxs_reg_32(hw_apbh_ch2_cmd)
mxs_reg_32(hw_apbh_ch2_bar)
mxs_reg_32(hw_apbh_ch2_sema)
mxs_reg_32(hw_apbh_ch2_debug1)
mxs_reg_32(hw_apbh_ch2_debug2)
mxs_reg_32(hw_apbh_ch3_curcmdar)
mxs_reg_32(hw_apbh_ch3_nxtcmdar)
mxs_reg_32(hw_apbh_ch3_cmd)
mxs_reg_32(hw_apbh_ch3_bar)
mxs_reg_32(hw_apbh_ch3_sema)
mxs_reg_32(hw_apbh_ch3_debug1)
mxs_reg_32(hw_apbh_ch3_debug2)
mxs_reg_32(hw_apbh_ch4_curcmdar)
mxs_reg_32(hw_apbh_ch4_nxtcmdar)
mxs_reg_32(hw_apbh_ch4_cmd)
mxs_reg_32(hw_apbh_ch4_bar)
mxs_reg_32(hw_apbh_ch4_sema)
mxs_reg_32(hw_apbh_ch4_debug1)
mxs_reg_32(hw_apbh_ch4_debug2)
mxs_reg_32(hw_apbh_ch5_curcmdar)
mxs_reg_32(hw_apbh_ch5_nxtcmdar)
mxs_reg_32(hw_apbh_ch5_cmd)
mxs_reg_32(hw_apbh_ch5_bar)
mxs_reg_32(hw_apbh_ch5_sema)
mxs_reg_32(hw_apbh_ch5_debug1)
mxs_reg_32(hw_apbh_ch5_debug2)
mxs_reg_32(hw_apbh_ch6_curcmdar)
mxs_reg_32(hw_apbh_ch6_nxtcmdar)
mxs_reg_32(hw_apbh_ch6_cmd)
mxs_reg_32(hw_apbh_ch6_bar)
mxs_reg_32(hw_apbh_ch6_sema)
mxs_reg_32(hw_apbh_ch6_debug1)
mxs_reg_32(hw_apbh_ch6_debug2)
mxs_reg_32(hw_apbh_ch7_curcmdar)
mxs_reg_32(hw_apbh_ch7_nxtcmdar)
mxs_reg_32(hw_apbh_ch7_cmd)
mxs_reg_32(hw_apbh_ch7_bar)
mxs_reg_32(hw_apbh_ch7_sema)
mxs_reg_32(hw_apbh_ch7_debug1)
mxs_reg_32(hw_apbh_ch7_debug2)
};
};
mxs_reg_32(hw_apbh_version)
};
#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
mxs_reg_32(hw_apbh_ctrl2)
mxs_reg_32(hw_apbh_channel_ctrl)
mxs_reg_32(hw_apbh_devsel)
mxs_reg_32(hw_apbh_dma_burst_size)
mxs_reg_32(hw_apbh_debug)
uint32_t reserved[36];
union {
struct {
mxs_reg_32(hw_apbh_ch_curcmdar)
mxs_reg_32(hw_apbh_ch_nxtcmdar)
mxs_reg_32(hw_apbh_ch_cmd)
mxs_reg_32(hw_apbh_ch_bar)
mxs_reg_32(hw_apbh_ch_sema)
mxs_reg_32(hw_apbh_ch_debug1)
mxs_reg_32(hw_apbh_ch_debug2)
} ch[16];
struct {
mxs_reg_32(hw_apbh_ch0_curcmdar)
mxs_reg_32(hw_apbh_ch0_nxtcmdar)
mxs_reg_32(hw_apbh_ch0_cmd)
mxs_reg_32(hw_apbh_ch0_bar)
mxs_reg_32(hw_apbh_ch0_sema)
mxs_reg_32(hw_apbh_ch0_debug1)
mxs_reg_32(hw_apbh_ch0_debug2)
mxs_reg_32(hw_apbh_ch1_curcmdar)
mxs_reg_32(hw_apbh_ch1_nxtcmdar)
mxs_reg_32(hw_apbh_ch1_cmd)
mxs_reg_32(hw_apbh_ch1_bar)
mxs_reg_32(hw_apbh_ch1_sema)
mxs_reg_32(hw_apbh_ch1_debug1)
mxs_reg_32(hw_apbh_ch1_debug2)
mxs_reg_32(hw_apbh_ch2_curcmdar)
mxs_reg_32(hw_apbh_ch2_nxtcmdar)
mxs_reg_32(hw_apbh_ch2_cmd)
mxs_reg_32(hw_apbh_ch2_bar)
mxs_reg_32(hw_apbh_ch2_sema)
mxs_reg_32(hw_apbh_ch2_debug1)
mxs_reg_32(hw_apbh_ch2_debug2)
mxs_reg_32(hw_apbh_ch3_curcmdar)
mxs_reg_32(hw_apbh_ch3_nxtcmdar)
mxs_reg_32(hw_apbh_ch3_cmd)
mxs_reg_32(hw_apbh_ch3_bar)
mxs_reg_32(hw_apbh_ch3_sema)
mxs_reg_32(hw_apbh_ch3_debug1)
mxs_reg_32(hw_apbh_ch3_debug2)
mxs_reg_32(hw_apbh_ch4_curcmdar)
mxs_reg_32(hw_apbh_ch4_nxtcmdar)
mxs_reg_32(hw_apbh_ch4_cmd)
mxs_reg_32(hw_apbh_ch4_bar)
mxs_reg_32(hw_apbh_ch4_sema)
mxs_reg_32(hw_apbh_ch4_debug1)
mxs_reg_32(hw_apbh_ch4_debug2)
mxs_reg_32(hw_apbh_ch5_curcmdar)
mxs_reg_32(hw_apbh_ch5_nxtcmdar)
mxs_reg_32(hw_apbh_ch5_cmd)
mxs_reg_32(hw_apbh_ch5_bar)
mxs_reg_32(hw_apbh_ch5_sema)
mxs_reg_32(hw_apbh_ch5_debug1)
mxs_reg_32(hw_apbh_ch5_debug2)
mxs_reg_32(hw_apbh_ch6_curcmdar)
mxs_reg_32(hw_apbh_ch6_nxtcmdar)
mxs_reg_32(hw_apbh_ch6_cmd)
mxs_reg_32(hw_apbh_ch6_bar)
mxs_reg_32(hw_apbh_ch6_sema)
mxs_reg_32(hw_apbh_ch6_debug1)
mxs_reg_32(hw_apbh_ch6_debug2)
mxs_reg_32(hw_apbh_ch7_curcmdar)
mxs_reg_32(hw_apbh_ch7_nxtcmdar)
mxs_reg_32(hw_apbh_ch7_cmd)
mxs_reg_32(hw_apbh_ch7_bar)
mxs_reg_32(hw_apbh_ch7_sema)
mxs_reg_32(hw_apbh_ch7_debug1)
mxs_reg_32(hw_apbh_ch7_debug2)
mxs_reg_32(hw_apbh_ch8_curcmdar)
mxs_reg_32(hw_apbh_ch8_nxtcmdar)
mxs_reg_32(hw_apbh_ch8_cmd)
mxs_reg_32(hw_apbh_ch8_bar)
mxs_reg_32(hw_apbh_ch8_sema)
mxs_reg_32(hw_apbh_ch8_debug1)
mxs_reg_32(hw_apbh_ch8_debug2)
mxs_reg_32(hw_apbh_ch9_curcmdar)
mxs_reg_32(hw_apbh_ch9_nxtcmdar)
mxs_reg_32(hw_apbh_ch9_cmd)
mxs_reg_32(hw_apbh_ch9_bar)
mxs_reg_32(hw_apbh_ch9_sema)
mxs_reg_32(hw_apbh_ch9_debug1)
mxs_reg_32(hw_apbh_ch9_debug2)
mxs_reg_32(hw_apbh_ch10_curcmdar)
mxs_reg_32(hw_apbh_ch10_nxtcmdar)
mxs_reg_32(hw_apbh_ch10_cmd)
mxs_reg_32(hw_apbh_ch10_bar)
mxs_reg_32(hw_apbh_ch10_sema)
mxs_reg_32(hw_apbh_ch10_debug1)
mxs_reg_32(hw_apbh_ch10_debug2)
mxs_reg_32(hw_apbh_ch11_curcmdar)
mxs_reg_32(hw_apbh_ch11_nxtcmdar)
mxs_reg_32(hw_apbh_ch11_cmd)
mxs_reg_32(hw_apbh_ch11_bar)
mxs_reg_32(hw_apbh_ch11_sema)
mxs_reg_32(hw_apbh_ch11_debug1)
mxs_reg_32(hw_apbh_ch11_debug2)
mxs_reg_32(hw_apbh_ch12_curcmdar)
mxs_reg_32(hw_apbh_ch12_nxtcmdar)
mxs_reg_32(hw_apbh_ch12_cmd)
mxs_reg_32(hw_apbh_ch12_bar)
mxs_reg_32(hw_apbh_ch12_sema)
mxs_reg_32(hw_apbh_ch12_debug1)
mxs_reg_32(hw_apbh_ch12_debug2)
mxs_reg_32(hw_apbh_ch13_curcmdar)
mxs_reg_32(hw_apbh_ch13_nxtcmdar)
mxs_reg_32(hw_apbh_ch13_cmd)
mxs_reg_32(hw_apbh_ch13_bar)
mxs_reg_32(hw_apbh_ch13_sema)
mxs_reg_32(hw_apbh_ch13_debug1)
mxs_reg_32(hw_apbh_ch13_debug2)
mxs_reg_32(hw_apbh_ch14_curcmdar)
mxs_reg_32(hw_apbh_ch14_nxtcmdar)
mxs_reg_32(hw_apbh_ch14_cmd)
mxs_reg_32(hw_apbh_ch14_bar)
mxs_reg_32(hw_apbh_ch14_sema)
mxs_reg_32(hw_apbh_ch14_debug1)
mxs_reg_32(hw_apbh_ch14_debug2)
mxs_reg_32(hw_apbh_ch15_curcmdar)
mxs_reg_32(hw_apbh_ch15_nxtcmdar)
mxs_reg_32(hw_apbh_ch15_cmd)
mxs_reg_32(hw_apbh_ch15_bar)
mxs_reg_32(hw_apbh_ch15_sema)
mxs_reg_32(hw_apbh_ch15_debug1)
mxs_reg_32(hw_apbh_ch15_debug2)
};
};
mxs_reg_32(hw_apbh_version)
};
#endif
#endif
#define APBH_CTRL0_SFTRST (1 << 31)
#define APBH_CTRL0_CLKGATE (1 << 30)
#define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
#define APBH_CTRL0_APB_BURST_EN (1 << 28)
#if defined(CONFIG_MX23)
#define APBH_CTRL0_RSVD0_MASK (0xf << 24)
#define APBH_CTRL0_RSVD0_OFFSET 24
#define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16)
#define APBH_CTRL0_RESET_CHANNEL_OFFSET 16
#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8)
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80
#elif defined(CONFIG_MX28)
#define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
#define APBH_CTRL0_RSVD0_OFFSET 16
#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100
#endif
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16)
#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16
#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0)
#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31)
#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30)
#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29)
#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28)
#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27)
#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26)
#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25)
#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24)
#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23)
#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22)
#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21)
#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20)
#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19)
#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18)
#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17)
#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16)
#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15)
#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14)
#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13)
#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12)
#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11)
#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10)
#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9)
#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8)
#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7)
#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6)
#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5)
#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4)
#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3)
#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2)
#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
#if defined(CONFIG_MX28)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16)
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#endif
#if defined(CONFIG_MX23)
#define APBH_DEVSEL_CH7_MASK (0xf << 28)
#define APBH_DEVSEL_CH7_OFFSET 28
#define APBH_DEVSEL_CH6_MASK (0xf << 24)
#define APBH_DEVSEL_CH6_OFFSET 24
#define APBH_DEVSEL_CH5_MASK (0xf << 20)
#define APBH_DEVSEL_CH5_OFFSET 20
#define APBH_DEVSEL_CH4_MASK (0xf << 16)
#define APBH_DEVSEL_CH4_OFFSET 16
#define APBH_DEVSEL_CH3_MASK (0xf << 12)
#define APBH_DEVSEL_CH3_OFFSET 12
#define APBH_DEVSEL_CH2_MASK (0xf << 8)
#define APBH_DEVSEL_CH2_OFFSET 8
#define APBH_DEVSEL_CH1_MASK (0xf << 4)
#define APBH_DEVSEL_CH1_OFFSET 4
#define APBH_DEVSEL_CH0_MASK (0xf << 0)
#define APBH_DEVSEL_CH0_OFFSET 0
#elif defined(CONFIG_MX28)
#define APBH_DEVSEL_CH15_MASK (0x3 << 30)
#define APBH_DEVSEL_CH15_OFFSET 30
#define APBH_DEVSEL_CH14_MASK (0x3 << 28)
#define APBH_DEVSEL_CH14_OFFSET 28
#define APBH_DEVSEL_CH13_MASK (0x3 << 26)
#define APBH_DEVSEL_CH13_OFFSET 26
#define APBH_DEVSEL_CH12_MASK (0x3 << 24)
#define APBH_DEVSEL_CH12_OFFSET 24
#define APBH_DEVSEL_CH11_MASK (0x3 << 22)
#define APBH_DEVSEL_CH11_OFFSET 22
#define APBH_DEVSEL_CH10_MASK (0x3 << 20)
#define APBH_DEVSEL_CH10_OFFSET 20
#define APBH_DEVSEL_CH9_MASK (0x3 << 18)
#define APBH_DEVSEL_CH9_OFFSET 18
#define APBH_DEVSEL_CH8_MASK (0x3 << 16)
#define APBH_DEVSEL_CH8_OFFSET 16
#define APBH_DEVSEL_CH7_MASK (0x3 << 14)
#define APBH_DEVSEL_CH7_OFFSET 14
#define APBH_DEVSEL_CH6_MASK (0x3 << 12)
#define APBH_DEVSEL_CH6_OFFSET 12
#define APBH_DEVSEL_CH5_MASK (0x3 << 10)
#define APBH_DEVSEL_CH5_OFFSET 10
#define APBH_DEVSEL_CH4_MASK (0x3 << 8)
#define APBH_DEVSEL_CH4_OFFSET 8
#define APBH_DEVSEL_CH3_MASK (0x3 << 6)
#define APBH_DEVSEL_CH3_OFFSET 6
#define APBH_DEVSEL_CH2_MASK (0x3 << 4)
#define APBH_DEVSEL_CH2_OFFSET 4
#define APBH_DEVSEL_CH1_MASK (0x3 << 2)
#define APBH_DEVSEL_CH1_OFFSET 2
#define APBH_DEVSEL_CH0_MASK (0x3 << 0)
#define APBH_DEVSEL_CH0_OFFSET 0
#endif
#if defined(CONFIG_MX28)
#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28
#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26)
#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26
#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24)
#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24
#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22)
#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22
#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20)
#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20
#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18)
#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18
#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16)
#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16
#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16)
#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16)
#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16)
#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14)
#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14
#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12)
#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12
#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10)
#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10
#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8)
#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8
#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6)
#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6
#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6)
#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6)
#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6)
#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4)
#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4
#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4)
#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4)
#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4)
#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2)
#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2
#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2)
#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2)
#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2)
#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3
#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0
#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0
#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1
#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
#endif
#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff
#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0
#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16)
#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16
#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12)
#define APBH_CHn_CMD_CMDWORDS_OFFSET 12
#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8)
#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7)
#define APBH_CHn_CMD_SEMAPHORE (1 << 6)
#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5)
#define APBH_CHn_CMD_NANDLOCK (1 << 4)
#define APBH_CHn_CMD_IRQONCMPLT (1 << 3)
#define APBH_CHn_CMD_CHAIN (1 << 2)
#define APBH_CHn_CMD_COMMAND_MASK 0x3
#define APBH_CHn_CMD_COMMAND_OFFSET 0
#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0
#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1
#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2
#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3
#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff
#define APBH_CHn_BAR_ADDRESS_OFFSET 0
#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24)
#define APBH_CHn_SEMA_RSVD2_OFFSET 24
#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16)
#define APBH_CHn_SEMA_PHORE_OFFSET 16
#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8)
#define APBH_CHn_SEMA_RSVD1_OFFSET 8
#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0)
#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0
#define APBH_CHn_DEBUG1_REQ (1 << 31)
#define APBH_CHn_DEBUG1_BURST (1 << 30)
#define APBH_CHn_DEBUG1_KICK (1 << 29)
#define APBH_CHn_DEBUG1_END (1 << 28)
#define APBH_CHn_DEBUG1_SENSE (1 << 27)
#define APBH_CHn_DEBUG1_READY (1 << 26)
#define APBH_CHn_DEBUG1_LOCK (1 << 25)
#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24)
#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23)
#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22)
#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21)
#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20)
#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5)
#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5
#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f
#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0
#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00
#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01
#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02
#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03
#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04
#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05
#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06
#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07
#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08
#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09
#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c
#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d
#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e
#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f
#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14
#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15
#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c
#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d
#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e
#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f
#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16)
#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16
#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff
#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0
#define APBH_VERSION_MAJOR_MASK (0xff << 24)
#define APBH_VERSION_MAJOR_OFFSET 24
#define APBH_VERSION_MINOR_MASK (0xff << 16)
#define APBH_VERSION_MINOR_OFFSET 16
#define APBH_VERSION_STEP_MASK 0xffff
#define APBH_VERSION_STEP_OFFSET 0
#endif /* __REGS_APBH_H__ */

229
u-boot/arch/arm/include/asm/imx-common/regs-bch.h Normal file
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@@ -0,0 +1,229 @@
/*
* Freescale i.MX28 BCH Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX28_REGS_BCH_H__
#define __MX28_REGS_BCH_H__
#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_bch_regs {
mxs_reg_32(hw_bch_ctrl)
mxs_reg_32(hw_bch_status0)
mxs_reg_32(hw_bch_mode)
mxs_reg_32(hw_bch_encodeptr)
mxs_reg_32(hw_bch_dataptr)
mxs_reg_32(hw_bch_metaptr)
uint32_t reserved[4];
mxs_reg_32(hw_bch_layoutselect)
mxs_reg_32(hw_bch_flash0layout0)
mxs_reg_32(hw_bch_flash0layout1)
mxs_reg_32(hw_bch_flash1layout0)
mxs_reg_32(hw_bch_flash1layout1)
mxs_reg_32(hw_bch_flash2layout0)
mxs_reg_32(hw_bch_flash2layout1)
mxs_reg_32(hw_bch_flash3layout0)
mxs_reg_32(hw_bch_flash3layout1)
mxs_reg_32(hw_bch_dbgkesread)
mxs_reg_32(hw_bch_dbgcsferead)
mxs_reg_32(hw_bch_dbgsyndegread)
mxs_reg_32(hw_bch_dbgahbmread)
mxs_reg_32(hw_bch_blockname)
mxs_reg_32(hw_bch_version)
};
#endif
#define BCH_CTRL_SFTRST (1 << 31)
#define BCH_CTRL_CLKGATE (1 << 30)
#define BCH_CTRL_DEBUGSYNDROME (1 << 22)
#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18)
#define BCH_CTRL_M2M_LAYOUT_OFFSET 18
#define BCH_CTRL_M2M_ENCODE (1 << 17)
#define BCH_CTRL_M2M_ENABLE (1 << 16)
#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10)
#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8)
#define BCH_CTRL_BM_ERROR_IRQ (1 << 3)
#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2)
#define BCH_CTRL_COMPLETE_IRQ (1 << 0)
#define BCH_STATUS0_HANDLE_MASK (0xfff << 20)
#define BCH_STATUS0_HANDLE_OFFSET 20
#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16)
#define BCH_STATUS0_COMPLETED_CE_OFFSET 16
#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8)
#define BCH_STATUS0_STATUS_BLK0_OFFSET 8
#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8)
#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8)
#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8)
#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8)
#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8)
#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8)
#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8)
#define BCH_STATUS0_ALLONES (1 << 4)
#define BCH_STATUS0_CORRECTED (1 << 3)
#define BCH_STATUS0_UNCORRECTABLE (1 << 2)
#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff
#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0
#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff
#define BCH_ENCODEPTR_ADDR_OFFSET 0
#define BCH_DATAPTR_ADDR_MASK 0xffffffff
#define BCH_DATAPTR_ADDR_OFFSET 0
#define BCH_METAPTR_ADDR_MASK 0xffffffff
#define BCH_METAPTR_ADDR_OFFSET 0
#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30)
#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30
#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28)
#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28
#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26)
#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26
#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24)
#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24
#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22)
#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22
#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20)
#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20
#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18)
#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18
#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16)
#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16
#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14)
#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14
#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12)
#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12
#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10)
#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10
#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8)
#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8
#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6)
#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6
#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4)
#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4
#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2)
#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2
#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0)
#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0
#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24)
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
#else
#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
#endif
#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12)
#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10)
#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10
#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff
#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
#else
#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
#endif
#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12)
#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10)
#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10
#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff
#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27)
#define BCH_DEBUG0_RSVD1_OFFSET 27
#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26)
#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25)
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16)
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16)
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16)
#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15)
#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14)
#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13)
#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12)
#define BCH_DEBUG0_KES_STANDALONE (1 << 11)
#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10)
#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9)
#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8)
#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6)
#define BCH_DEBUG0_RSVD0_OFFSET 6
#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f
#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0
#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff
#define BCH_DBGKESREAD_VALUES_OFFSET 0
#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff
#define BCH_DBGCSFEREAD_VALUES_OFFSET 0
#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff
#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0
#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff
#define BCH_DBGAHBMREAD_VALUES_OFFSET 0
#define BCH_BLOCKNAME_NAME_MASK 0xffffffff
#define BCH_BLOCKNAME_NAME_OFFSET 0
#define BCH_VERSION_MAJOR_MASK (0xff << 24)
#define BCH_VERSION_MAJOR_OFFSET 24
#define BCH_VERSION_MINOR_MASK (0xff << 16)
#define BCH_VERSION_MINOR_OFFSET 16
#define BCH_VERSION_STEP_MASK 0xffff
#define BCH_VERSION_STEP_OFFSET 0
#endif /* __MX28_REGS_BCH_H__ */

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/*
* Freescale i.MXS Register Accessors
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MXS_REGS_COMMON_H__
#define __MXS_REGS_COMMON_H__
#include <linux/types.h>
/*
* The i.MXS has interesting feature when it comes to register access. There
* are four kinds of access to one particular register. Those are:
*
* 1) Common read/write access. To use this mode, just write to the address of
* the register.
* 2) Set bits only access. To set bits, write which bits you want to set to the
* address of the register + 0x4.
* 3) Clear bits only access. To clear bits, write which bits you want to clear
* to the address of the register + 0x8.
* 4) Toggle bits only access. To toggle bits, write which bits you want to
* toggle to the address of the register + 0xc.
*
* IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
* can be set/cleared by pure write as in access type 1, some need to be
* explicitly set/cleared by using access type 2-3.
*
* The following macros and structures allow the user to either access the
* register in all aforementioned modes (by accessing reg_name, reg_name_set,
* reg_name_clr, reg_name_tog) or pass the register structure further into
* various functions with correct type information (by accessing reg_name_reg).
*
*/
#define __mxs_reg_8(name) \
uint8_t name[4]; \
uint8_t name##_set[4]; \
uint8_t name##_clr[4]; \
uint8_t name##_tog[4]; \
#define __mxs_reg_32(name) \
uint32_t name; \
uint32_t name##_set; \
uint32_t name##_clr; \
uint32_t name##_tog;
struct mxs_register_8 {
__mxs_reg_8(reg)
};
struct mxs_register_32 {
__mxs_reg_32(reg)
};
#define mxs_reg_8(name) \
union { \
struct { __mxs_reg_8(name) }; \
struct mxs_register_8 name##_reg; \
};
#define mxs_reg_32(name) \
union { \
struct { __mxs_reg_32(name) }; \
struct mxs_register_32 name##_reg; \
};
#endif /* __MXS_REGS_COMMON_H__ */

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/*
* Freescale i.MX28 GPMI Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX28_REGS_GPMI_H__
#define __MX28_REGS_GPMI_H__
#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_gpmi_regs {
mxs_reg_32(hw_gpmi_ctrl0)
mxs_reg_32(hw_gpmi_compare)
mxs_reg_32(hw_gpmi_eccctrl)
mxs_reg_32(hw_gpmi_ecccount)
mxs_reg_32(hw_gpmi_payload)
mxs_reg_32(hw_gpmi_auxiliary)
mxs_reg_32(hw_gpmi_ctrl1)
mxs_reg_32(hw_gpmi_timing0)
mxs_reg_32(hw_gpmi_timing1)
uint32_t reserved[4];
mxs_reg_32(hw_gpmi_data)
mxs_reg_32(hw_gpmi_stat)
mxs_reg_32(hw_gpmi_debug)
mxs_reg_32(hw_gpmi_version)
};
#endif
#define GPMI_CTRL0_SFTRST (1 << 31)
#define GPMI_CTRL0_CLKGATE (1 << 30)
#define GPMI_CTRL0_RUN (1 << 29)
#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
#define GPMI_CTRL0_LOCK_CS (1 << 27)
#define GPMI_CTRL0_UDMA (1 << 26)
#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24)
#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24
#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24)
#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24)
#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24)
#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24)
#define GPMI_CTRL0_WORD_LENGTH (1 << 23)
#define GPMI_CTRL0_CS_MASK (0x7 << 20)
#define GPMI_CTRL0_CS_OFFSET 20
#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17)
#define GPMI_CTRL0_ADDRESS_OFFSET 17
#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17)
#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17)
#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17)
#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff
#define GPMI_CTRL0_XFER_COUNT_OFFSET 0
#define GPMI_COMPARE_MASK_MASK (0xffff << 16)
#define GPMI_COMPARE_MASK_OFFSET 16
#define GPMI_COMPARE_REFERENCE_MASK 0xffff
#define GPMI_COMPARE_REFERENCE_OFFSET 0
#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16)
#define GPMI_ECCCTRL_HANDLE_OFFSET 16
#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13)
#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13
#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13)
#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13)
#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff
#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0
#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100
#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff
#define GPMI_ECCCOUNT_COUNT_MASK 0xffff
#define GPMI_ECCCOUNT_COUNT_OFFSET 0
#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2)
#define GPMI_PAYLOAD_ADDRESS_OFFSET 2
#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2)
#define GPMI_AUXILIARY_ADDRESS_OFFSET 2
#define GPMI_CTRL1_DECOUPLE_CS (1 << 24)
#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22)
#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22
#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20)
#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)
#define GPMI_CTRL1_BCH_MODE (1 << 18)
#define GPMI_CTRL1_DLL_ENABLE (1 << 17)
#define GPMI_CTRL1_HALF_PERIOD (1 << 16)
#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12)
#define GPMI_CTRL1_RDN_DELAY_OFFSET 12
#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11)
#define GPMI_CTRL1_DEV_IRQ (1 << 10)
#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9)
#define GPMI_CTRL1_BURST_EN (1 << 8)
#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7)
#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4)
#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4
#define GPMI_CTRL1_DEV_RESET (1 << 3)
#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
#define GPMI_CTRL1_CAMERA_MODE (1 << 1)
#define GPMI_CTRL1_GPMI_MODE (1 << 0)
#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8)
#define GPMI_TIMING0_DATA_HOLD_OFFSET 8
#define GPMI_TIMING0_DATA_SETUP_MASK 0xff
#define GPMI_TIMING0_DATA_SETUP_OFFSET 0
#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16)
#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16
#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24)
#define GPMI_TIMING2_UDMA_TRP_OFFSET 24
#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16)
#define GPMI_TIMING2_UDMA_ENV_OFFSET 16
#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8)
#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8
#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff
#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0
#define GPMI_DATA_DATA_MASK 0xffffffff
#define GPMI_DATA_DATA_OFFSET 0
#define GPMI_STAT_READY_BUSY_MASK (0xff << 24)
#define GPMI_STAT_READY_BUSY_OFFSET 24
#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16)
#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16
#define GPMI_STAT_DEV7_ERROR (1 << 15)
#define GPMI_STAT_DEV6_ERROR (1 << 14)
#define GPMI_STAT_DEV5_ERROR (1 << 13)
#define GPMI_STAT_DEV4_ERROR (1 << 12)
#define GPMI_STAT_DEV3_ERROR (1 << 11)
#define GPMI_STAT_DEV2_ERROR (1 << 10)
#define GPMI_STAT_DEV1_ERROR (1 << 9)
#define GPMI_STAT_DEV0_ERROR (1 << 8)
#define GPMI_STAT_ATA_IRQ (1 << 4)
#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3)
#define GPMI_STAT_FIFO_EMPTY (1 << 2)
#define GPMI_STAT_FIFO_FULL (1 << 1)
#define GPMI_STAT_PRESENT (1 << 0)
#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24)
#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24
#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16)
#define GPMI_DEBUG_DMA_SENSE_OFFSET 16
#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8)
#define GPMI_DEBUG_DMAREQ_OFFSET 8
#define GPMI_DEBUG_CMD_END_MASK 0xff
#define GPMI_DEBUG_CMD_END_OFFSET 0
#define GPMI_VERSION_MAJOR_MASK (0xff << 24)
#define GPMI_VERSION_MAJOR_OFFSET 24
#define GPMI_VERSION_MINOR_MASK (0xff << 16)
#define GPMI_VERSION_MINOR_OFFSET 16
#define GPMI_VERSION_STEP_MASK 0xffff
#define GPMI_VERSION_STEP_OFFSET 0
#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24)
#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24
#define GPMI_DEBUG2_BUSY (1 << 23)
#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20)
#define GPMI_DEBUG2_PIN_STATE_OFFSET 20
#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20)
#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16)
#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16
#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16)
#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12)
#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12
#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11)
#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10)
#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9)
#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8)
#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7)
#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6)
#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f
#define GPMI_DEBUG2_RDN_TAP_OFFSET 0
#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16)
#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16
#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff
#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0
#endif /* __MX28_REGS_GPMI_H__ */

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u-boot/arch/arm/include/asm/imx-common/regs-lcdif.h Normal file
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/*
* Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX_REGS_LCDIF_H__
#define __IMX_REGS_LCDIF_H__
#ifndef __ASSEMBLY__
#include <asm/imx-common/regs-common.h>
struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
defined(CONFIG_MX7)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */
mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */
#if defined(CONFIG_MX23)
uint32_t reserved1[4];
#endif
mxs_reg_32(hw_lcdif_timing) /* 0x60 */
mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
#if defined(CONFIG_MX23)
uint32_t reserved2[12];
#endif
mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
defined(CONFIG_MX7)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */
mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7)
mxs_reg_32(hw_lcdif_thres)
mxs_reg_32(hw_lcdif_as_ctrl)
mxs_reg_32(hw_lcdif_as_buf)
mxs_reg_32(hw_lcdif_as_next_buf)
mxs_reg_32(hw_lcdif_as_clrkeylow)
mxs_reg_32(hw_lcdif_as_clrkeyhigh)
mxs_reg_32(hw_lcdif_as_sync_delay)
mxs_reg_32(hw_lcdif_as_debug3)
mxs_reg_32(hw_lcdif_as_debug4)
mxs_reg_32(hw_lcdif_as_debug5)
#endif
};
#endif
#define LCDIF_CTRL_SFTRST (1 << 31)
#define LCDIF_CTRL_CLKGATE (1 << 30)
#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
#define LCDIF_CTRL_READ_WRITEB (1 << 28)
#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
#define LCDIF_CTRL_DVI_MODE (1 << 20)
#define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
#define LCDIF_CTRL_VSYNC_MODE (1 << 18)
#define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
#define LCDIF_CTRL_DATA_SELECT (1 << 16)
#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
#define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
#define LCDIF_CTRL_RUN (1 << 0)
#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
#define LCDIF_CTRL1_MODE86 (1 << 1)
#define LCDIF_CTRL1_RESET (1 << 0)
#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
#define LCDIF_CUR_BUF_ADDR_OFFSET 0
#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
#define LCDIF_NEXT_BUF_ADDR_OFFSET 0
#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
#define LCDIF_TIMING_CMD_HOLD_OFFSET 24
#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
#define LCDIF_TIMING_CMD_SETUP_OFFSET 16
#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
#define LCDIF_TIMING_DATA_HOLD_OFFSET 8
#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
#define LCDIF_TIMING_DATA_SETUP_OFFSET 0
#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
#define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
#if defined(CONFIG_MX23)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24
#else
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
#endif
#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
#endif /* __IMX_REGS_LCDIF_H__ */

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u-boot/arch/arm/include/asm/imx-common/regs-usbphy.h Normal file
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/*
* Freescale USB PHY Register Definitions
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
#ifndef __REGS_USBPHY_H__
#define __REGS_USBPHY_H__
#define USBPHY_CTRL 0x00000030
#define USBPHY_CTRL_SET 0x00000034
#define USBPHY_CTRL_CLR 0x00000038
#define USBPHY_CTRL_TOG 0x0000003C
#define USBPHY_PWD 0x00000000
#define USBPHY_TX 0x00000010
#define USBPHY_RX 0x00000020
#define USBPHY_DEBUG 0x00000050
#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14)
#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15)
#define USBPHY_CTRL_OTG_ID (1 << 27)
#define USBPHY_CTRL_CLKGATE (1 << 30)
#define USBPHY_CTRL_SFTRST (1 << 31)
#endif /* __REGS_USBPHY_H__ */

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u-boot/arch/arm/include/asm/imx-common/sata.h Normal file
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/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX_SATA_H_
#define __IMX_SATA_H_
/*
* SATA setup for i.mx6 quad based platform
*/
int setup_sata(void);
#endif

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u-boot/arch/arm/include/asm/imx-common/spi.h Normal file
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/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MXC_SPI_H_
#define __MXC_SPI_H_
/*
* Board-level chip-select callback
* Should return GPIO # to be used for chip-select
*/
int board_spi_cs_gpio(unsigned bus, unsigned cs);
#endif

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u-boot/arch/arm/include/asm/imx-common/sys_proto.h Normal file
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/*
* (C) Copyright 2009
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <asm/imx-common/regs-common.h>
#include <common.h>
#include "../arch-imx/cpu.h"
#define soc_rev() (get_cpu_rev() & 0xFF)
#define is_soc_rev(rev) (soc_rev() == rev)
/* returns MXC_CPU_ value */
#define cpu_type(rev) (((rev) >> 12) & 0xff)
#define soc_type(rev) (((rev) >> 12) & 0xf0)
/* both macros return/take MXC_CPU_ constants */
#define get_cpu_type() (cpu_type(get_cpu_rev()))
#define get_soc_type() (soc_type(get_cpu_rev()))
#define is_cpu_type(cpu) (get_cpu_type() == cpu)
#define is_soc_type(soc) (get_soc_type() == soc)
#define is_mx6() (is_soc_type(MXC_SOC_MX6))
#define is_mx7() (is_soc_type(MXC_SOC_MX7))
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
u32 get_cpu_speed_grade_hz(void);
u32 get_cpu_temp_grade(int *minc, int *maxc);
const char *get_imx_type(u32 imxtype);
u32 imx_ddr_size(void);
void sdelay(unsigned long);
void set_chipselect_size(int const);
void init_aips(void);
void init_src(void);
void imx_set_wdog_powerdown(bool enable);
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
void lcdif_power_down(void);
int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
#endif

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u-boot/arch/arm/include/asm/imx-common/syscounter.h Normal file
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/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
#define _ASM_ARCH_SYSTEM_COUNTER_H
/* System Counter */
struct sctr_regs {
u32 cntcr;
u32 cntsr;
u32 cntcv1;
u32 cntcv2;
u32 resv1[4];
u32 cntfid0;
u32 cntfid1;
u32 cntfid2;
u32 resv2[1001];
u32 counterid[1];
};
#define SC_CNTCR_ENABLE (1 << 0)
#define SC_CNTCR_HDBG (1 << 1)
#define SC_CNTCR_FREQ0 (1 << 8)
#define SC_CNTCR_FREQ1 (1 << 9)
#endif

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u-boot/arch/arm/include/asm/imx-common/video.h Normal file
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/*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX_VIDEO_H_
#define __IMX_VIDEO_H_
#include <linux/fb.h>
#include <ipu_pixfmt.h>
struct display_info_t {
int bus;
int addr;
int pixfmt;
int (*detect)(struct display_info_t const *dev);
void (*enable)(struct display_info_t const *dev);
struct fb_videomode mode;
};
#ifdef CONFIG_IMX_HDMI
extern int detect_hdmi(struct display_info_t const *dev);
#endif
#ifdef CONFIG_IMX_VIDEO_SKIP
extern struct display_info_t const displays[];
extern size_t display_count;
#endif
int ipu_set_ldb_clock(int rate);
#endif